WO2017054407A1 - 一种薄膜晶体管、阵列基板及相关制作方法、以及显示装置 - Google Patents

一种薄膜晶体管、阵列基板及相关制作方法、以及显示装置 Download PDF

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WO2017054407A1
WO2017054407A1 PCT/CN2016/075114 CN2016075114W WO2017054407A1 WO 2017054407 A1 WO2017054407 A1 WO 2017054407A1 CN 2016075114 W CN2016075114 W CN 2016075114W WO 2017054407 A1 WO2017054407 A1 WO 2017054407A1
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layer
insulating layer
siloxane material
array substrate
forming
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PCT/CN2016/075114
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English (en)
French (fr)
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程磊磊
许凯
袁广才
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京东方科技集团股份有限公司
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Priority to US15/311,642 priority Critical patent/US10256343B2/en
Publication of WO2017054407A1 publication Critical patent/WO2017054407A1/zh

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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/02—Materials and properties organic material

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a thin film transistor (TFT), an array substrate, a related manufacturing method, and a display device.
  • TFT thin film transistor
  • the electrode insulating layer is mostly made of the following two materials.
  • One is a high dielectric constant inorganic material such as silicon nitride and silicon dioxide, but it does not suppress the capacitance effect of the electrode to a low level while improving the threshold voltage of the TFT device.
  • the formation process of the insulating layer film of the inorganic material is complicated, and several depositions are required to complete the formation of the thick inorganic insulating film.
  • the other is an organic polymer material, which has the characteristics of easy regulation, simple processing and large-area production, and can be processed in a simple manner such as spin coating, coating and printing at room temperature, which greatly reduces the production cost. .
  • the dielectric constant of these polymer materials is relatively low, when used alone in the insulating layer of the TFT device, the threshold voltage of the thin film transistor is required to be high, resulting in a large leakage current, thereby affecting the polymer material as an insulating layer. Application on thin film transistors.
  • a method of fabricating a thin film transistor including the step of forming an insulating layer including the step of forming an insulating layer.
  • the step of forming an insulating layer includes:
  • the oxidized silicone material layer is cured to obtain the insulating layer.
  • forming a layer of silicone material includes:
  • the siloxane material layer is formed at a time by a coating process or a spin coating process.
  • the siloxane material layer is oxidized, including:
  • the siloxane material layer is subjected to an oxidation treatment by ultraviolet rays or ozone.
  • a method of fabricating an array substrate comprising the steps of forming a plurality of insulating layers.
  • the step of forming at least one insulating layer includes:
  • the oxidized silicone material layer is cured to obtain an insulating layer.
  • forming a layer of silicone material includes:
  • the siloxane material layer is formed at a time by a coating process or a spin coating process.
  • the siloxane material layer is oxidized, including:
  • the siloxane material layer is subjected to an oxidation treatment by ultraviolet rays or ozone.
  • a thin film transistor including not less than one insulating layer.
  • at least one of the insulating layers is a siloxane material layer pattern having an outer surface covering the inorganic silicon film.
  • an array substrate comprising not less than one insulating layer.
  • at least one of the insulating layers is a siloxane material layer pattern having an outer surface covering the inorganic silicon film.
  • the array substrate further includes:
  • a gate a gate, a source, and an active layer
  • the insulating layer includes: a first insulating layer disposed between the gate and the source; and a second insulating layer disposed between the source and the active layer;
  • the active layer is disposed between the first insulating layer and the source;
  • a first via hole penetrating is disposed at a first position of the second insulating layer corresponding to the active layer, and the source is connected to the active layer through the first via hole.
  • the source is located above the gate, and the array substrate further includes: a bit a pixel electrode above the source;
  • the insulating layer further includes: a third insulating layer disposed between the pixel electrode and the source;
  • the insulating layer further includes: a protective layer disposed over the pixel electrode.
  • a display device including the above array substrate.
  • the outer layer of the insulating layer is an inorganic silicon film, that is, an insulating layer material commonly used in the prior art.
  • the inner layer of the insulating layer is a siloxane material, which has the characteristics of low dielectric constant and high chemical stability, can stably suppress the capacitance effect generated by the thin film transistor electrode, and can be driven at a lower voltage, thereby effectively reducing Power consumption.
  • FIG. 1 is a schematic view showing a step of forming an insulating layer in a method of fabricating a thin film transistor of the present invention
  • FIG. 2 is a schematic view showing the detailed steps of forming an insulating layer in the method for fabricating a thin film transistor of the present invention
  • 3A-3J are flow charts showing the fabrication of the array substrate of the present invention.
  • an embodiment of the present invention provides a thin film transistor and a method of fabricating the same.
  • At least one of the insulating layers of the thin film transistor is a siloxane material layer pattern having an outer surface covering the inorganic silicon film.
  • the method of fabricating the thin film transistor includes the step of forming an insulating layer. As shown in FIG. 1, the step of forming an insulating layer includes:
  • the siloxane material is an organic polymer, and may be, for example, polydimethylsiloxane or a modified material based on the material.
  • the modified material may be functionalized by hydroxyl groups Polydimethylsiloxane or polystyrene block polydimethylsiloxane, and the like.
  • the siloxane material layer is oxidized to form an inorganic silicon film on the surface of the siloxane material layer.
  • the main component of the inorganic silicon film is silicon dioxide, which is a commonly used material for the insulating layer in the conventional thin film transistor.
  • the fabrication method of this embodiment uses a new insulating layer fabrication process.
  • the outer layer of the insulating layer is an inorganic silicon film, that is, an insulating layer material commonly used in the prior art;
  • the inner layer of the insulating layer is a siloxane material, which has the characteristics of low dielectric constant and high chemical stability.
  • the capacitor effect generated by the thin film transistor electrode can be stably suppressed, so that the driving can be performed at a lower voltage, thereby effectively reducing power consumption.
  • the detailed process of fabricating the insulating layer includes:
  • the siloxane material layer is oxidized by ultraviolet rays or ozone to change a chemical bond on the surface of the siloxane material layer to form an inorganic silicon film.
  • this step S23 is mainly to cure the outer layer of the inorganic silicon film to compensate for the hardness of the inner layer of the siloxane material.
  • the curing temperature of the step S23 may be in the vicinity of 55 ° C to 60 ° C, and the curing time may be between 3 h and 4 h.
  • the above is the detailed flow of fabricating the insulating layer in the embodiment of the present invention.
  • an inorganic silicon material is used as an insulating layer in the prior art, it is necessary to directly deposit an inorganic silicon material using a high-cost deposition process. Inorganic silicon materials have high surface energy, so repeated deposition is required to achieve a certain thickness requirement, and it is not suitable for the production requirements of large-sized display panels. Further, in the prior art, since the entire insulating layer is an inorganic silicon material, it is required to reach a temperature of 300 ° C when the inorganic silicon material is cured.
  • the insulating layer is first formed into a siloxane material layer by a lower cost coating process or a spin coating process, and the siloxane material is liquid, which is extremely low.
  • the surface energy so it is very easy to achieve a smooth, uniform coating, can be applied to the production requirements of large-size display panels.
  • the inorganic silicon material film on the outer surface of the insulating layer can be formed by a simple oxidation process, and since only the surface is an inorganic silicon material, the curing temperature only needs to be It is 60 ° C.
  • the fabrication method of the thin film transistor of the present embodiment is much smaller than the prior art in the process complexity.
  • the embodiment of the present invention further provides a method for fabricating an array substrate, and the insulating layer on the array substrate can also be fabricated by using the steps S21 to S23 described above.
  • the insulating layer near the electrode of the array substrate can effectively suppress the capacitive effect generated when the electrode is loaded with the signal after the manufacturing process provided by the present invention.
  • the protective layer that protects some functional patterns can also use the manufacturing process provided by the present invention, and the process complexity is greatly simplified compared to the prior art.
  • the detailed process includes:
  • Step 301 referring to FIG. 3A, the common electrode 2 and the gate electrode 3 are sequentially formed on the base substrate 1.
  • Step 302 referring to FIG. 3B, the first insulating layer 4 is formed by the method of the above steps S21 to S23.
  • Step 303 referring to FIG. 3C, the active layer 5 is formed by a mask process.
  • Step 304 referring to FIG. 3D, the second insulating layer 6 is formed by the method of the above steps S21 to S23.
  • Step 305 referring to FIG. 3E, through the mask process, a first via hole H1 and a second via hole H2 penetrating are formed at a position corresponding to the active layer 5 of the second insulating layer 6.
  • Step 306 referring to FIG. 3F, a source S is formed by a mask process, and the source S is connected to the active layer 5 through the first via H1.
  • the dual source structure forms two TFT conductive channels, which can effectively improve carrier migration efficiency.
  • Step 307 referring to FIG. 3G, the third insulating layer 7 is formed by the method of the above steps S21 to S23.
  • Step 308 referring to FIG. 3H, through a mask process, a third via hole is formed at a position corresponding to the active layer 5 of the third insulating layer, and the third via hole communicates with the second via hole H2 to form a fourth via hole H4.
  • Step 309 referring to FIG. 3I, a pixel electrode 8 is formed by a mask process, and the pixel electrode 8 is connected to the active layer 5 through the fourth via hole H4.
  • Step 310 referring to FIG. 3J, the protective layer 9 is formed by the method of the above steps S21 to S23.
  • the above is the method of fabricating the array substrate of the present embodiment, in which the pixel electrode is directly connected to the active layer as a drain to improve the response speed of the received data signal.
  • the drain since the drain is not required to be fabricated, the lateral occupation area of the drain is saved, thereby increasing the aperture ratio.
  • an array substrate wherein at least one of the insulating layers is a siloxane material layer pattern having an outer surface covering the inorganic silicon film.
  • the array substrate of this embodiment includes:
  • a gate 3 a source S and an active layer 5 formed on the base substrate 1;
  • first insulating layer 4 disposed between the gate 3 and the source S, and a second insulating layer 6 disposed between the source S and the active layer 5;
  • first insulating layer 4 and the second insulating layer 6 All are siloxane material layer patterns whose outer surface is covered with an inorganic silicon film.
  • the second insulating layer 6 is provided with a first via hole H1 penetrating through the first position of the active layer 5, and the source S is connected to the active layer 5 through the first via hole H1 on the second insulating layer 6.
  • the array substrate of the embodiment further includes: a pixel electrode 8 located above the source S, and a third insulating layer 7 disposed between the pixel electrode 8 and the source S.
  • the third insulating layer 7 is a siloxane material layer pattern whose outer surface is covered with an inorganic silicon film.
  • the second insulating layer 6 is provided with a second through hole corresponding to the second position of the active layer 5, and the third insulating layer 7 is provided with a second through hole corresponding to the second position of the active layer;
  • the second via hole communicates with the third via hole to form a fourth via hole H4.
  • the pixel electrode 8 is connected to the active layer 5 through the fourth via hole H4.
  • the array substrate of this embodiment may further include: a protective layer 9 disposed above the pixel electrode 8, and the protective layer 9 may be a siloxane material layer pattern whose outer surface covers the inorganic silicon film.
  • the insulating layer of the array substrate of the present embodiment is obtained by the novel insulating layer fabrication process of the present invention, and thus the same advantageous effects can be achieved.
  • embodiments of the present invention also provide a display device including the above array substrate. Since the display device has a lower dielectric constant, the display device can effectively suppress the capacitance effect generated by the electrodes, thereby providing a more stable display effect.

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Abstract

本发明公开了一种薄膜晶体管、阵列基板及相关制作方法、以及显示装置。本发明的薄膜晶体管的制作方法包括：形成绝缘层的步骤。其中，形成绝缘层的步骤进一步包括：形成硅氧烷材料层；对硅氧烷材料层进行氧化处理，使硅氧烷材料层的表面形成无机硅薄膜；对氧化处理后的硅氧烷材料层进行固化，得到绝缘层。在本发明中，绝缘层的外层为无机硅薄膜，即现有技术中常用的绝缘层材料；绝缘层的内层为硅氧烷材料，具有低介电常数和高化学稳定的特点，可稳定地抑制薄膜晶体管电极所产生的电容效应，从而能够以较低的电压进行驱动，有效降低能耗。

Description

一种薄膜晶体管、阵列基板及相关制作方法、以及显示装置
相关申请的交叉参考
本申请主张2015年9月30日在中国提交的中国专利申请号No.201510640918.7的优先权，其全部内容通过引用包含于此。
技术领域
本发明涉及液晶显示领域，特别涉及一种薄膜晶体管(TFT)、阵列基板及相关制作方法、以及显示装置。
背景技术
现有的氧化物TFT阵列基板的制程工艺中，电极绝缘层大多采用以下两种材料。一种是高介电常数的无机材料，如氮化硅和二氧化硅，但其在改善TFT器件阈值电压的同时，却无法做到将电极产生的电容效应抑制到较低水平。此外，无机材料的绝缘层薄膜的形成工艺复杂，且形成较厚的无机绝缘膜时需要几次沉积来完成。
另一种是有机聚合物材料，其具有性能易于调控、加工简便和适合大面积生产等特点，而且能在室温下用旋涂、涂布和打印等简单的方式进行加工，大大降低了生产成本。然而，由于这些聚合物材料的介电常数相对较低，单独使用于TFT器件的绝缘层时，对薄膜晶体管的阈值电压要求较高，导致漏电流较大，从而影响聚合物材料作为绝缘层在薄膜晶体管上的应用。
发明内容
本发明的目的是提供一种薄膜晶体管、阵列基板及相关制作方法、以及显示装置，其通过新的绝缘层制作工艺，能够有效抑制附近电极所产生的电容效应。
为了实现上述目的，根据本发明的实施例，提供一种薄膜晶体管的制作方法，其包括形成绝缘层的步骤。其中，所述形成绝缘层的步骤包括：
形成硅氧烷材料层；
对所述硅氧烷材料层进行氧化处理，使所述硅氧烷材料层的表面形成无机硅薄膜；
对氧化处理后的硅氧烷材料层进行固化，得到所述绝缘层。
在一个示例中，形成硅氧烷材料层，包括：
通过涂布工艺或者旋涂工艺，一次形成硅氧烷材料层。
在一个示例中，对所述硅氧烷材料层进行氧化处理，包括：
通过紫外线或臭氧对所述硅氧烷材料层进行氧化处理。
根据本发明的实施例，还提供一种阵列基板的制作方法，其包括形成多个绝缘层的步骤。其中，至少一个绝缘层的形成步骤，包括：
形成硅氧烷材料层；
对所述硅氧烷材料层进行氧化处理，使所述硅氧烷材料层的表面形成无机硅薄膜；
对氧化处理后的硅氧烷材料层进行固化，得到绝缘层。
在一个示例中，形成硅氧烷材料层，包括：
通过涂布工艺或者旋涂工艺，一次形成硅氧烷材料层。
在一个示例中，对所述硅氧烷材料层进行氧化处理，包括：
通过紫外线或臭氧对所述硅氧烷材料层进行氧化处理。
根据本发明的实施例，还提供一种薄膜晶体管，包括不少于一个的绝缘层。其中，至少一个绝缘层为外表面覆盖无机硅薄膜的硅氧烷材料层图形。
根据本发明的实施例，还提供一种阵列基板，包括不少于一个的绝缘层。其中，至少一个绝缘层为外表面覆盖无机硅薄膜的硅氧烷材料层图形。
本发明的实施例中，所述阵列基板还包括：
栅极、源极以及有源层；
所述绝缘层包括：设置在所述栅极与源极之间的第一绝缘层，以及设置在所述源极与有源层之间的第二绝缘层；
所述有源层设置在所述第一绝缘层与所述源极之间；
在所述第二绝缘层的对应于所述有源层的第一位置，设置有贯通的第一过孔，所述源极通过所述第一过孔与所述有源层连接。
在一个示例中，所述源极位于所述栅极上方，所述阵列基板还包括：位 于所述源极上方的像素电极；
所述绝缘层还包括：设置在所述像素电极与源极之间的第三绝缘层；
在所述第二绝缘层的对应于所述有源层的第二位置，设置有贯通的第二过孔，在所述第三绝缘层的对应于所述有源层的第二位置，设置有贯通的第三过孔；所述第二过孔与所述第三过孔连通形成第四过孔；所述像素电极通过所述第四过孔与有源层连接。
在一个示例中，所述绝缘层还包括：设置在所述像素电极上方的保护层。
根据本发明的实施例，还提供一种包括上述阵列基板的显示装置。
根据本发明的上述技术方案，本发明的有益效果如下：
在本发明的技术方案中，绝缘层的外层为无机硅薄膜，即现有技术中常用的绝缘层材料。此外，绝缘层的内层为硅氧烷材料，具有低介电常数和高化学稳定的特点，可稳定地抑制薄膜晶体管电极所产生的电容效应，从而能够以较低的电压进行驱动，有效降低功耗。
附图说明
图1为本发明的薄膜晶体管的制作方法中形成绝缘层的步骤示意图；
图2为本发明的薄膜晶体管的制作方法中形成绝缘层的详细步骤示意图；
图3A-图3J为本发明的阵列基板的制作流程图。
具体实施方式
为使本发明要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
针对现有技术存在的问题，本发明的一个实施例提供一种薄膜晶体管及其制作方法。该薄膜晶体管中的至少一个绝缘层为外表面覆盖无机硅薄膜的硅氧烷材料层图形。该薄膜晶体管的制作方法包括形成绝缘层的步骤。如图1所示，该形成绝缘层的步骤包括：
S11，形成硅氧烷材料层。其中，硅氧烷材料为有机聚合物，例如可以为聚二甲基硅氧烷或基于该材料的改性材料。该改性材料可以是经羟基功能化 的聚二甲基硅氧烷或聚苯乙烯嵌段式聚二甲基硅氧烷等。
S12，对硅氧烷材料层进行氧化处理，使该硅氧烷材料层的表面形成无机硅薄膜。其中，无机硅薄膜的主要成分为二氧化硅，二氧化硅正是现有薄膜晶体管中绝缘层常用的材料。
S13，对氧化处理后的硅氧烷材料层进行固化，得到绝缘层。
本实施例的制作方法使用了新的绝缘层制作工艺。通过该绝缘层制作工艺，绝缘层的外层为无机硅薄膜，即现有技术中常用的绝缘层材料；绝缘层的内层为硅氧烷材料，具有低介电常数和高化学稳定的特点，可稳定地抑制薄膜晶体管电极所产生的电容效应，从而能够以较低的电压进行驱动，有效降低功耗。
下面对上述步骤S11-步骤S13的绝缘层制作流程进行详细介绍。
如图2所示，本实施例中，制作绝缘层的详细流程包括：
S21，通过涂布工艺或者旋涂工艺形成硅氧烷材料层。
S22，通过紫外线或臭氧对所述硅氧烷材料层进行氧化处理，使硅氧烷材料层表面的化学键发生变化，生成无机硅薄膜。
S23，对氧化处理后的硅氧烷材料层进行固化，得到绝缘层。其中，本步骤S23主要是对外层无机硅薄膜进行固化，以弥补内层的硅氧烷材料的硬度。此外，作为可行方案，本步骤S23的固化温度可以是55℃～60℃附近，固化时间可以是3h～4h之间。
以上是本发明实施例中制作绝缘层的详细流程。在现有技术中采用无机硅材料作为绝缘层时，需要使用高成本的沉积工艺直接沉积无机硅材料。而无机硅材料具有很高的表面能，因此需要反复沉积才能达到一定的厚度要求，无法适用于大尺寸显示面板的制作要求。此外，现有技术中，由于整个绝缘层都是无机硅材料，因此在对无机硅材料进行固化时，需要温度达到300℃。
相比现有技术，本实施例的薄膜晶体管的制作方法中，绝缘层由成本更低的涂布工艺或旋涂工艺先形成硅氧烷材料层，该硅氧烷材料为液体，具有极低的表面能，因此非常容易达到平滑、均匀的涂层，能够适用于大尺寸显示面板的制作要求。进一步地，绝缘层外表面的无机硅材料薄膜则通过工艺简单氧化处理即可形成，且由于只有表面是无机硅材料，因此固化温度只需 要60℃。通过与现有技术对比可看出，本实施例的薄膜晶体管的制作方法在工艺复杂程度上要远小于现有技术。
本发明的实施例还提供一种阵列基板的制作方法，该阵列基板上的绝缘层也可以采用上述步骤S21至步骤S23的流程制作。例如：阵列基板电极附近的绝缘层在采用本发明提供的制作工艺后，能够有效抑制电极加载信号时产生的电容效应。或者，在阵列基板中，对一些功能图形起保护作用的保护层也可以使用本发明提供的制作工艺，相比现有技术，工艺复杂程度上得到了极大的简化。
下面结合一个实施方式，对阵列基板的制作进行详细介绍。
在本实施方式中，以制作底栅阵列基板为例，详细流程包括：
步骤301，参考图3A，在衬底基板1上依次形成公共电极2和栅极3。
步骤302，参考图3B，通过上述步骤S21-步骤S23的方法，形成第一绝缘层4。
步骤303，参考图3C，通过掩膜工艺，形成有源层5。
步骤304，参考图3D，通过上述步骤S21-步骤S23的方法，形成第二绝缘层6。
步骤305，参考图3E，通过掩膜工艺，在第二绝缘层6对应有源层5的位置，形成贯通的第一过孔H1和第二过孔H2。
步骤306，参考图3F，通过掩膜工艺，形成源极S，该源极S通过上述第一过孔H1与有源层5连接。
其中需要给予说明的是，在本实施方式中，作为示例，以双源极的阵列基板进行介绍。该双源极结构形成了两个TFT导电沟道，可有效提升载流子的迁移效率。
步骤307，参考图3G，通过上述步骤S21-步骤S23的方法形成第三绝缘层7。
步骤308，参考图3H，通过掩膜工艺，在第三绝缘层对应有源层5的位置，形成第三过孔，该第三过孔与第二过孔H2连通形成第四过孔H4。
步骤309，参考图3I，通过掩膜工艺，形成像素电极8，该像素电极8通过第四过孔H4，与有源层5连接。
步骤310，参考图3J，通过上述步骤S21-步骤S23的方法形成保护层9。
以上是本实施方式的阵列基板的制作方法，其中像素电极作为漏极直接与有源层连接可提高接收数据信号的响应速度。此外，由于不需要再制作漏极，因此节省了漏极的横向占用面积，进而提高了开口率。
对应地，根据本发明的实施例，还提供一种阵列基板，该阵列基板中的至少一个绝缘层为外表面覆盖无机硅薄膜的硅氧烷材料层图形。
典型地，如图3J所示，本实施例的阵列基板包括：
形成在衬底基板1上的栅极3、源极S以及有源层5；
设置在栅极3与源极S之间的第一绝缘层4，以及设置在源极S与有源层5之间的第二绝缘层6；该第一绝缘层4和第二绝缘层6均为外表面覆盖无机硅薄膜的硅氧烷材料层图形。其中，第二绝缘层6对应有源层5的第一位置，设置有贯通的第一过孔H1，源极S通过第二绝缘层6上的第一过孔H1与有源层5连接。
进一步地，本实施例的阵列基板还包括：位于源极S上方的像素电极8，以及设置在像素电极8与源极S之间的第三绝缘层7。该第三绝缘层7为外表面覆盖无机硅薄膜的硅氧烷材料层图形。
其中，第二绝缘层6对应有源层5的第二位置，设置有贯通的第二过孔，第三绝缘层7对应有源层的第二位置，设置有贯通的第三过孔；该第二过孔与该第三过孔连通形成第四过孔H4。像素电极8通过第四过孔H4与有源层5连接。
此外，本实施例的阵列基板还可以包括：设置在像素电极8上方的保护层9，该保护层9可以为外表面覆盖无机硅薄膜的硅氧烷材料层图形。
显然，本实施例的阵列基板的绝缘层由本发明的新的绝缘层制作工艺得到，因此能够达到相同的有益效果。
此外，本发明的实施例还提供一种包括上述阵列基板的显示装置。该显示装置由于绝缘层具有更低的介电常数，因此能够有效抑制电极所产生的电容效应，从而提供更为稳定的显示效果。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普 通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视本发明的保护范围。

Claims (12)

  1. 一种薄膜晶体管的制作方法，包括形成绝缘层的步骤，其中，
    所述形成绝缘层的步骤包括：
    形成硅氧烷材料层；
    对所述硅氧烷材料层进行氧化处理，使所述硅氧烷材料层的表面形成无机硅薄膜；
    对氧化处理后的硅氧烷材料层进行固化，得到所述绝缘层。
  2. 根据权利要求1所述的制作方法，其中，
    形成硅氧烷材料层，包括：
    通过涂布工艺或者旋涂工艺，一次形成硅氧烷材料层。
  3. 根据权利要求1或2所述的制作方法，其中，
    对所述硅氧烷材料层进行氧化处理，包括：
    通过紫外线或臭氧对所述硅氧烷材料层进行氧化处理。
  4. 一种阵列基板的制作方法，包括形成多个绝缘层的步骤，其中，
    至少一个绝缘层的形成步骤，包括：
    形成硅氧烷材料层；
    对所述硅氧烷材料层进行氧化处理，使所述硅氧烷材料层的表面形成无机硅薄膜；
    对氧化处理后的硅氧烷材料层进行固化，得到绝缘层。
  5. 根据权利要求4所述的制作方法，其中，
    形成硅氧烷材料层，包括：
    通过涂布工艺或者旋涂工艺，一次形成硅氧烷材料层。
  6. 根据权利要求4或5所述的制作方法，其中，
    对所述硅氧烷材料层进行氧化处理，包括：
    通过紫外线或臭氧对所述硅氧烷材料层进行氧化处理。
  7. 一种薄膜晶体管，包括不少于一个的绝缘层，其中，
    至少一个绝缘层为外表面覆盖无机硅薄膜的硅氧烷材料层图形。
  8. 一种阵列基板，包括不少于一个的绝缘层，其中，
    至少一个绝缘层为外表面覆盖无机硅薄膜的硅氧烷材料层图形。
  9. 根据权利要求8所述阵列基板，其中，还包括：
    栅极、源极以及有源层；
    所述绝缘层包括：设置在所述栅极与源极之间的第一绝缘层，以及设置在所述源极与有源层之间的第二绝缘层；
    所述有源层设置在所述第一绝缘层与所述源极之间；
    在所述第二绝缘层的对应于所述有源层的第一位置，设置有贯通的第一过孔，所述源极通过所述第一过孔与所述有源层连接。
  10. 根据权利要求9所述阵列基板，其中，所述源极位于所述栅极上方，所述阵列基板还包括：位于所述源极上方的像素电极；
    所述绝缘层还包括：设置在所述像素电极与源极之间的第三绝缘层；
    在所述第二绝缘层的对应于所述有源层的第二位置，设置有贯通的第二过孔，在所述第三绝缘层的对应于所述有源层的第二位置，设置有贯通的第三过孔；所述第二过孔与所述第三过孔连通形成第四过孔；所述像素电极通过所述第四过孔与有源层连接。
  11. 根据权利要求10所述阵列基板，其中，
    所述绝缘层还包括：设置在所述像素电极上方的保护层。
  12. 一种显示装置，其中，包括如权利要求8-11任一项所述的阵列基板。
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