WO2017054252A1 - 一种tft基板、tft开关管及其制造方法 - Google Patents

一种tft基板、tft开关管及其制造方法 Download PDF

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Publication number
WO2017054252A1
WO2017054252A1 PCT/CN2015/091442 CN2015091442W WO2017054252A1 WO 2017054252 A1 WO2017054252 A1 WO 2017054252A1 CN 2015091442 W CN2015091442 W CN 2015091442W WO 2017054252 A1 WO2017054252 A1 WO 2017054252A1
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layer
semiconductor layer
gate
regions
thinned
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French (fr)
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石龙强
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/889,533 priority Critical patent/US9798208B2/en
Publication of WO2017054252A1 publication Critical patent/WO2017054252A1/zh
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136218—Shield electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/122—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode having a particular pattern
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT substrate, a TFT switch tube, and a method of fabricating the same.
  • Thin film field effect transistors based on oxide semiconductors are hotspots in the field of display in the future, and have been extensively researched and developed in recent years.
  • the amorphous indium gallium zinc oxide (a-IGZO) film as an active channel layer can have a mobility of up to 80 cm 2 /Vs, while the mobility of amorphous silicon (a-Si) is only 0.5 to 0.8 cm 2 /Vs.
  • a-IGZO is compatible with a-Si large-volume production process. Therefore, IGZO has great application prospects in the next generation of liquid crystal display (LCD) and organic light emitting diode (OLED).
  • LCD liquid crystal display
  • OLED organic light emitting diode
  • a Schottky contact is formed when the metal is in contact with the IGZO, and the semiconductor band is bent at the interface of the contact to form a barrier.
  • the presence of a barrier results in a large interfacial resistance, the Schottky resistance.
  • Schottky Resistor Causes Insufficient On-State Current of TFT Components, Subthreshold Swing (Subthreshold Swing, SS) is too large, component stability is degraded, which will affect the picture display quality.
  • reducing the contact resistance of metal and IGZO to form Ohmic contact is an important factor in determining the performance of semiconductor components.
  • One of the methods for forming an ohmic contact in the prior art is to dope heavily (n+IGZO) in a semiconductor region in contact with a metal, so that the depletion region of the interface is narrowed, and electrons have more opportunities for direct tunneling (tunneling effect). ).
  • the prior art ohmic contact method requires an additional doping step, thereby increasing the manufacturing cost.
  • the technical problem to be solved by the present invention is to provide a TFT substrate, a TFT switch tube and a method of manufacturing the same, which can eliminate the doping step and achieve a good ohmic contact, thereby solving the Schottky contact problem.
  • a technical solution adopted by the present invention is to provide a method for manufacturing a TFT switch tube, the method comprising: providing a substrate; and providing a gate layer on the substrate, wherein the gate layer includes an intermediate region and Side regions respectively located on both sides of the intermediate portion; at least a portion of the opposite side regions are thinned along the thickness direction of the gate layer to form two thinned regions, the thickness of the thinned region is smaller than the thickness of the intermediate portion; a semiconductor layer is disposed above the layer; a source layer and a drain layer are disposed on the semiconductor layer, wherein the regions in which the source layer and the drain layer respectively contact the semiconductor layer respectively correspond to the two thinned regions, so that the light of the backlight can pass through the thin layer The region is then irradiated into the semiconductor layer such that an ohmic contact is formed between the semiconductor layer and the source and drain layers.
  • the step of disposing the semiconductor layer above the gate layer further comprises: providing a gate insulating layer on the gate layer.
  • the step of disposing the gate layer on the substrate further comprises: disposing a metal layer on the substrate by physical vapor deposition; performing photolithography, etching, and stripping processes on the metal layer to form a gate layer.
  • the step of thinning at least a portion of the opposite side region along the thickness direction of the gate layer further includes performing photolithography, etching, and stripping processes on at least a portion of the side region to form a thinned region.
  • the material of the semiconductor layer is indium gallium zinc oxide; the step of disposing the semiconductor layer above the gate layer further comprises: disposing an indium gallium zinc oxide layer on the gate insulating layer by physical vapor deposition; The gallium zinc oxide layer is subjected to photolithography, etching, and stripping processes to form a semiconductor layer, and the semiconductor layer is disposed corresponding to the thinned region and the intermediate region.
  • the step of disposing the source layer and the drain layer on the semiconductor layer further includes: disposing a metal layer on the semiconductor layer by physical vapor deposition; performing photolithography, etching, and stripping processes on the metal layer to form a source
  • the electrode layer and the drain layer, and the regions where the source layer and the drain layer are in contact with the semiconductor layer respectively correspond to the two thinned regions.
  • the TFT switch tube includes: a substrate; a gate layer disposed on the substrate, wherein the gate layer includes an intermediate region and a respectively a side region located on both sides of the intermediate portion, at least a portion of the side region being thinned along the thickness direction of the gate layer to form two thinned regions, the thickness of the thinned region being smaller than the thickness of the intermediate portion; the semiconductor layer being disposed at Above the gate layer; the source layer and the drain layer are disposed on the semiconductor layer, wherein the regions in which the source layer and the drain layer respectively contact the semiconductor layer respectively correspond to the two thinned regions, so that the light of the backlight can pass through the thin layer The region is then irradiated into the semiconductor layer such that an ohmic contact is formed between the semiconductor layer and the source and drain layers.
  • the TFT switch tube further includes: a gate insulating layer disposed between the gate layer and the semiconductor layer.
  • the material of the semiconductor layer is indium gallium zinc oxide.
  • a TFT substrate including a TFT switch tube the TFT switch tube includes: a substrate; a gate layer disposed on the substrate, wherein the gate The pole layer includes an intermediate portion and side regions respectively located on both sides of the intermediate portion, and at least a portion of the side regions are thinned along the thickness direction of the gate layer to form two thinned regions, wherein the thickness of the thinned region is smaller than that of the intermediate portion a semiconductor layer disposed above the gate layer; a source layer and a drain layer disposed on the semiconductor layer, wherein the regions in which the source layer and the drain layer respectively contact the semiconductor layer correspond to the two thinned regions respectively, such that The light of the backlight can be irradiated into the semiconductor layer through the thinned region, thereby forming an ohmic contact between the semiconductor layer and the source layer and the drain layer.
  • the TFT switch tube further includes: a gate insulating layer disposed between the gate layer and the semiconductor layer.
  • the material of the semiconductor layer is indium gallium zinc oxide.
  • the manufacturing method of the TFT switch tube of the present invention is specifically: firstly providing a substrate, and then providing a gate layer on the substrate, wherein the gate layer includes an intermediate region and The side regions on the two sides of the intermediate portion are respectively located, and at least a portion of the opposite side regions are thinned along the thickness direction of the gate layer to form two thinned regions, wherein the thickness of the thinned region is smaller than the thickness of the intermediate portion, further A semiconductor layer is disposed above the gate layer, and finally a source layer and a drain layer are disposed on the semiconductor layer, wherein the regions where the source layer and the drain layer respectively contact the semiconductor layer respectively correspond to the two thinned regions, so that the light of the backlight An ohmic contact can be formed between the semiconductor layer and the source layer and the drain layer by being irradiated into the semiconductor layer through the thinned region. Therefore, the present invention only needs to form a doped region by a process such as illumination during the manufacturing process, and does
  • FIG. 1 is a flowchart of a method for manufacturing a TFT switch tube according to an embodiment of the present invention
  • Figure 2 is a process diagram corresponding to the method shown in Figure 1;
  • FIG. 3 is a schematic structural diagram of a TFT switch tube according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a liquid crystal display device according to an embodiment of the present invention.
  • FIG. 1 is a flowchart of a method for manufacturing a TFT switch tube according to an embodiment of the present invention
  • FIG. 2 is a process diagram corresponding to the method shown in FIG.
  • the method of this embodiment includes the following steps:
  • Step S1 providing a substrate 11.
  • the substrate 11 is preferably a glass substrate, and the substrate 11 is cleaned, dried, and the like while the substrate 11 is provided to provide a clean glass substrate.
  • Step S2 A gate layer 120 is disposed on the substrate 11, wherein the gate layer 120 includes an intermediate region 121 and side regions 122 respectively located at two sides of the intermediate region 121.
  • the step is specifically: firstly, a metal layer 12 is disposed on the substrate 11 by physical vapor deposition, and then the metal layer 12 is subjected to photolithography, etching, and stripping processes to form the gate layer 120.
  • the etching process in this step is preferably wet etching, and an etching solution can be selected by using ammonium persulfate, sulfuric acid/chromic acid, sulfuric acid or hydrogen peroxide. Since the cost of the etching solution is low, the method of selecting wet etching in this step can reduce the cost of etching.
  • Step S3 At least a portion of the opposite side region 122 is thinned along the thickness direction of the gate layer 120 to form two thinned regions 123 having a thickness smaller than the thickness of the intermediate portion 121.
  • the ratio of the thickness of the thinned region 123 to the thickness of the intermediate portion 121 is approximately 1:100.
  • the side region 122 is first subjected to photolithography, etching, and stripping processes to form a thinned region 123.
  • the etching process of this step is preferably dry etching.
  • the active group in the plasma formed by the etching gas under the acceleration of the electric field chemically reacts with the material to be corroded to form a volatile substance and is carried away with the gas flow.
  • the etching gas includes a fluorocarbon compound, a fluorinated hydrocarbon, and the like. Since dry etching can accurately control the pattern of etching by controlling the electric field, dry etching can be used in this step to improve the etching precision.
  • Step S4 A semiconductor layer 13 is provided over the gate layer 120.
  • the gate insulating layer 15 is further disposed on the gate layer 120.
  • the material of the semiconductor layer 120 is preferably an indium gallium zinc oxide compound.
  • This step is specifically to provide an indium gallium zinc oxide compound layer on the gate insulating layer 15 by physical vapor deposition.
  • the indium gallium zinc oxide compound layer is then subjected to photolithography, etching, and stripping processes to form a semiconductor layer 13, which is disposed corresponding to the thinned region 123 and the intermediate region 121.
  • the etching process of this step is preferably wet etching.
  • the selection of the etching solution is as described above, and will not be described herein.
  • Step S5 providing a source layer 140 and a drain layer 141 on the semiconductor layer 13, wherein the regions where the source layer 140 and the drain layer 141 are respectively in contact with the semiconductor layer 13 respectively correspond to the two thinned regions 123, so that the light of the backlight
  • the thinned region 123 can be irradiated into the semiconductor layer 13 to form an ohmic contact between the semiconductor layer 13 and the source layer 140 and the drain layer 141.
  • photo-generated carriers are generated after the light is irradiated onto the semiconductor layer 13, and doped regions (N+IGZO) 131 and 133 are formed, so that the semiconductor layer 13 and the source layer 140 and the drain layer 141 have good ohms. Contact to reduce contact impedance.
  • a metal layer 14 is disposed on the semiconductor layer 13 by physical vapor deposition, and then the metal layer 14 is photolithographically, etched, and stripped to form a source layer 140 and a drain layer 141. Further, the regions where the source layer 140 and the drain layer 141 are in contact with the semiconductor layer 13 correspond to the two thinned regions 123, respectively.
  • the etching process of this step is preferably wet etching.
  • the selection of the etching solution is as described above, and will not be described herein.
  • this embodiment it is only necessary to form a doped region by a process such as illumination during the manufacturing process, and no additional doping operation is required, thereby saving manufacturing costs. Further, this embodiment can achieve good ohmic contact, thereby solving the problem of Schottky contact.
  • the present embodiment adopts a combination of dry and wet etching methods, and saves cost while ensuring etching precision.
  • FIG. 3 is a schematic structural diagram of a TFT switch tube according to an embodiment of the present invention.
  • the TFT switch 10 of the present embodiment includes a substrate 11, a gate layer 120, a semiconductor layer 13, a source layer 140, and a drain layer 141.
  • the gate layer 120 is disposed on the substrate 11.
  • the gate layer 120 includes an intermediate region 121 and side regions 122 respectively located at two sides of the intermediate region 121. At least a portion of the side regions 122 are thinned along the thickness direction of the gate layer 120 to form two thinned regions 123.
  • the thickness of the thinned region 123 is smaller than the thickness of the intermediate portion 121. Alternatively, the ratio of the thickness of the thinned region 123 to the thickness of the intermediate portion 121 is approximately 1:100.
  • the semiconductor layer 13 is disposed above the gate layer 120. Further, a gate insulating layer 15 is further disposed between the gate layer 120 and the semiconductor layer 13.
  • the material of the semiconductor layer 13 is preferably an indium gallium zinc oxide compound.
  • the source layer 140 and the drain layer 141 are disposed on the semiconductor layer 13, wherein the regions where the source layer 140 and the drain layer 141 are respectively in contact with the semiconductor layer 13 respectively correspond to the two thinned regions 123, so that the light of the backlight can pass through the thin layer.
  • the region 123 is then irradiated into the semiconductor layer 13, thereby forming an ohmic contact between the semiconductor layer 13 and the source layer 140 and the drain layer 141.
  • photo-generated carriers are generated after the illumination of the semiconductor layer 13 to form doped regions (N+IGZO) 131 and 133, so that the semiconductor layer 13 has good ohmic contact with the source layer 140 and the drain layer 141. , thereby reducing the contact impedance.
  • the embodiment of the present invention further provides a liquid crystal display device.
  • the liquid crystal display device 40 includes a display panel 41 and a backlight module 42 .
  • the backlight module 42 provides a backlight source to the display panel 41 .
  • the display panel 41 further includes a TFT substrate 411, a color filter substrate 412, and a liquid crystal layer 413 between the TFT substrate 411 and the color filter substrate 412.
  • the TFT substrate 411 of the present embodiment is the TFT switch tube 10 described above.
  • this embodiment it is only necessary to form a doped region by a process such as illumination during the manufacturing process, and no additional doping operation is required, thereby saving manufacturing costs. Further, this embodiment can achieve good ohmic contact, thereby solving the problem of Schottky contact.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
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Abstract

公开了一种TFT基板、TFT开关管及其制造方法，该方法包括：在基板（11）上设置栅极层（120）；对栅极层（120）的侧区域（122）的至少一部分沿着栅极层（120）的厚度方向进行薄型化处理，以形成两薄型化区域（123）；在栅极层（120）的上方设置半导体层（13）；在半导体层（13）上设置源极层（140）和漏极层（141），其中源极层（140）和漏极层（141）分别与半导体层（13）接触的区域分别对应两薄型化区域（123）。通过上述方式，能够省去掺杂步骤，并达到良好的欧姆接触，从而解决Schottky接触的问题。

Description

一种TFT基板、TFT开关管及其制造方法
【技术领域】
本发明涉及显示技术领域，尤其是涉及一种TFT基板、TFT开关管及其制造方法。
【背景技术】
基于氧化物半导体的薄膜场效应晶体管(TFT)是未来显示领域的热点，近年来得到了广泛的研究和发展。其中，作为有源沟道层的无定形铟镓锌氧化合物(a-IGZO)薄膜，迁移率可高达80cm2/Vs，而非晶硅（a-Si）的迁移率仅0.5~0.8cm2/Vs。并且a-IGZO可与a-Si大尺寸量产制程兼容。因此，IGZO在下一代液晶显示(LCD)和有机发光二极管(OLED)中具有很大的应用前景。
但是，在金属和IGZO相接触时形成Schottky（肖特基）接触，在接触的界面处半导体能带弯曲，形成势垒。势垒的存在会导致大的界面电阻，即Schottky（肖特基）电阻。Schottky电阻会导致TFT元件开态电流不足，亚阈值摆幅(Subthreshold Swing，SS)过大，元件稳定性下降，从而会影响画面显示品质。
所以，降低金属和IGZO的接触电阻，形成Ohmic（欧姆）接触，是决定半导体元件性能好坏的一个重要因素。现有技术的欧姆接触形成的方法之一是在与金属接触的半导体区域进行重掺杂(n+IGZO)，使得界面的空乏区变窄，电子有更多的机会直穿隧(穿隧效应)。但是现有技术的欧姆接触方式需要额外进行掺杂步骤，从而增加了制作成本。
【发明内容】
本发明主要解决的技术问题是提供一种TFT基板、TFT开关管及其制造方法，能够省去掺杂步骤，并达到良好的欧姆接触，从而解决Schottky接触的问题。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种TFT开关管的制造方法，该方法包括：提供一基板；在基板上设置栅极层，其中，栅极层包括中间区域和分别位于中间区域两侧的侧区域；对侧区域的至少一部分沿着栅极层的厚度方向进行薄型化处理，以形成两薄型化区域，薄型化区域的厚度小于中间区域的厚度；在栅极层的上方设置半导体层；在半导体层上设置源极层和漏极层，其中源极层和漏极层分别与半导体层接触的区域分别对应两薄型化区域，使得背光源的光能够通过薄型化区域后照射到半导体层中，从而使半导体层与源极层和漏极层之间形成欧姆接触。
其中，在栅极层的上方设置半导体层的步骤之前进一步包括：在栅极层上设置栅极绝缘层。
其中，在基板上设置栅极层的步骤进一步包括：通过物理气相沉积的方法在基板上设置一金属层；对金属层进行光刻、蚀刻以及脱膜工艺，以形成栅极层。
其中，对侧区域的至少一部分沿着栅极层的厚度方向进行薄型化处理的步骤进一步包括：对侧区域的至少一部分进行光刻、蚀刻以及脱膜工艺，以形成薄型化区域。
其中，半导体层的材质为铟镓锌氧化合物；在栅极层的上方设置半导体层的步骤进一步包括：通过物理气相沉积的方法在栅极绝缘层上设置一铟镓锌氧化合物层；对铟镓锌氧化合物层进行光刻、蚀刻以及脱膜工艺，以形成半导体层，半导体层对应薄型化区域和中间区域设置。
其中，在半导体层上设置源极层和漏极层的步骤进一步包括：通过物理气相沉积的方法在半导体层上设置一金属层；对金属层进行光刻、蚀刻以及脱膜工艺，以形成源极层和漏极层，并且源极层和漏极层与半导体层接触的区域分别对应两薄型化区域。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种TFT开关管，该TFT开关管包括：基板；栅极层，设置在基板上，其中，栅极层包括中间区域和分别位于中间区域两侧的侧区域，侧区域的至少一部分沿着栅极层的厚度方向进行薄型化处理，以形成两薄型化区域，薄型化区域的厚度小于中间区域的厚度；半导体层，设置在栅极层的上方；源极层和漏极层，设置在半导体层上，其中源极层和漏极层分别与半导体层接触的区域分别对应两薄型化区域，使得背光源的光能够通过薄型化区域后照射到半导体层中，从而使半导体层与源极层和漏极层之间形成欧姆接触。
其中，TFT开关管进一步包括：栅极绝缘层，设置在栅极层和半导体层之间。
其中，半导体层的材质为铟镓锌氧化合物。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种TFT基板，该TFT基板包括TFT开关管，该TFT开关管包括：基板；栅极层，设置在基板上，其中，栅极层包括中间区域和分别位于中间区域两侧的侧区域，侧区域的至少一部分沿着栅极层的厚度方向进行薄型化处理，以形成两薄型化区域，薄型化区域的厚度小于中间区域的厚度；半导体层，设置在栅极层的上方；源极层和漏极层，设置在半导体层上，其中源极层和漏极层分别与半导体层接触的区域分别对应两薄型化区域，使得背光源的光能够通过薄型化区域后照射到半导体层中，从而使半导体层与源极层和漏极层之间形成欧姆接触。
其中，TFT开关管进一步包括：栅极绝缘层，设置在栅极层和半导体层之间。
其中，半导体层的材质为铟镓锌氧化合物。
本发明的有益效果是：区别于现有技术的情况，本发明的TFT开关管的制造方法具体为：首先提供一基板，然后在基板上设置栅极层，其中，栅极层包括中间区域和分别位于中间区域两侧的侧区域，进而对侧区域的至少一部分沿着栅极层的厚度方向进行薄型化处理，以形成两薄型化区域，薄型化区域的厚度小于中间区域的厚度，进一步在栅极层的上方设置半导体层，最后在半导体层上设置源极层和漏极层，其中源极层和漏极层分别与半导体层接触的区域分别对应两薄型化区域，使得背光源的光能够通过薄型化区域后照射到半导体层中，从而使半导体层与源极层和漏极层之间形成欧姆接触。因此，本发明只需要在制造过程中通过光照等工艺就可以形成掺杂区域，不需要额外进行掺杂操作，从而节省制作成本，并能达到良好的欧姆接触，从而解决Schottky接触的问题。
【附图说明】
图1是本发明实施例提供的一种TFT开关管的制造方法的流程图；
图2是对应图1所示的方法的制程图；
图3是本发明实施例提供的一种TFT开关管的结构示意图；
图4是本发明实施例提供的一种液晶显示装置的结构示意图。
【具体实施方式】
请一并参阅图1和图2，图1是本发明实施例提供的一种TFT开关管的制造方法的流程图，图2是对应图1所示的方法的制程图。如图1和图2所示，本实施例的方法包括以下步骤：
步骤S1：提供一基板11。
本步骤中，基板11优选为玻璃基板，在提供基板11的同时对基板11进行清洗、烘干等操作，以提供一干净的玻璃基板。
步骤S2：在基板11上设置栅极层120，其中，栅极层120包括中间区域121和分别位于中间区域121两侧的侧区域122。
本步骤具体为：首先通过物理气相沉积的方法在基板11上设置一金属层12，然后对金属层12进行光刻、蚀刻以及脱膜工艺，以形成栅极层120。
其中，本步骤的蚀刻工艺优选为湿蚀刻，可选择过硫酸铵、硫酸/铬酸、硫酸或双氧水做成蚀刻液。由于蚀刻液的成本较低，因此本步骤选择湿蚀刻的方式可以降低蚀刻的成本。
步骤S3：对侧区域122的至少一部分沿着栅极层120的厚度方向进行薄型化处理，以形成两薄型化区域123，薄型化区域123的厚度小于中间区域121的厚度。可选的，薄型化区域123的厚度与中间区域121的厚度之比大概为1：:100。
本步骤中，具体为首先对侧区域122的至少一部分进行光刻、蚀刻以及脱膜工艺，以形成薄型化区域123。
其中，本步骤的蚀刻工艺优选为干蚀刻。具体而言，利用蚀刻气体在电场加速作用下形成的等离子体中的活性基，与被腐蚀材料发生化学反应，形成挥发性物质并随着气流带走。其中，蚀刻气体包括氟碳化合物、氟化的碳氢化合物等。由于干蚀刻可以通过控制电场来准确控制蚀刻的图形，因此本步骤采用干蚀刻可以提高蚀刻的精度。
步骤S4：在栅极层120的上方设置半导体层13。
在本步骤之前，还包括在栅极层120上设置栅极绝缘层15。
其中，半导体层120的材质优选为铟镓锌氧化合物。本步骤具体为通过物理气相沉积的方法在栅极绝缘层15上设置一铟镓锌氧化合物层。然后对铟镓锌氧化合物层进行光刻、蚀刻以及脱膜工艺，以形成半导体层13，半导体层13对应薄型化区域123和中间区域121设置。
其中，本步骤的蚀刻工艺优选为湿蚀刻。蚀刻液的选择如前文所述，在此不再赘述。
步骤S5：在半导体层13上设置源极层140和漏极层141，其中源极层140和漏极层141分别与半导体层13接触的区域分别对应两薄型化区域123，使得背光源的光能够通过薄型化区域123后照射到半导体层13中，从而使半导体层13与源极层140和漏极层141之间形成欧姆接触。如图2所示，光照照射到半导体层13后产生光生载流子，形成掺杂区域（N+IGZO）131和133，使得半导体层13与源极层140和漏极层141有良好的欧姆接触，从而降低接触阻抗。
本步骤中，具体为通过物理气相沉积的方法在半导体层13上设置一金属层14，然后对金属层14进行光刻、蚀刻以及脱膜工艺，以形成源极层140和漏极层141，并且源极层140和漏极层141与半导体层13接触的区域分别对应两薄型化区域123。
其中，本步骤的蚀刻工艺优选为湿蚀刻。蚀刻液的选择如前文所述，在此不再赘述。
因此，本实施例只需要在制造过程中通过光照等工艺就可以形成掺杂区域，不需要额外进行掺杂操作，从而节省制作成本。进一步的，本实施例可以达到良好的欧姆接触，从而解决Schottky接触的问题。
更进一步的，本实施例采用干、湿蚀刻方法的结合，在既保证了蚀刻精度的前提下，还节省了成本。
本发明实施例还提供了一种TFT开关管，该TFT开关管通过前文所述的方法制造而成。具体请参阅图3，图3是本发明实施例提供的一种TFT开关管的结构示意图。
如图3所示，本实施例的TFT开关管10包括基板11、栅极层120、半导体层13、源极层140和漏极层141。
其中，栅极层120设置在基板11上。其中，栅极层120包括中间区域121和分别位于中间区域121两侧的侧区域122，侧区域122的至少一部分沿着栅极层120的厚度方向进行薄型化处理，以形成两薄型化区域123，薄型化区域123的厚度小于中间区域121的厚度。可选的，薄型化区域123的厚度与中间区域121的厚度之比大概为1：100。
半导体层13设置在栅极层120的上方。进一步的，在栅极层120和半导体层13之间还设置有一栅极绝缘层15。本实施例中，半导体层13的材质优选为铟镓锌氧化合物。
源极层140和漏极层141设置在半导体层13上，其中源极层140和漏极层141分别与半导体层13接触的区域分别对应两薄型化区域123，使得背光源的光能够通过薄型化区域123后照射到半导体层13中，从而使半导体层13与源极层140和漏极层141之间形成欧姆接触。如图所示，光照照射到半导体层13后产生光生载流子，形成掺杂区域（N+IGZO）131和133，使得半导体层13与源极层140和漏极层141有良好的欧姆接触，从而降低接触阻抗。
本发明实施例还提供一种液晶显示装置，如图4所示，液晶显示装置40包括显示面板41和背光模组42，背光模组42向显示面板41提供背光光源。其中显示面板41进一步包括相对设置的TFT基板411、彩膜基板412以及TFT基板411和彩膜基板412之间的液晶层413。本实施例的TFT基板411为前文所述的TFT开关管10。
因此，本实施例只需要在制造过程中通过光照等工艺就可以形成掺杂区域，不需要额外进行掺杂操作，从而节省制作成本。进一步的，本实施例可以达到良好的欧姆接触，从而解决Schottky接触的问题。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (12)

  1. 一种TFT开关管的制造方法，其中，所述方法包括：
    提供一基板；
    在所述基板上设置栅极层，其中，所述栅极层包括中间区域和分别位于所述中间区域两侧的侧区域；
    对所述侧区域的至少一部分沿着所述栅极层的厚度方向进行薄型化处理，以形成两薄型化区域，所述薄型化区域的厚度小于所述中间区域的厚度；
    在所述栅极层的上方设置半导体层；
    在所述半导体层上设置源极层和漏极层，其中所述源极层和漏极层分别与所述半导体层接触的区域分别对应两所述薄型化区域，使得背光源的光能够通过所述薄型化区域后照射到所述半导体层中，从而使所述半导体层与所述源极层和漏极层之间形成欧姆接触。
  2. 根据权利要求1所述的方法，其中，所述在所述栅极层的上方设置半导体层的步骤之前进一步包括：
    在所述栅极层上设置栅极绝缘层。
  3. 根据权利要求1所述的方法，其中，在所述基板上设置栅极层的步骤进一步包括：
    通过物理气相沉积的方法在所述基板上设置一金属层；
    对所述金属层进行光刻、蚀刻以及脱膜工艺，以形成所述栅极层。
  4. 根据权利要求1所述的方法，其中，所述对所述侧区域的至少一部分沿着所述栅极层的厚度方向进行薄型化处理的步骤进一步包括：
    对所述侧区域的至少一部分进行光刻、蚀刻以及脱膜工艺，以形成所述薄型化区域。
  5. 根据权利要求2所述的方法，其中，所述半导体层的材质为铟镓锌氧化合物；
    所述在所述栅极层的上方设置半导体层的步骤进一步包括：
    通过物理气相沉积的方法在所述栅极绝缘层上设置一铟镓锌氧化合物层；
    对所述铟镓锌氧化合物层进行光刻、蚀刻以及脱膜工艺，以形成所述半导体层，所述半导体层对应所述薄型化区域和中间区域设置。
  6. 根据权利要求1所述的方法，其中，所述在所述半导体层上设置源极层和漏极层的步骤进一步包括：
    通过物理气相沉积的方法在所述半导体层上设置一金属层；
    对所述金属层进行光刻、蚀刻以及脱膜工艺，以形成所述源极层和漏极层，并且所述源极层和所述漏极层与所述半导体层接触的区域分别对应两所述薄型化区域。
  7. 一种TFT开关管，其中，所述TFT开关管包括：
    基板；
    栅极层，设置在所述基板上，其中，所述栅极层包括中间区域和分别位于所述中间区域两侧的侧区域，所述侧区域的至少一部分沿着所述栅极层的厚度方向进行薄型化处理，以形成两薄型化区域，所述薄型化区域的厚度小于所述中间区域的厚度；
    半导体层，设置在所述栅极层的上方；
    源极层和漏极层，设置在所述半导体层上，其中所述源极层和漏极层分别与所述半导体层接触的区域分别对应两所述薄型化区域，使得背光源的光能够通过所述薄型化区域后照射到所述半导体层中，从而使所述半导体层与所述源极层和漏极层之间形成欧姆接触。
  8. 根据权利要求7所述的TFT开关管，其中，所述TFT开关管进一步包括：
    栅极绝缘层，设置在所述栅极层和所述半导体层之间。
  9. 根据权利要求7所述的TFT开关管，其中，所述半导体层的材质为铟镓锌氧化合物。
  10. 一种TFT基板，其中，所述TFT基板包括TFT开关管，所述TFT开关管包括：
    基板；
    栅极层，设置在所述基板上，其中，所述栅极层包括中间区域和分别位于所述中间区域两侧的侧区域，所述侧区域的至少一部分沿着所述栅极层的厚度方向进行薄型化处理，以形成两薄型化区域，所述薄型化区域的厚度小于所述中间区域的厚度；
    半导体层，设置在所述栅极层的上方；
    源极层和漏极层，设置在所述半导体层上，其中所述源极层和漏极层分别与所述半导体层接触的区域分别对应两所述薄型化区域，使得背光源的光能够通过所述薄型化区域后照射到所述半导体层中，从而使所述半导体层与所述源极层和漏极层之间形成欧姆接触。
  11. 根据权利要求10所述的TFT基板，其中，所述TFT开关管进一步包括：
    栅极绝缘层，设置在所述栅极层和所述半导体层之间。
  12. 根据权利要求10所述的TFT基板，其中，所述半导体层的材质为铟镓锌氧化合物。
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