WO2017046673A1 - Électrode et procédé de fabrication de dispositif à semi-conducteur - Google Patents

Électrode et procédé de fabrication de dispositif à semi-conducteur Download PDF

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Publication number
WO2017046673A1
WO2017046673A1 PCT/IB2016/055295 IB2016055295W WO2017046673A1 WO 2017046673 A1 WO2017046673 A1 WO 2017046673A1 IB 2016055295 W IB2016055295 W IB 2016055295W WO 2017046673 A1 WO2017046673 A1 WO 2017046673A1
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Prior art keywords
insulator
conductor
transistor
semiconductor
electrode
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PCT/IB2016/055295
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English (en)
Japanese (ja)
Inventor
笹川慎也
栃林克明
飯田裕太
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株式会社半導体エネルギー研究所
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Publication of WO2017046673A1 publication Critical patent/WO2017046673A1/fr

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Definitions

  • the present invention relates to, for example, a transistor and a semiconductor device, and a manufacturing method thereof.
  • the present invention relates to, for example, a display device, a light-emitting device, a lighting device, a power storage device, a storage device, a processor, and an electronic device.
  • the present invention relates to a method for manufacturing a display device, a liquid crystal display device, a light-emitting device, a memory device, and an electronic device.
  • the present invention relates to a driving method of a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a memory device, or an electronic device.
  • one embodiment of the present invention is not limited to the above technical field.
  • the technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • a display device, a light-emitting device, a lighting device, an electro-optical device, a semiconductor circuit, and an electronic device may include a semiconductor device.
  • An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a semiconductor of a transistor included in a large display device.
  • a transistor including an oxide semiconductor can be used by improving part of a production facility for a transistor using amorphous silicon, and thus has an advantage of suppressing capital investment.
  • a transistor using an oxide semiconductor is known to have extremely small leakage current in a non-conduction state.
  • a low power consumption CPU using a characteristic in which a transistor including an oxide semiconductor has low leakage current is disclosed (see Patent Document 1).
  • Patent Document 2 a method in which a transistor using an oxide film semiconductor is formed by embedding a gate electrode in an opening is disclosed (see Patent Document 2 and Patent Document 3).
  • An object is to provide a fine transistor. Another object is to provide a transistor with low parasitic capacitance. Another object is to provide a transistor with high frequency characteristics. Another object is to provide a transistor with favorable electrical characteristics. Another object is to provide a transistor with stable electrical characteristics. Another object is to provide a transistor with a large on-state current. Another object is to provide a transistor with a low off-state current. Another object is to provide a novel transistor. Another object is to provide a semiconductor device including the transistor. Another object is to provide a semiconductor device with high operating speed. Another object is to provide a highly integrated semiconductor device. Another object is to provide a novel semiconductor device. Another object is to provide a module including the semiconductor device. Another object is to provide an electronic device including the semiconductor device or the module.
  • an insulating layer is formed over the first conductive layer, a mask layer is formed over the insulating layer, a resist mask is formed over the mask layer by a lithography method, and the resist mask is formed on a side surface of the resist mask.
  • a product is formed, an opening is formed in the mask layer by etching the mask layer using the resist mask and the product as an etching mask, and the insulating layer is formed as a first conductive layer using the mask layer as an etching mask.
  • An electrode manufacturing method is characterized by forming an opening in an insulating layer by etching until reaching the upper surface of the layer, and forming a second conductive layer in the opening.
  • One embodiment of the present invention is the method for manufacturing an electrode according to (1), in which the product is formed by plasma treatment using a gas containing carbon and fluorine.
  • One embodiment of the present invention is the method for manufacturing an electrode according to (1) or (2), in which the first conductive layer is a conductor containing tungsten.
  • the insulating layer is formed by forming a first insulator, forming a first metal oxide over the first insulator, and forming a second metal over the first metal oxide.
  • An insulator is formed, a second metal oxide is formed on the second insulator, a third insulator is formed on the second metal oxide, and the third insulator is formed on the third insulator.
  • a fourth insulator is formed, a third metal oxide is formed on the fourth insulator, and a fifth insulator is formed on the third metal oxide.
  • One embodiment of the present invention is the electrode manufacturing method according to (4), in which the first metal oxide is a metal oxide containing hafnium.
  • the second metal oxide and the third metal oxide are metal oxides containing aluminum. is there.
  • the first insulator is formed, the second insulator is formed over the first insulator, and the first metal oxide is formed over the second insulator.
  • One embodiment of the present invention is the method for manufacturing an electrode according to (7), wherein the first metal oxide is a metal oxide containing aluminum.
  • the insulating layer is formed by forming a first insulator, forming a first metal oxide over the first insulator, and forming a second metal over the first metal oxide.
  • One embodiment of the present invention is the method for manufacturing an electrode according to (9), in which the first metal oxide is a metal oxide containing aluminum.
  • One embodiment of the present invention is a method for manufacturing a semiconductor device, in which the semiconductor device includes a wiring layer and a transistor, the transistor includes a source electrode, a drain electrode, and a gate electrode, and the wiring layer includes a source electrode, It is electrically connected to the drain electrode or the gate electrode through a plug electrode, and the plug electrode is manufactured by using the electrode manufacturing method according to any one of (1) to (10).
  • This is a method for manufacturing a semiconductor device.
  • One embodiment of the present invention is a method for manufacturing a module, wherein the module is an electrode manufactured using the method for manufacturing an electrode according to any one of (1) to (10), or (11).
  • a method for manufacturing a module comprising: a semiconductor device manufactured using the method for manufacturing a semiconductor device; and a printed circuit board.
  • One embodiment of the present invention is a method for manufacturing an electronic device, and the electronic device includes an electrode manufactured using the method for manufacturing an electrode according to any one of (1) to (10), and (11)
  • An electronic device comprising: a semiconductor device manufactured using the method for manufacturing a semiconductor device described above; or a module manufactured using the method for manufacturing a module described in (12); and a speaker or an operation key. This is a manufacturing method.
  • the oxide semiconductor may be replaced with another semiconductor.
  • a fine transistor can be provided.
  • a transistor with low parasitic capacitance can be provided.
  • a transistor with high frequency characteristics can be provided.
  • a transistor with favorable electrical characteristics can be provided.
  • a transistor with stable electric characteristics can be provided.
  • a transistor with a large on-state current can be provided.
  • a transistor with low off-state current can be provided.
  • a novel transistor can be provided.
  • a semiconductor device including the transistor can be provided.
  • a semiconductor device with high operating speed can be provided.
  • a highly integrated semiconductor device can be provided.
  • a novel semiconductor device can be provided.
  • a module including the semiconductor device can be provided.
  • an electronic device including the semiconductor device or the module can be provided.
  • FIG. 14 is a cross-sectional view of a device including an electrode according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a method for manufacturing an electrode according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a method for manufacturing an electrode according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a method for manufacturing an electrode according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a method for manufacturing an electrode according to one embodiment of the present invention.
  • 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention.
  • 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention.
  • 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention.
  • 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention.
  • 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a transistor according to one embodiment of the present invention.
  • FIGS. Sectional TEM image of CAAC-OS, planar TEM image and image analysis image thereof.
  • FIG. 6 shows changes in crystal parts of an In—Ga—Zn oxide due to electron irradiation.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • 4A to 4C are a top view and cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention.
  • FIG. 10 is a circuit diagram of a memory device according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 10 is a circuit diagram of a memory device according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • 6A and 6B are a circuit diagram and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • FIG. 10 is a block diagram illustrating a CPU according to one embodiment of the present invention.
  • FIG. 10 is a circuit diagram of a memory element according to one embodiment of the present invention.
  • the top view which shows an imaging device.
  • the top view which shows the pixel of an imaging device.
  • Sectional drawing which shows an imaging device.
  • FIG. 6 illustrates a configuration example of an RF tag.
  • 4A and 4B are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • 6A and 6B are a circuit diagram and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention.
  • 4A and 4B are a block diagram, a circuit diagram, and a waveform diagram for illustrating one embodiment of the present invention.
  • 6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating one embodiment of the present invention.
  • FIG. 14 illustrates an electronic device according to one embodiment of the present invention.
  • FIG. 14 illustrates an electronic device according to one embodiment of the present invention.
  • FIG. 14 illustrates an electronic device according to one embodiment of the present invention.
  • 6 illustrates an example of using an RF tag according to one embodiment of the present invention.
  • the cross-sectional SEM image of an Example The cross-sectional SEM image of an Example.
  • the cross-sectional SEM image of an Example. The cross-sectional SEM image of an Example.
  • the shape of an object is defined by “diameter”, “particle diameter”, “size”, “size”, “width”, etc., the length of one side in the smallest cube in which the object fits Alternatively, it may be read as the equivalent circle diameter in one cross section of the object.
  • the equivalent circle diameter in one cross section of an object refers to the diameter of a perfect circle having an area equal to that of one cross section of the object.
  • a voltage often indicates a potential difference between a certain potential and a reference potential (for example, a ground potential (GND) or a source potential).
  • a reference potential for example, a ground potential (GND) or a source potential.
  • a voltage can be rephrased as a potential.
  • the impurity of the semiconductor means, for example, a component other than the main component constituting the semiconductor.
  • an element having a concentration of less than 0.1 atomic% is an impurity.
  • impurities for example, semiconductor DOS (Density of State) may be formed, carrier mobility may be reduced, and crystallinity may be reduced.
  • examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component.
  • hydrogen also included in water
  • lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like are examples of impurities that change the characteristics of the semiconductor.
  • oxygen vacancies may be formed by mixing impurities such as hydrogen, for example.
  • impurities such as hydrogen, for example.
  • examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.
  • the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed
  • the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
  • the channel width is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a source and a drain in a region where a channel is formed. This is the length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
  • the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, apparent channel width). May be different).
  • the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible.
  • the ratio of the channel region formed on the side surface of the semiconductor may be large. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.
  • an apparent channel width which is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is expressed as “enclosed channel width ( SCW: Surrounded Channel Width).
  • SCW Surrounded Channel Width
  • channel width in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width.
  • channel width in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by obtaining a cross-sectional TEM image and analyzing the image. it can.
  • the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.
  • A when A is described as having a shape protruding from B, in a top view or a cross-sectional view, it indicates that at least one end of A has a shape that is outside of at least one end of B. There is a case. Therefore, when it is described that A has a shape protruding from B, for example, in a top view, it can be read that one end of A has a shape outside of one end of B.
  • parallel refers to a state in which two straight lines are arranged at an angle of ⁇ 10 ° to 10 °. Therefore, the case of ⁇ 5 ° to 5 ° is also included.
  • substantially parallel means a state in which two straight lines are arranged at an angle of ⁇ 30 ° to 30 °.
  • Vertical refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.
  • substantially vertical means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.
  • FIG. 1 is a cross-sectional view of an apparatus including an electrode according to one embodiment of the present invention.
  • the conductive layer 110 over the insulating layer 105, the insulating layer 160 over the conductive layer 110, and the insulating layer 160 have openings, and the conductive layers 170 and 172 are disposed in the openings. Electrode.
  • the insulating layer 105 is formed.
  • the insulating layer 105 can be formed over the substrate, the conductive layer, or the semiconductor device.
  • the insulating layer 105 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an atomic layer.
  • the deposition can be performed using an ALD (Atomic Layer Deposition) method or the like.
  • the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like.
  • PECVD Plasma Enhanced CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal Organic CVD
  • the thermal CVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used.
  • a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma.
  • a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge.
  • plasma damage during film formation does not occur, so that a film with few defects can be obtained.
  • the ALD method is also a film forming method that can reduce plasma damage to an object to be processed.
  • the ALD method does not cause plasma damage during film formation, a film with few defects can be obtained.
  • the CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio.
  • the ALD method since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.
  • the composition of the obtained film can be controlled by the flow rate ratio of the source gases.
  • a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases.
  • a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film.
  • metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon oxide, silicon oxynitride, nitriding oxide Silicon or silicon nitride may be used. Further, the insulating layer 105 may be a multilayer film by appropriately forming one or more insulators as described above.
  • a conductive layer 110 is formed over the insulating layer 105.
  • the conductive layer 110 tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used.
  • the conductive layer 110 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that the conductive layer 110 may be formed using a lithography method.
  • the insulating layer 115 is formed over the conductive layer 110.
  • the insulating layer 115 can be formed by a method similar to that for the insulating layer 105.
  • metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon oxide, silicon oxynitride, Silicon nitride oxide, silicon nitride, or the like may be used.
  • the insulating layer 115 may be a multilayer film formed by appropriately selecting one or more insulators from the above.
  • the first mask layer 120 is formed over the insulating layer 115.
  • the first mask layer tantalum nitride, tungsten nitride, titanium nitride, tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum tungsten alloy, or the like can be used.
  • the first mask layer 120 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a second mask layer 125 is formed over the first mask layer 120.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like may be used.
  • the second mask layer can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 2A).
  • an organic film 130 is formed on the second mask layer 125 by using a coating method or the like.
  • a resist 135 is applied over the organic film 130 by a coating method or the like (see FIG. 2B).
  • the organic film 130 may improve the adhesion between the second mask layer 125 and the resist 135 through the organic film 130.
  • the organic film 130 may not be used.
  • a resist mask 140 having openings is formed using a lithography method.
  • the dimension of the opening of the resist mask 140 is expressed as a dimension 140S (see FIG. 3A).
  • a resist is exposed through a mask.
  • a resist mask is formed by removing or leaving the exposed region using a developer.
  • a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask.
  • the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
  • an immersion technique may be used in which exposure is performed by filling a liquid (for example, water) between the substrate and the projection lens.
  • an electron beam or an ion beam may be used.
  • a mask is not necessary when an electron beam or an ion beam is used.
  • the resist mask is removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process in addition to the dry etching process, or performing a dry etching process in addition to the wet etching process. be able to.
  • a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used as the dry etching apparatus.
  • the capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes.
  • a configuration in which a plurality of different high-frequency power supplies are applied to one electrode of the parallel plate electrode may be employed.
  • mold electrode may be sufficient.
  • mold electrode may be sufficient.
  • a dry etching apparatus having a high-density plasma source can be used.
  • an inductively coupled plasma (ICP) etching apparatus can be used as the dry etching apparatus having a high-density plasma source.
  • the product 137 is preferably a product containing carbon and fluorine.
  • the product 137 By forming the product 137 on the side surface of the resist mask 140 and the side surface of the organic material film 145, it is possible to form an opening that is reduced by the film thickness of the product 137 formed on the side surface from the dimension 140S of the opening. .
  • the dimension of the reduced opening is represented as dimension 145S.
  • the above dry etching apparatus is preferably used.
  • the gas used for the plasma treatment for example, C 4 F 6 gas, C 2 F 6 gas, C 4 F 8 gas, CF 4 gas, SF 6 gas, CHF 3 gas, or the like may be used alone or in combination of two or more gases. Can be used.
  • oxygen gas, helium gas, argon gas, hydrogen gas, or the like can be appropriately added to the above gas.
  • a gas capable of generating a product containing carbon and fluorine by a plasma containing carbon and fluorine for example, it is preferable to use a gas in which helium gas, argon gas, hydrogen gas, or the like is appropriately added to any one of C 4 F 6 gas, C 4 F 8 gas, or CHF 3 gas.
  • the second mask layer 125 and the first mask layer 120 are etched using the resist mask 140, the organic material film 145, and the product 137 as an etching mask, and the second mask layer 150 and the first mask layer 155 are formed.
  • the resist mask 140, the organic film 145, and the product 137 are etched and disappeared during the etching of the second mask layer 125 and the first mask layer 120.
  • a dimension of the bottom portion of the first mask layer 155 is represented as a dimension 155S (see FIG. 4A).
  • the insulating layer 115 is etched until it reaches the upper surface of the conductive layer 110, so that the insulating layer 160 having an opening is formed.
  • the second mask layer 150 is etched and thinned. Or it may disappear.
  • the size 160S of the bottom of the opening of the insulating layer 160 is smaller than the size 155s of the bottom of the mask layer 155 (see FIG. 4B).
  • the conductive layer 165 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive layer 165 is formed so as to fill the opening formed in the insulating layer 160. Therefore, it is preferable to use the CVD method (particularly the MCVD method).
  • the conductive layer 165 is a multilayer of a conductor formed by the ALD method and a conductor formed by the MCVD method.
  • a film may be preferable.
  • titanium nitride may be formed by an ALD method, and then tungsten may be formed by an MCVD method (see FIG. 5).
  • CMP chemical mechanical polishing
  • FIG. 6A to 6C are a top view and cross-sectional views of a semiconductor device according to one embodiment of the present invention.
  • FIG. 6A is a top view.
  • 6B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 illustrated in FIG.
  • FIG. 6C is a cross-sectional view corresponding to the dashed-dotted line A3-A4 illustrated in FIG. Note that in the top view of FIG. 6A, some elements are omitted for clarity.
  • this transistor includes an insulator 401 over a substrate 400 and an insulator 301 over the insulator 401.
  • the insulator 301 has an opening, and the conductor 310a and the conductor 310b are disposed in the opening.
  • this transistor includes the insulator 302 over the insulator 301 and the conductors 310a and 310b, the insulator 303 over the insulator 302, the insulator 402 over the insulator 303, and the insulator 402.
  • a conductor 433 is embedded in the first opening
  • a conductor 431 is embedded in the second opening
  • a conductor 429 is embedded in the third opening
  • a conductor is formed in the fourth opening.
  • a conductor 437 is embedded.
  • this transistor includes a conductor 434 having a region in contact with the conductor 433 over the insulator 410, a conductor 432 having a region in contact with the conductor 431 over the insulator 410, and a conductor 429 over the insulator 410.
  • a conductor 430 having a region in contact with the conductor 410 and a conductor 438 having a region in contact with the conductor 437 over the insulator 410.
  • the semiconductor 406b includes a region 407 in contact with the upper surface of the semiconductor 406b and the conductors 416a1 and 416a2.
  • the conductor 404 functions as a first gate electrode.
  • the conductor 404 can have a stacked structure with a conductor having a function of suppressing permeation of oxygen. For example, an increase in electric resistance due to oxidation of the conductor 404 can be prevented by forming a conductor having a function of suppressing oxygen permeation as a lower layer.
  • the insulator 412 functions as a gate insulator.
  • the conductors 416a1 and 416a2 each have a function as a source electrode or a drain electrode.
  • the conductors 416a1 and 416a2 can have a stacked structure with a conductor having a function of suppressing permeation of oxygen. For example, by forming a conductor having a function of suppressing permeation of oxygen as an upper layer, an increase in electrical resistance due to oxidation of the conductors 416a1 and 416a2 can be prevented. Note that the electrical resistance value of the conductor can be measured using a two-terminal method or the like.
  • the resistance of the semiconductor 406b can be controlled by a potential applied to the conductor 404. That is, conduction / non-conduction between the conductor 416a1 and the conductor 416a2 can be controlled by a potential applied to the conductor 404.
  • the upper surface of the semiconductor 406b is in contact with the conductor 416a1 and the conductor 416a2.
  • the insulator 406a and the semiconductor 406b can be electrically surrounded by an electric field of the conductor 404 functioning as a gate electrode.
  • a structure of a transistor that electrically surrounds a semiconductor by an electric field of a gate electrode is referred to as a surrounded channel (s-channel) structure. Therefore, a channel may be formed in the entire semiconductor 406b.
  • a large current can flow between the source and the drain of the transistor, and a current (ON current) at the time of conduction can be increased.
  • the insulator 406a and the semiconductor 406b are surrounded by the electric field of the conductor 404, current during non-conduction (off-state current) can be reduced.
  • the conductor 310a functions as a second gate electrode.
  • the conductor 310a can have a stacked structure with a conductive film having a function of suppressing permeation of oxygen. For example, a decrease in conductivity due to oxidation of the conductor 310a can be prevented by forming a conductor having a function of suppressing oxygen permeation as a lower layer.
  • the insulator 302, the insulator 303, and the insulator 402 have a function as a gate insulating film.
  • the threshold voltage of this transistor can be controlled by the potential applied to the conductor 310a. Further, the threshold voltage of this transistor can be controlled by injecting electrons into the insulator 303 by a potential applied to the conductor 310a. Further, by electrically connecting the first gate electrode and the second gate electrode, a current (ON current) at the time of conduction can be increased. Note that the function of the first gate electrode and the function of the second gate electrode may be interchanged.
  • FIG. 12A illustrates an example in which the first gate electrode and the second gate electrode are electrically connected.
  • a conductor 440 is embedded in an opening reaching the conductor 404 through the insulator 410, and the upper surface of the conductor 440 and the conductor 444 formed on the insulator 410 are electrically connected.
  • a conductor 442 is embedded in an opening reaching the conductor 310c through the insulator 410, the insulator 408, the insulator 412, the insulator 406c, the insulator 402, the insulator 303, and the insulator 302.
  • the upper surface of the conductor 442 and the conductor 444 are electrically connected. That is, the conductor 404 having a function as the first gate electrode is electrically connected to the conductor 310c having a function as the second gate electrode through the conductor 440, the conductor 444, and the conductor 442.
  • an insulator having a function of blocking impurities such as hydrogen and oxygen By surrounding the transistor with an insulator having a function of blocking impurities such as hydrogen and oxygen, electrical characteristics of the transistor can be stabilized.
  • an insulator having a function of blocking impurities such as hydrogen and oxygen may be used as the insulator 408 as the insulator 408, an insulator having a function of blocking impurities such as hydrogen and oxygen may be used as the insulator 408
  • Examples of the insulator having a function of blocking impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, and lanthanum.
  • An insulator containing neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.
  • the insulator 408 includes a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride oxide, or nitride Silicon or the like may be used.
  • the insulator 408 preferably includes aluminum oxide.
  • oxygen can be added to the insulator 412 serving as a base layer of the insulator 408. The added oxygen becomes excess oxygen in the insulator 412.
  • the insulator 408 includes aluminum oxide, entry of impurities such as hydrogen into the semiconductor 406b can be suppressed.
  • the insulator 408 includes aluminum oxide, outward diffusion of excess oxygen added to the insulator 412 can be reduced.
  • the insulator 401 aluminum oxide, magnesium oxide, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide may be used.
  • the insulator 401 preferably includes aluminum oxide or silicon nitride.
  • the insulator 401 includes aluminum oxide or silicon nitride, entry of impurities such as hydrogen into the semiconductor 406b can be suppressed.
  • the insulator 401 includes aluminum oxide or silicon nitride, outward diffusion of oxygen can be reduced.
  • the insulator 301 for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum is used. Or a single layer or a stacked layer.
  • the insulator 301 preferably includes silicon oxide or silicon oxynitride.
  • the insulator 303 for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum or
  • the metal oxide film may be used as a single layer or a stacked layer.
  • the insulator 303 preferably includes silicon nitride, hafnium oxide, or aluminum oxide.
  • Examples of the insulator 302 and the insulator 402 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.
  • the insulating material may be used as a single layer or a stacked layer.
  • the insulator 402 preferably includes silicon oxide or silicon oxynitride.
  • the insulator 410 preferably includes an insulator having a low relative dielectric constant.
  • the insulator 410 includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having a hole Or it is preferable to have resin etc.
  • the insulator 410 is formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having a hole And a laminated structure of resin.
  • silicon oxide and silicon oxynitride are thermally stable, a laminated structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon.
  • the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
  • the insulator 412 for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum is used. Or a single layer or a stacked layer.
  • the insulator 412 preferably includes silicon oxide or silicon oxynitride.
  • the insulator 412 preferably includes an insulator having a high relative dielectric constant.
  • the insulator 412 includes gallium oxide, hafnium oxide, an oxide including aluminum and hafnium, an oxynitride including aluminum and hafnium, an oxide including silicon and hafnium, or an oxynitride including silicon and hafnium. It is preferable.
  • the insulator 412 preferably has a stacked structure of silicon oxide or silicon oxynitride and an insulator with a high relative dielectric constant. Since silicon oxide and silicon oxynitride are thermally stable, a stacked structure having high thermal stability and high relative dielectric constant can be obtained by combining with an insulator having high relative dielectric constant.
  • a trap center may be formed at the interface between aluminum oxide, gallium oxide, or hafnium oxide and silicon oxide or silicon oxynitride. .
  • the trap center can change the threshold voltage of the transistor in the positive direction by capturing electrons.
  • Examples of the conductor 416a1 and the conductor 416a2 include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium,
  • a conductor including one or more of platinum, silver, indium, tin, tantalum, and tungsten may be used as a single layer or a stacked layer.
  • an alloy film or a compound film may be used.
  • a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, or titanium and nitrogen A conductive material or the like may be used.
  • Conductor 310a, conductor 310b, conductor 310c, conductor 404, conductor 429, conductor 430, conductor 431, conductor 432, conductor 433, conductor 434, conductor 437, conductor 438, conductor 440, conductor 442, and conductor 444 include, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum
  • a conductor containing one or more of ruthenium, silver, indium, tin, tantalum, and tungsten may be used in a single layer or a stacked layer.
  • an alloy film or a compound film may be used.
  • a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, or titanium and nitrogen A conductive material or the like may be used.
  • An oxide semiconductor is preferably used as the semiconductor 406b.
  • silicon including strained silicon
  • germanium silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like may be used.
  • an oxide including one or more elements other than oxygen included in the semiconductor 406b or two or more elements is preferably used.
  • silicon including strained silicon
  • germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like may be used.
  • FIGS. 7A, 7B, and 7C are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 7A is a top view.
  • FIG. 7B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 illustrated in FIG.
  • FIG. 7C is a cross-sectional view corresponding to the dashed-dotted line A3-A4 illustrated in FIG. Note that in the top view of FIG. 7A, some elements are omitted for clarity.
  • a conductor 404 that functions as a gate electrode, and a conductor 416a1 that functions as a source electrode or 416a2 that functions as a drain electrode A difference from the structure of the transistor illustrated in FIGS. 6A and 6B is that there is no overlapping region.
  • the conductor 404 functioning as a gate electrode and the conductor 416a1 functioning as a source electrode or 416a2 functioning as a drain electrode have a function as a gate electrode by having no overlapping region.
  • a parasitic capacitance between the conductor 404 and the conductor 416a1 functioning as a source electrode or 416a2 functioning as a drain electrode can be reduced, which is preferable for high-speed operation of the transistor. Further, current leakage between the conductor 404 functioning as a gate electrode and the conductor 416a1 functioning as a source electrode or 416a2 functioning as a drain electrode can be prevented.
  • the other configurations are referred to above.
  • FIGS. 8A, 8B, and 8C are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 8A is a top view.
  • FIG. 8B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 illustrated in FIG.
  • FIG. 8C is a cross-sectional view corresponding to the dashed-dotted line A3-A4 illustrated in FIG. Note that in the top view of FIG. 8A, some elements are omitted for clarity.
  • the conductor 416a1 having a function as a source electrode or the conductor 416a2 having a function as a drain electrode is not provided, and the function as a source region is not provided.
  • An opening that reaches the insulator 406a through the insulator 410, the insulator 408, the insulator 412, the region 407a1, and the semiconductor 406b; the insulator 410; 6A and 6B show an opening that reaches the insulator 406a through the body 408, the insulator 412, the region 407a2, and the semiconductor 406b, and that the insulator 412 and the insulator 406c are formed along the side surface of the conductor 404. This is different from the structure of the transistor shown. The other configurations are referred to above.
  • FIGS. 9A, 9B, and 9C are a top view and cross-sectional views of a semiconductor device according to one embodiment of the present invention.
  • FIG. 9A is a top view.
  • FIG. 9B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 illustrated in FIG.
  • FIG. 9C is a cross-sectional view corresponding to the dashed-dotted line A3-A4 illustrated in FIG. Note that in the top view of FIG. 9A, some elements are omitted for clarity.
  • this transistor includes an insulator 401 over a substrate 400 and an insulator 301 over the insulator 401.
  • the insulator 301 has an opening, and the conductor 310a and the conductor 310b are disposed in the opening.
  • this transistor includes the insulator 302 over the insulator 301 and the conductors 310a and 310b, the insulator 303 over the insulator 302, the insulator 402 over the insulator 303, and the insulator 402.
  • An insulator 406c in contact with the top surface of the semiconductor 406b, an insulator 412 over the insulator 406c, a conductor 404 disposed over the semiconductor 406b with the insulator 412 and the insulator 406c interposed therebetween, and the insulator 410 and conductor 404
  • An insulator 428 over the insulator 408, and a first opening reaching the conductor 310b through the insulator 428, the insulator 408, the insulator 418, the insulator 410, the insulator 402, the insulator 303, and the insulator 302
  • a second opening that reaches the conductor 416a1 through the insulator 428, the insulator 408, the insulator 418, and the insulator 410, and the conductor 416a2 through the insulator 428,
  • a conductor 433, a conductor 431, a conductor 429, or a conductor 437 is embedded in each opening, and a conductor 434 having a region in contact with the conductor 433 over the insulator 428 and a conductor 431 over the insulator 428.
  • the semiconductor 406b includes a region 407 in contact with the upper surface of the semiconductor 406b and the conductors 416a1 and 416a2.
  • the conductor 404 functions as a first gate electrode.
  • the conductor 404 can have a stacked structure with a conductor having a function of suppressing permeation of oxygen. For example, an increase in electric resistance due to oxidation of the conductor 404 can be prevented by forming a conductor having a function of suppressing oxygen permeation as a lower layer.
  • the insulator 412 functions as a gate insulator.
  • the conductor 416a1 and the conductor 416a2 have a function as a source electrode or a drain electrode.
  • the conductors 416a1 and 416a2 can have a stacked structure with a conductor having a function of suppressing permeation of oxygen. For example, by forming a conductor having a function of suppressing permeation of oxygen as an upper layer, an increase in electrical resistance due to oxidation of the conductors 416a1 and 416a2 can be prevented.
  • the resistance of the semiconductor 406b can be controlled by a potential applied to the conductor 404. That is, conduction / non-conduction between the conductor 416a1 and the conductor 416a2 can be controlled by a potential applied to the conductor 404.
  • the region functioning as the gate electrode is formed in a self-aligned manner so as to fill the opening formed in the insulator 410 or the like, so that a TGSA s-channel FET (Trench Gate Self Aligns) is formed.
  • TGSA s-channel FET Trench Gate Self Aligns
  • the length of a region where the bottom surface of the conductor 404 functioning as a gate electrode faces in parallel with the top surface of the semiconductor 406b with the insulator 412 and the insulator 406c interposed therebetween is defined as a gate line width.
  • the gate line width can be smaller than the opening of the insulator 410 reaching the semiconductor 406b. That is, the gate line width can be made smaller than the minimum processing dimension.
  • the gate line width can be set to 5 nm to 60 nm, preferably 5 nm to 30 nm.
  • the switching characteristics of the transistor may be deteriorated.
  • the positional relationship between the conductor 404 and the conductors 416a1 and 416a2 varies depending on the thickness of the insulator 406c and the insulator 412.
  • the relationship between the thickness of the conductors 416a1 and 416a2 functioning as a source electrode and a drain electrode and the thickness of the insulator 412 functioning as a gate insulating film affects the electrical characteristics of this transistor. I understand that.
  • the electric field from the gate electrode can be obtained by setting the thickness of the insulator 412 in the region between the conductor 416a1 and the conductor 416a2 to be equal to or less than the thickness of the conductor 416a1 or the conductor 416a2. Since this is applied to the entire channel formation region, the transistor operates favorably.
  • the thickness of the insulator 412 in the region between the conductor 416a1 and the conductor 416a2 is 30 nm or less, preferably 10 nm or less.
  • the thickness of the conductor 416a1 or the thickness of the conductor 416a2 can be a small value.
  • the end portion of the conductor 416a1 has a region facing the conductor 404 with the insulator 406c and the insulator 412 interposed therebetween.
  • the end portion of the conductor 416a2 includes a region facing the conductor 404 with the insulator 406c and the insulator 412 interposed therebetween, but the area of these regions can be further reduced. Therefore, this transistor has a configuration in which the parasitic capacitance in these regions is kept small.
  • the conductor 310a functions as a second gate electrode.
  • the conductor 310a can be a multilayer film including a conductive film having a function of suppressing permeation of oxygen.
  • a decrease in conductivity due to oxidation of the conductor 310a can be prevented.
  • the insulator 301, the insulator 303, and the insulator 402 function as a gate insulating film.
  • the threshold voltage of this transistor can be controlled by the potential applied to the conductor 310a. Further, the threshold voltage of this transistor can be controlled by injecting electrons into the insulator 303 by a potential applied to the conductor 310c. Further, by electrically connecting the first gate electrode and the second gate electrode, a current (ON current) at the time of conduction can be increased. Note that the function of the first gate electrode and the function of the second gate electrode may be interchanged.
  • FIG. 12B illustrates an example in which the first gate electrode and the second gate electrode are electrically connected.
  • An opening that reaches the conductor 404 through the insulator 428, the insulator 408, and the insulator 418 is embedded with a conductor 440, and the conductor 444 formed on the top surface of the conductor 440 and the insulator 428 Are electrically connected.
  • a conductor 442 is embedded in an opening that reaches the conductor 310c through the insulator 428, the insulator 408, the insulator 418, the insulator 410, the insulator 402, the insulator 303, and the insulator 302.
  • the upper surface of the conductor 442 and the conductor 444 are electrically connected. That is, the conductor 404 having a function as the first gate electrode is electrically connected to the conductor 310c having a function as the second gate electrode through the conductor 440, the conductor 444, and the conductor 442. Is done.
  • Examples of the insulator 418 and the insulator 428 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.
  • the insulating material may be used as a single layer or a stacked layer.
  • the insulator 418 and the insulator 428 preferably include silicon oxide or silicon oxynitride. The other configurations are referred to above.
  • Transistor structure 5> Here, a transistor having a structure different from that in FIG. 9 is described with reference to FIGS.
  • FIG. 10A, 10B, and 10C are a top view and cross-sectional views of a semiconductor device according to one embodiment of the present invention.
  • FIG. 10A is a top view.
  • FIG. 10B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 illustrated in FIG.
  • FIG. 10C is a cross-sectional view corresponding to the dashed-dotted line A3-A4 illustrated in FIG. Note that in the top view of FIG. 4A, some elements are omitted for clarity.
  • This transistor has a plurality of channel formation regions for one gate electrode, which is different from the structure of the transistor shown in FIGS. 9A, 9B, and 9C.
  • 10A, 10B, and 10C illustrate an example having three channel formation regions, the number of channel regions is not limited to this. Note that the conductor 433, the conductor 434, and the conductor 310b are omitted in FIG. For other structures, the structure of the transistor illustrated in FIGS. 9A, 9B, and 9C is referred to.
  • FIGS. 11A, 11B, and 11C are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 11A is a top view.
  • FIG. 11B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 illustrated in FIG.
  • FIG. 11C is a cross-sectional view corresponding to the dashed-dotted line A3-A4 illustrated in FIG. Note that in the top view of FIG. 11A, some elements are omitted for clarity.
  • This transistor shows an example of a structure in which the channel width is larger than the gate line width shown in FIG. Note that the conductor 433, the conductor 434, and the conductor 310b are omitted in FIG. For other structures, the structure of the transistor illustrated in FIGS. 9A, 9B, and 9C is referred to.
  • one embodiment of the present invention is described in this embodiment. Alternatively, in another embodiment, one embodiment of the present invention will be described. Note that one embodiment of the present invention is not limited thereto. That is, in this embodiment and other embodiments, various aspects of the invention are described; therefore, one embodiment of the present invention is not limited to a particular aspect. For example, as an embodiment of the present invention, an example in which the channel formation region of a transistor includes an oxide semiconductor, an example in which a transistor includes an oxide semiconductor, or the like has been described. It is not limited to this. Depending on circumstances or circumstances, various transistors in one embodiment of the present invention may include various semiconductors.
  • various transistors in one embodiment of the present invention can include, for example, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or organic You may have at least one, such as a semiconductor. Alternatively, for example, depending on the case or the situation, various transistors in one embodiment of the present invention may not include an oxide semiconductor.
  • An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor.
  • a non-single-crystal oxide semiconductor a CAAC-OS (c-axis-aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like oxide OS) : Amorphous-like oxide semiconductor) and amorphous oxide semiconductor.
  • oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors.
  • a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.
  • Amorphous structures are generally isotropic, have no heterogeneous structure, are metastable, have no fixed atomic arrangement, have a flexible bond angle, have short-range order, but long-range order It is said that it does not have.
  • a stable oxide semiconductor cannot be called a complete amorphous oxide semiconductor.
  • an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a complete amorphous oxide semiconductor.
  • an a-like OS is not isotropic but has an unstable structure having a void (also referred to as a void). In terms of being unstable, a-like OS is physically similar to an amorphous oxide semiconductor.
  • CAAC-OS First, the CAAC-OS will be described.
  • a CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).
  • CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction)
  • XRD X-ray Diffraction
  • CAAC-OS having an InGaZnO 4 crystal classified into the space group R-3m is subjected to structural analysis by an out-of-plane method
  • a diffraction angle (2 ⁇ ) as illustrated in FIG. Shows a peak near 31 °. Since this peak is attributed to the (009) plane of the InGaZnO 4 crystal, in CAAC-OS, the crystal has a c-axis orientation, and the plane on which the c-axis forms a CAAC-OS film (formation target) It can also be confirmed that it faces a direction substantially perpendicular to the upper surface.
  • a peak may also appear when 2 ⁇ is around 36 °.
  • the peak where 2 ⁇ is around 36 ° is attributed to the crystal structure classified into the space group Fd-3m. Therefore, the CAAC-OS preferably does not show the peak.
  • FIG. 13E shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. From FIG. 13E, a ring-shaped diffraction pattern is confirmed. Therefore, it can be seen that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation even by electron diffraction using an electron beam with a probe diameter of 300 nm. Note that the first ring in FIG. 13E is considered to be caused by the (010) plane and the (100) plane of the InGaZnO 4 crystal. Further, the second ring in FIG. 13E is considered to be due to the (110) plane and the like.
  • FIG. 14A shows a high-resolution TEM image of a cross section of the CAAC-OS observed from a direction substantially parallel to the sample surface.
  • a spherical aberration correction function was used for observation of the high-resolution TEM image.
  • a high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image.
  • the Cs-corrected high resolution TEM image can be observed, for example, with an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.
  • FIG. 14A shows a pellet that is a region where metal atoms are arranged in layers. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellet can also be referred to as a nanocrystal (nc).
  • the CAAC-OS can also be referred to as an oxide semiconductor including CANC (C-Axis aligned nanocrystals).
  • CANC C-Axis aligned nanocrystals.
  • the pellet reflects the unevenness of the CAAC-OS formation surface or top surface and is parallel to the CAAC-OS formation surface or top surface.
  • FIGS. 14B and 14C show Cs-corrected high-resolution TEM images of the plane of the CAAC-OS observed from the direction substantially perpendicular to the sample surface.
  • FIGS. 14D and 14E are images obtained by performing image processing on FIGS. 14B and 14C, respectively.
  • an image processing method will be described.
  • an FFT image is acquired by performing a fast Fourier transform (FFT) process on FIG.
  • FFT fast Fourier transform
  • IFFT inverse fast Fourier transform
  • the image acquired in this way is called an FFT filtered image.
  • the FFT filtered image is an image obtained by extracting periodic components from the Cs-corrected high-resolution TEM image, and shows a lattice arrangement.
  • FIG. 14D the portion where the lattice arrangement is disturbed is indicated by a broken line.
  • a region surrounded by a broken line is one pellet.
  • the location shown with the broken line is the connection part of a pellet and a pellet. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape.
  • the shape of a pellet is not necessarily a regular hexagonal shape, and is often a non-regular hexagonal shape.
  • FIG. 14E a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned is indicated by a dotted line, and the change in the orientation of the lattice arrangement is shown. It is indicated by a broken line.
  • a clear crystal grain boundary cannot be confirmed even in the vicinity of the dotted line.
  • the CAAC-OS has a c-axis alignment and a crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction to have a strain. Therefore, the CAAC-OS can also be referred to as an oxide semiconductor having CAAcrystal (c-axis-aligned ab-plane-anchored crystal).
  • the CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated by entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).
  • the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element.
  • an element such as silicon which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor.
  • heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.
  • an oxide semiconductor has impurities or defects, characteristics may fluctuate due to light, heat, or the like.
  • an impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source.
  • oxygen vacancies in the oxide semiconductor may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.
  • a CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density.
  • the carrier is less than 8 ⁇ 10 11 cm ⁇ 3 , preferably less than 1 ⁇ 10 11 cm ⁇ 3 , more preferably less than 1 ⁇ 10 10 cm ⁇ 3 , and a carrier of 1 ⁇ 10 ⁇ 9 cm ⁇ 3 or more.
  • a dense oxide semiconductor can be obtained.
  • Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.
  • the CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.
  • nc-OS is analyzed by XRD.
  • XRD X-ray diffraction
  • FIG. 15B shows a diffraction pattern (nanobeam electron diffraction pattern) when an electron beam having a probe diameter of 1 nm is incident on the same sample. From FIG. 15B, a plurality of spots are observed in the ring-shaped region. Therefore, nc-OS does not confirm order when an electron beam with a probe diameter of 50 nm is incident, but confirms order when an electron beam with a probe diameter of 1 nm is incident.
  • the nc-OS has a highly ordered region, that is, a crystal in a thickness range of less than 10 nm. Note that there are some regions where a regular electron diffraction pattern is not observed because the crystal faces in various directions.
  • FIG. 15D illustrates a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the formation surface.
  • the nc-OS has a region in which a crystal part can be confirmed, such as a portion indicated by an auxiliary line, and a region in which a clear crystal part cannot be confirmed in a high-resolution TEM image.
  • a crystal part included in the nc-OS has a size of 1 nm to 10 nm, particularly a size of 1 nm to 3 nm in many cases. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor.
  • the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image.
  • the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.
  • the nc-OS has a periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
  • the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.
  • nc-OS is an oxide semiconductor having RANC (Random Aligned nanocrystals), or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.
  • the nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.
  • the a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.
  • FIG. 16 shows a high-resolution cross-sectional TEM image of the a-like OS.
  • FIG. 16A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation.
  • FIG. 16B is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e ⁇ ) of 4.3 ⁇ 10 8 e ⁇ / nm 2 .
  • electrons (e ⁇ ) of 4.3 ⁇ 10 8 e ⁇ / nm 2 .
  • the a-like OS Since it has a void, the a-like OS has an unstable structure.
  • the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, a change in structure due to electron irradiation is shown.
  • a-like OS, nc-OS, and CAAC-OS are prepared. Each sample is an In—Ga—Zn oxide.
  • a high-resolution cross-sectional TEM image of each sample is acquired.
  • Each sample has a crystal part by a high-resolution cross-sectional TEM image.
  • a unit cell of an InGaZnO 4 crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction.
  • the spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, in the following, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less is regarded as a crystal part of InGaZnO 4 .
  • the lattice fringes correspond to the ab plane of the InGaZnO 4 crystal.
  • FIG. 17 is an example in which the average size of the crystal parts (22 to 30 locations) of each sample was investigated. Note that the length of the lattice stripes described above is the size of the crystal part. From FIG. 17, it can be seen that in the a-like OS, the crystal part becomes larger in accordance with the cumulative irradiation amount of electrons related to acquisition of a TEM image or the like. According to FIG. 17, in the crystal part (also referred to as initial nucleus) which was about 1.2 nm in the initial observation by TEM, the cumulative dose of electrons (e ⁇ ) is 4.2 ⁇ 10 8 e ⁇ / nm. it can be seen that grown to a size of about 1.9nm in 2.
  • FIG. 17 shows that the crystal part sizes of the nc-OS and the CAAC-OS are approximately 1.3 nm and 1.8 nm, respectively, regardless of the cumulative electron dose.
  • a Hitachi transmission electron microscope H-9000NAR was used for electron beam irradiation and TEM observation.
  • the electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7 ⁇ 10 5 e ⁇ / (nm 2 ⁇ s), and an irradiation region diameter of 230 nm.
  • the crystal part may be grown by electron irradiation.
  • the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.
  • the a-like OS has a lower density than the nc-OS and the CAAC-OS.
  • the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition.
  • the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of single crystals having the same composition.
  • An oxide semiconductor having a density of less than 78% of the single crystal is difficult to form.
  • the density of single crystal InGaZnO 4 having a rhombohedral structure is 6.357 g / cm 3 .
  • the density of a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3.
  • the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm 3 or more and 6.3 g / less than cm 3 .
  • oxide semiconductors have various structures and various properties.
  • the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.
  • the semiconductor 406b is an oxide semiconductor containing indium, for example.
  • the carrier mobility electron mobility
  • the semiconductor 406b preferably contains an element M.
  • the element M is preferably aluminum, gallium or tin.
  • Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten.
  • the element M may be a combination of a plurality of the aforementioned elements.
  • the element M is an element having a high binding energy with oxygen, for example.
  • the element M is an element having a function of increasing the energy gap of the oxide semiconductor, for example.
  • the semiconductor 406b preferably contains zinc. An oxide semiconductor may be easily crystallized when it contains zinc.
  • the semiconductor 406b is not limited to the oxide semiconductor containing indium.
  • the semiconductor 406b may be, for example, an oxide semiconductor containing zinc, an oxide semiconductor containing gallium, an oxide semiconductor containing tin, or the like that does not contain indium, such as zinc tin oxide, gallium tin oxide, and gallium oxide. I do not care.
  • an oxide with a wide energy gap is used, for example.
  • the energy gap of the semiconductor 406b is, for example, 2.5 eV to 4.2 eV, preferably 2.8 eV to 3.8 eV, and more preferably 3 eV to 3.5 eV.
  • the insulator 406a and the insulator 406c are oxides including one or more elements other than oxygen included in the semiconductor 406b, or two or more elements. Since the insulator 406a and the insulator 406c are composed of one or more elements other than oxygen constituting the semiconductor 406b, or two or more elements, the interface between the insulator 406a and the semiconductor 406b and the interface between the semiconductor 406b and the insulator 406c , Interface states are difficult to form.
  • the insulator 406a, the semiconductor 406b, and the insulator 406c contain indium will be described.
  • the insulator 406a is an In—M—Zn oxide
  • In is preferably less than 50 atomic%
  • M is higher than 50 atomic%, and more preferably, In is 25 atomic%. Less than, M is higher than 75 atomic%.
  • the semiconductor 406b is an In—M—Zn oxide
  • the In is preferably higher than 25 atomic%
  • the M is lower than 75 atomic%, and more preferably, In is higher than 34 atomic%.
  • M is less than 66 atomic%.
  • the insulator 406c is an In-M-Zn oxide
  • In is preferably less than 50 atomic%
  • M is higher than 50 atomic%, and more preferably In is 25 atomic%. Less than, M is higher than 75 atomic%.
  • the insulator 406c may be formed using the same kind of oxide as the insulator 406a.
  • the semiconductor 406b an oxide having an electron affinity higher than those of the insulators 406a and 406c is used.
  • the semiconductor 406b has a higher electron affinity than the insulator 406a and the insulator 406c by 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV, and more preferably 0.15 eV to 0.4 eV.
  • An oxide is used. Note that the electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band.
  • the insulator 406c preferably contains indium gallium oxide.
  • the gallium atom ratio [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.
  • the insulator 406a and / or the insulator 406c may be gallium oxide.
  • gallium oxide is used as the insulator 406c, leakage current generated between the conductor 416a1 or the conductor 416a2 and the conductor 404 can be reduced. That is, the off-state current of the transistor can be reduced.
  • the stacked body of the insulator 406a, the semiconductor 406b, and the insulator 406c has a band diagram in which energy continuously changes (also referred to as a continuous junction) in the vicinity of each interface.
  • the semiconductor 406b may have a thickness of 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more, more preferably 60 nm or more, and more preferably 100 nm or more.
  • the semiconductor 406b having a region with a thickness of 300 nm or less, preferably 200 nm or less, and more preferably 150 nm or less may be used. Note that as the channel formation region is reduced, the electrical characteristics of the transistor may be improved as the semiconductor 406b is thinner. Therefore, the thickness of the semiconductor 406b may be less than 10 nm.
  • the thickness of the insulator 406c is preferably as small as possible.
  • the insulator 406c may have a region less than 10 nm, preferably 5 nm or less, more preferably 3 nm or less.
  • the insulator 406c has a function of blocking entry of elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator into the semiconductor 406b where a channel is formed. Therefore, the insulator 406c preferably has a certain thickness.
  • the insulator 406c may have a thickness of 0.3 nm or more, preferably 1 nm or more, and more preferably 2 nm or more.
  • the insulator 406c preferably has a property of blocking oxygen in order to suppress outward diffusion of oxygen released from the insulator 402 and the like.
  • the insulator 406a is preferably thick and the insulator 406c is preferably thin.
  • the insulator 406a may have a region with a thickness of 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more, more preferably 60 nm or more.
  • the thickness of the insulator 406a By increasing the thickness of the insulator 406a, the distance from the interface between the adjacent insulator and the insulator 406a to the semiconductor 406b where a channel is formed can be increased.
  • the insulator 406a having a region with a thickness of 200 nm or less, preferably 120 nm or less, more preferably 80 nm or less may be used.
  • silicon in the oxide semiconductor may serve as a carrier trap or a carrier generation source. Therefore, the lower the silicon concentration of the semiconductor 406b, the better.
  • silicon in the oxide semiconductor may serve as a carrier trap or a carrier generation source. Therefore, the lower the silicon concentration of the semiconductor 406b, the better.
  • the semiconductor 406b and the insulator 406a for example, in secondary ion mass spectrometry (SIMS), less than 1 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3. less than 3, more preferably a region comprising a silicon concentration of less than 2 ⁇ 10 18 atoms / cm 3 .
  • SIMS secondary ion mass spectrometry
  • SIMS 406b and the insulator 406c in SIMS, less than 1 ⁇ 10 19 atoms / cm 3 , preferably less than 5 ⁇ 10 18 atoms / cm 3 , more preferably less than 2 ⁇ 10 18 atoms / cm 3
  • the insulator 406a and the insulator 406c are 2 ⁇ 10 20 atoms / cm 3 or less, preferably 5 ⁇ 10 19 atoms / cm 3 or less, more preferably 1 ⁇ 10 19 atoms / cm 3 or less, more preferably SIMS 5 ⁇ having 10 18 atoms / cm 3 or less of the hydrogen concentration and a region.
  • the nitrogen concentration of the semiconductor 406b it is preferable to reduce the nitrogen concentrations of the insulator 406a and the insulator 406c.
  • the insulator 406a and the insulator 406c are less than 5 ⁇ 10 19 atoms / cm 3 in SIMS, preferably 5 ⁇ 10 18 atoms / cm 3 or less, more preferably 1 ⁇ 10 18 atoms / cm 3 or less, and still more preferably The region has a nitrogen concentration of 5 ⁇ 10 17 atoms / cm 3 or less.
  • the semiconductor 406b preferably has a region where the copper concentration is 1 ⁇ 10 19 atoms / cm 3 or less, 5 ⁇ 10 18 atoms / cm 3 or less, or 1 ⁇ 10 18 atoms / cm 3 or less.
  • the above three-layer structure is an example.
  • a two-layer structure without the insulator 406a or the insulator 406c may be used.
  • a four-layer structure including any of the insulators or semiconductors exemplified as the insulator 406a, the semiconductor 406b, and the insulator 406c above or below the insulator 406a or above or below the insulator 406c may be employed.
  • Any one of the above may be used as an n-layer structure (n is an integer of 5 or more).
  • an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a single semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • there is a semiconductor substrate having an insulator region inside the semiconductor substrate for example, an SOI (Silicon On Insulator) substrate.
  • the conductor substrate examples include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • a substrate having a metal nitride examples include a substrate having a metal oxide, and the like.
  • a substrate in which a conductor or a semiconductor is provided on an insulator substrate examples include a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like.
  • a substrate in which an element is provided may be used.
  • the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.
  • a flexible substrate may be used as the substrate 400.
  • a method for providing a transistor over a flexible substrate there is a method in which after a transistor is manufactured over a non-flexible substrate, the transistor is peeled off and transferred to the substrate 400 which is a flexible substrate.
  • a separation layer is preferably provided between the non-flexible substrate and the transistor.
  • a sheet, a film, a foil, or the like in which fibers are knitted may be used as the substrate 400.
  • the substrate 400 may have elasticity. Further, the substrate 400 may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape.
  • the substrate 400 has a region having a thickness of, for example, 5 ⁇ m to 700 ⁇ m, preferably 10 ⁇ m to 500 ⁇ m, and more preferably 15 ⁇ m to 300 ⁇ m.
  • a semiconductor device including a transistor can be reduced in weight.
  • the substrate 400 may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate 400 due to a drop or the like can be reduced. That is, a durable semiconductor device can be provided.
  • the substrate 400 which is a flexible substrate
  • a metal, an alloy, a resin, glass, or fiber thereof can be used as the substrate 400 which is a flexible substrate.
  • the substrate 400, which is a flexible substrate is preferable because the deformation due to the environment is suppressed as the linear expansion coefficient is lower.
  • a material having a linear expansion coefficient of 1 ⁇ 10 ⁇ 3 / K or less, 5 ⁇ 10 ⁇ 5 / K or less, or 1 ⁇ 10 ⁇ 5 / K or less is used as the substrate 400 that is a flexible substrate.
  • the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
  • aramid has a low coefficient of linear expansion, it is suitable as the substrate 400 that is a flexible substrate.
  • the substrate 400 is prepared.
  • the insulator 401 is formed.
  • the insulator 401 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulator to be the insulator 301 is formed over the insulator 401.
  • the insulator to be the insulator 301 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a groove reaching the insulator 401 is formed in the insulator to be the insulator 301.
  • the groove includes, for example, a hole and an opening.
  • the groove may be formed by wet etching, but dry etching is preferable for fine processing.
  • the insulator 401 is preferably an insulator that functions as an etching stopper film when the insulator to be the insulator 301 is etched to form a groove.
  • the insulator 401 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film.
  • a conductor to be the conductor 310a or the conductor 310b is formed.
  • the conductor to be the conductor 310a or the conductor 310b desirably includes a conductor having a function that hardly transmits oxygen.
  • tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
  • a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used.
  • the conductor to be the conductor 310a or the conductor 310b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductor to be the conductor 310a or the conductor 310b over the insulator 301 is removed.
  • the conductor 310a and the conductor 310b remain only in the groove, so that a wiring layer having a flat upper surface can be formed.
  • a conductor to be the conductor 310a or the conductor 310b may be formed over the insulator 301, and the conductor 310a and the conductor 310b may be formed by a lithography method or the like.
  • the insulator 302 is formed over the insulator 301 and over the conductor 310a and the conductor 310b.
  • the insulator 302 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • An insulator 303 is formed over the insulator 302.
  • the insulator 303 preferably has a function of suppressing permeation of impurities such as hydrogen and oxygen. For example, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film is preferably used.
  • the insulator 303 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 402 is formed over the insulator 303.
  • the insulator 402 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • treatment for adding oxygen to the insulator 402 may be performed. Examples of the treatment for adding oxygen include an ion implantation method and a plasma treatment method. Note that oxygen added to the insulator 402 becomes excess oxygen.
  • the insulator 306 a is formed over the insulator 402.
  • the insulator 306a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • treatment for adding oxygen to the insulator 306a may be performed.
  • the treatment for adding oxygen include an ion implantation method and a plasma treatment method. Note that oxygen added to the insulator 306a becomes excess oxygen.
  • a semiconductor 306b is formed over the insulator 306a.
  • the first heat treatment may be performed at 250 ° C to 650 ° C, preferably 450 ° C to 600 ° C, more preferably 520 ° C to 570 ° C.
  • the first heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.
  • the first heat treatment may be performed in a reduced pressure state.
  • the first heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. Good.
  • the crystallinity of the semiconductor can be increased, impurities such as hydrogen and water can be removed, and the like.
  • plasma treatment including oxygen may be performed in a reduced pressure state.
  • the plasma treatment including oxygen it is preferable to use an apparatus having a power source that generates high-density plasma using microwaves, for example.
  • a plasma power source that applies RF (Radio Frequency) may be provided on the substrate side.
  • High density oxygen radicals can be generated by using high density plasma, and by applying RF to the substrate side, oxygen radicals generated by the high density plasma can be efficiently introduced into the semiconductor 306b.
  • plasma treatment containing oxygen may be performed to supplement oxygen that has been desorbed after performing plasma treatment containing an inert gas using this apparatus.
  • the conductor 414 is formed over the semiconductor 306b.
  • the conductor 414 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIGS. 18A, 18B, and 18C).
  • the conductor 414 is processed by a lithography method or the like to form a conductor 415 (see FIGS. 19A, 19B, and 19C).
  • the insulator 306a, the semiconductor 306b, and the conductor 415 are processed by a lithography method or the like, so that a multilayer film including the insulator 406a, the semiconductor 406b, the conductor 416a1, and the conductor 416a2 is formed.
  • the region 407 is formed by damaging the upper surface of the semiconductor 306b. Since the region 407 includes a region where the resistance of the semiconductor 406b is reduced, the contact resistance between the conductor 415 and the semiconductor 406b is reduced.
  • the insulator 402 is also etched, and part of the region may be thinned. That is, the insulator 402 may have a shape having a protrusion in a region in contact with the multilayer film (see FIGS. 20A, 20B, and 20C).
  • the insulator 406c is formed.
  • the insulator 406c can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 412 is formed over the insulator 406c.
  • the insulator 412 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a conductor to be the conductor 404 is formed.
  • the conductor to be the conductor 404 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductor to be the conductor 404 is processed using a lithography method or the like to form the conductor 404 (see FIGS. 21A to 21C).
  • an insulator 408 is formed.
  • the insulator 408 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 410 is formed.
  • the insulator 410 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a spin coating method, a dip method, a droplet discharge method (such as an ink jet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, or a curtain coater method can be used.
  • the insulator 410 may be formed so that the upper surface has flatness.
  • the insulator 410 may have a flat upper surface immediately after film formation.
  • the insulator 410 may have flatness by removing the insulator and the like from the upper surface so as to be parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a flattening process.
  • the planarization process include a CMP process and a dry etching process. Note that the top surface of the insulator 410 does not have to have flatness (see FIGS. 22A, 22B, and 22C).
  • the conductor 411 is formed over the insulator 410.
  • the conductor 411 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulator 413 is formed over the conductor 411.
  • the insulator 413 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an organic film 421 is formed over the insulator 413 by a coating method or the like (see FIGS. 23A, 23B, and 23C).
  • a resist mask 420 is formed on the organic film 421 using a lithography method or the like.
  • the adhesion between the insulator 413 and the resist mask 420 may be improved (FIGS. 24A, 24B, and 24C). reference.).
  • the organic film 421 is etched to be an organic film 422, but at the same time, a product 424 is also formed on the side surface of the organic film 422.
  • the product 424 is preferably a product containing carbon and fluorine.
  • the size of the opening of the resist mask is reduced by the film thickness of the product 424 formed on the side surface.
  • the above dry etching apparatus is preferably used.
  • the gas used for the plasma treatment for example, C 4 F 6 gas, C 2 F 6 gas, C 4 F 8 gas, CF 4 gas, SF 6 gas, CHF 3 gas, or the like may be used alone or in combination of two or more gases. Can be used.
  • oxygen gas, helium gas, argon gas, hydrogen gas, or the like can be appropriately added to the above gas.
  • a gas capable of generating a product containing carbon and fluorine by a plasma containing carbon and fluorine for example, it is preferable to use a gas in which helium gas, argon gas, hydrogen gas, or the like is appropriately added to any one of C 4 F 6 gas, C 4 F 8 gas, or CHF 3 gas.
  • part of the insulator 413 is etched using the resist mask 420, the organic film 422, and the product 424 as an etching mask to form the insulator 419.
  • C 4 F 6 gas, C 4 F 8 gas, CF 4 gas, SF 6 gas, CHF 3 gas, or the like can be used alone or in combination of two or more gases.
  • oxygen gas, helium gas, argon gas, hydrogen gas, or the like can be appropriately added to the above gas.
  • the dry etching apparatus described above can be used as the dry etching apparatus, it is preferable to use a dry etching apparatus having a configuration in which high-frequency power sources having different frequencies are connected to the parallel plate electrodes.
  • part of the conductor 411 is etched to form the conductor 417.
  • the gas used for dry etching for example, C 4 F 6 gas, C 4 F 8 gas, CF 4 gas, SF 6 gas, CHF 3 gas, Cl 2 gas, BCl 3 gas, SiCl 4 gas, or the like is used as a single gas or Two or more gases can be mixed and used. Alternatively, oxygen gas, helium gas, argon gas, hydrogen gas, or the like can be appropriately added to the above gas. At this time, the resist mask 420 and the organic film 422 may be etched away.
  • the dry etching apparatus the above-described dry etching apparatus may be used. Through the above steps, a hard mask including the conductor 417 and the insulator 419 is formed (see FIGS. 26A, 26B, and 26C).
  • the hard mask may be a single layer including only the conductor 417.
  • the above-described plasma treatment may be performed to form the product 424 on the side surface of the resist and the organic material film 422.
  • the first opening, the second opening, the third opening, and the fourth opening are formed by a dry etching method using the hard mask including the conductor 417 and the insulator 419 as an etching mask. .
  • the first opening is formed by etching until the top surface of the conductor 310b is reached through the insulator 410, the insulator 408, the insulator 412, the insulator 406c, the insulator 402, the insulator 303, and the insulator 302.
  • the second opening is formed by etching until it reaches the upper surface of the conductor 416a1 through the insulator 410, the insulator 408, the insulator 412, and the insulator 406c.
  • the third opening is formed by etching until it reaches the upper surface of the conductor 416a2 through the insulator 410, the insulator 408, the insulator 412, and the insulator 406c.
  • the fourth opening is formed by etching until it reaches the upper surface of the conductor 404 through the insulator 410 and the insulator 408.
  • a gas used for dry etching for example, a gas similar to the above-described etching can be used.
  • a dry etching apparatus similar to the above can be used.
  • first opening, the second opening, the third opening, and the fourth opening can be formed by one lithography, so that the process can be shortened and the productivity can be improved. It is.
  • each opening may be formed by using a lithography method.
  • some openings may be collectively formed using a lithography method (see FIGS. 27A, 27B, and 27C).
  • each insulator of each opening can be processed continuously using the same dry etching apparatus.
  • the processing can be performed without exposing the substrate to the air atmosphere for each processing of each insulator, and the substrate is corroded, contaminated, or attached with dust. Can be prevented or productivity can be improved.
  • the dry etching apparatus has two chambers, it is preferable for the stability of the etching rate, etc., to separate the gas species used for etching, for example, the gas chamber containing chlorine and the gas containing fluorine. It is. Or it can also be set as the parallel processing which performs the same process in two chambers. Parallel processing is preferable because productivity can be improved.
  • plasma treatment using oxygen gas may be continuously performed after processing the first opening, the second opening, the third opening, and the fourth opening.
  • Etching products may adhere to the first opening, the second opening, the third opening, and the fourth opening by the processing, but they are removed by plasma treatment using oxygen gas. Can do.
  • the upper surface of the conductor 404 at the bottom of the opening is oxidized.
  • a metal oxide may be formed. Metal oxides can be insulators or resistors. Therefore, it is preferable to remove the metal oxide.
  • a cleaning treatment may be performed to remove the metal oxide.
  • cleaning treatment cleaning using a chemical solution, pure water or cleaning using carbon dioxide gas added to pure water can be performed.
  • cleaning device a spin cleaning machine or a batch type cleaning device can be used.
  • the conductor 435 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductor 435 is formed so as to fill the first opening, the second opening, the third opening, and the fourth opening. Therefore, it is preferable to use the CVD method (particularly the MCVD method).
  • the conductor 435 is a multilayer of a conductor formed by the ALD method and a conductor formed by the MCVD method.
  • a film may be preferable.
  • titanium nitride may be formed by ALD, and then tungsten may be formed by MCVD (see FIGS. 28A, 28B, and 28C).
  • first CMP treatment is performed on the conductor 435 until the top surface of the insulator 419 is reached (see FIGS. 29A, 29B, and 29C).
  • second CMP treatment is performed on the conductor 435 and the insulator 419 until the top surface of the insulator 410 is reached. Accordingly, the conductor 433 is embedded in the first opening, the conductor 431 is embedded in the second opening, the conductor 429 is embedded in the third opening, and the fourth opening Is embedded with a conductor 437 (see FIGS. 30A, 30B, and 30C).
  • a conductor to be the conductor 434, the conductor 432, the conductor 430, and the conductor 438 is formed over the insulator 410, the conductor 433, the conductor 431, the conductor 429, and the conductor 437. Then, the conductor 434, the conductor 432, the conductor 430, and the conductor 438 are etched by a lithography method so that the conductor 434, the conductor 432, the conductor 430, and the conductor 438 are etched. Form.
  • the transistor illustrated in FIG. 6 can be manufactured (see FIGS. 6A, 6B, and 6C).
  • the insulator 306a, the semiconductor 306b, and the conductor 414 are processed by a lithography method or the like, so that a multilayer film including the insulator 406a, the semiconductor 406b, and the conductor 415 is formed.
  • the region 407 is formed by damaging the upper surface of the semiconductor 306b. Since the region 407 includes a region where the resistance of the semiconductor 406b is reduced, the contact resistance between the conductor 415 and the semiconductor 406b is reduced.
  • the insulator 402 is also etched, and part of the region may be thinned. In other words, the insulator 402 may have a shape with a protrusion in a region in contact with the multilayer film (see FIGS. 32A to 32C).
  • the insulator 446 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, a spin coating method, a dip method, a droplet discharge method (such as an ink jet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, or a curtain coater method can be used.
  • a conductor 426 is formed over the insulator 446.
  • the conductor 426 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductor 426 is formed so as to fill a step portion on the top surface of the insulator 446. Therefore, it is preferable to use the CVD method (particularly the MCVD method).
  • the conductor 426 is a multilayer of a conductor formed by the ALD method and a conductor formed by the MCVD method.
  • a film may be preferable.
  • titanium nitride may be formed by ALD, and then tungsten may be formed by MCVD.
  • an insulator 427 is formed over the conductor 426.
  • the insulator 427 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a spin coating method, a dipping method, a droplet discharge method (such as an ink jet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, or a curtain coater method can be used (See FIGS. 33A, 33B, and 33C.)
  • first CMP treatment is performed on the insulator 427 and the conductor 426 until the thickness of the conductor 426 is reduced to about half.
  • a slurry suitable for the insulator is preferably used (see FIGS. 34A, 34B, and 34C).
  • a second CMP process is performed on the remaining conductor 426 and insulator 446 until the insulator 446 is exposed and the surface of the insulator 446 is planarized, whereby the insulator 409 is formed.
  • the second CMP treatment it is desirable to use a slurry prepared so that the polishing rate of the insulator 446 is as slow as possible with respect to the polishing rate of the conductor 426.
  • the use of the slurry is preferable because the flatness of the surface of the insulator 446 may be further improved.
  • the CMP processing apparatus has an end point detection function for notifying that the insulator 446 is exposed in the second CMP processing.
  • the end point detection function is preferable because the film thickness controllability of the insulator 446 after the second CMP treatment may be improved (see FIGS. 35A, 35B, and 35C).
  • an insulator 409 is formed on the insulator 446 so as to have a flat upper surface by CMP treatment or the like. Also good.
  • the top surface of the insulator 446 may have flatness immediately after film formation. However, the top surface of the insulator 446 may not have flatness.
  • a resist mask 423 is formed over the insulator 409 by a lithography method or the like.
  • a lithography method for example, an organic film may be provided between the insulator 409 and the resist mask 423.
  • a single layer of a conductor or a stacked film of a conductor and an insulator may be formed over the insulator 409, and a hard mask may be formed by a lithography method (FIGS. 36A, 36B, and 36C). )reference.).
  • the insulator 409 is processed by a dry etching method until it reaches the insulator 402, so that the insulator 410 is formed. At this time, etching may be performed until the insulator 402 reaches the insulator 303.
  • a gas used for dry etching for example, C 4 F 6 gas, CF 4 gas, SF 6 gas, or CHF 3 gas can be used.
  • oxygen gas, helium gas, argon gas, hydrogen gas, or the like can be appropriately added to the above gas.
  • the dry etching apparatus described above can be used as the dry etching apparatus, it is preferable to use a dry etching apparatus having a configuration in which high-frequency power sources having different frequencies are connected to the parallel plate electrodes.
  • the conductor 415 is processed by a dry etching method to be separated into a conductor 416a1 and a conductor 416a2.
  • CF 4 gas for example, C 4 F 6 gas, CF 4 gas, SF 6 , Cl 2 gas, BCl 3 gas, SiCl 4 or the like is used alone or in combination of two or more. be able to.
  • oxygen gas, helium gas, argon gas, or hydrogen gas may be appropriately added to the above gas.
  • a mixture of CF 4 gas, Cl 2 gas and oxygen gas may be used.
  • the dry etching apparatus the above-described dry etching apparatus may be used.
  • the semiconductor 406b has an exposed region.
  • the exposed region 407 of the semiconductor 406b may be removed by the above-described etching of the conductor 415 (see FIGS. 37A, 37B, and 37C).
  • impurities such as a residual component of an etching gas may adhere to the exposed region of the semiconductor 406b.
  • a chlorine-based gas is used as an etching gas
  • chlorine or the like may adhere.
  • a hydrocarbon-based gas is used as an etching gas
  • carbon or hydrogen may adhere. If the substrate is exposed to the air after processing by dry etching, the exposed region of the semiconductor 406b may be corroded. Therefore, it is preferable to perform plasma treatment using oxygen gas continuously after processing by dry etching because the impurities can be removed and corrosion of an exposed region of the semiconductor 406b can be prevented.
  • the impurities may be removed by, for example, a cleaning process using diluted hydrofluoric acid or a cleaning process using ozone or the like. A plurality of cleaning processes may be combined. Accordingly, the exposed region of the semiconductor 406b, in other words, the channel formation region has a high resistance.
  • the contact resistance value between the conductors 416a1 and 416a2 and the semiconductor 406b is reduced as described above, and favorable transistor characteristics are obtained. Is preferable.
  • an insulator to be the insulator 406c is formed, and an insulator to be the insulator 412 is formed over the insulator to be the insulator 406c.
  • the insulator to be the insulator 406c and the insulator to be the insulator 412 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator to be the insulator 406c and the insulator to be the insulator 412 are formed with a uniform thickness over the side surface and the bottom surface of the opening formed by the insulator 410, the conductor 416a1, and the conductor 416a2. Therefore, it is preferable to use the ALD method.
  • a conductor to be the conductor 404 is formed.
  • the conductor to be the conductor 404 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a conductor to be the conductor 404 is formed so as to fill an opening formed by the insulator 410 or the like. Therefore, it is preferable to use the CVD method (particularly the MCVD method).
  • the conductor 404 is formed of a conductor formed by the ALD method and an MCVD method. It may be preferable to form a multilayer film with a conductor to be formed. For example, titanium nitride may be formed by ALD, and then tungsten may be formed by MCVD.
  • the conductor to be the conductor 404 is reached by using CMP or the like to reach the top surface of the insulator 410. Polishing and planarization are performed to form the conductor 404, the insulator 412, and the insulator 406c.
  • the conductor 404 functioning as a gate electrode can be formed in a self-aligned manner without using a lithography method.
  • the conductor 404 functioning as a gate electrode can be formed without considering the alignment accuracy between the conductor 404 functioning as a gate electrode and the conductors 416a1 and 416a2 functioning as source and drain electrodes. Therefore, the area of the semiconductor device can be reduced. Further, since a lithography process is not required, productivity can be improved by simplifying the process (see FIGS. 38A, 38B, and 38C).
  • the insulator 418 is formed over the insulator 410, the insulator 412, and the insulator 406c.
  • the insulator 418 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulator 408 is formed over the insulator 418.
  • the insulator 408 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an oxygen oxide film is formed using a plasma containing oxygen, so that oxygen in the plasma can be added to the upper surface of the insulator 418 as excess oxygen.
  • the second heat treatment may be performed at any timing after the formation of the insulator to be the insulator 408.
  • excess oxygen contained in the insulator 418 moves to the semiconductor 406b through the insulator 410, the insulator 402, and the insulator 406a.
  • excess oxygen contained in the insulator 418 passes through the insulator 412 and moves to the semiconductor 406b.
  • excess oxygen contained in the insulator 418 passes through the insulator 406c and moves to the semiconductor 406b. In this manner, excess oxygen moves to the semiconductor 406b through the three paths, so that defects (oxygen vacancies) in the semiconductor 406b can be reduced.
  • the second heat treatment may be performed at a temperature at which excess oxygen (oxygen) contained in the insulator 418 diffuses to the semiconductor 406b.
  • the description about the first heat treatment may be referred to.
  • the second heat treatment is preferably performed at a temperature lower than that of the first heat treatment.
  • the temperature difference between the first heat treatment and the second heat treatment is 20 ° C. or higher and 150 ° C. or lower, preferably 40 ° C. or higher and 100 ° C. or lower.
  • excess oxygen (oxygen) can be prevented from being released from the insulator 402.
  • the second heat treatment may not be performed when the equivalent heat treatment can be performed by heating at the time of forming each layer.
  • the insulator 428 is formed over the insulator 408.
  • the insulator 428 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIGS. 39A, 39B, and 39C).
  • the conductor 411 is formed over the insulator 428.
  • the conductor 411 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulator 413 is formed over the conductor 411.
  • the insulator 413 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an organic film 421 is formed over the insulator 413 by a coating method or the like (see FIGS. 40A, 40B, and 40C).
  • a resist mask 420 is formed on the organic film 421 using a lithography method or the like.
  • the adhesion between the insulator 413 and the resist mask 420 may be improved (FIGS. 41A, 41B, and 41C). )reference.).
  • the organic film 421 is etched to be an organic film 422, but at the same time, a product 424 is also formed on the side surface of the organic film 422.
  • the product 424 is preferably a product containing carbon and fluorine.
  • the size of the opening of the resist mask is reduced by the film thickness of the product 424 formed on the side surface.
  • an opening mask that is smaller than the minimum dimension of the opening formed by the resist mask that can be formed by the lithography apparatus to be used can be formed (see FIGS. 42A, 42B, and 42C).
  • the above dry etching apparatus is preferably used.
  • the gas used for the plasma treatment for example, C 4 F 6 gas, C 2 F 6 gas, C 4 F 8 gas, CF 4 gas, SF 6 gas, CHF 3 gas, or the like may be used alone or in combination of two or more gases. Can be used.
  • oxygen gas, helium gas, argon gas, hydrogen gas, or the like can be appropriately added to the above gas.
  • a gas capable of generating a product containing carbon and fluorine by a plasma containing carbon and fluorine for example, it is preferable to use a gas in which helium gas, argon gas, hydrogen gas, or the like is appropriately added to any one of C 4 F 6 gas, C 4 F 8 gas, or CHF 3 gas.
  • the insulator 413 is etched until it reaches the upper surface of the conductor 411, so that the insulator 419 is formed.
  • C 4 F 6 gas, C 4 F 8 gas, CF 4 gas, SF 6 gas, CHF 3 gas, or the like can be used alone or in combination of two or more gases.
  • oxygen gas, helium gas, argon gas, hydrogen gas, or the like can be appropriately added to the above gas.
  • the dry etching apparatus described above can be used as the dry etching apparatus, it is preferable to use a dry etching apparatus having a configuration in which high-frequency power sources having different frequencies are connected to the parallel plate electrodes.
  • the conductor 411 is etched until it reaches the upper surface of the insulator 410, so that the conductor 417 is formed.
  • the gas used for dry etching for example, C 4 F 6 gas, C 4 F 8 gas, CF 4 gas, SF 6 gas, CHF 3 gas, Cl 2 gas, BCl 3 gas, SiCl 4 gas, or the like is used as a single gas or Two or more gases can be mixed and used. Alternatively, oxygen gas, helium gas, argon gas, hydrogen gas, or the like can be appropriately added to the above gas.
  • the resist mask 420 and the organic film 422 may be etched away.
  • the dry etching apparatus the above-described dry etching apparatus may be used. Through the above steps, a hard mask including the conductor 417 and the insulator 419 is formed (see FIGS. 43A, 43B, and 43C).
  • the hard mask may be a single layer including only the conductor 417.
  • the above-described plasma treatment may be performed to form the product 424 on the side surface of the resist and the organic material film 422.
  • the first opening, the second opening, the third opening, and the fourth opening are formed by a dry etching method using the hard mask including the conductor 417 and the insulator 419 as an etching mask. .
  • the first opening is formed by etching until the top surface of the conductor 310b is reached through the insulator 410, the insulator 408, the insulator 412, the insulator 406c, the insulator 402, the insulator 303, and the insulator 302.
  • the second opening is formed by etching until it reaches the upper surface of the conductor 416a1 through the insulator 410, the insulator 408, the insulator 412, and the insulator 406c.
  • the third opening is formed by etching until it reaches the upper surface of the conductor 416a2 through the insulator 410, the insulator 408, the insulator 412, and the insulator 406c.
  • the fourth opening is formed by etching until it reaches the upper surface of the conductor 404 through the insulator 410 and the insulator 408.
  • a gas used for dry etching for example, a gas similar to the above-described etching can be used.
  • a dry etching apparatus similar to the above can be used.
  • first opening, the second opening, the third opening, and the fourth opening can be formed by one lithography, so that the process can be shortened and the productivity can be improved. It is.
  • each opening may be formed using a lithography method (see FIGS. 44A, 44B, and 44C).
  • each insulator of each opening can be processed continuously using the same dry etching apparatus.
  • the processing can be performed without exposing the substrate to the air atmosphere for each processing of each insulator, and the substrate is corroded, contaminated, or attached with dust. Can be prevented or productivity can be improved.
  • the dry etching apparatus has two chambers, it is preferable for the stability of the etching rate, etc., to separate the gas species used for etching, for example, the gas chamber containing chlorine and the gas containing fluorine. It is. Or it can also be set as the parallel processing which performs the same process in two chambers. Parallel processing is preferable because productivity can be improved.
  • plasma treatment using oxygen gas may be continuously performed after processing the first opening, the second opening, the third opening, and the fourth opening. This is because the etching product may adhere to the first opening, the second opening, the third opening, and the fourth opening due to the processing, but by plasma treatment using oxygen gas. Can be removed.
  • the upper surface of the conductor 404 at the bottom of the opening is oxidized.
  • a metal oxide may be formed. Metal oxides can be insulators or resistors. Therefore, it is preferable to remove the metal oxide.
  • a cleaning treatment may be performed to remove the metal oxide.
  • cleaning treatment cleaning using a chemical solution, pure water or cleaning using carbon dioxide gas added to pure water can be performed.
  • cleaning device a spin cleaning machine or a batch type cleaning device can be used.
  • the conductor 435 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductor 435 is formed so as to fill the first opening, the second opening, the third opening, and the fourth opening. Therefore, it is preferable to use the CVD method (particularly the MCVD method).
  • the conductor 435 includes a conductor formed by the ALD method and a conductor formed by the MCVD method. It may be preferable to form a multilayer film with a conductor to be formed. For example, titanium nitride may be formed by an ALD method, and then tungsten may be formed by an MCVD method (see FIGS. 45A, 45B, and 45C).
  • first CMP treatment is performed on the conductor 435 until the top surface of the insulator 419 is reached (see FIGS. 46A, 46B, and 46C).
  • a second CMP process is performed until the conductor 435 and the insulator 419 reach the upper surface of the insulator 428. Accordingly, the conductor 433 is embedded in the first opening, the conductor 431 is embedded in the second opening, the conductor 429 is embedded in the third opening, and the fourth opening Is embedded with a conductor 437 (see FIGS. 47A, 47B, and 47C).
  • a conductor to be the conductor 434, the conductor 432, the conductor 430, and the conductor 438 is formed over the insulator 410, the conductor 433, the conductor 431, the conductor 429, and the conductor 437.
  • the conductor 434, the conductor 432, the conductor 430, and the conductor 438 are formed by etching a part of the conductor to be the conductor 434, the conductor 432, the conductor 430, and the conductor 438 by a lithography method. To do.
  • the transistor illustrated in FIGS. 9A to 9C can be manufactured (see FIGS. 9A, 9B, and 9C).
  • FIG. 48 illustrates an example of a semiconductor device (memory device) using the transistor according to one embodiment of the present invention, which can retain stored data even in a state where power is not supplied and has no limitation on the number of writing operations.
  • a semiconductor device illustrated in FIG. 48A includes a transistor 3200 including a first semiconductor, a transistor 3300 including a second semiconductor, and a capacitor 3400. Note that the above-described transistor can be used as the transistor 3300.
  • the transistor 3300 is preferably a transistor with low off-state current.
  • a transistor including an oxide semiconductor can be used. Since the off-state current of the transistor 3300 is small, stored data can be held in a specific node of the semiconductor device for a long time. That is, a refresh operation is not required or the frequency of the refresh operation can be extremely low, so that the semiconductor device with low power consumption is obtained.
  • the first wiring 3001 is electrically connected to the source of the transistor 3200
  • the second wiring 3002 is electrically connected to the drain of the transistor 3200
  • the third wiring 3003 is electrically connected to one of a source and a drain of the transistor 3300
  • the fourth wiring 3004 is electrically connected to the gate of the transistor 3300.
  • the gate of the transistor 3200 and the other of the source and the drain of the transistor 3300 are electrically connected to one electrode of the capacitor 3400
  • the fifth wiring 3005 is electrically connected to the other electrode of the capacitor 3400.
  • the semiconductor device illustrated in FIG. 48A has the property that the potential of the gate of the transistor 3200 can be held; thus, information can be written, held, and read as described below.
  • the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the node FG electrically connected to the gate of the transistor 3200 and one electrode of the capacitor 3400. That is, predetermined charge is supplied to the gate of the transistor 3200 (writing).
  • predetermined charge is supplied to the gate of the transistor 3200 (writing).
  • the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off and the transistor 3300 is turned off, so that charge is held at the node FG (holding).
  • the second wiring 3002 has a charge held in the node FG. Take a potential according to the amount. This is because, when the transistor 3200 is an n-channel type, the apparent threshold voltage V th_H when a high level charge is applied to the gate of the transistor 3200 is the low level charge applied to the gate of the transistor 3200. This is because it becomes lower than the apparent threshold voltage V th_L in the case of being present.
  • the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for bringing the transistor 3200 into a “conducting state”.
  • the potential of the fifth wiring 3005 can be set to a potential V 0 between V th_H and V th_L .
  • the transistor 3200 is in a “conducting state” if the potential of the fifth wiring 3005 is V 0 (> V th_H ).
  • the transistor 3200 remains in the “non-conductive state” even when the potential of the fifth wiring 3005 becomes V 0 ( ⁇ V th_L ). Therefore, by determining the potential of the second wiring 3002, information held in the node FG can be read.
  • the fifth wiring 3005 is supplied with a potential at which the transistor 3200 is in a “non-conducting state”, that is, a potential lower than V th_H regardless of the potential supplied to the node FG. Thus, only a desired memory cell information may be read.
  • the fifth wiring 3005 is supplied with a potential at which the transistor 3200 becomes “conductive” regardless of the potential supplied to the node FG, that is, a potential higher than V th_H. Thus, only the desired memory cell information may be read.
  • FIG. 49 is a cross-sectional view of the semiconductor device corresponding to FIG.
  • the semiconductor device illustrated in FIG. 49 includes a transistor 3200, a transistor 3300, and a capacitor 3400.
  • the transistor 3300 and the capacitor 3400 are provided above the transistor 3200. Note that although an example in which the transistor illustrated in FIG. 1 is used as the transistor 3300 is described, the semiconductor device according to one embodiment of the present invention is not limited thereto. Therefore, the above description of the transistor is referred to as appropriate.
  • the semiconductor device illustrated in FIG. 49 illustrates the case where the transistor 3200 is a Fin type.
  • the transistor 3200 is a transistor using the semiconductor substrate 450.
  • the transistor 3200 includes a region 474a in the semiconductor substrate 450, a region 474b in the semiconductor substrate 450, an insulator 462, and a conductor 454.
  • the region 474a and the region 474b function as a source region and a drain region.
  • the insulator 462 functions as a gate insulator.
  • the conductor 454 functions as a gate electrode. Therefore, the resistance of the channel formation region can be controlled by the potential applied to the conductor 454. That is, conduction / non-conduction between the region 474a and the region 474b can be controlled by a potential applied to the conductor 454.
  • a single semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide may be used.
  • a single crystal silicon substrate is preferably used as the semiconductor substrate 450.
  • a semiconductor substrate having an impurity imparting n-type conductivity As the semiconductor substrate 450, a semiconductor substrate having an impurity imparting n-type conductivity is used. However, as the semiconductor substrate 450, a semiconductor substrate having an impurity imparting p-type conductivity may be used. In that case, a well having an impurity imparting n-type conductivity may be provided in a region to be the transistor 3200. Alternatively, the semiconductor substrate 450 may be i-type.
  • the upper surface of the semiconductor substrate 450 preferably has a (110) plane.
  • the on-state characteristics of the transistor 3200 can be improved.
  • the region 474a and the region 474b are regions having an impurity imparting p-type conductivity. In this manner, the transistor 3200 constitutes a p-channel transistor.
  • the transistor 3200 may be an n-channel transistor.
  • the transistor 3200 is separated from an adjacent transistor by the region 460 or the like.
  • the region 460 is a region having an insulating property.
  • 49 includes an insulator 464, an insulator 466, an insulator 468, an insulator 470, an insulator 472, an insulator 475, an insulator 402, an insulator 410, and an insulator. 408, an insulator 428, an insulator 465, an insulator 467, an insulator 469, an insulator 498, a conductor 480a, a conductor 480b, a conductor 480c, a conductor 478a, and a conductor 478b, a conductor 478c, a conductor 476a, a conductor 476b, a conductor 476c, a conductor 479a, a conductor 479b, a conductor 479c, a conductor 477a, a conductor 477b, and a conductor 477c, a conductor 484a, a conductor 484b, a conductor 484c, a conductor 484d,
  • the insulator 464 is provided over the transistor 3200.
  • the insulator 466 is provided over the insulator 464.
  • the insulator 468 is provided over the insulator 466.
  • the insulator 470 is provided over the insulator 468.
  • the insulator 472 is provided over the insulator 470.
  • the insulator 475 is disposed over the insulator 472.
  • the transistor 3300 is provided over the insulator 475.
  • the insulator 408 is provided over the transistor 3300.
  • the insulator 428 is provided over the insulator 408.
  • the insulator 465 is disposed over the insulator 428.
  • the capacitor 3400 is provided over the insulator 465.
  • the insulator 469 is provided over the capacitor 3400.
  • the insulator 464 includes an opening reaching the region 474a, an opening reaching the region 474b, and an opening reaching the conductor 454.
  • a conductor 480a, a conductor 480b, or a conductor 480c is embedded in each opening.
  • the insulator 466 includes an opening reaching the conductor 480a, an opening reaching the conductor 480b, and an opening reaching the conductor 480c.
  • a conductor 478a, a conductor 478b, or a conductor 478c is embedded in each opening.
  • the insulator 468 includes an opening reaching the conductor 478a, an opening reaching the conductor 478b, and an opening reaching the conductor 478c.
  • a conductor 476a, a conductor 476b, or a conductor 476c is embedded in each opening.
  • a conductor 479a in contact with the conductor 476a, a conductor 479b in contact with the conductor 476b, and a conductor 479c in contact with the conductor 476c are provided.
  • the insulator 472 includes an opening reaching the conductor 479a through the insulator 470, an opening reaching the conductor 479b through the insulator 470, and an opening reaching the conductor 479c through the insulator 470. And having.
  • conductors 477a, 477b, or 477c are embedded in the openings, respectively.
  • the insulator 475 includes an opening overlapping with the channel formation region of the transistor 3300, an opening reaching the conductor 477a, an opening reaching the conductor 477b, and an opening reaching the conductor 477c.
  • a conductor 484d, a conductor 484a, a conductor 484b, or a conductor 484c is embedded in each opening.
  • the conductor 484d may function as a bottom gate electrode of the transistor 3300.
  • electrical characteristics such as a threshold voltage of the transistor 3300 may be controlled by applying a certain potential to the conductor 484d.
  • the conductor 484d and the top gate electrode of the transistor 3300 may be electrically connected.
  • the on-state current of the transistor 3300 can be increased.
  • the punch-through phenomenon can be suppressed, electrical characteristics in the saturation region of the transistor 3300 can be stabilized.
  • the insulator 402 includes an opening reaching the conductor 484a, an opening reaching the conductor 484c, and an opening reaching the conductor 484b.
  • the insulator 428 also includes three openings that reach the conductor 484a, the conductor 484b, and the conductor 484c through the insulator 408, the insulator 410, and the insulator 402, and the insulator 408 and the insulator 410. And two openings reaching one conductor of the source electrode or the drain electrode of the transistor 3300 and an opening reaching the conductor of the gate electrode of the transistor 3300 through the insulator 408.
  • a conductor 483a, a conductor 483b, a conductor 483c, a conductor 483e, a conductor 483f, or a conductor 483d are embedded in the openings.
  • the insulator 465 includes an opening reaching the conductor 485a, an opening reaching the conductor 485b, and an opening reaching the conductor 485c.
  • a conductor 487a, a conductor 487b, or a conductor 487c is embedded in each opening.
  • a conductor 488a in contact with the conductor 487a, a conductor 488b in contact with the conductor 487b, and a conductor 488c in contact with the conductor 487c are provided.
  • the insulator 467 includes an opening reaching the conductor 488a and an opening reaching the conductor 488b.
  • a conductor 490a or a conductor 490b is embedded in each opening.
  • the conductor 488c is in contact with the conductor 494 of one electrode of the capacitor 3400.
  • a conductor 489a in contact with the conductor 490a and a conductor 489b in contact with the conductor 490b are provided over the insulator 467.
  • the insulator 469 includes an opening reaching the conductor 489a, an opening reaching the conductor 489b, and an opening reaching the conductor 496 which is the other electrode of the capacitor 3400.
  • a conductor 491a, a conductor 491b, or a conductor 491c is embedded in each opening.
  • a conductor 492a in contact with the conductor 491a, a conductor 492b in contact with the conductor 491b, and a conductor 492c in contact with the conductor 491c are provided.
  • Examples of the insulating material 469 and the insulator 498 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.
  • the body may be used in a single layer or a stack.
  • the insulator 401 aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or oxide Tantalum may be used.
  • One or more of 469 or the insulator 498 preferably includes an insulator having a function of blocking impurities such as hydrogen and oxygen.
  • an insulator having a function of blocking impurities such as hydrogen and oxygen is provided in the vicinity of the transistor 3300, electrical characteristics of the transistor 3300 can be stabilized.
  • Examples of the insulator having a function of blocking impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, and lanthanum.
  • An insulator containing neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.
  • a conductor containing one or more of copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten may be used in a single layer or a stacked layer.
  • it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.
  • An oxide semiconductor is preferably used as the semiconductor 406b.
  • silicon including strained silicon
  • germanium silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like may be used.
  • an oxide including one or more elements other than oxygen included in the semiconductor 406b or two or more elements is preferably used.
  • silicon including strained silicon
  • germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like may be used.
  • the source or the drain of the transistor 3200 includes a conductor 480a, a conductor 478a, a conductor 476a, a conductor 479a, a conductor 477a, a conductor 484a, a conductor 483a, a conductor 485a, and a conductor 483e is electrically connected to a conductor which is one of a source electrode and a drain electrode of the transistor 3300.
  • the conductor 454 that is a gate electrode of the transistor 3200 includes a conductor 480c, a conductor 478c, a conductor 476c, a conductor 479c, a conductor 477c, a conductor 484c, a conductor 483c, and a conductor 483c. It is electrically connected to a conductor which is the other of the source electrode and the drain electrode of the transistor 3300 through the body 485c and the conductor 483f.
  • the capacitor 3400 is electrically connected to one of a source electrode and a drain electrode of the transistor 3300, the conductor 483f, the conductor 485c, the conductor 487c, and the conductor 488c.
  • a conductor 494 which is one of the electrodes, an insulator 498, and a conductor 496 which is the other electrode of the capacitor 3400. Note that it is preferable that the capacitor 3400 be formed above or below the transistor 3300 because the size of the semiconductor device can be reduced.
  • the transistor 3300 over the transistor 3200 and the capacitor 3400 over the transistor 3300 are described in this embodiment, one or more transistors including a semiconductor similar to the transistor 330 are included over the transistor 3200. It does not matter even if it has a configuration.
  • the capacitor 3400 may be provided over the transistor 3200 and the transistor 3300 may be provided over the capacitor 3400. With such a structure, the degree of integration of the semiconductor device can be further increased (see FIG. 50).
  • FIG. 9 For other structures, the description of FIG. 9 and the like can be referred to as appropriate.
  • the semiconductor device illustrated in FIG. 48B is different from the semiconductor device illustrated in FIG. 48A in that the transistor 3200 is not provided. In this case as well, information writing and holding operations can be performed by operations similar to those of the semiconductor device illustrated in FIG.
  • the potential of one electrode of the capacitor 3400 is V
  • the capacitance of the capacitor 3400 is C
  • the capacitance component of the third wiring 3003 is CB
  • the potential of the third wiring 3003 is before the charge is redistributed.
  • the potential of the third wiring 3003 after the charge is redistributed is (CB ⁇ VB0 + C ⁇ V) / (CB + C). Therefore, when the potential of one electrode of the capacitor 3400 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell, the third wiring 3003 in the case where the potential V1 is held.
  • information can be read by comparing the potential of the third wiring 3003 with a predetermined potential.
  • a transistor to which the first semiconductor is applied is used as a driver circuit for driving the memory cell, and a transistor to which the second semiconductor is applied is stacked over the driver circuit as the transistor 3300. do it.
  • the semiconductor device described above can hold stored data for a long time by using a transistor with an off-state current that includes an oxide semiconductor. That is, a refresh operation is unnecessary or the frequency of the refresh operation can be extremely low, so that a semiconductor device with low power consumption can be realized.
  • stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).
  • the semiconductor device since the semiconductor device does not require a high voltage for writing information, the element hardly deteriorates.
  • the semiconductor device according to one embodiment of the present invention is a semiconductor device in which the number of rewritable times which is a problem in the conventional nonvolatile memory is not limited and the reliability is drastically improved. Further, since data is written depending on the conductive state and non-conductive state of the transistor, high-speed operation is possible. This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.
  • FIGS. 51A and 51B are cross-sectional views of a semiconductor device of one embodiment of the present invention.
  • 51A, the X1-X2 direction indicates the channel length direction
  • FIG. 51B the Y1-Y2 direction indicates the channel width direction.
  • the semiconductor device illustrated in FIGS. 51A and 51B includes a transistor 2200 using a first semiconductor material in a lower portion and a transistor 2100 using a second semiconductor material in an upper portion.
  • FIGS. 51A and 51B illustrate an example in which the transistor illustrated in FIGS. 9A and 9B is used as the transistor 2100 including the second semiconductor material.
  • the first semiconductor material and the second semiconductor material are preferably materials having different band gaps.
  • the first semiconductor material is a semiconductor material other than an oxide semiconductor (silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductor, etc.
  • the second semiconductor material can be an oxide semiconductor.
  • a transistor using single crystal silicon or the like as a material other than an oxide semiconductor can easily operate at high speed.
  • a transistor including an oxide semiconductor is used as the transistor described in the above embodiment, excellent subthreshold characteristics can be obtained and the transistor can be a minute transistor. Further, since the switch speed is high, high speed operation is possible, and since the off current is low, the leakage current is small.
  • the transistor 2200 may be either an n-channel transistor or a p-channel transistor, and an appropriate transistor may be used depending on a circuit.
  • the specific structure of the semiconductor device, such as a material and a structure used, is not necessarily limited to that described here.
  • the transistor 2100 is provided over the transistor 2200 with the insulator 2201, the insulator 2207, and the insulator 2208 provided therebetween.
  • a plurality of wirings 2202 are provided between the transistors 2200 and 2100.
  • wirings and electrodes provided in the upper layer and the lower layer are electrically connected by a plurality of plugs 2203 embedded in various insulators.
  • An insulator 2204 that covers the transistor 2100 and a wiring 2205 over the insulator 2204 are provided.
  • the area occupied by the circuit is reduced, and a plurality of circuits can be arranged at a higher density.
  • hydrogen in the insulator provided in the vicinity of the semiconductor film of the transistor 2200 terminates dangling bonds of silicon, and the reliability of the transistor 2200 is increased. There is an effect to improve.
  • hydrogen in the insulator provided in the vicinity of the semiconductor film of the transistor 2100 is one of the factors that generate carriers in the oxide semiconductor. In some cases, the reliability of the transistor 2100 may be reduced.
  • the transistor 2100 including an oxide semiconductor is stacked over the transistor 2200 including a silicon-based semiconductor material, it is particularly preferable to provide the insulator 2207 having a function of preventing hydrogen diffusion therebetween. It is effective. In addition to improving the reliability of the transistor 2200 by confining hydrogen in the lower layer with the insulator 2207, it is possible to simultaneously improve the reliability of the transistor 2100 by suppressing diffusion of hydrogen from the lower layer to the upper layer. it can.
  • the insulator 2207 for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.
  • aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used.
  • a block film having a function of preventing hydrogen diffusion is preferably formed over the transistor 2100 so as to cover the transistor 2100 including the oxide semiconductor film.
  • a material similar to that of the insulator 2207 can be used, and aluminum oxide is particularly preferably used.
  • excess oxygen can be added to a lower insulator during the film formation, and the excess oxygen is transferred to the oxide semiconductor layer of the transistor 2100 by a thermal process, so that defects in the oxide semiconductor layer are removed. There is an effect to repair.
  • the aluminum oxide film has a high blocking effect that prevents the film from permeating both impurities such as hydrogen and moisture and oxygen.
  • the block film may be used by stacking the insulators 2204 or may be provided below the insulators 2204.
  • the transistor 2200 can be a transistor of various types as well as a planar transistor.
  • a transistor of FIN (fin) type, TRI-GATE (trigate) type, or the like can be used. Examples of cross-sectional views in that case are shown in FIGS. 51 (E) and (F).
  • An insulator 2212 is provided over the semiconductor substrate 2211.
  • the semiconductor substrate 2211 has a convex portion (also referred to as a fin) with a thin tip. Note that an insulator may be provided on the convex portion. The insulator functions as a mask for preventing the semiconductor substrate 2211 from being etched when the convex portion is formed.
  • the convex part does not need to have a thin tip, for example, it may be a substantially rectangular parallelepiped convex part or a thick convex part.
  • a gate insulator 2214 is provided on the convex portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided thereon.
  • a source region and a drain region 2215 are formed in the semiconductor substrate 2211. Note that although the example in which the semiconductor substrate 2211 includes a convex portion is described here, the semiconductor device according to one embodiment of the present invention is not limited thereto. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion.
  • FIG. 51C shows a structure of a so-called CMOS circuit in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and gates thereof are connected.
  • FIG. 51D A circuit diagram illustrated in FIG. 51D illustrates a structure in which the sources and drains of the transistors 2100 and 2200 are connected to each other. With such a configuration, it can function as a so-called analog switch.
  • This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.
  • FIG. 52 is a block diagram illustrating a configuration example of a CPU in which some of the above-described transistors are used.
  • ALU 1191 arithmetic logic unit (ALU)
  • ALU controller 1192 an instruction decoder 1193
  • an interrupt controller 1194 an interrupt controller 1194
  • timing controller 1195 a register 1196
  • register controller 1197 a register controller 1197
  • bus interface 1198 a bus interface 1198.
  • a rewritable ROM 1199 and a ROM interface 1189 As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used.
  • the ROM 1199 and the ROM interface 1189 may be provided in separate chips.
  • the CPU illustrated in FIG. 52 is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application. For example, the configuration including the CPU or the arithmetic circuit illustrated in FIG.
  • the CPU 52 may be a single core, and a plurality of the cores may be included, and each core may operate in parallel. Further, the number of bits that the CPU can handle with the internal arithmetic circuit or the data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, or the like.
  • Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.
  • the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191.
  • the interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program.
  • the register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.
  • a memory cell is provided in the register 1196.
  • the above-described transistor, memory device, or the like can be used as the memory cell of the register 1196.
  • the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, whether to hold data by a flip-flop or to hold data by a capacitor in a memory cell included in the register 1196 is selected. When data retention by the flip-flop is selected, the power supply voltage is supplied to the memory cell in the register 1196. When holding of data in the capacitor is selected, data is rewritten to the capacitor and supply of power supply voltage to the memory cells in the register 1196 can be stopped.
  • FIG. 53 is an example of a circuit diagram of a memory element that can be used as the register 1196.
  • the memory element 1200 includes a circuit 1201 in which stored data is volatilized by power-off, a circuit 1202 in which stored data is not volatilized by power-off, a switch 1203, a switch 1204, a logic element 1206, and a capacitor 1207. Circuit 1220 having.
  • the circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210.
  • the memory element 1200 may further include other elements such as a diode, a resistance element, and an inductor, as necessary.
  • the memory device described above can be used for the circuit 1202.
  • GND (0 V) or a potential at which the transistor 1209 is turned off is continuously input to the gate of the transistor 1209 of the circuit 1202.
  • the gate of the transistor 1209 is grounded through a load such as a resistor.
  • the switch 1203 is configured using a transistor 1213 of one conductivity type (eg, n-channel type), and the switch 1204 is configured using a transistor 1214 of conductivity type (eg, p-channel type) opposite to the one conductivity type.
  • a transistor 1213 of one conductivity type eg, n-channel type
  • the switch 1204 is configured using a transistor 1214 of conductivity type (eg, p-channel type) opposite to the one conductivity type.
  • the first terminal of the switch 1203 corresponds to one of the source and the drain of the transistor 1213
  • the second terminal of the switch 1203 corresponds to the other of the source and the drain of the transistor 1213
  • the switch 1203 corresponds to the gate of the transistor 1213.
  • conduction or non-conduction between the first terminal and the second terminal that is, the conduction state or non-conduction state of the transistor 1213 is selected.
  • the first terminal of the switch 1204 corresponds to one of the source and the drain of the transistor 1214
  • the second terminal of the switch 1204 corresponds to the other of the source and the drain of the transistor 1214
  • the switch 1204 is input to the gate of the transistor 1214.
  • the control signal RD selects the conduction or non-conduction between the first terminal and the second terminal (that is, the conduction state or non-conduction state of the transistor 1214).
  • One of a source and a drain of the transistor 1209 is electrically connected to one of a pair of electrodes of the capacitor 1208 and a gate of the transistor 1210.
  • the connection part is referred to as a node M2.
  • One of a source and a drain of the transistor 1210 is electrically connected to a wiring that can supply a low power supply potential (eg, a GND line), and the other is connected to the first terminal of the switch 1203 (the source and the drain of the transistor 1213 On the other hand).
  • a second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is electrically connected to a first terminal of the switch 1204 (one of the source and the drain of the transistor 1214).
  • a second terminal of the switch 1204 (the other of the source and the drain of the transistor 1214) is electrically connected to a wiring that can supply the power supply potential VDD.
  • a second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213), a first terminal of the switch 1204 (one of a source and a drain of the transistor 1214), an input terminal of the logic element 1206, and the capacitor 1207
  • One of the pair of electrodes is electrically connected.
  • the connection part is referred to as a node M1.
  • the other of the pair of electrodes of the capacitor 1207 can be configured to receive a constant potential. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input.
  • the other of the pair of electrodes of the capacitor 1207 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential.
  • the other of the pair of electrodes of the capacitor 1208 can have a constant potential.
  • a low power supply potential such as GND
  • a high power supply potential such as VDD
  • the other of the pair of electrodes of the capacitor 1208 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential.
  • the capacitor 1207 and the capacitor 1208 can be omitted by positively using a parasitic capacitance of a transistor or a wiring.
  • a control signal WE is input to a first gate (first gate electrode) of the transistor 1209.
  • the switch 1203 and the switch 1204 are selected to be in a conductive state or a non-conductive state between the first terminal and the second terminal by a control signal RD different from the control signal WE.
  • the terminals of the other switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state.
  • FIG. 53 illustrates an example in which the signal output from the circuit 1201 is input to the other of the source and the drain of the transistor 1209.
  • a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is an inverted signal obtained by inverting the logic value by the logic element 1206 and is input to the circuit 1201 through the circuit 1220. .
  • FIG. 53 illustrates an example in which a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is input to the circuit 1201 through the logic element 1206 and the circuit 1220. It is not limited to. A signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) may be input to the circuit 1201 without inversion of the logical value. For example, when there is a node in the circuit 1201 that holds a signal in which the logical value of the signal input from the input terminal is inverted, the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) An output signal can be input to the node.
  • a transistor other than the transistor 1209 among the transistors used for the memory element 1200 can be a film formed of a semiconductor other than an oxide semiconductor or a channel in the substrate 1190.
  • a transistor in which a channel is formed in a silicon film or a silicon substrate can be used.
  • all the transistors used for the memory element 1200 can be transistors whose channels are formed using an oxide semiconductor.
  • the memory element 1200 may include a transistor whose channel is formed using an oxide semiconductor in addition to the transistor 1209, and the remaining transistors are formed using a semiconductor layer other than the oxide semiconductor or the substrate 1190. It can also be a transistor.
  • a flip-flop circuit can be used.
  • the logic element 1206 for example, an inverter, a clocked inverter, or the like can be used.
  • data stored in the circuit 1201 can be held by the capacitor 1208 provided in the circuit 1202 while the power supply voltage is not supplied to the memory element 1200.
  • a transistor in which a channel is formed in an oxide semiconductor has extremely low off-state current.
  • the off-state current of a transistor in which a channel is formed in an oxide semiconductor is significantly lower than the off-state current of a transistor in which a channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 1209, the signal held in the capacitor 1208 is maintained for a long time even when the power supply voltage is not supplied to the memory element 1200. In this manner, the memory element 1200 can hold stored data (data) even while the supply of power supply voltage is stopped.
  • the memory element is characterized by performing a precharge operation; therefore, after the supply of power supply voltage is resumed, the time until the circuit 1201 retains the original data again is shortened. be able to.
  • the signal held by the capacitor 1208 is input to the gate of the transistor 1210. Therefore, after the supply of the power supply voltage to the memory element 1200 is restarted, the state (conductive state or nonconductive state) of the transistor 1210 is determined in accordance with the signal held by the capacitor 1208, and data can be read from the circuit 1202. it can. Therefore, the original signal can be accurately read even if the potential corresponding to the signal held in the capacitor 1208 slightly fluctuates.
  • a storage element 1200 for a storage device such as a register or a cache memory included in the processor, loss of data in the storage device due to stop of supply of power supply voltage can be prevented.
  • the state before the power supply stop can be restored in a short time. Accordingly, power can be stopped in a short time in the entire processor or in one or a plurality of logic circuits constituting the processor, so that power consumption can be suppressed.
  • the storage element 1200 has been described as an example of using the CPU, the storage element 1200 can be applied to an LSI such as a DSP (Digital Signal Processor), a custom LSI, a PLD (Programmable Logic Device), or an RF-Tag (Radio Frequency Tag). It is.
  • LSI Digital Signal Processor
  • PLD Programmable Logic Device
  • RF-Tag Radio Frequency Tag
  • FIG. 54A is a top view illustrating an example of an imaging device 200 according to one embodiment of the present invention.
  • the imaging device 200 includes a pixel unit 210, a peripheral circuit 260 for driving the pixel unit 210, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290.
  • the pixel unit 210 includes a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more).
  • the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 are connected to the plurality of pixels 211 and have a function of supplying signals for driving the plurality of pixels 211, respectively.
  • peripheral circuit 260 the peripheral circuit 270, the peripheral circuit 280, the peripheral circuit 290, and the like are all referred to as “peripheral circuits” or “driving circuits” in some cases.
  • peripheral circuit 260 can be said to be part of the peripheral circuit.
  • the imaging apparatus 200 preferably includes a light source 291.
  • the light source 291 can emit the detection light P1.
  • the peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, and a conversion circuit.
  • the peripheral circuit may be manufactured over a substrate over which the pixel portion 210 is formed. Further, a semiconductor device such as an IC chip may be used for part or all of the peripheral circuit. Note that one or more of the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 may be omitted from the peripheral circuit.
  • the pixel 211 may be inclined and arranged in the pixel portion 210 included in the imaging device 200.
  • the pixel interval (pitch) in the row direction and the column direction can be shortened. Thereby, the quality of imaging in the imaging apparatus 200 can be further improved.
  • a single pixel 211 included in the imaging apparatus 200 is configured by a plurality of sub-pixels 212, and a color image display is realized by combining each sub-pixel 212 with a filter (color filter) that transmits light in a specific wavelength band. Information can be acquired.
  • FIG. 55A is a top view illustrating an example of the pixel 211 for acquiring a color image.
  • a pixel 211 illustrated in FIG. 55A includes a sub-pixel 212 (hereinafter also referred to as “sub-pixel 212R”) provided with a color filter that transmits light in the red (R) wavelength band, and a green (G) wavelength.
  • Sub-pixel 212 (hereinafter also referred to as “sub-pixel 212G”) provided with a color filter that transmits light in the band and sub-pixel 212 (hereinafter referred to as “color filter” that transmits light in the blue (B) wavelength band.
  • B blue
  • sub-pixel 212B also referred to as “sub-pixel 212B”.
  • the sub-pixel 212 can function as a photosensor.
  • the subpixel 212 (subpixel 212R, subpixel 212G, and subpixel 212B) is electrically connected to the wiring 231, the wiring 247, the wiring 248, the wiring 249, and the wiring 250. Further, the sub-pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 253.
  • the wiring 248, the wiring 249, and the wiring 250 connected to the pixel 211 in the n-th row are respectively referred to as a wiring 248 [n], a wiring 249 [n], and a wiring 250 [n].
  • the wiring 253 connected to the pixel 211 in the m-th column is referred to as a wiring 253 [m].
  • the wiring 253 connected to the subpixel 212R included in the pixel 211 in the m-th column is the wiring 253 [m] R
  • the wiring 253 connected to the subpixel 212G is the wiring 253 [m] G
  • a wiring 253 connected to the subpixel 212B is described as a wiring 253 [m] B.
  • the subpixel 212 is electrically connected to a peripheral circuit through the wiring.
  • the imaging apparatus 200 has a configuration in which subpixels 212 provided with color filters that transmit light in the same wavelength band of adjacent pixels 211 are electrically connected via a switch.
  • the sub-pixel 212 included in the pixel 211 arranged in n rows (n is an integer of 1 to p) and m columns (m is an integer of 1 to q) is adjacent to the pixel 211.
  • a connection example of the sub-pixel 212 included in the pixel 211 arranged in n + 1 rows and m columns is shown.
  • a subpixel 212R arranged in n rows and m columns and a subpixel 212R arranged in n + 1 rows and m columns are connected via a switch 201.
  • sub-pixel 212G arranged in n rows and m columns and the sub-pixel 212G arranged in n + 1 rows and m columns are connected via a switch 202.
  • sub-pixel 212B arranged in n rows and m columns and the sub-pixel 212B arranged in n + 1 rows and m columns are connected via a switch 203.
  • the color filter used for the sub-pixel 212 is not limited to red (R), green (G), and blue (B), and transmits cyan (C), yellow (Y), and magenta (M) light, respectively.
  • a color filter may be used.
  • a full color image can be acquired by providing the sub-pixel 212 that detects light of three different wavelength bands in one pixel 211.
  • a color filter that transmits yellow (Y) light is provided in addition to the sub-pixel 212 provided with a color filter that transmits red (R), green (G), and blue (B) light.
  • a color filter that transmits yellow (Y) light is provided in addition to the sub-pixel 212 provided with a color filter that transmits cyan (C), yellow (Y), and magenta (M) light.
  • a color filter that transmits blue (B) light is provided.
  • a pixel 211 having a sub-pixel 212 may be used.
  • the sub-pixel 212 that detects light in the red wavelength band, the sub-pixel 212 that detects light in the green wavelength band, and the sub-pixel 212 that detects light in the blue wavelength band may not be 1: 1: 1.
  • the number of subpixels 212 provided in the pixel 211 may be one, but two or more are preferable. For example, by providing two or more subpixels 212 that detect light in the same wavelength band, redundancy can be increased and the reliability of the imaging apparatus 200 can be increased.
  • IR Infrared
  • ND Neutral Density filter
  • a lens may be provided in the pixel 211.
  • the photoelectric conversion element provided in the sub-pixel 212 can receive incident light efficiently.
  • the light 256 is supplied to the photoelectric conversion element 220 through the lens 255, the filter 254 (filter 254R, the filter 254G, and the filter 254B) formed in the pixel 211, the pixel circuit 230, and the like. It can be set as the structure made to enter.
  • part of the light 256 indicated by the arrow may be blocked by part of the wiring 257. Therefore, a structure in which a lens 255 and a filter 254 are disposed on the photoelectric conversion element 220 side as illustrated in FIG. 56B so that the photoelectric conversion element 220 receives light 256 efficiently is preferable.
  • a photoelectric conversion element in which a pn-type junction or a pin-type junction is formed may be used.
  • the photoelectric conversion element 220 may be formed using a substance having a function of generating charges by absorbing radiation.
  • the substance having a function of absorbing radiation and generating a charge include selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, and cadmium zinc alloy.
  • the photoelectric conversion element 220 when selenium is used for the photoelectric conversion element 220, the photoelectric conversion element 220 having a light absorption coefficient over a wide wavelength band such as X-rays and gamma rays in addition to visible light, ultraviolet light, and infrared light can be realized.
  • a wide wavelength band such as X-rays and gamma rays in addition to visible light, ultraviolet light, and infrared light
  • one pixel 211 included in the imaging apparatus 200 may include a sub-pixel 212 including a first filter in addition to the sub-pixel 212 illustrated in FIG.
  • 57A and 57B are cross-sectional views of elements included in the imaging device.
  • An imaging device illustrated in FIG. 57A includes a transistor 351 using silicon provided over a silicon substrate 300, transistors 353 and 354 using oxide semiconductors stacked over the transistor 351, and a silicon substrate. 300 includes a photodiode 360 having an anode 361 and a cathode 362. Each transistor and photodiode 360 has electrical connection with various plugs 370 and wirings 371. Further, the anode 361 of the photodiode 360 is electrically connected to the plug 370 through the low resistance region 363.
  • the imaging device is provided in contact with the layer 305 including the transistor 351 and the photodiode 360 provided over the silicon substrate 300, the layer 320 including the wiring 371, and the layer 320 including the wiring 371.
  • a layer 331 including the transistor 354 and a layer 340 provided in contact with the layer 331 and including a wiring 372 and a wiring 373.
  • the light-receiving surface of the photodiode 360 is provided on the surface of the silicon substrate 300 opposite to the surface on which the transistor 351 is formed. With this configuration, an optical path can be secured without being affected by various transistors and wirings. Therefore, a pixel with a high aperture ratio can be formed. Note that the light receiving surface of the photodiode 360 may be the same as the surface on which the transistor 351 is formed.
  • the layer 305 may be a layer including a transistor including an oxide semiconductor.
  • the layer 305 may be omitted, and the pixel may be formed using only a transistor including an oxide semiconductor.
  • the photodiode 360 provided in the layer 305 and the transistor provided in the layer 331 can be formed to overlap with each other. Then, the integration degree of pixels can be increased. That is, the resolution of the imaging device can be increased.
  • the imaging device can have a structure in which a photodiode 365 is provided over a transistor on the layer 340 side.
  • the layer 305 includes a transistor 351 and a transistor 352 using silicon
  • the layer 320 includes a wiring 371
  • the layer 331 includes a transistor 353 including an oxide semiconductor layer.
  • the transistor 354 includes a photodiode 365 in the layer 340
  • the photodiode 365 includes a semiconductor layer 366, a semiconductor layer 367, and a semiconductor layer 368, and includes a wiring 373 and a wiring through a plug 370. 374 is electrically connected.
  • the aperture ratio can be increased.
  • the photodiode 365 a pin-type diode element using an amorphous silicon film, a microcrystalline silicon film, or the like may be used.
  • the photodiode 365 has a structure in which an n-type semiconductor layer 368, an i-type semiconductor layer 367, and a p-type semiconductor layer 366 are sequentially stacked.
  • Amorphous silicon is preferably used for the i-type semiconductor layer 367.
  • amorphous silicon, microcrystalline silicon, or the like containing a dopant imparting each conductivity type can be used.
  • the photodiode 365 using amorphous silicon as a photoelectric conversion layer has high sensitivity in the wavelength region of visible light and can easily detect weak visible light.
  • an insulator 380 is provided between the layer 305 including the transistor 351 and the photodiode 360 and the layer 331 including the transistor 353 and the transistor 354.
  • the position of the insulator 380 is not limited.
  • Hydrogen in the insulator provided in the vicinity of the channel formation region of the transistor 351 has an effect of terminating the dangling bond of silicon and improving the reliability of the transistor 351.
  • hydrogen in the insulator provided in the vicinity of the transistor 353, the transistor 354, and the like is one of the factors that generate carriers in the oxide semiconductor. Therefore, the reliability of the transistor 353, the transistor 354, and the like may be reduced. Therefore, in the case where a transistor including an oxide semiconductor is stacked over a transistor including a silicon-based semiconductor, an insulator 380 having a function of blocking hydrogen is preferably provided therebetween. By confining hydrogen below the insulator 380, the reliability of the transistor 351 can be improved.
  • the insulator 381 over the transistors 353 and 354 because diffusion of oxygen in the oxide semiconductor can be prevented.
  • the RF tag in this embodiment has a storage circuit inside, stores necessary information in the storage circuit, and exchanges information with the outside using non-contact means, for example, wireless communication. Because of these characteristics, the RF tag can be used in an individual authentication system that identifies an article by reading individual information about the article. Note that extremely high reliability is required for use in these applications.
  • FIG. 58 is a block diagram illustrating a configuration example of an RF tag.
  • the RF tag 800 includes an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communication device 801 (also referred to as an interrogator or a reader / writer).
  • the RF tag 800 includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a storage circuit 810, and a ROM 811.
  • a material that can sufficiently suppress a reverse current such as an oxide semiconductor, may be used for the transistor including the rectifying action included in the demodulation circuit 807.
  • action resulting from a reverse current can be suppressed, and it can prevent that the output of a demodulation circuit is saturated. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linear.
  • the RF tag 800 described in this embodiment can be used for any of the methods.
  • the antenna 804 is for transmitting and receiving a radio signal 803 to and from the antenna 802 connected to the communication device 801. Further, the rectifier circuit 805 rectifies an input AC signal generated by receiving a radio signal by the antenna 804, for example, half-wave double voltage rectification, and the signal rectified by a capacitive element provided in the subsequent stage. It is a circuit for generating an input potential by smoothing. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling not to input more than a certain amount of power to a subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large.
  • the constant voltage circuit 806 is a circuit for generating a stable power supply voltage from the input potential and supplying it to each circuit. Note that the constant voltage circuit 806 may include a reset signal generation circuit.
  • the reset signal generation circuit is a circuit for generating a reset signal of the logic circuit 809 using a stable rise of the power supply voltage.
  • the demodulation circuit 807 is a circuit for demodulating an input AC signal by detecting an envelope and generating a demodulated signal.
  • the modulation circuit 808 is a circuit for performing modulation in accordance with data output from the antenna 804.
  • a logic circuit 809 is a circuit for analyzing and processing the demodulated signal.
  • the memory circuit 810 is a circuit that holds input information and includes a row decoder, a column decoder, a storage area, and the like.
  • the ROM 811 is a circuit for storing a unique number (ID) or the like and outputting it according to processing.
  • the memory circuit described in the above embodiment can be used for the memory circuit 810. Since the memory circuit of one embodiment of the present invention can retain information even when the power is turned off, the memory circuit can be preferably used for an RF tag. Further, the memory circuit of one embodiment of the present invention does not cause a difference in maximum communication distance between data reading and writing because power (voltage) necessary for data writing is significantly smaller than that of a conventional nonvolatile memory. It is also possible. Furthermore, it is possible to suppress the occurrence of malfunction or erroneous writing due to insufficient power during data writing.
  • the memory circuit of one embodiment of the present invention can also be applied to the ROM 811 because it can be used as a nonvolatile memory.
  • the producer separately prepares a command for writing data in the ROM 811 so that the user cannot freely rewrite the command.
  • By shipping the product after the producer writes the unique number before shipping it is possible to assign a unique number only to the good products to be shipped, rather than assigning a unique number to all the produced RF tags, The unique number of the product after shipment does not become discontinuous, and customer management corresponding to the product after shipment becomes easy.
  • a liquid crystal element also referred to as a liquid crystal display element
  • a light-emitting element also referred to as a light-emitting display element
  • the light-emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electroluminescence), organic EL, and the like.
  • a display device using an EL element an EL display device
  • a display device using a liquid crystal element a liquid crystal display device
  • the display device described above includes a panel in which the display element is sealed, and a module in which an IC or the like including a controller is mounted on the panel.
  • the display device described below indicates an image display device or a light source (including a lighting device).
  • ICs integrated circuits
  • COG Chip on Glass
  • a module with a FPC (Flexible Printed Circuits), TCP (Tape Carrier Package), a module having a printed wiring board at the end of TCP, or a display element ) Shall be included in the display device.
  • FIG. 59 illustrates an example of an EL display device according to one embodiment of the present invention.
  • FIG. 59A shows a circuit diagram of a pixel of an EL display device.
  • FIG. 59B is a top view showing the entire EL display device.
  • FIG. 59C is an MN cross section corresponding to part of the dashed-dotted line MN in FIG.
  • FIG. 59A is an example of a concave view of a pixel used in the EL display device.
  • An EL display device illustrated in FIG. 59A includes a switch element 743, a transistor 741, a capacitor 742, and a light-emitting element 719.
  • FIG. 59A and the like illustrate an example of a circuit configuration, and thus transistors can be added.
  • transistors it is also possible not to add a transistor, a switch, a passive element, or the like at each node in FIG.
  • a gate of the transistor 741 is electrically connected to one end of the switch element 743 and one electrode of the capacitor 742.
  • a source of the transistor 741 is electrically connected to the other electrode of the capacitor 742 and electrically connected to one electrode of the light-emitting element 719.
  • a power supply potential VDD is supplied to a drain of the transistor 741.
  • the other end of the switch element 743 is electrically connected to the signal line 744.
  • a constant potential is applied to the other electrode of the light-emitting element 719. Note that the constant potential is set to the ground potential GND or lower.
  • a transistor is preferably used as the switch element 743.
  • the area of a pixel can be reduced and an EL display device with high resolution can be obtained.
  • the productivity of the EL display device can be increased. Note that as the transistor 741 and / or the switch element 743, for example, a transistor illustrated in FIG. 9 or the like can be used.
  • FIG. 59B is a top view of the EL display device.
  • the EL display device includes a substrate 700, a substrate 750, a sealant 734, a driver circuit 735, a driver circuit 736, a pixel 737, and an FPC 732.
  • the sealant 734 is disposed between the substrate 700 and the substrate 750 so as to surround the pixel 737, the drive circuit 735, and the drive circuit 736. Note that the drive circuit 735 and / or the drive circuit 736 may be disposed outside the sealant 734.
  • FIG. 59C is a cross-sectional view of the EL display device corresponding to part of the dashed-dotted line MN in FIG.
  • FIG. 59C illustrates a region where the transistor 741 includes an insulator 712a over a substrate 700 and a conductor 704a, and is over the insulator 712a and the conductor 704a and partially overlaps with the conductor 704a.
  • a structure including an insulator 706c in contact with the upper surface of the semiconductor 706b, an insulator 718b over the insulator 706c, and a conductor 714a disposed over the semiconductor 706b with the insulator 718b and the insulator 706c interposed therebetween is shown. Note that the structure of the transistor 741 is an example, and a structure different from the structure illustrated in FIG. 59C may be employed.
  • the conductor 704a functions as a gate electrode
  • the insulator 712a functions as a gate insulator
  • the conductor 716a1 functions as a drain electrode
  • the conductor 716a2 functions as a source electrode
  • the insulator 718b functions as a gate insulator
  • the conductor 714a functions as a gate electrode.
  • the electrical characteristics of the insulator 706a, the semiconductor 706b, and the insulator 706c may fluctuate when exposed to light. Therefore, it is preferable that at least one of the conductor 704a, the conductor 716a1, the conductor 716a2, and the conductor 714a has a light-blocking property.
  • an insulator 706d which is over the conductor 704b over the substrate 700 and partially overlaps with the conductor 704b, a semiconductor 706e over the insulator 706d, and a semiconductor 706e
  • the conductors 716a3 and 716a4 that are in contact with the upper surface of the semiconductor 706, the insulator 710 that is in contact with the upper surface of the conductor 716a3 and the upper surface of the conductor 716a4, the insulator 706f that is in contact with the upper surface of the semiconductor 706e, and the insulator 718b on the insulator 706f
  • a conductor 714b provided over the semiconductor 706e with the insulator 718b and the insulator 706f interposed therebetween.
  • the conductor 704b functions as one electrode and the conductor 714b functions as the other electrode.
  • the capacitor 742 can be manufactured using a film in common with the transistor 741.
  • the conductors 704a and 704b are preferably the same kind of conductors. In that case, the conductor 704a and the conductor 704b can be formed through the same process.
  • the conductors 714a and 714b are preferably the same kind of conductors. In that case, the conductor 714a and the conductor 714b can be formed through the same process.
  • a capacitor 742 illustrated in FIG. 59C is a capacitor having a large capacitance per occupied area. Accordingly, FIG. 59C illustrates an EL display device with high display quality. Note that the structure of the capacitor 742 is an example, and a structure different from the structure illustrated in FIG. 59C may be used.
  • An insulator 728 is provided over the transistor 741 and the capacitor 742, and an insulator 720 is provided over the insulator 728.
  • the insulator 728 and the insulator 720 may have an opening reaching the conductor 716a2 functioning as a source electrode of the transistor 741.
  • a conductor 781 is provided over the insulator 720. The conductor 781 may be electrically connected to the transistor 741 through the openings of the insulator 728 and the insulator 720. The conductor 781 may be electrically connected to one electrode of the capacitor 742 through the openings of the insulator 728 and the insulator 720.
  • a partition 784 having an opening reaching the conductor 781 is provided over the conductor 781.
  • a light-emitting layer 782 that is in contact with the conductor 781 through the opening of the partition 784 is provided over the partition 784.
  • a conductor 783 is provided over the light-emitting layer 782.
  • a region where the conductor 781, the light emitting layer 782, and the conductor 783 overlap with each other serves as the light emitting element 719.
  • the FPC 732 is connected to a wiring 733a through a terminal 731.
  • the conductor 733a may be formed using the same kind of conductor or semiconductor as the conductor or semiconductor included in the transistor 741.
  • FIG. 60A is a circuit diagram illustrating a configuration example of a pixel of a liquid crystal display device.
  • a pixel illustrated in FIG. 60A includes a transistor 751, a capacitor 752, and an element (liquid crystal element) 753 in which liquid crystal is filled between a pair of electrodes.
  • one of a source and a drain is electrically connected to the signal line 755 and a gate is electrically connected to the scanning line 754.
  • one electrode is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode is electrically connected to a wiring for supplying a common potential.
  • one electrode is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode is electrically connected to a wiring for supplying a common potential.
  • the common potential applied to the wiring to which the other electrode of the capacitor 752 is electrically connected may be different from the common potential applied to the other electrode of the liquid crystal element 753.
  • the top view of the liquid crystal display device is the same as that of the EL display device.
  • a cross-sectional view of the liquid crystal display device corresponding to the dashed-dotted line MN in FIG. 59B is illustrated in FIG.
  • the FPC 732 is connected to a wiring 733a through a terminal 731.
  • the wiring 733a may be formed using the same kind of conductor or semiconductor as the conductor or semiconductor included in the transistor 751.
  • FIG. 60B illustrates a structure of the capacitor 752 corresponding to the capacitor 742 in FIG. 59C; however, the structure is not limited thereto.
  • An insulator 721 and an insulator 728 are provided over the transistor 751 and the capacitor 752.
  • the insulator 721 and the insulator 728 have an opening reaching the transistor 751.
  • a conductor 791 is provided over the insulator 721.
  • the conductor 791 is electrically connected to the transistor 751 through the openings of the insulator 721 and the insulator 728.
  • the conductor 791 is electrically connected to one electrode of the capacitor 752 through the openings of the insulator 721 and the insulator 728.
  • An insulator 792 functioning as an alignment film is provided over the conductor 791.
  • a liquid crystal layer 793 is provided over the insulator 792.
  • An insulator 794 functioning as an alignment film is provided over the liquid crystal layer 793.
  • a spacer 795 is provided over the insulator 794.
  • a conductor 796 is provided over the spacer 795 and the insulator 794.
  • a substrate 797 is provided over the conductor 796.
  • a display device including a capacitor with a small occupied area can be provided, or a display device with high display quality can be provided.
  • a high-definition display device can be provided.
  • a display element, a display device that is a device including a display element, a light-emitting element, and a light-emitting device that is a device including a light-emitting element have various forms or have various elements. Can do.
  • a display element, a display device, a light emitting element, or a light emitting device includes, for example, an EL element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element), an LED (white LED, red LED, green LED, blue LED, etc.) ), Transistor (transistor that emits light in response to current), electron-emitting device, liquid crystal device, electronic ink, electrophoretic device, grating light valve (GLV), plasma display panel (PDP), MEMS (micro electro mechanical system) ) Display device, digital micromirror device (DMD), DMS (digital micro shutter), IMOD (interferometric modulation) device, shutter type MEMS display device, optical interference type MEMS display device, electro Wetti Grayed element, a piezoelectric ceramic display, has at least one such display device using a carbon nanotube.
  • An example of a display device using an EL element is an EL display.
  • a display device using an electron-emitting device there is a field emission display (FED), a SED type flat display (SED: Surface-conduction Electron-emitter Display), or the like.
  • FED field emission display
  • SED SED type flat display
  • a display device using a liquid crystal element there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like.
  • An example of a display device using electronic ink or an electrophoretic element is electronic paper.
  • part or all of the pixel electrode may have a function as a reflective electrode.
  • part or all of the pixel electrode may have aluminum, silver, or the like.
  • a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.
  • Graphene or graphite may be a multilayer film in which a plurality of layers are stacked.
  • a nitride semiconductor such as an n-type GaN semiconductor having a crystal can be easily formed thereon.
  • a p-type GaN semiconductor having a crystal or the like can be provided thereon to form an LED.
  • an AlN layer may be provided between graphene or graphite and an n-type GaN semiconductor having a crystal.
  • the GaN semiconductor included in the LED may be formed by MOCVD. However, by providing graphene, the GaN semiconductor included in the LED can be formed by a sputtering method.
  • FIG. 61A is a block diagram of the semiconductor device 900.
  • the semiconductor device 900 includes a power supply circuit 901, a circuit 902, a voltage generation circuit 903, a circuit 904, a voltage generation circuit 905, and a circuit 906.
  • the power supply circuit 901 is a circuit that generates a reference voltage V ORG .
  • the voltage V ORG may be a plurality of voltages instead of a single voltage.
  • the voltage V ORG can be generated based on the voltage V 0 given from the outside of the semiconductor device 900.
  • the semiconductor device 900 can generate the voltage V ORG based on a single power supply voltage given from the outside. Therefore, the semiconductor device 900 can operate without applying a plurality of power supply voltages from the outside.
  • the circuits 902, 904, and 906 are circuits that operate with different power supply voltages.
  • the power supply voltage of the circuit 902 is a voltage applied based on the voltage V ORG and the voltage V SS (V ORG > V SS ).
  • the power supply voltage of the circuit 904 is a voltage applied based on the voltage V POG and the voltage V SS (V POG > V ORG ).
  • the power supply voltage of the circuit 906 is a voltage applied based on the voltage V ORG , the voltage V SS, and the voltage V NEG (V ORG > V SS > V NEG ). Note that if the voltage VSS is equal to the ground potential (GND), the types of voltages generated by the power supply circuit 901 can be reduced.
  • GND ground potential
  • the voltage generation circuit 903 is a circuit that generates the voltage V POG .
  • the voltage generation circuit 903 can generate the voltage V POG based on the voltage V ORG supplied from the power supply circuit 901. Therefore, the semiconductor device 900 including the circuit 904 can operate based on a single power supply voltage supplied from the outside.
  • the voltage generation circuit 905 is a circuit that generates a voltage V NEG .
  • the voltage generation circuit 905 can generate the voltage V NEG based on the voltage V ORG supplied from the power supply circuit 901. Therefore, the semiconductor device 900 including the circuit 906 can operate based on a single power supply voltage given from the outside.
  • FIG. 61B illustrates an example of a circuit 904 that operates at the voltage V POG
  • FIG. 61C illustrates an example of a waveform of a signal for operating the circuit 904.
  • the transistor 911 is illustrated.
  • Signal applied to the gate of the transistor 911 is generated, for example, based on the voltage V POG and voltage V SS.
  • the signal is a voltage V SS during operation of the conductive state of transistor 911 voltage V POG, during operation of the non-conductive state.
  • the voltage V POG is higher than the voltage V ORG as illustrated in FIG. Therefore, the transistor 911 can more reliably perform an operation of more reliably conducting between the source (S) and the drain (D).
  • the circuit 904 can be a circuit in which malfunctions are reduced.
  • FIG. 61D illustrates an example of a circuit 906 that operates at the voltage V NEG
  • FIG. 61E illustrates an example of a waveform of a signal for operating the circuit 906.
  • FIG. 61D illustrates a transistor 912 having a back gate.
  • Signal applied to the gate of the transistor 912 for example, generated based on the voltage V ORG and the voltage V SS.
  • the signal voltage V ORG during operation of the conductive state of transistor 911 is generated based on the voltage V SS during operation of a non-conductive state.
  • a signal given to the back gate of the transistor 912 is generated based on the voltage V NEG .
  • the voltage V NEG is smaller than the voltage V SS (GND) as illustrated in FIG. Therefore, the threshold voltage of the transistor 912 can be controlled to shift positively. Therefore, the transistor 912 can be more reliably turned off, and the current flowing between the source (S) and the drain (D) can be reduced.
  • the circuit 906 can be a circuit in which malfunctions are reduced and power consumption is reduced.
  • the voltage V NEG may be directly applied to the back gate of the transistor 912.
  • a signal to be supplied to the gate of the transistor 912 may be generated based on the voltage V ORG and the voltage V NEG and the signal may be supplied to the back gate of the transistor 912.
  • FIGS. 62A and 62B show modified examples of FIGS. 61D and 61E.
  • a transistor 922 whose conduction state can be controlled by the control circuit 921 is illustrated between the voltage generation circuit 905 and the circuit 906.
  • the transistor 922 is an n-channel OS transistor.
  • Control signal S BG control circuit 921 is output a signal for controlling the conduction state of the transistor 922.
  • transistors 912A and 912B included in the circuit 906 are OS transistors which are the same as the transistor 922.
  • control signal S BG is transistor 922 in a conducting state at the high level, the node N BG becomes voltage V NEG. Thereafter, when the control signal SBG is at a low level, the node NBG becomes electrically floating. Since the transistor 922 is an OS transistor, the off-state current is small. Therefore, even if the node NBG is electrically floating, the voltage V NEG once applied can be held.
  • FIG. 63A shows an example of a circuit configuration applicable to the voltage generation circuit 903 described above.
  • a voltage generation circuit 903 illustrated in FIG. 63A is a five-stage charge pump including diodes D1 to D5, capacitors C1 to C5, and an inverter INV.
  • the clock signal CLK is supplied to the capacitors C1 to C5 directly or via the inverter INV.
  • the power supply voltage of the inverter INV is a voltage applied based on the voltage V ORG and the voltage V SS
  • the voltage V POG boosted to a positive voltage five times the voltage V ORG is given by applying the clock signal CLK.
  • the forward voltage of the diodes D1 to D5 is 0V. Further, by changing the number of stages of the charge pump, it is possible to obtain a desired voltage V POG.
  • FIG. 63B shows an example of a circuit configuration applicable to the voltage generation circuit 905 described above.
  • a voltage generation circuit 905 illustrated in FIG. 63B is a four-stage charge pump including diodes D1 to D5, capacitors C1 to C5, and an inverter INV.
  • the clock signal CLK is supplied to the capacitors C1 to C5 directly or via the inverter INV.
  • the power supply voltage of the inverter INV is a voltage applied based on the voltage V ORG and the voltage V SS
  • the stepped down voltage V NEG can be obtained.
  • the forward voltage of the diodes D1 to D5 is 0V.
  • the desired voltage V NEG can be obtained by changing the number of stages of the charge pump.
  • circuit configuration of the voltage generation circuit 903 described above is not limited to the configuration of the circuit diagram illustrated in FIG. Modified examples of the voltage generation circuit 903 are illustrated in FIGS. 64A to 64C, 65A, and 65B.
  • a voltage generation circuit 903A illustrated in FIG. 64A includes transistors M1 to M10, capacitors C11 to C14, and an inverter INV1.
  • the clock signal CLK is supplied directly to the gates of the transistors M1 to M10 or via the inverter INV1.
  • a clock signal CLK By providing a clock signal CLK, and it is possible to obtain a voltage V POG boosted four times the positive voltage of the voltage V ORG.
  • a desired voltage V POG can be obtained by changing the number of stages.
  • a voltage generation circuit 903A illustrated in FIG. 64A can reduce off-state current by using the transistors M1 to M10 as OS transistors, and can suppress leakage of charges held in the capacitors C11 to C14. Therefore, the voltage V ORG can be efficiently boosted from the voltage V POG .
  • a voltage generation circuit 903B illustrated in FIG. 64B includes transistors M11 to M14, capacitors C15 and C16, and an inverter INV2.
  • the clock signal CLK is supplied directly to the gates of the transistors M11 to M14 or via the inverter INV2. By providing the clock signal CLK, it is possible to obtain a voltage V POG that is boosted to a positive voltage that is twice the voltage V ORG .
  • a voltage generation circuit 903B illustrated in FIG. 64B can reduce off-state current by using the transistors M11 to M14 as OS transistors, and can suppress leakage of charges held in the capacitors C15 and C16. Therefore, the voltage V ORG can be efficiently boosted from the voltage V POG .
  • a voltage generation circuit 903C illustrated in FIG. 64C includes an inductor I1, a transistor M15, a diode D6, and a capacitor C17.
  • the conduction state of the transistor M15 is controlled by the control signal EN.
  • a voltage V POG obtained by boosting the voltage V ORG can be obtained by the control signal EN. Since the voltage generation circuit 903C illustrated in FIG. 64C uses the inductor I1 to increase the voltage, the voltage generation circuit 903C can increase the voltage with high conversion efficiency.
  • a voltage generation circuit 903D illustrated in FIG. 65A corresponds to a structure in which the diodes D1 to D5 of the voltage generation circuit 903 illustrated in FIG. 63A are replaced with diode-connected transistors M16 to M20.
  • the voltage generation circuit 903D illustrated in FIG. 65A can reduce off-state current by using the transistors M16 to M20 as OS transistors, and can suppress leakage of charges held in the capacitors C1 to C5. Therefore, the voltage V ORG can be efficiently boosted from the voltage V POG .
  • a voltage generation circuit 903E illustrated in FIG. 65B corresponds to a structure in which the transistors M16 to M20 in the voltage generation circuit 903D illustrated in FIG. 65A are replaced with transistors M21 to M25 having back gates. Since the voltage generation circuit 903E illustrated in FIG. 65B can supply the same voltage as the gate to the back gate, the amount of current flowing through the transistor can be increased. Therefore, the voltage V ORG can be efficiently boosted from the voltage V POG .
  • Voltage generating circuit 905A shown in FIG. 66 (A) by providing a clock signal CLK, and it is possible to obtain a voltage V NEG stepped down from the voltage V SS to 3 times the negative voltage of the voltage V ORG.
  • the voltage generation circuits 905A to 905E shown in FIGS. 66A to 66C, 67A and 67B are shown in FIGS. 43A to 43C, 44A and 44B, respectively.
  • the voltage applied to each wiring is changed or the arrangement of elements is changed.
  • 66A to 66C, 67A, and 67B, as in the voltage generation circuits 903A to 903E, can be efficiently reduced from the voltage V ORG to the voltage V NEG .
  • the semiconductor device can reduce the type of power supply voltage applied from the outside.
  • a display module 6000 shown in FIG. 68 includes a touch panel 6004 connected to the FPC 6003, a display panel 6006 connected to the FPC 6005, a backlight unit 6007, a frame 6009, a printed circuit board 6010, between the upper cover 6001 and the lower cover 6002.
  • a battery 6011 is included. Note that the backlight unit 6007, the battery 6011, the touch panel 6004, and the like may not be provided.
  • the semiconductor device of one embodiment of the present invention can be used for, for example, the display panel 6006 or an integrated circuit mounted on a printed board.
  • the shapes and dimensions of the upper cover 6001 and the lower cover 6002 can be changed as appropriate in accordance with the sizes of the touch panel 6004 and the display panel 6006.
  • a resistive touch panel or a capacitive touch panel can be used by being superimposed on the display panel 6006.
  • the counter substrate (sealing substrate) of the display panel 6006 can have a touch panel function.
  • an optical sensor can be provided in each pixel of the display panel 6006 and an optical touch panel function can be added.
  • a touch sensor electrode may be provided in each pixel of the display panel 6006 to add a capacitive touch panel function.
  • the backlight unit 6007 has a light source 6008.
  • the light source 6008 may be provided at the end of the backlight unit 6007 and a light diffusing plate may be used.
  • the frame 6009 has a function as an electromagnetic shield for blocking electromagnetic waves generated from the printed board 6010 in addition to a protective function of the display panel 6006.
  • the frame 6009 may function as a heat sink.
  • the printed board 6010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal.
  • a power supply for supplying power to the power supply circuit an external commercial power supply or a battery 6011 provided separately may be used. Note that the battery 6011 can be omitted when a commercial power source is used.
  • the display module 6000 may be additionally provided with a member such as a polarizing plate, a retardation plate, and a prism sheet.
  • FIG. 69A is a perspective view showing a cross-sectional structure of a package using a lead frame type interposer.
  • a chip 551 corresponding to a semiconductor device according to one embodiment of the present invention is connected to a terminal 552 over the interposer 550 by a wire bonding method.
  • the terminal 552 is disposed on the surface on which the chip 551 of the interposer 550 is mounted.
  • the chip 551 may be sealed with a mold resin 553, but is sealed with a part of each terminal 552 exposed.
  • FIG. 69B shows the structure of a module of an electronic device (mobile phone) in which a package is mounted on a circuit board.
  • a package 602 and a battery 604 are mounted on a printed wiring board 601.
  • a printed wiring board 601 is mounted by an FPC 603 on a panel 600 provided with a display element.
  • An electronic device or a lighting device can be manufactured using the semiconductor device of one embodiment of the present invention.
  • a highly reliable electronic device or lighting device can be manufactured using the semiconductor device of one embodiment of the present invention.
  • an electronic device or a lighting device with improved detection sensitivity of a touch sensor can be manufactured using the semiconductor device of one embodiment of the present invention.
  • Examples of the electronic device include a television device (also referred to as a television or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a mobile phone or a mobile phone device). ), Large game machines such as portable game machines, portable information terminals, sound reproducing devices, and pachinko machines.
  • the electronic device or the lighting device of one embodiment of the present invention has flexibility, it can be incorporated along an inner wall or an outer wall of a house or a building, or a curved surface of an interior or exterior of an automobile.
  • the electronic device of one embodiment of the present invention may include a secondary battery, and it is preferable that the secondary battery can be charged using non-contact power transmission.
  • Secondary batteries include, for example, lithium ion secondary batteries such as lithium polymer batteries (lithium ion polymer batteries) using gel electrolyte, nickel metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead storage batteries, air secondary batteries, nickel A zinc battery, a silver zinc battery, etc. are mentioned.
  • lithium ion secondary batteries such as lithium polymer batteries (lithium ion polymer batteries) using gel electrolyte, nickel metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead storage batteries, air secondary batteries, nickel A zinc battery, a silver zinc battery, etc. are mentioned.
  • the electronic device of one embodiment of the present invention may include an antenna. By receiving a signal with an antenna, video, information, and the like can be displayed on the display unit. Further, when the electronic device has a secondary battery, the antenna may be used for non-contact power transmission.
  • FIG. 70A illustrates a portable game machine including a housing 7101, a housing 7102, a display portion 7103, a display portion 7104, a microphone 7105, speakers 7106, operation keys 7107, a stylus 7108, and the like.
  • the semiconductor device according to one embodiment of the present invention can be used for an integrated circuit, a CPU, or the like incorporated in the housing 7101. With the use of the light-emitting device according to one embodiment of the present invention for the display portion 7103 or the display portion 7104, a portable game machine that has an excellent usability and is unlikely to deteriorate in quality can be provided. Note that although the portable game machine illustrated in FIG. 70A includes two display portions 7103 and 7104, the number of display portions included in the portable game device is not limited thereto.
  • FIG. 70B illustrates a smart watch, which includes a housing 7302, display portions 7304, 7305, and 7306, operation buttons 7311 and 7312, a connection terminal 7313, a band 7321, a clasp 7322, and the like.
  • the semiconductor device according to one embodiment of the present invention can be used for a memory, a CPU, or the like incorporated in the housing 7302.
  • FIG. 70C illustrates a portable information terminal which includes an operation button 7503, an external connection port 7504, a speaker 7505, a microphone 7506, and the like in addition to a display portion 7502 incorporated in a housing 7501.
  • the semiconductor device according to one embodiment of the present invention can be used for a mobile memory, a CPU, or the like incorporated in the housing 7501.
  • the display portion 7502 can have very high definition, the display portion 7502 can perform various displays such as full high-definition, 4k, or 8k while being small and medium, and can obtain a very clear image. it can.
  • FIG. 70D illustrates a video camera, which includes a first housing 7701, a second housing 7702, a display portion 7703, operation keys 7704, a lens 7705, a connection portion 7706, and the like.
  • the operation key 7704 and the lens 7705 are provided in the first housing 7701, and the display portion 7703 is provided in the second housing 7702.
  • the first housing 7701 and the second housing 7702 are connected by a connection portion 7706, and the angle between the first housing 7701 and the second housing 7702 can be changed by the connection portion 7706. is there.
  • the video on the display portion 7703 may be switched in accordance with the angle between the first housing 7701 and the second housing 7702 in the connection portion 7706.
  • the imaging device of one embodiment of the present invention can be provided at a position where the lens 7705 is focused.
  • the semiconductor device according to one embodiment of the present invention can be used for an integrated circuit, a CPU, or the like incorporated in the first housing
  • FIG. 70E illustrates digital signage, which includes a display portion 7922 provided on a utility pole 7921.
  • the display device according to one embodiment of the present invention can be used for the control circuit of the display portion 7922.
  • FIG. 71A illustrates a laptop personal computer, which includes a housing 8121, a display portion 8122, a keyboard 8123, a pointing device 8124, and the like.
  • the semiconductor device according to one embodiment of the present invention can be applied to a CPU or a memory built in the housing 8121. Note that since the display portion 8122 can have very high definition, the display portion 8122 can display 8k while being small and medium-sized, and a very clear image can be obtained.
  • FIG. 71B shows the appearance of an automobile 9700.
  • FIG. 71C illustrates a driver seat of a car 9700.
  • the automobile 9700 includes a vehicle body 9701, wheels 9702, a dashboard 9703, lights 9704, and the like.
  • the semiconductor device of one embodiment of the present invention can be used for a display portion of the automobile 9700 and an integrated circuit for control.
  • the semiconductor device of one embodiment of the present invention can be provided in the display portion 9710 to the display portion 9715 illustrated in FIG.
  • the display portion 9710 and the display portion 9711 are display devices or input / output devices provided on a windshield of an automobile.
  • a display device or an input / output device of one embodiment of the present invention is a so-called see-through state in which an electrode of the display device or the input / output device is made of a light-transmitting conductive material so that the opposite side can be seen through. Display devices or input / output devices. If the display device or the input / output device is in a see-through state, the view is not hindered even when the automobile 9700 is driven. Thus, the display device or the input / output device of one embodiment of the present invention can be provided on the windshield of the automobile 9700.
  • a transistor for driving the display device or the input / output device is provided in the display device or the input / output device, an organic transistor using an organic semiconductor material, a transistor using an oxide semiconductor, or the like, A transistor having a light-transmitting property may be used.
  • a display portion 9712 is a display device provided in the pillar portion.
  • the field of view blocked by the pillar can be complemented by displaying an image from the imaging means provided on the vehicle body on the display portion 9712.
  • a display portion 9713 is a display device provided in the dashboard portion.
  • the view blocked by the dashboard can be complemented. That is, by projecting an image from the imaging means provided outside the automobile, the blind spot can be compensated and safety can be improved. Also, by displaying a video that complements the invisible part, it is possible to confirm the safety more naturally and without a sense of incongruity.
  • FIG. 71D shows the interior of an automobile in which bench seats are used for the driver seat and the passenger seat.
  • the display portion 9721 is a display device or an input / output device provided in the door portion.
  • the field of view blocked by the door can be complemented by displaying an image from an imaging unit provided on the vehicle body on the display portion 9721.
  • the display portion 9722 is a display device provided on the handle.
  • the display unit 9723 is a display device provided at the center of the seat surface of the bench seat. Note that the display device can be installed on a seating surface or a backrest portion, and the display device can be used as a seat heater using heat generated by the display device as a heat source.
  • the display portion 9714, the display portion 9715, or the display portion 9722 can provide various other information such as navigation information, a speedometer and a tachometer, a travel distance, an oil supply amount, a gear state, and an air conditioner setting.
  • display items, layouts, and the like displayed on the display unit can be changed as appropriate according to the user's preference.
  • the above information can also be displayed on the display portion 9710 to the display portion 9713, the display portion 9721, and the display portion 9723.
  • the display portions 9710 to 9715 and the display portions 9721 to 9723 can also be used as lighting devices.
  • the display portions 9710 to 9715 and the display portions 9721 to 9723 can also be used as heating devices.
  • FIG. 72A shows the appearance of the camera 8000.
  • FIG. A camera 8000 includes a housing 8001, a display portion 8002, operation buttons 8003, a shutter button 8004, a coupling portion 8005, and the like.
  • a lens 8006 can be attached to the camera 8000.
  • the coupling portion 8005 includes electrodes, and can connect a strobe device or the like in addition to a finder 8100 described later.
  • the camera 8000 is configured such that the lens 8006 can be removed from the housing 8001 and replaced, but the lens 8006 and the housing may be integrated.
  • An image can be taken by pressing a shutter button 8004.
  • the display portion 8002 has a function as a touch panel and can capture an image by touching the display portion 8002.
  • the display device or the input / output device of one embodiment of the present invention can be applied to the display portion 8002.
  • FIG. 72B shows an example in which a finder 8100 is attached to a camera 8000.
  • the viewfinder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.
  • the housing 8101 includes a coupling portion that engages with the coupling portion 8005 of the camera 8000, and the finder 8100 can be attached to the camera 8000.
  • the coupling portion includes an electrode, and an image received from the camera 8000 via the electrode can be displayed on the display portion 8102.
  • the button 8103 has a function as a power button.
  • a button 8103 can be used to switch display on the display portion 8102 on and off.
  • the semiconductor device of one embodiment of the present invention can be applied to an integrated circuit or an image sensor in the housing 8101.
  • the camera 8000 and the viewfinder 8100 are separate electronic devices and are configured to be detachable.
  • a housing 8001 of the camera 8000 includes one embodiment of the present invention.
  • a finder provided with a display device or an input / output device may be incorporated.
  • FIG. 72C shows the appearance of the head mounted display 8200.
  • the head mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like.
  • a battery 8206 is built in the mounting portion 8201.
  • a cable 8205 supplies power from the battery 8206 to the main body 8203.
  • the main body 8203 includes a wireless receiver and the like, and can display video information such as received image data on the display portion 8204.
  • the mounting portion 8201 may be provided with a plurality of electrodes at a position where the user touches the user.
  • the main body 8203 may have a function of recognizing the user's viewpoint by detecting a current flowing through the electrode in accordance with the movement of the user's eyeball. Moreover, you may have a function which monitors a user's pulse by detecting the electric current which flows into the said electrode.
  • the mounting portion 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display portion 8204. Further, the movement of the user's head or the like may be detected, and the video displayed on the display unit 8204 may be changed in accordance with the movement.
  • the semiconductor device of one embodiment of the present invention can be applied to the integrated circuit in the main body 8203.
  • the RF tag has a wide range of uses. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 73A), vehicles (bicycles, FIG. 73, etc.) (See (B)), packaging containers (wrapping paper, bottles, etc., see FIG. 73C), recording media (DVD, video tape, etc., see FIG.
  • the RF tag 4000 according to one embodiment of the present invention is fixed to an article by being attached to the surface or embedded.
  • a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin and fixed to each article.
  • the RF tag 4000 according to one embodiment of the present invention achieves small size, thinness, and light weight, and thus does not impair the design of the article itself even after being fixed to the article.
  • an authentication function can be provided. Counterfeiting can be prevented.
  • the RF tag according to one embodiment of the present invention by attaching the RF tag according to one embodiment of the present invention to packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved. Can be planned. Even in the case of vehicles, the security against theft or the like can be improved by attaching the RF tag according to one embodiment of the present invention.
  • operating power including writing and reading of information can be reduced by using an RF tag including a semiconductor device according to one embodiment of the present invention for each application described in this embodiment. It is possible to increase the communication distance. In addition, since the information can be held for a very long period even when the power is cut off, it can be suitably used for applications where the frequency of writing and reading is low.
  • an opening was formed by the method of Embodiment 1 in order to produce the electrode shown in FIG. 1, and the cross-section of the opening was observed using a scanning electron microscope (SEM). .
  • a first silicon oxide film having a thickness of 100 nm was formed on a single crystal silicon wafer by a thermal oxidation method.
  • a first tungsten film with a thickness of 50 nm was formed over the first silicon oxide film by a sputtering method.
  • a first aluminum oxide film with a thickness of 20 nm was formed over the first tungsten film by using the ALD method.
  • a second silicon oxide film having a thickness of 30 nm was formed over the first aluminum oxide film by a CVD method.
  • a first In—Ga—Zn oxide film is formed to a thickness of 20 nm over the second silicon oxide film by a sputtering method, and sputtering is performed over the first In—Ga—Zn oxide film.
  • a second In—Ga—Zn oxide was formed to a thickness of 15 nm by a method.
  • a second tungsten film was formed to a thickness of 20 nm over the second In—Ga—Zn oxide by a sputtering method.
  • a second aluminum oxide film with a thickness of 40 nm was formed over the second tungsten film by a sputtering method.
  • a third silicon oxide film with a thickness of 250 nm was formed over the second aluminum oxide film by a CVD method.
  • a third tungsten film with a thickness of 90 nm was formed over the third silicon oxide film by a sputtering method.
  • a silicon nitride film having a thickness of 130 nm was formed over the third tungsten film by a CVD method.
  • plasma treatment was performed using a dry etching apparatus.
  • a dry etching apparatus a dry etching apparatus having a configuration in which a high frequency power source having a different frequency is connected to each of parallel plate type electrodes is used.
  • the plasma treatment uses a mixed gas of C 4 F 8 gas (flow rate 50 sccm) and argon gas (flow rate 16 sccm), applies 500 W of high frequency power to the upper electrode at a pressure of 3.3 Pa, and 100 W to the lower electrode.
  • the high frequency power was applied and the treatment time was 30 seconds.
  • the product was formed on the side surface of the organic film while forming the product on the side surface of the resist mask and simultaneously etching the organic film using the resist mask as an etching mask.
  • the organic film was not completely etched. The steps up to here were performed to prepare Sample 2.
  • the organic film, the silicon nitride film, and the third tungsten film were etched until they reached the surface of the third silicon oxide film.
  • the dry etching apparatus used was the apparatus used for the plasma treatment described above. Etching of the organic film is performed using CF 4 gas (flow rate 80 sccm), applying high frequency power of 500 W to the upper electrode and applying high frequency power of 100 W to the lower electrode at a pressure of 3 Pa, and processing time of 13 seconds. It was.
  • the silicon nitride film is etched by using a mixed gas of CHF 3 gas (flow rate 67 sccm) and oxygen gas (flow rate 13 sccm), applying a high frequency power of 550 W to the upper electrode at a pressure of 5.3 Pa, and A high frequency power of 350 W was applied and the treatment time was 40 sec.
  • Etching of the third tungsten film uses a mixed gas of CF 4 gas (flow rate 22 sccm), chlorine gas (flow rate 11 sccm), and oxygen gas (flow rate 22 sccm). High frequency power was applied, 200 W high frequency power was applied to the lower electrode, and the treatment time was 37 seconds.
  • etching was performed using the hard mask made of the silicon nitride film and the third tungsten film as an etching mask until the third silicon oxide film and the second aluminum oxide film reached the upper surface of the second tungsten film.
  • the dry etching apparatus the apparatus used for the above-described etching was used.
  • a high frequency power of 2000 W was applied, a high frequency power of 2000 W was applied to the lower electrode, and the treatment time was 35 seconds.
  • Etching of the second aluminum oxide film uses a mixed gas of C 4 F 8 gas (flow rate 8 sccm), argon gas (475 sccm), and hydrogen gas (16 sccm) at a pressure of 2.6 Pa to the upper electrode at 1000 W.
  • the high frequency power was applied, 1200 W high frequency power was applied to the lower electrode, and the treatment time was 27 sec.
  • oxygen plasma treatment was continuously performed.
  • the oxygen plasma treatment is performed using oxygen gas (flow rate 200 sccm), applying a high frequency power of 500 W to the upper electrode at a pressure of 1.3 Pa, applying a high frequency power of 100 W to the lower electrode, and a processing time of 10 seconds. It was.
  • the above process was performed to prepare Sample 6.
  • a sample 5 was manufactured in which a hard mask was formed without performing plasma treatment, and the third silicon film and the second aluminum oxide film were etched using the hard mask as an etching mask.
  • FIG. 74 shows a cross-sectional SEM photograph of Sample 1 after the resist mask is formed.
  • FIG. 74A shows a 50 nm design.
  • the opening diameter of the top portion of the resist mask was 72.4 nm, and the opening diameter of the bottom portion was 62.5 nm.
  • FIG. 74B shows a 100 nm design.
  • the opening diameter of the top portion of the resist mask was 137.0 nm, and the opening diameter of the bottom portion was 117.0 nm.
  • FIG. 75 shows a cross-sectional SEM photograph of Sample 2 after the plasma treatment.
  • FIG. 75A shows a 50 nm design in which the opening diameter of the top portion of the resist mask was 46.6 nm and the opening diameter of the bottom portion was 36.7 nm.
  • FIG. 75B shows a design of 100 nm, the opening diameter of the top portion of the resist mask was 123.0 nm, and the opening diameter of the bottom portion was 65.5 nm. Since the opening diameter is significantly smaller after the plasma treatment than after the resist mask formation shown in FIG. 74, the product is removed from the resist side and the organic film side by performing the plasma treatment. It was found that it was formed.
  • FIG. 76 shows a cross-sectional SEM photograph of Sample 3 in which a hard mask is formed without performing plasma treatment for comparison.
  • FIG. 76A shows a 50 nm design, in which the opening diameter of the top portion of the third tungsten film which is one of the hard masks is 66.5 nm, and the opening diameter of the bottom portion is 51.6 nm.
  • FIG. 76B shows a design of 100 nm. The opening system of the top portion of the third tungsten film, which is one of hard masks, was 113.0 nm, and the opening diameter of the bottom portion was 108.0 nm.
  • FIG. 77 shows a cross-sectional SEM photograph of Sample 4 on which a hard mask was formed after the plasma treatment.
  • FIG. 77A shows a 50 nm design, in which the opening diameter of the top portion of the third tungsten film which is one of the hard masks is 53.6 nm and the opening diameter of the bottom portion is 39.7 nm.
  • FIG. 77B shows a design of 100 nm.
  • the opening system of the top portion of the third tungsten film, which is one of hard masks, was 104.0 nm, and the opening diameter of the bottom portion was 98.2 nm. Since the opening diameter is smaller than the opening diameter of the opening where the hard mask is formed without performing the plasma treatment shown in FIG. 76, it is understood that a hard mask having a small opening diameter can be formed by performing the plasma treatment. It was.
  • FIG. 78 shows a cross-sectional SEM photograph of Sample 5 in which an opening is formed by etching the third silicon oxide film and the second aluminum oxide film without performing plasma treatment.
  • FIG. 78A shows a design of 50 nm, the opening diameter of the top portion of the third silicon oxide film is 69.4 nm, and the opening diameter of the bottom portion of the second aluminum oxide film is 34.2 nm.
  • FIG. 78B shows a design of 100 nm, the opening diameter of the top portion of the third silicon oxide film was 119.0 nm, and the opening diameter of the bottom portion of the second aluminum oxide film was 71.6 nm.
  • FIG. 79 shows a cross-sectional SEM photograph of Sample 6 in which an opening is formed by etching the third silicon oxide film and the second aluminum oxide film after the plasma treatment.
  • FIG. 79A shows a design of 50 nm, the opening diameter of the top portion of the third silicon oxide film was 55.1 nm, and the opening diameter of the bottom portion of the second aluminum oxide film was 27.6 nm.
  • FIG. 79B shows a design of 100 nm, the opening diameter of the top portion of the third silicon oxide film is 103.0 nm, and the opening diameter of the bottom portion of the second aluminum oxide film is 65.0 nm.
  • the opening diameter can be reduced from about 14.4 nm to about 16.0 nm at the top portion, The size could be reduced by 6.6 nm.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un micro-transistor. L'invention concerne également un transistor ayant une faible capacité parasite. L'invention concerne également un transistor ayant des caractéristiques haute fréquence. L'invention concerne également un transistor ayant un fort courant à l'état passant. L'invention concerne également un dispositif à semi-conducteur ayant ledit transistor. L'invention concerne également un dispositif à semi-conducteur ayant un haut degré d'intégration. L'invention concerne également une nouvelle électrode. L'électrode est fabriquée : par formation d'une couche isolante sur une première couche conductrice ; par formation d'une couche de masque sur la couche isolante ; par formation d'un masque de résine photosensible sur la couche de masque par lithographie ; par formation d'un produit sur la surface latérale du masque de résine photosensible ; par gravure de la couche de masque en utilisant le masque de résine photosensible et le produit comme masque de gravure ; par formation d'une ouverture dans la couche isolante par gravure, utilisant la couche de masque comme masque de gravure, de la couche isolante jusqu'à la surface supérieure de la première couche conductrice ; par formation d'une seconde couche conductrice dans l'ouverture.
PCT/IB2016/055295 2015-09-18 2016-09-05 Électrode et procédé de fabrication de dispositif à semi-conducteur WO2017046673A1 (fr)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000164571A (ja) * 1998-11-27 2000-06-16 Sony Corp コンタクトホール形成方法およびプラズマエッチング方法
JP2013200566A (ja) * 2009-12-18 2013-10-03 Semiconductor Energy Lab Co Ltd 表示装置の駆動方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000164571A (ja) * 1998-11-27 2000-06-16 Sony Corp コンタクトホール形成方法およびプラズマエッチング方法
JP2013200566A (ja) * 2009-12-18 2013-10-03 Semiconductor Energy Lab Co Ltd 表示装置の駆動方法

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