WO2017045372A1 - 显示面板的封装结构、转接板、封装方法及显示装置 - Google Patents

显示面板的封装结构、转接板、封装方法及显示装置 Download PDF

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Publication number
WO2017045372A1
WO2017045372A1 PCT/CN2016/075191 CN2016075191W WO2017045372A1 WO 2017045372 A1 WO2017045372 A1 WO 2017045372A1 CN 2016075191 W CN2016075191 W CN 2016075191W WO 2017045372 A1 WO2017045372 A1 WO 2017045372A1
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Prior art keywords
display panel
interposer
package
chip
chipset
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PCT/CN2016/075191
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English (en)
French (fr)
Inventor
张博
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京东方科技集团股份有限公司
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Priority to US15/535,894 priority Critical patent/US10614988B2/en
Publication of WO2017045372A1 publication Critical patent/WO2017045372A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J11/00—Gas-filled discharge tubes with alternating current induction of the discharge, e.g. alternating current plasma display panels [AC-PDP]; Gas-filled discharge tubes without any main electrode inside the vessel; Gas-filled discharge tubes with at least one main electrode outside the vessel
    • H01J11/20—Constructional details
    • H01J11/46—Connecting or feeding means, e.g. leading-in conductors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/841—Self-supporting sealing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J11/00—Gas-filled discharge tubes with alternating current induction of the discharge, e.g. alternating current plasma display panels [AC-PDP]; Gas-filled discharge tubes without any main electrode inside the vessel; Gas-filled discharge tubes with at least one main electrode outside the vessel
    • H01J11/10—AC-PDPs with at least one main electrode being out of contact with the plasma
    • H01J11/12—AC-PDPs with at least one main electrode being out of contact with the plasma with main electrodes provided on both sides of the discharge space
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00

Definitions

  • Embodiments of the present invention relate to a package structure of a display panel, an adapter board, a packaging method, and a display device.
  • LEDs Light Emitting Diodes
  • OLEDs Organic Light Emitting Diodes
  • PDPs Plasma Display Panels
  • LCDs Liquid Crystal Displays
  • COG chip on glass
  • the COG is a carrier that fixes the driving chip on the display panel and uses the display panel to package the driving chip.
  • the package pin on the driving chip is pressed and connected by an anisotropic conductive film (ACF).
  • ACF anisotropic conductive film
  • An embodiment of the present invention provides a package structure of a display panel, including: a display panel, a chip set for controlling the display panel, and an adapter board, wherein the chipset is located above the display panel, An adapter board is located between the chipset and the display panel; a surface of the bumper facing the side of the display panel is gold; and a package pin of each chip in the chipset passes the The adapter board is electrically connected to the display panel.
  • the adapter plate is a through silicon via adapter plate.
  • the package structure further includes: an anisotropic conductive film between the interposer and the display panel, the interposer passing the anisotropic conductive film and the The display panel is electrically connected.
  • the package structure further includes an underfill that fills at least a portion of the area between the interposer and the chipset.
  • the overall material of the bumps on the side of the adapter plate facing the display panel is gold.
  • Another embodiment of the present invention provides a display device including the package structure of the above display panel.
  • Another embodiment of the present invention provides an adapter plate, the surface of the bump on at least one side of the adapter plate being gold.
  • the overall material of the bump is gold.
  • a further embodiment of the present invention provides a method for packaging a display panel, comprising: using a reflow soldering process to control a package pin of each chip in a chip set for controlling the display panel and a first side electrical property of the adapter board And connecting the second side of the riser board to the display panel by a flip-chip glass packaging process, wherein a surface of the bump of the second side of the riser board is gold.
  • the second side of the interposer board is electrically connected to the display panel by using a flip-chip glass encapsulation process, and an anisotropic conductive film is formed on the second side of the interposer board.
  • an anisotropic conductive film is formed on a side of the display panel facing the interposer; and electrically passing the interposer and the display panel through the anisotropic conductive film by a hot pressing process Sexual connection.
  • the packaging method further includes : filling an underfill between the adapter plate and the chip set.
  • FIG. 1 is a cross-sectional view showing a package structure of a display panel according to an embodiment of the present invention
  • FIG. 2 is a flowchart of a method for packaging a package structure of a display panel according to an embodiment of the present invention
  • 3a and 3b are schematic cross-sectional views of an adapter plate according to an embodiment of the present invention.
  • the display panel is to be displayed, and a plurality of chips, such as a driver chip, a power chip, a memory chip, etc., need to be disposed in the peripheral circuit.
  • a driver chip such as a driver chip, a power chip, a memory chip, etc.
  • COG packaging technology only There are driver chips that can be placed on the display panel using COG packaging technology.
  • Other chips are not suitable for COG packaging technology to be placed on the display panel due to the design of the package pins.
  • one method is to change the package pin design of all other chips, so that it can be set on the display panel by using COG packaging technology.
  • the package structure, the adapter board, the packaging method and the display device of the display panel are provided by using the surface of the bump on one side as the gold adapter board and various chips in the chip group of the display panel. After the electrical and mechanical connection package, the chipset will be installed using COG packaging technology.
  • the adapter board is integrally disposed on the display panel, and the method is more suitable for setting various chips in the chipset for controlling the display panel on the display panel and performing mass production in a large scale.
  • each film layer in the drawings do not reflect the true proportion of the package structure and the adapter plate of the display panel provided by the embodiments of the present invention, and the purpose is only to explain the related technical content.
  • An embodiment of the present invention provides a package structure of a display panel.
  • the display panel includes a display panel 1 , a chip set 2 for controlling the display panel, and an adapter board 3 .
  • the chipset 2 is located above the display panel 1, and the adapter board 3 is located between the chipset 2 and the display panel 1.
  • the surface 310 of the bump 31 facing the side of the display panel 1 is gold, and the package pins 210 of the chips 21 in the chip set 2 are electrically connected to the display panel 1 through the interposer 3 .
  • the package pins 210 of the chips 21 in the chipset 2 are electrically connected to the package pins 11 of the display panel 1 through the interposer 3 .
  • the package pins 11 of the display panel 1 are generally disposed in a peripheral area of the display panel 1, corresponding to respective signal lines in the display panel, for transmitting signals of the chips to the signal lines in the display panel through the package pins.
  • the signal lines of the display panel can be connected to different types of chips, and the corresponding connection relationship between the signal lines and the chips can be implemented in all existing ways, and will not be described here.
  • the chipset is located above the display panel, and the package pins of the chips in the chipset are electrically connected to the display panel through the adapter board. Since the package pins of each chip in the chipset are directly connected to the adapter board, the high temperature generated by the package pins of the chips in the chipset directly connected to the display panel is prevented from being brought to the display panel. Destruction; and because the surface of the bump on the side of the adapter plate facing the display panel is gold, gold has excellent electrical conductivity, high temperature resistance, moisture resistance, high stability, high oxidation resistance, and good electrical and mechanical connectivity.
  • the packaging of the chip reduces the difficulty and cost of the packaging process, and can greatly increase the integration density of the chip and the device package on the display panel, and is suitable for the development trend of the display product, which is light and short, and mass production.
  • the bump of the adapter plate facing the display panel may be a structure in which the surface is gold and the center is other metal materials, or the center and the surface are both
  • the structure of gold is not limited here.
  • the adapter plate 3 faces the side of the display panel 1 in order to simplify the manufacturing process and to make the performance of the bumps electrically stable and thermally expandable.
  • the material of the point 31 is gold, that is, the center and the surface of the bump are made of a uniform material.
  • the package pin 210 of each chip 21 in the chip set 2 generally passes through a bump disposed on a side of the interposer 3 facing away from the display panel 1 . 32 is electrically connected to the adapter plate 3.
  • the package pin 210 of each chip 21 in the chipset 2 can be electrically connected to the adapter board 3 by other means, which is not limited herein.
  • the bump may be a solder electrode or a package pin or the like, which is not limited herein.
  • the interposer may be a through silicon via (TSV) interposer, and of course, other functions capable of implementing the interposer in the embodiment of the present invention.
  • TSV through silicon via
  • the type of the adapter plate, for example, the glass through-hole adapter plate and the ceramic through-hole adapter plate are not limited herein.
  • the adapter board is a TSV adapter board.
  • the above package structure provided in the embodiment of the present invention further includes: an anisotropic conductive adhesive film 4 between the adapter plate 3 and the display panel 1 , and the adapter plate 3 passes The anisotropic conductive film 4 and the display panel 1 are electrically connected.
  • the bumps 31 in the interposer 3 are electrically connected to the package leads 11 of the display panel 1 through the anisotropic conductive film 4.
  • the anisotropic conductive film 4 can be an existing anisotropic conductive film, which will not be described in detail herein.
  • the anisotropic conductive film 4 mainly includes an adhesive 41 having an insulating function and conductive particles 42.
  • the conductive particles 42 are in contact with each other, thereby realizing the bump 31 and the package.
  • the electrical connection of the pin 11; and the region of the anisotropic conductive film 4 not located between the corresponding bump 31 and the package pin 11 is not compressed, wherein the conductive particles 42 do not contact each other and do not conduct electricity. .
  • the anisotropic conductive film 4 is made conductive in the direction along the corresponding bump 31 and the package pin 11 (for example, the vertical direction), and is connected perpendicular to the corresponding bump 31 and the package pin 11.
  • the direction (for example, the horizontal direction) is insulating.
  • the above package structure provided by the embodiment of the present invention further includes: filling the adapter board 3 and the chip set 2 At least part of the area is filled with glue 5 at the bottom.
  • the underfill can be filled in the interposer and the chipset. All areas between.
  • the chip set for controlling the display panel includes at least: a driving chip, a memory chip, and a power chip. It is known that, in addition to the above-mentioned chips, there are other chips that can be applied to the display panel for controlling the display panel. These chips can be disposed in the above-mentioned chipset, which is not limited herein.
  • an embodiment of the present invention further provides a method for packaging a display panel, as shown in FIG. 2, including:
  • the package pins of the chips in the chipset are directly connected to the adapter board, the package pins of the chips in the chipset are directly connected to the display panel.
  • the generated high temperature causes damage to the display panel; and since the surface of the bump of the adapter plate facing the second side of the display panel is gold, the gold has high conductivity, high temperature resistance, moisture resistance, high stability, and oxidation resistance. Excellent characteristics such as high performance and good electrical and mechanical connectivity, meeting the requirements of the existing COG packaging process, so it is possible to use the existing COG packaging process without changing the package pin design of each chip in the existing chipset.
  • the adapter board can realize the packaging of various chips on the display panel, thereby reducing the packaging process difficulty and cost, and greatly improving the integration density of the chip and the device package on the display panel, thereby being suitable for the development of the display product in a light and short period. Trends and mass production.
  • the adapter board 3 includes: a transition substrate and bumps on both sides of the adapter substrate.
  • the bumps on the first side of the adapter substrate are electrically connected to the package pins of the chips in the chipset, and the bumps on the second side of the adapter substrate are electrically connected to the display panel.
  • a bump on the first side of the transfer substrate The bumps on the second side correspond to electrical connections.
  • the package pin of each chip in the chip set for controlling the display panel is electrically connected to the first side of the interposer board by using a reflow soldering process in step S201.
  • a reflow soldering process in step S201.
  • the interposer may be a through silicon via (TSV) interposer, and of course, the function of the interposer in the embodiment of the present invention may be implemented.
  • TSV through silicon via
  • each chip in the chipset for controlling the display panel is controlled by a reflow soldering process in step S201. After the package pin is electrically connected to the first side of the adapter board, the method further includes:
  • an underfill process may be used to fill the underfill layer between the interposer and the chipset by using an underfill process based on the “capillary effect” technology, which is not limited herein.
  • the step S202 electrically connects the second side of the interposer board to the display panel by using a flip-chip glass packaging process, for example, it can be performed as follows:
  • the adapter plate and the display panel are electrically connected through an anisotropic conductive film by a hot pressing process.
  • the bump on the second side of the interposer and the package pin on the display panel are electrically connected through the anisotropic conductive film by a hot pressing process.
  • an embodiment of the present invention further provides a display device, including the above package structure provided by the embodiment of the present invention.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other indispensable components of the display device are understood by those skilled in the art, and are not described herein, nor should they be construed as limiting the embodiments of the present invention.
  • an embodiment of the present invention further provides an adapter plate 3'.
  • the surface 310' of the bump 31' on at least one side of the adapter plate 3' is gold.
  • the overall material of the bump 31" of the adapter plate 3" is gold.
  • the interposer may be a through silicon via (TSV) interposer, and of course, the interposer in the embodiment of the present invention may be implemented.
  • TSV through silicon via
  • the chipset is located above the display panel, and the package pins of each chip in the chipset are electrically connected through the adapter board and the display panel. connection. Since the package pins of each chip in the chipset are directly connected to the adapter board, the high temperature generated by the package pins of the chips in the chipset directly connected to the display panel is prevented from being brought to the display panel. Destruction; and because the surface of the bump on the side of the adapter plate facing the display panel is gold, gold has excellent electrical conductivity, high temperature resistance, moisture resistance, high stability, high oxidation resistance, and good electrical and mechanical connectivity.
  • the packaging of the chip reduces the difficulty and cost of the packaging process, and can greatly increase the integration density of the chip and the device package on the display panel, and is suitable for the development trend of the display product, which is light and short, and mass production.

Abstract

提供一种显示面板的封装结构、转接板、封装方法及显示装置。显示面板（1）的封装结构包括：显示面板（1）、用于控制显示面板（1）的芯片组（2）、以及转接板（3），其中，芯片组（2）位于显示面板（1）的上方，转接板（3）位于芯片组（2）与显示面板（1）之间；转接板（3）面向显示面板（1）一侧的凸点（31）的表面（310）为金；芯片组（2）中各芯片（21）的封装引脚（210）通过转接板（3）与显示面板（1）电性连接。这样，可以采用现有的COG封装工艺通过转接板就能实现显示面板上各种芯片的封装，从而降低封装工艺难度和成本，并能够提高显示面板上芯片的集成密度，适用于显示产品轻薄短小的发展趋势和大规模量产。

Description

显示面板的封装结构、转接板、封装方法及显示装置 技术领域
本发明实施例涉及一种显示面板的封装结构、转接板、封装方法及显示装置。
背景技术
随着电子、通信产业的发展，对发光二极管(Light Emitting Diode，LED)、有机发光二极管(Organic Light Emitting Diode，OLED)、等离子显示器(Plasma Display Panel，PDP)及液晶显示器(Liquid Crystal Display，LCD)等平板显示器件的需求与日俱增。平板显示器件的发展趋势是轻、薄、短、小，需要具有高密度、小体积、高安装自由度等特点的封装技术来满足以上需求，因此，覆晶玻璃(Chip on Glass，COG)封装技术应运而生。
COG是将驱动芯片固定于显示面板上，运用显示面板做封装驱动芯片的载体，驱动芯片上的封装引脚利用各向异性导电胶膜(Anisotropic Conductive Film,ACF)通过压接的方式与显示面板上的对应的封装引脚实现电性连接。
发明内容
本发明实施例提供一种显示面板的封装结构，包括：显示面板、用于控制所述显示面板的芯片组、以及转接板，其中，所述芯片组位于所述显示面板的上方，所述转接板位于所述芯片组与所述显示面板之间；所述转接板面向所述显示面板一侧的凸点的表面为金；所述芯片组中各芯片的封装引脚通过所述转接板与所述显示面板电性连接。
在一个示例中，所述转接板为硅通孔转接板。
在一个示例中，所述封装结构还包括：位于所述转接板与所述显示面板之间的各向异性导电胶膜，所述转接板通过所述各向异性导电胶膜与所述显示面板电性连接。
在一个示例中，所述封装结构还包括：填充于所述转接板与所述芯片组的之间的至少部分区域的底部填充胶。
在一个示例中，所述转接板面向所述显示面板一侧的所述凸点的整体材质为金。
本发明另一实施例提供一种显示装置，包括上述显示面板的封装结构。
本发明又一实施例提供一种转接板，所述转接板至少一侧的凸点的表面为金。
在一个示例中，所述凸点的整体材质为金。
本发明又一实施例提供一种显示面板的封装方法，包括：采用回流焊接工艺将用于控制所述显示面板的芯片组中的各芯片的封装引脚与转接板的第一侧电性连接；以及采用覆晶玻璃封装工艺将所述转接板的第二侧与所述显示面板电性连接，其中所述转接板的第二侧的凸点的表面为金。
在一个示例中，采用覆晶玻璃封装工艺将所述转接板的第二侧与所述显示面板电性连接，执行为：在所述转接板的第二侧形成各向异性导电胶膜；或在所述显示面板面向所述转接板的一侧形成各向异性导电胶膜；以及采用热压工艺将所述转接板与所述显示面板通过所述各向异性导电胶膜电性连接。
在一个示例中，在采用回流焊接工艺将用于控制所述显示面板的芯片组中的各芯片的封装引脚与所述转接板的第一侧电性连接之后，所述封装方法还包括：在所述转接板与所述芯片组之间填充底部填充胶。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明实施例提供的显示面板的封装结构的剖面示意图；
图2为本发明实施例提供的显示面板的封装结构的封装方法的流程图；
图3a和图3b分别为本发明实施例提供的转接板的剖面示意图。
具体实施方式
众所周知，显示面板要实现显示，外围电路中需要设置多个芯片，例如驱动芯片，电源芯片，储存芯片等。但是在目前的显示面板封装结构中，只 有驱动芯片可以采用COG封装技术设置在显示面板上，其它芯片由于封装引脚的设计不适合采用COG封装技术设置在显示面板上。在相关技术中，要实现将其它芯片也设置在显示面板上，有以下两种方法：一种方法就是改变其它所有芯片的封装引脚设计，使其可以采用COG封装技术设置在显示面板上，但是实际上显示面板中除了驱动芯片还需要很多其它的芯片和器件，且不同的芯片一般均由不同的厂家生产，要将所有的这些芯片重新设计势必会导致极大的工艺难度和成本上升。另一种方法就是采用热回流工艺使其它芯片与显示面板进行电连接。但是热回流工艺的温度一般在220-260°之间，而显示面板的最高耐受温度为80°-90°，因此采用热回流工艺会破坏整个显示面板的性能。因此，这两种方法均不适合于将其它芯片设置于显示面板上进行大规模的集成量产。
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本发明实施例提供的一种显示面板的封装结构、转接板、封装方法及显示装置，通过使用一侧的凸点的表面为金的转接板与显示面板的芯片组中的各种芯片进行电气和机械连接封装后再采用COG封装技术将安装了芯片组 的转接板整体设置在显示面板上，这种方法更适用于将用于控制显示面板的芯片组中的各种芯片设置于显示面板上并进行大规模的量产。
附图中各膜层的厚度和形状不反映本发明实施例提供的显示面板的封装结构、转接板的真实比例，目的只是示意说明相关技术内容。
本发明实施例提供了一种显示面板的封装结构，如图1所示，包括：显示面板1、用于控制显示面板的芯片组2以及转接板3。芯片组2位于显示面板1的上方，转接板3位于芯片组2和显示面板1之间。转接板3面向显示面板1的一侧的凸点31的表面310为金，芯片组2中的各芯片21的封装引脚210通过转接板3与显示面板1电性连接。例如，芯片组2中的各芯片21的封装引脚210通过转接板3与显示面板1的封装引脚11电性连接。显示面板1的封装引脚11通常设置于显示面板1的周边区域，与显示面板中的各个信号线对应，用于通过封装引脚将芯片的信号传输至显示面板中的信号线。显示面板的信号线可以有多种，分别连接不同功能的芯片，关于信号线与芯片的对应连接关系可以采用现有可实现的所有方式，此处不再赘述。
本发明实施例提供的上述显示面板的封装结构，芯片组位于显示面板的上方，芯片组中的各芯片的封装引脚通过转接板与显示面板电性连接。由于芯片组中各芯片的封装引脚是直接与转接板电性连接的，避免了芯片组中各芯片的封装引脚直接与显示面板电性连接时所产生的高温对显示面板带来的破坏；并且由于转接板面向显示面板的一侧的凸点的表面为金，由于金具有导电性高、耐高温、耐湿、稳定性高、抗氧化性高以及电气和机械连接性好等优良特性，满足现有COG封装工艺的要求，因此可以不需要改变现有的芯片组中各芯片的封装引脚设计，而是采用现有的COG封装工艺通过转接板就能实现显示面板上各种芯片的封装，从而降低封装工艺难度和成本，并能够极大的提高显示面板上芯片和器件封装的集成密度，进而适用于显示产品轻薄短小的发展趋势和大规模量产。
进一步地，例如，在本发明实施例提供的上述封装结构中，转接板面向显示面板一侧的凸点可以是表面为金以及中心为其它金属材料的结构，也可以是中心和表面均为金的结构，在此不作限定。
为简化制作工艺以及使得凸点的电传导性、热膨胀性等性能比较稳定，在本发明实施例提供的上述封装结构中，转接板3面向显示面板1一侧的凸 点31的材质为金，即凸点的中心和表面为材质均一的金属。
例如，在本发明实施例提供的上述封装结构中，如图1所示，芯片组2中各芯片21的封装引脚210一般通过设置于转接板3背离显示面板1的一侧的凸点32与转接板3电性连接。当然，芯片组2中各芯片21的封装引脚210也可以通过其它方式与转接板3进行电性连接，在此不作限定。
需要说明的是，在本发明实施例提供的上述封装结构中，凸点可以是指焊接电极或封装引脚等，在此不作限定。
例如，在本发明实施例提供的上述封装结构中，转接板可以是硅通孔(Through Silicon Via，TSV)转接板，当然也可以是能够实现本发明实施例中转接板功能的其他类型转接板，例如，玻璃通孔转接板、陶瓷通孔转接板，在此不作限定。
例如，在本发明实施例提供的上述封装结构中，转接板为TSV转接板。
进一步地，例如，在本发明实施例提供的上述封装结构，如图1所示，还包括：位于转接板3和显示面板1之间的各向异性导电胶膜4，转接板3通过各向异性导电胶膜4和显示面板1实现电性连接。
例如，转接板3中的凸点31通过各向异性导电胶膜4与显示面板1的封装引脚11实现电性连接。
进一步地，例如，在本发明实施例提供的上述封装结构中，各向异性导电胶膜4可采用现有的各向异性导电胶膜，在此不作详述。
例如，如图1所示，各向异性导电胶膜4主要包括：具有绝缘功能的黏着剂41和导电粒子42。经后，各向异性导电胶膜4的位于转接板3的凸点31以及其对应的显示面板1的封装引脚11之间区域中，导电粒子42彼此接触，进而实现凸点31和封装引脚11的电性连接；而各向异性导电胶膜4的不位于对应的凸点31和封装引脚11之间的区域未被压缩，其中的导电粒子42互不接触从而不起导电作用。这样，各向异性导电胶膜4实现了在沿对应凸点31和封装引脚11连线方向(例如竖直方向)上具有导电性，在垂直于对应凸点31和封装引脚11连线的方向(例如，水平方向)上具有绝缘性。
进一步地，例如，由于芯片21的封装引脚210和转接板3的凸点32的材质一般不相同，因此热膨胀系数也不同。芯片组2中各芯片21的封装引脚210与转接板3中的凸点32电性连接时会产生高温，由于封装引脚210和凸 点32非常小，且膨胀系数不同，稍微的热变形就可能会造成电性连接失效的结果，导致封装引脚或凸点出现破裂。为了保证封装引脚210和凸点32之间电性连接的可靠性，本发明实施例提供的上述封装结构，如图1所示，还包括：填充于转接板3和芯片组2的之间的至少部分区域底部填充胶5。
例如，为了最大程度的保证芯片组2中的各芯片21的封装引脚210与转接板3的凸点32电气与机械连接的可靠性，底部填充胶可以填充于转接板和芯片组之间的全部区域。
进一步地，例如，在本发明实施例提供的上述封装结构中，用于控制显示面板的芯片组至少包括：驱动芯片、存储芯片和电源芯片。众所周知，除上述芯片外，还有其他可以应用于显示面板中用于控制显示面板的芯片，这些芯片均可以设置于上述芯片组中，在此不作限定。
基于同一发明构思，本发明实施例还提供了一种显示面板的封装方法，如图2所示，包括：
S201、采用回流焊接工艺将用于控制显示面板的芯片组中的各芯片的封装引脚与转接板的第一侧电性连接；
S202、采用覆晶玻璃(COG)封装工艺将转接板的与所述第一侧相反的第二侧与显示面板电性连接，其中转接板的第二侧的凸点的表面材质为金。
本发明实施例提供的上述封装方法，由于芯片组中各芯片的封装引脚是直接与转接板电性连接的，避免了芯片组中各芯片的封装引脚直接与显示面板电性连接时所产生的高温对显示面板带来的破坏；并且由于转接板面向显示面板的第二侧的凸点的表面为金，由于金具有导电性高、耐高温、耐湿、稳定性高、抗氧化性高以及电气和机械连接性好等优良特性，满足现有COG封装工艺的要求，因此可以不需要改变现有的芯片组中各芯片的封装引脚设计，而是采用现有的COG封装工艺通过转接板就能实现显示面板上各种芯片的封装，从而降低封装工艺难度和成本，并能够极大的提高显示面板上芯片和器件封装的集成密度，进而适用于显示产品轻薄短小的发展趋势和大规模量产。
例如，转接板3包括：转接基板和位于转接基板两侧的凸点。其中，转接基板的第一侧的凸点用于与芯片组中的各芯片的封装引脚电性连接，转接基板的第二侧的凸点用于与显示面板电性连接。转接基板的第一侧的凸点与 第二侧的凸点对应电性连接。
因此，在本发明实施例提供的上述封装方法中，在步骤S201采用回流焊接工艺将用于控制显示面板的芯片组中的各芯片的封装引脚与转接板的第一侧电性连接之前，例如还包括：
在转接基板第一侧上形成与芯片组中各芯片的封装引脚对应的凸点阵列，以及在转接基板第二侧上形成与显示面板的封装引脚对应的表面为金的凸点阵列。
进一步地，在本发明实施例提供的上述封装方法中，转接板可以是硅通孔(Through Silicon Via，TSV)转接板，当然也可以是能够实现本发明实施例中转接板功能的其他类型转接板，例如，玻璃通孔转接板、陶瓷通孔转接板，在此不作限定。
进一步地，例如，由于芯片的封装引脚和转接板的凸点的材质一般不相同，因此热膨胀系数也不同。芯片组中各芯片的封装引脚与转接板中的凸点电性连接时会产生高温，由于封装引脚和凸点非常小，且膨胀系数不同，稍微的热变形就可能会造成电性连接失效的结果，导致封装引脚或凸点出现破裂。为了保证封装引脚和凸点之间电性连接的可靠性，在本发明实施例提供的上述封装方法中，在步骤S201采用回流焊接工艺将用于控制显示面板的芯片组中的各芯片的封装引脚与转接板的第一侧电性连接之后，还包括：
在转接板和芯片组之间填充底部填充胶。
例如，在本发明实施例提供的上述封装方法中，可以采用基于“毛细管效应”技术的底部填充工艺在转接板与芯片组之间填充底部填充胶，在此不作限定。
进一步地，例如，在本发明实施例提供的上述封装方法中，步骤S202采用覆晶玻璃封装工艺将转接板的第二侧与显示面板电性连接，例如可以执行为：
在转接板的第二侧形成各向异性导电胶膜；或在显示面板面向转接板的一侧形成各向异性导电胶膜；
采用热压工艺将转接板与显示面板通过各向异性导电胶膜电性连接。
例如，在本发明实施例提供的上述封装方法中，采用热压工艺将转接板第二侧的凸点与显示面板上的封装引脚通过各向异性导电胶膜电性连接。
基于同一发明构思，本发明实施例还提供了一种显示装置，包括本发明实施例提供的上述封装结构。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明实施例的限制。该显示装置的实施可以参见上述封装结构的实施例，重复之处不再赘述。
基于同一发明构思，本发明实施例还提供了一种转接板3'，如图3a和图3b所示，该转接板3'至少一侧的凸点31'的表面310'为金。
例如，在发明实施例提供的转接板中，如图3b所示，该转接板3”的凸点31”的整体材质为金。
进一步地，例如，在本发明实施例提供的上述封装结构中，转接板可以是硅通孔(Through Silicon Via，TSV)转接板，当然也可以是能够实现本发明实施例中转接板功能的其他类型转接板，例如，玻璃通孔转接板、陶瓷通孔转接板，在此不作限定。
本发明实施例提供的上述显示面板的封装结构、转接板、封装方法及显示装置，芯片组位于显示面板的上方，芯片组中的各芯片的封装引脚通过转接板与显示面板电性连接。由于芯片组中各芯片的封装引脚是直接与转接板电性连接的，避免了芯片组中各芯片的封装引脚直接与显示面板电性连接时所产生的高温对显示面板带来的破坏；并且由于转接板面向显示面板的一侧的凸点的表面为金，由于金具有导电性高、耐高温、耐湿、稳定性高、抗氧化性高以及电气和机械连接性好等优良特性，满足现有COG封装工艺的要求，因此可以不需要改变现有的芯片组中各芯片的封装引脚设计，而是采用现有的COG封装工艺通过转接板就能实现显示面板上各种芯片的封装，从而降低封装工艺难度和成本，并能够极大的提高显示面板上芯片和器件封装的集成密度，进而适用于显示产品轻薄短小的发展趋势和大规模量产。
虽然上文中已经用一般性说明及具体实施方式，对本发明实施例作了详尽的描述，但在本发明实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本发明精神的基础上所做的这些修改或改进，均属于本发明要求保护的范围。
本申请要求于2015年9月16日递交的中国专利申请第201510590867.1 号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (11)

  1. 一种显示面板的封装结构，包括：显示面板、用于控制所述显示面板的芯片组、以及转接板，其中，
    所述芯片组位于所述显示面板的上方，所述转接板位于所述芯片组与所述显示面板之间；
    所述转接板面向所述显示面板一侧的凸点的表面为金；
    所述芯片组中各芯片的封装引脚通过所述转接板与所述显示面板电性连接。
  2. 如权利要求1所述的封装结构，其中，所述转接板为硅通孔转接板。
  3. 如权利要求1或2所述的封装结构，还包括：位于所述转接板与所述显示面板之间的各向异性导电胶膜，所述转接板通过所述各向异性导电胶膜与所述显示面板电性连接。
  4. 如权利要求1至3中任一项所述的封装结构，还包括：填充于所述转接板与所述芯片组的之间的至少部分区域的底部填充胶。
  5. 如权利要求1至4中任一项所述的封装结构，其中，所述转接板面向所述显示面板一侧的所述凸点的整体材质为金。
  6. 一种显示装置，包括如权利要求1至5中任一项所述的显示面板的封装结构。
  7. 一种转接板，所述转接板至少一侧的凸点的表面为金。
  8. 如权利要求7所述的转接板，其中，所述凸点的整体材质为金。
  9. 一种显示面板的封装方法，包括：
    采用回流焊接工艺将用于控制所述显示面板的芯片组中的各芯片的封装引脚与转接板的第一侧电性连接；以及
    采用覆晶玻璃封装工艺将所述转接板的第二侧与所述显示面板电性连接，其中所述转接板的第二侧的凸点的表面为金。
  10. 如权利要求9所述的封装方法，其中，采用覆晶玻璃封装工艺将所述转接板的第二侧与所述显示面板电性连接，执行为：
    在所述转接板的第二侧形成各向异性导电胶膜；或在所述显示面板面向所述转接板的一侧形成各向异性导电胶膜；以及
    采用热压工艺将所述转接板与所述显示面板通过所述各向异性导电胶膜电性连接。
  11. 如权利要求9或10所述的封装方法，其中，在采用回流焊接工艺将用于控制所述显示面板的芯片组中的各芯片的封装引脚与所述转接板的第一侧电性连接之后，所述封装方法还包括：
    在所述转接板与所述芯片组之间填充底部填充胶。
PCT/CN2016/075191 2015-09-16 2016-03-01 显示面板的封装结构、转接板、封装方法及显示装置 WO2017045372A1 (zh)

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