CN111081700A - 具有增强型热管理的半导体装置封装及相关系统 - Google Patents

具有增强型热管理的半导体装置封装及相关系统 Download PDF

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Publication number
CN111081700A
CN111081700A CN201910994476.4A CN201910994476A CN111081700A CN 111081700 A CN111081700 A CN 111081700A CN 201910994476 A CN201910994476 A CN 201910994476A CN 111081700 A CN111081700 A CN 111081700A
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die
device package
carrier
semiconductor device
relatively high
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CN111081700B (zh
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阿龙·T·伦德
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Micron Technology Inc
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Micron Technology Inc
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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Abstract

本申请案涉及具有增强型热管理的半导体装置封装及相关系统。一种半导体装置封装包括：载体衬底，其具有中心阱；逻辑裸片，其面对并以可操作方式耦合到所述载体衬底的TSV；及一或多个存储器裸片，其位于所述阱中且接近所述逻辑裸片的面对所述载体衬底的表面而以可操作方式耦合到所述逻辑裸片。还揭示一种电子系统。

Description

具有增强型热管理的半导体装置封装及相关系统
技术领域
本文中所揭示的实施例涉及半导体装置封装。更特定来说，本文中所揭示的实施例涉及经配置以用于增强型热管理且包括相对高电力半导体裸片及一或多个相关联相对低电力半导体裸片的半导体装置封装，且涉及相关系统。
背景技术
在半导体工业中制作包括具有不同功能性的半导体裸片(例如堆叠于相对高电力裸片上的一或多个相对低电力裸片)的半导体装置封装变得越来越普遍。举例来说，可将多个存储器裸片(例如DRAM裸片)堆叠于被配置为存储器控制器的逻辑裸片上且将所得组合件配置为所谓的混合存储器立方体以用于连接到较高层级封装。其它组合件可将中心处理器单元(CPU)裸片、专用集成电路(ASIC)裸片或现场可编程门阵列(FPGA)与多个存储器裸片(例如DRAM、SRAM、FRAM、MRAM、EEPROM、FLASH中的一或多者以及其它类型的存储器裸片)进行组合。尽管产生紧凑封装，但存储器裸片堆叠有效地用作绝缘毯覆层以容纳在操作中由较高电力逻辑裸片产生的热。在此组合件上方安置散热器以与存储器裸片堆叠的顶部接触有点无效，这是因为散热器并不与高电力裸片、具体来说相对高电力裸片占用面积中的产生很大部分热的部分直接接触。
尽管已提出若干种冷却方法来解决上述问题，但此类方法为昂贵的，在一些情形中为复杂的且在大多数情形中无法广泛应用于具有不同功能性的相对高电力半导体裸片的各种不同组合件、不同集成电路配置以及用于电力、接地/偏置及数据的不同I/O引脚配置。
发明内容
在实施例中，一种半导体装置封装包括：载体，其包括TSV且包含位于其中心区域中的阱；相对高电力半导体裸片，其延伸于所述载体的表面上方、所述阱上方且在所述载体的所述表面上以可操作方式耦合到所述载体的TSV；及一或多个相对低电力半导体裸片，其位于所述载体的所述阱中且以可操作方式耦合到所述相对高电力半导体裸片。
在实施例中，一种半导体装置封装包括：逻辑裸片，其延伸于载体衬底的表面上方；及一或多个存储器裸片，其面对所述逻辑裸片的面对所述载体衬底的表面而以可操作方式耦合到所述逻辑裸片，所述一或多个存储器裸片从接近所述表面延伸到所述载体衬底中的阱中。
在实施例中，一种电子系统包括输入装置、输出装置及存储器装置。所述存储器装置包括：具备TSV功能的载体衬底，其具有从中穿过的中心阱；及半导体裸片堆叠，其延伸到所述阱中且与另一半导体裸片可操作连通，所述另一半导体裸片延伸于所述载体衬底的表面上方且与所述载体衬底的TSV可操作连通。所述电子系统进一步包括电子信号处理装置，所述电子信号处理装置以可操作方式耦合到所述存储器装置、所述输入装置及所述输出装置。
附图说明
图1是根据本发明的实施例的半导体装置封装的示意性侧视横截面立面图；
图2是根据本发明的另一实施例的半导体装置封装的示意性侧视横截面立面图；
图3是根据本发明的实施例的经配置以供与半导体装置封装的实施例一起使用的载体衬底的示意性透视图；且
图4是根据本发明的实施例的并入有半导体装置封装的电子系统的框图。
具体实施方式
本文中所描述的半导体装置封装包含以下各项的组合件：相对高电力半导体裸片，其以可操作方式耦合到相对低电力半导体裸片中的一或多者；相对低电力半导体裸片，其以可操作方式耦合到相对高电力裸片且延伸到载体衬底中的阱中，所述载体衬底经配置以将组合件以可操作方式耦合到外部电路。散热器延伸于相对高电力裸片上方且与所述相对高电力裸片热接触。
以下描述提供特定细节(例如大小、形状、材料组合物及定向)，以便提供对本发明的实施例的透彻描述。然而，所属领域的技术人员将理解，可在无需采用这些特定细节的情况下实践本发明的实施例。本发明的实施例可结合工业中所采用的常规制作技术来实践。另外，下文提供的描述并不形成用于制作半导体装置封装的完整工艺流程。下文仅详细地描述用于理解本发明的实施例所必需的那些工艺动作及结构。可通过常规制作工艺而执行用以形成完整半导体装置封装的额外动作。
本文中所呈现的图式仅出于说明性目的，且并非意指任何特定材料、组件、结构、装置或系统的实际视图。预期图式中所描绘的形状会因(举例来说)制造技术及/或公差而有所变化。因此，本文中所描述的实施例不应视为限于如所图解说明的特定形状或区域，而是包含因(举例来说)制造而引起的形状偏差。举例来说，被图解说明或描述为盒状的区域可具有粗糙及/或非线性特征，且被图解说明或描述为圆的区域可包含一些粗糙及/或线性特征。此外，所图解说明的表面之间的锐角可被修圆，且反之亦然。因此，图中所图解说明的区域本质上为示意性的，且其形状并非打算图解说明区域的精确形状且并非限制本权利要求书的范围。所述图式未必按比例绘制。
如本文中所使用，术语“包括(comprising)”、“包含(including)”、“含有(containing)”、“由…表征(characterized by)”及其语法等效内容为包含性或开放式术语，其不排除额外未叙述元件或方法动作，但还包含较限制性术语“由…组成(consistingof)”及“基本上由…组成(consisting essentially of)”以及其语法等效内容。如本文中所使用，关于材料、结构、特征或方法动作的术语“可(may)”指示此被预期用于本发明的实施例的实施方案中且此术语优先于较限制性术语“是(is)”而使用以避免对于应该或必须排除可与所述材料、结构、特征或方法动作组合使用的其它兼容材料、结构、特征及方法的任何暗示。
如本文中所使用，术语“纵向”、“垂直”、“横向”及“水平”是参考其中或其上形成一或多个结构及/或特征的衬底(例如，基底材料、基底结构、基底构造等)的主平面，且未必由地球的重力场界定。“横向”或“水平”方向是大体上平行于衬底的主平面的方向，而“纵向”或“垂直”方向是大体上垂直于衬底的主平面的方向。衬底的主平面由衬底的与衬底的其它表面相比具有相对大面积的表面界定。
如本文中所使用，为便于描述，可使用空间相对术语(例如“下方”、“下面”、“下部”、“底部”、“上面”、“上方”、“上部”、“顶部”、“前”、“后”、“左”、“右”等等)来描述一个元件或特征与另一元件或特征的关系，如各图中所图解说明。除非另有说明，否则除各图中所描绘的定向之外，所述空间相对术语还打算囊括材料的不同定向。举例来说，如果颠倒各图中的材料，那么被描述为在其它元件或特征“上方”或“上面”或者“上”或“顶部上”的元件则将被定向为在其它元件或特征“下面”或“下方”或者“底下”或“底部上”。因此，术语“上方”可囊括对所属领域的技术人员将为明显的上面及下面的定向两者(此取决于使用所述术语的上下文)。可以其它方式(例如，旋转90度、反转、翻转)定向材料且相应地解释本文中所使用的空间相对描述语。此外，除非明确陈述，否则由前述术语中的任一者指定的关系不需要指示或预期一个元件与另一元件的实际直接物理接触。
如本文中所使用，除非上下文另有明确指示，否则单数形式“一(a、an)”及“所述(the)”也打算包含复数形式。
如本文中所使用，术语“经配置(configured)及“配置(configuration)”是指至少一个结构及至少一个设备中的一或多者的以预定方式促进所述结构及设备中的一或多者的操作的大小、形状、材料组合物、定向及布置。
如本文中所使用，参考给定参数、性质或条件的术语“大体上(substantially)”意指且包含所属领域的技术人员将理解到如下程度：给定参数、性质或条件以一定程度的变化(例如在可接受制造公差内)来满足。通过实例方式，取决于大体上满足的特定参数、性质或条件，所述参数、性质或条件可得到至少90.0％满足、至少95.0％满足、至少99.0％满足或甚至至少99.9％满足。
如本文中所使用，参考用于特定参数的数值的“约(about)”或“大约(approximately)”包含所述数值以及所属领域的技术人员将理解的、在针对所述特定参数的可接受公差内的从所述数值的一定程度的变化。举例来说，参考数值的“约”或“大约”可包含在从所述数值的90.0％到110.0％的范围内(例如在从所述数值的95.0％到105.0％的范围内、在从所述数值的97.5％到102.5％的范围内、在从所述数值的99.0％到101.0％的范围内、在从所述数值的99.5％到100.5％的范围内或在从所述数值的99.9％到100.1％的范围内)的额外数值。
如本文中所使用，除非另有指示，否则术语“层”及“膜”意指且包含驻存于结构上的材料的层面、薄片或涂层，所述层面或涂层可在所述材料的部分之间为连续或不连续的，且可为保形或非保形的。
如本文中所使用，术语“衬底”意指且包含在其上形成额外材料的基底材料或构造。衬底可为半导体衬底、支撑结构上的基底半导体层、金属电极、玻璃材料、陶瓷材料或其上形成有一个或多个材料、层、结构或区域的半导体衬底。半导体衬底上的材料可包含但不限于半导电材料、绝缘材料、导电材料等。衬底可为常规硅衬底或其它块体衬底，包括半导电材料层。如本文中所使用，术语“块体衬底”不仅意指且包含硅晶片，而且意指且包含绝缘体上硅(“SOI”)衬底(例如蓝宝石上硅(“SOS”)衬底及玻璃上硅(“SOG”)衬底)、在基底半导体底座上的外延硅层及其它半导体或光电材料(例如硅锗、锗、砷化镓、氮化镓及磷化铟)。衬底可为经掺杂或未经掺杂的。
如本文中所使用，术语“包括(comprising)”、“包含(including)”、“含有(containing)”、“由…表征(characterized by)”及其语法等效内容为包含性或开放式术语，其不排除额外未叙述元件或方法步骤，但还包含较限制性术语“由…组成(consistingof)”及“基本上由…组成(consisting essentially of)”以及其语法等效内容。
如本文中所使用，术语“经配置(configured)”是指至少一个结构及至少一个设备中的一或多者的以预定方式促进所述结构及设备中的一或多者的操作的大小、形状、材料组合物及布置。
如本文中所使用，关于材料、结构、特征或方法动作的术语“可(may)”指示此被预期用于本发明的实施例的实施方案中且此术语优先于较限制性术语“是(is)”而使用以避免对于应该或必须排除可与所述材料、结构、特征或方法动作组合使用的其它兼容材料、结构、特征及方法的任何暗示。
如本文中所使用，术语“在…之间(between)”是用于描述一种材料、区域或子区域相对于至少两个其它材料、区域或子区域的相对安置的空间相对术语。术语“在…之间”可囊括一种材料、区域或子区域直接邻近于其它材料、区域或子区域的安置以及一种材料、区域或子区域间接邻近于其它材料、区域或子区域的安置两者。
如本文中所使用，术语“接近(proximate)”是用于描述一种材料、区域或子区域靠近另一材料、区域或子区域的安置的空间相对术语。术语“接近”包含间接邻近于、直接邻近于以及在…内部的安置。
如本文中所使用，当提及材料或区域时，术语“相邻(neighboring)”意指且指代所识别组合物的下一最接近材料或区域。除所识别组合物之外的其它组合物的材料或区域可安置于一种材料或区域与所识别组合物的其“相邻”材料或区域之间。举例来说，“相邻”于导电材料区域的钝化材料区域为(例如)多个钝化材料区域中的最接近于特定导电材料区域的钝化材料区域。“邻近”材料或区域可直接或间接接近所识别组合物的区域或材料。
如本文中所使用，术语“重布层”或“RDL”意指且包含呈横向延伸迹线的形式且放置成邻近承载接合垫或其它金属化物的电子组件的表面的导电元件，所述迹线在两个组件的所选择横向偏移位置处实现组件到组件电连接。重布层(RDL)可包括至少一个导电区域(例如，单个导电迹线层，或垂直互连的多个层)，所述至少一个导电区域安置于绝缘(例如，介电)材料中且可通过从导电迹线延伸到RDL的相对主表面的导电触点而接达。
如本文中所使用，通过非限制性实例方式，术语“相对高电力半导体裸片”意指且包含呈存储器控制器、CPU、ASIC或FPGA形式的逻辑。此外，“相对高电力”半导体裸片意指且包含具有高电力密度的一或多个区域的裸片，举例来说移动逻辑裸片。如本文中所使用，通过非限制性实例方式，术语“相对低电力半导体裸片”意指且包含呈DRAM、SRAM、FRAM、MRAM、EEPROM或FLASH形式的存储器。更广泛地，如本文中所使用，当在普通组合件或封装中的半导体裸片的上下文中使用时，术语“相对高电力半导体裸片”及“相对低电力半导体裸片”通过相互比较方式而非在绝对意义上使用。换句话说，相对高电力半导体裸片是与另外一或若干相对低电力相关联半导体裸片相比而如此表征的。
现在将参考图式，其中在通篇中相似编号是指相似组件。所述图式未必按比例绘制。
图1是根据本发明的实施例的半导体装置封装100的示意性侧视横截面立面图。半导体装置封装100包含载体衬底102，所述载体衬底可简单地表征为“载体”，配置有贯穿衬底通路(TSV)104，如图3中所展示。载体衬底102可包括通常被称作FR-4的玻璃环氧树脂层压体或展现可与封装的其它组件兼容的性质的另一材料，例如玻璃材料、陶瓷材料或硅材料(例如，熔融二氧化硅)。如果载体衬底102由导电或半导电材料制作，那么TSV104中的导电材料可利用给通路孔加衬的介电材料而与衬底材料电隔离，如所属领域的技术人员已知。
在其有源表面110上并入有集成电路108的相对高电力半导体裸片106(例如，具有高电力密度的一或多个区域的裸片)安装于载体衬底102的表面112上方且通过从有源表面110突出的导电元件114而以可操作方式耦合到载体衬底102的TSV 104，所述导电元件可包括焊料球或凸块、导电螺柱、立柱或柱或者其它常规导电元件。在一个实施例中，采用焊料凸块且将其回焊以接合到TSV 104。在另一实施例中，采用铜柱且将其扩散接合到铜TSV104。可将介电底填充材料(未展示)安置于半导体裸片106与载体衬底102之间，以机械地固定半导体裸片106且防止导电元件114之间的短路。半导体裸片106还以可操作方式耦合到一或多个相对低电力半导体裸片116以用于递送电力及接地/偏置信号。如果适合金属化物存在于半导体裸片106的有源表面110上，那么一或若干半导体裸片116可直接以可操作方式耦合到半导体裸片106。否则，一或若干半导体裸片116可通过有源表面110上的重布层(RDL)118的导电迹线而以可操作方式耦合，RDL 118的导电迹线还通过从RDL 118突出的额外导电元件114而以可操作方式耦合到载体衬底102的TSV 104。任何适合数目个半导体裸片116可以可操作方式耦合到半导体裸片106。举例来说，如果半导体裸片116为DRAM裸片，那么一个、四个、八个、十二个或十六个裸片可以可操作方式耦合，且如果采用多个半导体裸片，那么可将此类裸片布置成堆叠。
如果采用多个半导体裸片116，那么半导体裸片116的所得堆叠由TSV 120及导电柱122(举例来说，铜柱)互连，所述导电柱通过扩散接合而物理及电连接到TSV 120。介电底填充材料(为清晰起见，未展示)(例如非导电膜(NCF)或毛细管底填充物)可任选地位于邻近半导体裸片116之间的空间中以提供半导体裸片116之间的额外相互物理接合且环绕导电柱122并防止柱之间的短路。如上所述，半导体裸片116的堆叠直接以可操作方式耦合到半导体裸片106或在RDL 118的与半导体裸片106相对的主表面上以可操作方式耦合到所述RDL的导电迹线。仅以实例方式，注意半导体裸片116可或可不为相同类型。换句话说，再次仅以实例方式，半导体裸片116可包括DRAM、NAND或NOR快闪存储器、3DXP存储器或次要逻辑。在此实例中，邻近半导体裸片116的TSV 120可横向偏移，且通过延伸到邻近半导体裸片116的TSV的位置的迹线而相互耦合，如所属领域的技术人员已知。
半导体裸片116或半导体裸片116的堆叠背对半导体裸片106而从RDL 118延伸到载体衬底102的阱124中。可采用任选散热器126，所述任选散热器通过热界面材料(TIM，未展示)而至少与半导体裸片116的最远地延伸到阱124中的表面128接触。散热器126可任选地包括裙部(skirt)130(以虚线展示)，且当散热器126接触半导体裸片116的最远地延伸到阱124中的表面128(如由箭头所指示)时，所述裙部可横向部分地或完全地环绕与其接触的半导体裸片116或半导体裸片116的堆叠。
散热器132可延伸于半导体裸片106上方、通过TIM(未展示)而与所述半导体裸片的后侧134接触。散热器132还可经定大小(如以虚线所展示)以用于通过TIM而与半导体裸片106的横向外围136接触，并且被配置有接近载体衬底102的表面112的向外且向下展开表面(如所展示)，以适应底填充材料(如果采用)的横向扩展。散热器132的外围部分138可接触载体衬底102的表面112且通过导热粘合剂140而接合到所述表面。
载体衬底102的TSV 104可通过外部导电元件142而将半导体装置封装100以可操作方式耦合到较高层级封装(未展示)，所述外部导电元件可包括焊料球或凸块、导电柱、立柱或螺柱或者导电焊盘。
图2是根据本发明的实施例的半导体装置封装100′的示意性侧视横截面立面图。半导体装置封装100′包含载体衬底102，所述载体衬底可简单地表征为“载体”，配置有贯穿衬底通路(TSV)104，如图3中所展示。载体衬底102可包括通常被称作FR-4的玻璃环氧树脂层压体或展现可与封装的其它组件兼容的性质的另一材料，例如玻璃材料、陶瓷材料或硅材料(例如，熔融二氧化硅)。如果载体衬底102由导电或半导电材料制作，那么TSV 104中的导电材料可利用给通路孔加衬的介电材料而与衬底材料电隔离，如所属领域的技术人员已知。
在其有源表面110上并入有集成电路108的相对高电力半导体裸片106(例如，具有高电力密度的一或多个区域的裸片)安装于载体衬底102的表面112上方。半导体裸片106通过导电元件113而以可操作方式耦合到中介层118′的导电迹线，所述导电元件从有源表面110突出且可包括焊料球或凸块、导电螺柱、立柱或柱或者其它常规导电元件。在一个实施例中，采用焊料凸块且将其回焊以接合到中介层118′的端子。在另一实施例中，采用铜柱且将其扩散接合到中介层118′的端子。可将介电底填充材料(未展示)安置于半导体裸片106与中介层118′之间，以机械地固定半导体裸片106且防止导电元件113之间的短路。中介层118′通过导电元件114而以可操作方式耦合到载体衬底102的TSV 104，所述导电元件从中介层118′突出且(如在导电元件113的情形中)可包括焊料球或凸块、导电螺柱、立柱或柱或者其它常规导电元件。还可将介电底填充材料安置于中介层118′与载体衬底102之间。一或多个相对低电力半导体裸片116在中介层118′的与半导体裸片106相对的侧上以可操作方式耦合到所述中介层的端子。中介层118′可促进半导体装置封装100′的组件之间的信号路由以及提供半导体裸片106与半导体裸片116之间的热绝缘。任何适合数目个半导体裸片116可以可操作方式耦合到半导体裸片106。举例来说，如果半导体裸片116为DRAM裸片，那么一个、四个、八个、十二个或十六个裸片可以可操作方式耦合，且如果采用多个半导体裸片，那么可将此类裸片布置成堆叠。
如果采用多个半导体裸片116，那么半导体裸片116的所得堆叠由TSV 120及导电柱122(举例来说，铜柱)互连，所述导电柱通过扩散接合而物理及电连接到TSV 120。介电底填充材料(为清晰起见，未展示)(例如非导电膜(NCF)或毛细管底填充物)可任选地位于邻近半导体裸片116之间的空间中以提供半导体裸片116之间的额外相互物理接合且环绕导电柱122并防止柱之间的短路。仅以实例方式，注意半导体裸片116可或可不为相同类型。换句话说，再次仅以实例方式，半导体裸片116可包括DRAM、NAND或NOR快闪存储器、3DXP存储器或次要逻辑。在此实例中，邻近半导体裸片116的TSV 120可横向偏移，且通过延伸到邻近半导体裸片116的TSV的位置的迹线而相互耦合，如所属领域的技术人员已知。
半导体裸片116或半导体裸片116的堆叠背对半导体裸片106而从中介层118′延伸到载体衬底102的阱124中。可采用任选散热器126，所述任选散热器通过热界面材料(TIM，未展示)而至少与半导体裸片116的最远地延伸到阱124中的表面128接触。散热器126可任选地包括裙部130(以虚线展示)，且当散热器126接触半导体裸片116的最远地延伸到阱124中的表面128(如由箭头所展示)时，所述裙部可围绕半导体裸片116或半导体裸片116的堆叠的外围的至少部分延伸，从而横向部分地或完全地环绕与其接触的半导体裸片116的堆叠。
散热器132可延伸于半导体裸片106上方、通过TIM(未展示)而与所述半导体裸片的后侧134接触。散热器132还可经定大小(如以虚线所展示)以用于通过TIM而与半导体裸片106的横向外围136以及中介层118′接触，并且被配置有接近载体衬底102的表面112的向外且向下展开表面(如所展示)，以适应中介层118′与载体衬底102之间的底填充材料(如果采用)的横向扩展。当然，如果中介层118′横向大于半导体裸片106且在半导体裸片106与中介层118′之间采用底填充物，那么散热器132可被配置有介于半导体裸片106与中介层118′之间的额外展开表面(未展示)。散热器132的外围部分138可接触载体衬底102的表面112且通过导热粘合剂140而接合到所述表面。
载体衬底102的TSV 104可通过外部导电元件142而将半导体装置封装100以可操作方式耦合到较高层级封装(未展示)，所述外部导电元件可包括焊料球或凸块、导电柱、立柱或螺柱或者导电焊盘。
在图2的实施例的一个特定实施方案中，中介层118′可被配置为数据缓冲器芯片。
在本发明的任一实施例的特定实施方案中，如果相对高电力半导体裸片106为具备TSV功能的，那么有源表面110可从图1及2中所展示的位置倒置(如图2中的虚线所展示)，使得集成电路108面对散热器132且通过TIM而与所述散热器接触。相对低电力半导体裸片116可接着邻近半导体裸片106的(经倒置)后侧134而堆叠且通过RDL 118或中介层118′而以可操作方式耦合到所述后侧，半导体裸片116的堆叠再次延伸到载体衬底102的阱124中。替代地，半导体裸片106可为具备TSV功能的，其中有源表面110面对半导体裸片116的堆叠。在具有此配置的情况下，预期可将一或多个额外半导体裸片(举例来说，SRAM或MRAM裸片)堆叠于被配置为存储器控制器的半导体裸片106上，且放置成与散热器132直接进行热连通。此外，预期可将展现不同功能性的多个裸片106的其它组合进行堆叠，举例来说，将CPU堆叠于存储器控制器上方。
在以上实施例中的每一者中且通过特定但非限制性实例方式，预期相对高电力裸片106可为被配置为存储器控制器的逻辑裸片，且相对低电力裸片可各自为DRAM的形式。
如所属领域的技术人员将了解，与混合存储器立方体及其它常规多裸片封装配置相比，根据本发明的实施例的半导体封装可通过以较低成本进行增强型热管理(通过消除逻辑裸片中的TSV、消除主动冷却要求)及较低构造成本而提供优越性能。来自逻辑裸片及存储器裸片堆叠的热的相互隔离、结合在相反方向上从所述两个源吸走热的散热器以及由包括中介层的实施例所提供的热源之间的绝缘可对这些半导体装置封装提供大幅度增强型温度控制。另外，此类封装可为3D封装解决方案提供较大市场份额。此外，与常规3D封装相比，可以较低电力实现较高封装性能，这是因为将信号长度减小到大约40μm到约60μm，从而减小驱动器大小(电力)及信号距离(等待时间)。举例来说，八裸片存储器堆叠可展现小于约半毫米的高度。
根据本发明的实施例的半导体装置封装可用于本发明的电子系统的实施例中。举例来说，图4是根据本发明的实施例的说明性电子系统200的框图。电子系统200可包括(举例来说)计算机或计算机硬件组件、服务器或其它联网硬件组件、蜂窝式电话(例如，“智能电话”)、数码相机、个人数字助理(PDA)、便携式媒体(例如，音乐)播放器、Wi-Fi或具蜂窝能力的平板计算机(例如，
Figure BDA0002239322150000101
或
Figure BDA0002239322150000102
平板计算机)、另一无线装置、电子书、导航装置、显示器、芯片集、机顶盒、游戏系统、交通工具或其组件、照明系统、传感器、手表等。电子系统200包含至少一个存储器装置202。存储器装置202可包含(举例来说)半导体装置封装100或100′的实施例。如本文中所揭示，此存储器装置202可包含存储器裸片及用于其它功能的一或多个其它半导体裸片配置(例如，被配置为存储器控制器的逻辑裸片)。电子系统200可进一步包含至少一个电子信号处理器半导体裸片204(通常称作“微处理器”，其包括CPU、ASIC或FPGA)，所述至少一个电子信号处理器半导体裸片可被并入到半导体装置封装100或100′中。在一些实施例中，存储器控制器及微处理器可包括在半导体封装100或100′中的单独经堆叠裸片。在其它实施例中，存储器控制器及微处理器功能可被并入于单个半导体裸片中。电子系统200可进一步包含用于由用户将信息输入到电子系统200中的一或多个输入装置206，例如鼠标或其它指向装置、键盘、触摸垫、按钮或控制面板。电子系统200可进一步包含用于将资讯(例如，射频、视觉或音频输出)输出给用户的一或多个输出装置208，例如调制解调器、
Figure BDA0002239322150000103
收发器、监视器、显示器、打印机、音频输出插孔、扬声器等。在一些实施例中，输入装置206及输出装置208可包括可用于将信息输入到电子系统200及将视觉信息输出给用户两者的单个触摸屏装置。输入装置206及输出装置208可与存储器装置202及电子信号处理器装置204中的一或多者进行电通信。还预期替代单独存储器202及信号处理器装置204，可将具有不同功能性的半导体裸片的单个组合件配置为封装中的系统，所述系统包含处理器及/或如先前所述的其它裸片功能性。
尽管已结合各图描述特定说明性实施例，但所属领域的技术人员将认识到并了解：由本发明囊括的实施例不限于本文中明确展示及描述的那些实施例。而是，可在不背离由本发明囊括的实施例的范围的情况下做出对本文中所描述的实施例的许多添加、删除及修改，例如后文中所主张的那些内容，包含合法等效内容。另外，来自一个所揭示实施例的特征可与另一所揭示实施例的特征组合，同时仍囊括于本发明的范围内。

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1.一种半导体装置封装，其包括：
载体，其包括TSV且包含位于其中心区域中的阱；
相对高电力半导体裸片，其延伸于所述载体的表面上方、所述阱上方且在所述载体的所述表面上以可操作方式耦合到所述载体的TSV；及
一或多个相对低电力半导体裸片，其位于所述载体的所述阱中且以可操作方式耦合到所述相对高电力半导体裸片。
2.根据权利要求1所述的半导体装置封装，其进一步包括位于所述相对高电力半导体裸片上的重布层，所述重布层以可操作方式耦合到所述一或多个相对低电力半导体裸片且耦合到所述载体的TSV。
3.根据权利要求2所述的半导体装置封装，其中所述重布层位于所述相对高电力半导体裸片的包括集成电路的有源表面上方。
4.根据权利要求2所述的半导体装置封装，其中所述相对高电力半导体裸片的包括集成电路的有源表面背对所述重布层，且所述相对高电力半导体裸片的TSV将所述集成电路以可操作方式耦合到所述重布层。
5.根据权利要求2所述的半导体装置封装，其中所述重布层及所述相对高电力半导体裸片利用导电元件来以可操作方式耦合到所述载体的TSV，所述导电元件从所述重布层及所述相对高电力半导体裸片的表面突出且延伸到所述载体的所述表面。
6.根据权利要求1所述的半导体装置封装，其进一步包括介于所述载体与所述相对高电力半导体裸片之间的中介层，所述中介层以可操作方式耦合到所述相对高电力半导体裸片、所述一或多个相对低电力半导体裸片且耦合到所述载体的TSV。
7.根据权利要求6所述的半导体装置封装，其中所述相对高电力半导体裸片的包括集成电路的有源表面面对所述中介层。
8.根据权利要求6所述的半导体装置封装，其中所述相对高电力半导体裸片的包括集成电路的有源表面背对所述中介层，且所述中介层以可操作方式耦合到所述相对高电力半导体裸片的TSV。
9.根据权利要求6所述的半导体装置封装，其中所述相对高电力半导体裸片通过导电元件而以可操作方式耦合到所述中介层，所述导电元件延伸于所述相对高电力半导体裸片及所述中介层的面对表面之间，且所述中介层通过导电元件而以可操作方式耦合到所述载体的TSV，所述导电元件延伸于所述中介层及所述载体的面对表面之间。
10.根据权利要求6所述的半导体装置封装，其中所述中介层被配置为数据缓冲器芯片。
11.根据权利要求1所述的半导体装置封装，其进一步包括延伸于所述相对高电力半导体裸片上方且与所述相对高电力半导体裸片热接触的散热器。
12.根据权利要求11所述的半导体装置封装，其中所述散热器延伸到所述载体的面对所述相对高电力半导体裸片的所述表面。
13.根据权利要求1所述的半导体装置封装，其进一步包括至少部分地位于所述载体的所述阱中的散热器，所述散热器与相对低电力裸片的背对所述相对高电力裸片的表面热接触。
14.根据权利要求13所述的半导体装置封装，其中所述散热器包括裙部，所述裙部朝向所述相对高电力半导体裸片且围绕所述一或多个相对低电力半导体裸片的外围的至少部分延伸。
15.根据权利要求1所述的半导体装置封装，其中所述一或多个相对低电力半导体裸片包括多个经堆叠裸片，所述多个经堆叠裸片中的至少一些经堆叠裸片包括TSV，且所述TSV利用与所述TSV以可操作方式耦合的导电元件来以可操作方式耦合于堆叠中的裸片之间。
16.根据权利要求1所述的半导体装置封装，其进一步包括位于所述载体的背对所述相对高电力半导体裸片的表面上且以可操作方式耦合到所述载体的TSV的导电元件。
17.一种半导体装置封装，其包括：
逻辑裸片，其延伸于载体衬底的表面上方；及
一或多个存储器裸片，其面对所述逻辑裸片的面对所述载体衬底的表面而以可操作方式耦合到所述逻辑裸片，所述一或多个存储器裸片从接近所述表面延伸到所述载体衬底中的阱中。
18.根据权利要求17所述的半导体装置封装，其中所述逻辑裸片被配置为存储器控制器，且所述一或多个存储器裸片包括多个具备TSV功能的裸片。
19.根据权利要求17所述的半导体装置封装，其进一步包括位于所述逻辑裸片与所述载体衬底之间的重布层及中介层中的一者。
20.根据权利要求17所述的半导体装置封装，其进一步包括以下各项中的至少一者：
散热器，其在所述逻辑裸片的背对所述载体衬底的表面上延伸于所述逻辑裸片上方，所述散热器与背对所述衬底的所述表面热接触，所述散热器包括外围部分，所述外围部分延伸于所述逻辑裸片的侧上方且与所述载体衬底的面对所述逻辑裸片的表面热接触；或
散热器，其至少部分地定位到所述阱中且与存储器裸片的背对所述逻辑裸片的表面热接触。
21.根据权利要求20所述的半导体装置封装，其中至少部分地定位于所述阱中的所述散热器包括延伸于所述一或多个存储器裸片的至少一些侧上方的裙部。
22.根据权利要求17所述的半导体装置封装，其中所述逻辑裸片被配置为中央处理单元CPU、专用集成电路ASIC或现场可编程门阵列FPGA。
23.一种电子系统，其包括：
输入装置；
输出装置；
存储器装置，其包括：
具备TSV功能的载体衬底，其具有从中穿过的中心阱；及
半导体裸片堆叠，其延伸到所述阱中且与另一半导体裸片可操作连通，所述另一半导体裸片延伸于所述载体衬底的表面上方且与所述载体衬底的TSV可操作连通；以及
电子信号处理装置，其以可操作方式耦合到所述存储器装置、所述输入装置及所述输出装置。
24.根据权利要求23所述的电子系统，其中所述另一半导体裸片包括所述电子信号处理装置。
25.根据权利要求23所述的电子系统，其进一步包括位于所述另一半导体裸片与所述载体衬底之间且与所述另一半导体裸片及所述载体衬底可操作连通的重布层或中介层。
26.根据权利要求23所述的电子系统，其进一步包括散热器或半导体裸片中的至少一者，所述散热器在所述另一半导体裸片的背对所述载体衬底的表面上与所述另一半导体裸片热接触，所述半导体裸片与位于所述载体衬底的所述中心阱内的所述半导体裸片堆叠热接触。
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