WO2017041661A1 - 一种半导体元件及其制备方法 - Google Patents

一种半导体元件及其制备方法 Download PDF

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WO2017041661A1
WO2017041661A1 PCT/CN2016/097754 CN2016097754W WO2017041661A1 WO 2017041661 A1 WO2017041661 A1 WO 2017041661A1 CN 2016097754 W CN2016097754 W CN 2016097754W WO 2017041661 A1 WO2017041661 A1 WO 2017041661A1
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layer
buffer layer
semiconductor device
superlattice structure
substrate
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PCT/CN2016/097754
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English (en)
French (fr)
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周圣伟
卓昌正
林兓兓
张家宏
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厦门市三安光电科技有限公司
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Publication of WO2017041661A1 publication Critical patent/WO2017041661A1/zh
Priority to US15/607,484 priority Critical patent/US10096746B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method of fabricating the same.
  • the cutting technology of semiconductor components has gradually evolved from diamond knife cutting to ordinary laser cutting.
  • the wavelength of laser light is 355 nm or 266 nm, which is characterized in that it can draw both sapphire substrates and various films. Layers, such as gallium nitride layers, Bragg reflectors, metal layers, and the like.
  • the surface of the epitaxial wafer can be split by a laser to form a surface dicing road, or a hidden scribe line can be formed by using a laser focusing substrate to achieve the purpose of separating a single core particle.
  • the impurities formed by laser ablation adhere to the sidewall of the scribe line, blocking the emission of light, and affecting the external quantum efficiency of the semiconductor element. Therefore, in order to avoid the influence of the burning impurities on the brightness of the light, the laser is used to soak the etching after the laser is formed into a dicing line to remove the laser burning impurities and clean the side walls of the cutting track.
  • PVD method The physical vapor deposition method (PVD method) has the characteristics of simple process, low environmental pollution, low consumption of raw materials, uniform film formation and strong adhesion to substrates, and is now more and more applied to semiconductors.
  • PVD method In the preparation of components, it is usually used for the preparation of epitaxial wafer underlayers, such as depositing an aluminum nitride layer as a buffer layer, which can reduce defects between the buffer substrate and the epitaxial layer due to lattice mismatch and thermal mismatch. And stress, improving the device quality of semiconductor components.
  • the aluminum nitride layer formed by the PVD method has characteristics such as polylattice and anisotropy, it is easily corroded by a chemical solution, so when the epitaxial wafer contains a buffer layer formed by a PVD method, the epitaxial layer is further extended by a laser. After the surface of the sheet is immersed, the chemical solution is immersed, which easily causes over-corrosion of the buffer layer or the contact surface between the buffer layer and the substrate, resulting in abnormal electrical properties of the core particles formed and lowering the production yield.
  • the present invention provides a semiconductor device including at least AN iJl and Al y ⁇ , - y layer (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l) superlattice structure buffer layer, the superlattice structure buffer layer is used to reduce chemical solution during sidewall etching of the chip process The degree of corrosion increases the chip yield.
  • a method for preparing the superlattice structure buffer layer is prepared by the same method to achieve the effect of the present invention.
  • the technical solution provided by the present invention is: a semiconductor device, comprising: a substrate, a buffer layer, an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer, wherein the buffer layer is including A Ni-J1 and AlyOi- y layer (0 ⁇ 1, 0 ⁇ y ⁇ l) a cyclically laminated superlattice structure layer; the buffer layer is used to reduce the degree of corrosion of the chemical solution during sidewall etching of the chip process, Improve chip yield.
  • Al X N iJ1 in the first cyclic lamination layer in the buffer layer is disposed between the Al y O layer and the substrate.
  • the Al X N iJl thickness is ⁇ A1 y O layer thickness.
  • the Al X N J1 has a thickness of 5 to 500 angstroms.
  • the Al y O layer has a thickness of 5 to 500 angstroms.
  • a buffer layer and the N-type semiconductor layer further comprise a non-trapped semiconductor layer.
  • the number of cycles of the superlattice structure layer is ⁇ 2.
  • the superlattice structure buffer layer proposed by the present invention is equivalent to dividing a conventional aluminum nitride single layer buffer layer into a multilayer film structure and inserting into the multilayer film.
  • the AlyO y layer the experimental results show that the contact surface of the A1 ⁇ ⁇ , J1 and Al y O y layers is more resistant to corrosion by the Al X N body than the chemical solution, so the superlattice structure of the structure increases AlxN.
  • the superlattice structure layer can increase the light extraction efficiency and improve the external quantum efficiency of the semiconductor element.
  • the present invention provides a method for preparing a semiconductor device, the method comprising: Sl, providing a substrate; S2, depositing on the surface of the substrate by physical vapor deposition a superlattice structure buffer layer composed of AlxNiJl and AlyOi- y layers (0 ⁇ 1, 0 ⁇ y ⁇ l), wherein the buffer layer reduces the corrosion degree of the chemical solution and improves the chip yield in the subsequent chip process; S3, use An epitaxial layer composed of an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer is deposited on the surface of the buffer layer by a chemical vapor deposition method, wherein the buffer layer prepared at a low temperature is annealed and recrystallized in a subsequent high-temperature epitaxial layer preparation process, and is used for The stress in the post deposition process is released.
  • the method uses a PVD method to deposit a superlattice structure buffer layer, and enters the AlyCU y layer to utilize its anti-corrosion properties. And the difference in lattice characteristics with AlxNiJl improves the characteristics of the buffer layer in the semiconductor device of the present invention, and releases the stress generated by the subsequent deposition of the epitaxial layer, which makes it more advantageous for the subsequent chip end process.
  • the Al x NiJ1 is deposited on the surface of the substrate by physical vapor deposition, and the Al y O v layer is deposited on the surface of the A1 ⁇ ⁇ and J1, and sequentially laminated to form a superlattice.
  • Structural buffer layer is deposited on the surface of the substrate by physical vapor deposition, and the Al y O v layer is deposited on the surface of the A1 ⁇ ⁇ and J1, and sequentially laminated to form a superlattice.
  • the step S3 further comprises: depositing a non-tough semiconductor layer on the surface of the buffer layer, and then depositing the N-type semiconductor layer.
  • the Al X N iJl thickness is ⁇ A1 y O y layer thickness.
  • the Al X N 1 ! 4 layer has a thickness of 5 to 500 angstroms.
  • the Al y O y layer has a thickness of 5 to 500 angstroms.
  • the number of cycles of the superlattice structure layer is ⁇ 2.
  • the present invention has at least the following beneficial effects:
  • a semiconductor device wherein the buffer layer comprises an A1 X NJ1 and an Al y C y layer (0)
  • the alternate arrangement of the ⁇ layer and the ⁇ layer increases the interface, thereby improving the corrosion resistance of the buffer layer as a whole.
  • the layer itself has corrosion resistance, which further enhances the corrosion resistance of the buffer layer and avoids the over-corrosion phenomenon of the side wall corrosion of the chip process.
  • the PVD may be depleted of oxygen during the deposition process. Therefore, the present invention uses the PVD method to deposit a superlattice structure buffer layer including an Al y O y layer, Al y O y
  • the corrosion resistance of the layer and its difference in lattice characteristics from AlxNiJl improve the characteristics of the buffer layer and release subsequent deposition of epitaxial deposition. The stress generated by the process.
  • FIG. 1 is a schematic structural view of a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural view of a buffer layer according to Embodiment 1 of the present invention.
  • FIG 3 is a schematic structural view of a semiconductor device according to a second embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a semiconductor device according to a third embodiment of the present invention.
  • the figure indicates: 10. substrate; 20. buffer layer; 21.A1 X NJ1 ; 22. ⁇ 1 ⁇ ⁇ layer; 30. ⁇ -type semiconductor layer; 40. luminescent layer; 50. ⁇ -type semiconductor layer; Non-difficult semiconductor layer; . ⁇ 1 ⁇ ⁇ 1 body; b. Al X N i J121 and Al y O layer 22 contact interface.
  • a semiconductor device of the present invention includes a substrate 10, a buffer layer 20, an N-type semiconductor layer 30, a light-emitting layer 40, and a P-type semiconductor layer 50, wherein the buffer layer 20 is a superlattice structure layer comprising at least 5 to 500 ⁇ of Al x Njl21 and a thickness of 5 to 500 angstroms of AlyC y layer 22 (0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l), and a superlattice structure The number of cycles of the layer ⁇ 2, ⁇ ! 4 layer 21 thickness ⁇ ⁇ 04 layer 22 thickness.
  • the buffer layer 20 is formed by a superlattice structure comprising an A NiJ ⁇ 1 and an AlyCU y layer 22, which reduces the degree of corrosion of the chemical solution on the sidewall during the sidewall etching of the subsequent chip process. Improve chip yield.
  • the buffer layer 20 is a multilayer film laminated structure
  • the refractive index difference of the light of the different layers of the light is adjusted by the different material layers, the refractive angle of the light emitted by the buffer layer 20 is adjusted, the light extraction efficiency is increased, and the semiconductor component is improved.
  • the present invention provides a method of fabricating a semiconductor device:
  • the substrate is sapphire, SiC (6H-SiC or 4H-SiC), Si, GaAs, GaN substrate or lattice constant close to the nitride semiconductor Crystal oxide, here a sapphire substrate is preferred.
  • the buffer layer 20 can reduce the corrosion degree of the chemical solution and improve the chip yield in the sidewall etching process of the subsequent chip process; and the conventional MOCVD method cannot deposit the Al yO i y layer 22 containing the oxygen element, so the present invention utilizes The PVD method introduces the Al y C y layer 22 to achieve the structural features of the present invention.
  • S3 the wafer on which the buffer layer 20 is deposited is transferred into the MOCVD chamber, and an epitaxial layer composed of the N-type semiconductor layer 30, the light-emitting layer 40, and the P-type semiconductor layer 50 is deposited on the surface of the buffer layer 20 by MOCVD.
  • the high temperature environment in the subsequent epitaxial layer preparation process acts on the buffer layer 20 for low temperature PVD growth to anneal and recrystallize.
  • the annealing process of the buffer layer is beneficial to release the stress in the post deposition process and improve the crystal quality of the semiconductor device.
  • the method of the present invention utilizes a combination of a PVD method and an MOCVD method to prepare a semiconductor device.
  • a buffer layer 20 is deposited by a PVD method to obtain a buffer layer 20 containing an oxygen element, and a buffer layer is formed without affecting the deposition of the aluminum nitride layer by the PVD method.
  • the degree of corrosion of the buffer layer 20 by the chemical solution is reduced, and the chemical solution is improved. Electrical properties of the processed components.
  • an epitaxial layer composed of the N-type semiconductor layer 30, the light-emitting layer 40, and the P-type semiconductor layer 50 is deposited on the surface of the buffer layer 20 by MOCVD to form a semiconductor element.
  • the buffer layer 20 of the present invention comprises a layer of 5 to 500 angstroms and a layer of AlyOi- y having a thickness of 5 to 500 angstroms.
  • a superlattice structure layer of 22 ( ⁇ 1, 0 ⁇ y ⁇ l), and the A1 X N lx layer 21 is placed in the AlyOi- y layer 22 in the first cyclic layer stack of the superlattice structure layer
  • the number of cycles is ⁇ 2
  • the thickness of the A1 XN ⁇ layer 21 is ⁇ A1 y O layer 22 thickness.
  • the preparation method adopted in this embodiment is different from the preparation method in the first embodiment: S2, the substrate 10 is placed in the PV D machine chamber, and the thickness of the substrate 10 is deposited on the surface of the substrate 10 by the PVD method.
  • a superlattice structure buffer layer 20 composed of layer 22 (0 ⁇ 1, 0 ⁇ y ⁇ l).
  • an Al X N i J121 is deposited on the surface of the substrate 10, and then Al X N i
  • the Al y O y layer 22 is deposited on the surface of J121, and sequentially laminated to form a superlattice structure; the number of cycles of the superlattice structure is at least two.
  • the test results show that A1 X NJ121 can be deposited on the surface of the substrate 10 first, or AlyOi- y layer 22 can be deposited first.
  • the buffer layer 20 prepared in this embodiment can reduce the degree of corrosion of the chemical solution and improve the chip yield during the sidewall etching process of the subsequent chip process.
  • the present embodiment is different from Embodiment 1 in that a non-tough semiconductor layer 60 is deposited between the buffer layer 20 and the N-type semiconductor layer 30, and the crystal quality of the subsequent epitaxial layer is further improved by using the layer. , improve the photoelectric performance of semiconductor components.

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Abstract

一种半导体元件及其制造方法。半导体元件包括具有Al xN 1-x层和Al yO 1-y层(0＜x＜1，0＜y＜1)的超晶格结构缓冲层（20），其采用物理气相沉积（PVD）方法实现。超晶格结构缓冲层（20）在芯片制程的侧壁腐蚀过程中，可减小化学溶液的腐蚀程度，提高芯片良率。

Description

发明名称：一种半导体元件及其制备方法
技术领域
[0001] 本发明属于半导体技术领域， 特别涉及一种半导体元件及其制备方法。
背景技术
[0002] 半导体元件的切割技术由金刚石刀切割逐渐发展为普通激光切割， 一般来说， 激光的波长为 355nm或者 266nm， 其特点在于它既能划幵蓝宝石衬底， 也能划幵 各种膜层， 比如氮化镓层， 布拉格反射层、 金属层等。 而针对切割而言， 既可 以利用激光对外延片的表面进行划裂形成表面切割道， 也可以利用激光聚焦衬 底内部形成隐形切割道， 从而达到分离单个芯粒的目的。
[0003] 当使用激光对外延片的表面进行划裂形成表面切割道吋， 激光烧灼后形成的杂 质附着于切割道侧壁， 阻挡了光的出射， 影响半导体元件的外量子效率。 故为 避免该烧灼杂质对发光亮度的影响， 通常是在激光形成切割道后再使用化学溶 液浸泡腐蚀以去除激光烧灼杂质， 清洁切割道的侧壁。
[0004] 物理气相沉积法 （PVD法） 具有工艺过程简单、 对环境污染小、 原材消耗少、 成膜均匀致密、 与基板的结合力强等特点， 目前被越来越多地应用于半导体元 件的制备中， 通常较多地用于外延片底层的制备， 例如沉积氮化铝层作为缓冲 层， 可降低及缓冲衬底与外延层之间因晶格失配和热失配产生的缺陷和应力， 改善半导体元件的器件质量。
[0005] 然而由于 PVD法形成的氮化铝层具有多晶格及各向异性等特性， 其较易被化学 溶液腐蚀， 故当外延片包含 PVD法形成的缓冲层吋， 再利用激光对外延片表面 切割后浸泡化学溶液吋容易产生缓冲层或缓冲层与衬底接触表面的过腐蚀现象 ， 导致形成的芯粒电性异常， 降低生产良率。
技术问题
问题的解决方案
技术解决方案
[0006] 针对上述问题， 本发明提出了一种半导体元件， 包括至少具有 A N iJl和 Al y Ο,— y层 （0<x<l， 0<y<l) 的超晶格结构缓冲层， 所述超晶格结构缓冲层在芯 片制程的侧壁腐蚀过程中， 用于减小化学溶液的腐蚀程度， 提高芯片良率。 同 吋提出一种制备方法， 制备获得该超晶格结构缓冲层， 实现本发明效果。
[0007] 本发明提供的技术方案为： 一种半导体元件， 包括： 衬底、 缓冲层、 N型半导 体层、 发光层和 P型半导体层， 其中， 所述缓冲层为包括 A Ni— J1和 AlyOi— y层 (0<χ<1, 0<y<l) 循环层叠的超晶格结构层； 所述缓冲层在芯片制程的侧 壁腐蚀过程中， 用于减小化学溶液的腐蚀程度， 提高芯片良率。
[0008] 优选的， 所述缓冲层中第一个循环层叠层中 Al XN iJl置于 Al yO 层与所述衬 底之间。
[0009] 优选的， 所述 Al XN iJl厚度≥A1 yO 层厚度。
[0010] 优选的， 所述 Al XN J1厚度为 5〜500埃。
[0011] 优选的， 所述 Al yO 层厚度为 5〜500埃。
[0012] 优选的， 所述缓冲层与 N型半导体层之间还包括一非惨杂半导体层。
[0013] 优选的， 所述超晶格结构层的循环次数≥2。
[0014] 相较于常规氮化铝单层结构， 本发明提出的超晶格结构缓冲层， 相当于将常规 氮化铝单层缓冲层分割成多层薄膜结构， 并在多层膜中插入 AlyO y层， 实验结 果发现， A1 ΧΝ , J1和 Al yO y层的接触面较 Al XN 本体对化学溶液的腐蚀耐受 性更强， 因此本结构的超晶格结构增加了 AlxN
Figure imgf000003_0001
从而 提升缓冲层的抗化学溶液腐蚀的特性； 且由于 AlyO y层的存在， 使得缓冲层的 晶格应力发生改变， 最终形成的超晶格缓冲层较原氮化铝缓冲层的晶体质量得 到提高， 从而在后续芯片制程的侧壁腐蚀过程中， 即使用化学溶液腐蚀处理去 除芯粒侧壁附着物吋， 降低对缓冲层的腐蚀程度， 减小对芯粒电性能的影响。 同吋， 由于多层膜对于光的折射角度的改变， 此超晶格结构层可增加光的取出 效率， 提升半导体元件的外量子效率。
[0015] 同吋， 为制备上述半导体底层结构， 本发明提供一种半导体元件的制备方法， 所述方法包括： Sl、 提供一衬底； S2、 利用物理气相沉积法于所述衬底表面沉 积 AlxNiJl和 AlyOi— y层 （0<χ<1， 0<y<l) 组成的超晶格结构缓冲层， 所述 缓冲层在后续芯片制程吋减小化学溶液的腐蚀程度， 提高芯片良率； S3、 利用 化学气相沉积法于所述缓冲层表面沉积 N型半导体层、 发光层和 P型半导体层组 成的外延层， 其中， 低温制备的缓冲层在后续高温外延层制备过程中实现退火 再结晶， 用于释放在后沉积制程中的应力。
[0016] 因为常规化学气相沉积法 （MOCVD) 无法在沉积过程中惨入氧元素， 故本方 法利用 PVD法沉积形成超晶格结构缓冲层， 弓 I入 AlyCU y层， 利用其抗腐蚀特性 ， 及与 AlxNiJl晶格特性差异， 改善本发明半导体元件中缓冲层特性， 释放后 续沉积外延层产生的应力， 同吋使其更利于后续芯片端制程。
[0017] 优选的， 所述步骤 S2中， 利用物理气相沉积法先于衬底表面沉积 AlxNiJl, 再于所述 A1 ΧΝ , J1表面沉积 Al yO v层， 并依次循环层叠形成超晶格结构缓冲层
[0018] 优选的， 所述两种方法中步骤 S3还包括， 于缓冲层表面先沉积一非惨杂半导体 层， 再沉积 N型半导体层。
[0019] 优选的， 所述 Al XN iJl厚度≥A1 yO y层厚度。
[0020] 优选的， 所述 Al XN 1!4层厚度为5〜500埃。
[0021] 优选的， 所述 Al yO y层厚度为 5〜500埃。
[0022] 优选的， 所述超晶格结构层的循环次数≥2。
发明的有益效果
有益效果
[0023] 本发明至少具有以下有益效果：
[0024] 1、 本发明提出的一种半导体元件， 其缓冲层为包括 A1XNJ1和 AlyC y层 （0
<x<l, 0<y<l) 的超晶格结构， 由于 A Njl与 AlyOi— y层界面处， 对化学 溶液的腐蚀耐受性较强， 因此， 相对于单层 A1XNJ1， ^^^层和^^^层的 交替排列， 使其界面增多， 从而整体提高缓冲层的抗腐蚀性，
Figure imgf000004_0001
层本身具有的抗腐蚀性， 进一步增强缓冲层的抗腐蚀性， 避免芯片制程侧壁腐 蚀吋的过腐蚀现象。
[0025] 2、 相较于 MOCVD法沉积膜层， PVD在沉积过程中可惨入氧元素， 因此本发明 利用 PVD法沉积包括 Al yO y层的超晶格结构缓冲层， Al yO y层的抗腐蚀性及其 与 AlxNiJl的晶格特性差异， 改善了缓冲层特性， 进而释放后续沉积外延沉积 过程产生的应力。
[0026] 3、 利用超晶格多层膜结构对于光的折射角度的影响， 改善光的取出效率， 进 而提升半导体元件的内外量子效率。
对附图的简要说明
附图说明
[0027] 附图用来提供对本发明的进一步理解， 并且构成说明书的一部分， 与本发明的 实施例一起用于解释本发明， 并不构成对本发明的限制。 此外， 附图数据是描 述概要， 不是按比例绘制。
[0028] 图 1为本发明实施例一之半导体元件结构示意图。
[0029] 图 2为本发明实施例一之缓冲层结构示意图。
[0030] 图 3为本发明实施例二之半导体元件结构示意图。
[0031] 图 4为本发明实施例三之半导体元件结构示意图。
[0032] 图中标示： 10.衬底； 20.缓冲层； 21.A1XNJ1; 22.Α1γΟ 层； 30. Ν型半导 体层； 40.发光层； 50.Ρ型半导体层； 60.非惨杂半导体层； .Α1χΝ^1本体； b. Al XN i J121与 Al yO 层 22接触界面。
本发明的实施方式
[0033] 下面结合附图和实施例对本发明的具体实施方式进行详细说明。
[0034] 实施例 1
[0035] 参看附图 1〜2， 本发明中的一种半导体元件， 包括衬底 10， 缓冲层 20， N性半 导体层 30、 发光层 40和 P型半导体层 50， 其中， 缓冲层 20为至少包含厚度为 5〜5 00埃的 AlxNjl21和厚度为 5〜500埃的 AlyC y层 22 (0<x<l, 0<y<l) 的超 晶格结构层， 且超晶格结构层的循环次数≥2， ^ !4层21的厚度≥^ 04层22 厚度。 实验发现， 当 A NiJl l厚度与 AlyCU y层 22厚度比值越大吋， 缓冲层 20 的晶格质量越优。 本发明结构中， 禾 1」用包含 A NiJ^l和 AlyCU y层 22的超晶格 结构形成缓冲层 20， 减小后续芯片制程的侧壁腐蚀过程中， 化学溶液对侧壁的 腐蚀程度， 提高芯片良率。
[0036] 继续参看附图 1~2， 相对于 Al XN ^层21本体 a， Al XN ^层21与 Al yO 层 22接触 界面位置 b对化学溶液的腐蚀耐受性更强， 因此， 相对于常规结构中的单层氮化 铝层， A1 ΧΝ , J121和 Al yO 层 22的交替排列使其接触界面 b增多， 从而整体提 高缓冲层 20的抗腐蚀性； 同吋由于 Α1 γΟ 层材料 22本身具有的抗腐蚀性， 进一 步增强缓冲层 20的抗腐蚀性， 避免芯片制程中侧壁腐蚀吋的过腐蚀现象。 另外 ， 因 A1 ΧΝ , J121和 Al yO 层 22晶格差异较大， 故超晶格结构中 Al XN J121和 A1 yO 层 22接触界面被挤压变形， 从而使得缓冲层 20整体释放应力的能力增加， 缓解后续沉积外延层的晶格应力， 改善因应力造成的翘曲。 同吋， 当缓冲层 20 为多层膜层叠结构吋， 利用其不同材料层对光的折射率差异， 调节缓冲层 20对 发光层 40发射光的折射角度， 增大光取出效率， 提高半导体元件的外量子效率
[0037] 为实现上述结构及其作用， 本发明提出一种半导体元件的制备方法：
[0038] Sl、 提供衬底 10， 所述衬底为蓝宝石、 SiC (6H-SiC或 4H-SiC) 、 Si、 GaAs 、 GaN衬底或晶格常数 （lattice constant)接近于氮化物半导体的单晶氧化物， 此 处优选蓝宝石衬底。
[0039] S2、 将衬底 10置入 PVD机台腔室， 利用 PVD法于衬底 10表面沉积至少包括厚度 为 5〜500埃的 Al xN jl21和厚度为 5〜500埃的 Al yC y层 22 (θ< χ< 1 , 0< y < l ) 的超晶格结构缓冲层 20， 超晶格结构的循环次数≥2， A1 XN J121的厚度≥Al y O y层 22厚度。 缓冲层 20在后续芯片制程的侧壁腐蚀过程， 可减小化学溶液的腐 蚀程度， 提高芯片良率； 而因为常规 MOCVD法无法沉积含氧元素的 Al yO i— y 层 22， 故本发明利用 PVD法引入 Al yC y层 22， 实现了本发明的结构特征。
[0040] S3、 将沉积有缓冲层 20的晶片转入 MOCVD腔室， 利用 MOCVD法于缓冲层 20 表面沉积 N型半导体层 30、 发光层 40和 P型半导体层 50组成的外延层， 其中， 后 续外延层制备过程中的高温环境对低温 PVD生长的缓冲层 20起到使其退火再结 晶的作用， 缓冲层的退火过程有利于释放在后沉积制程中的应力， 改善半导体 元件的晶体质量。
[0041] 本发明方法利用 PVD法与 MOCVD法相结合的方式制备半导体元件， 首先利用 PVD法沉积缓冲层 20， 获得含氧元素的缓冲层 20， 在不影响 PVD法沉积的氮化 铝层形成缓冲层的基础上减小缓冲层 20被化学溶液腐蚀的程度， 改善化学溶液 处理后的元件电学性能。 随后， 在缓冲层 20表面利用 MOCVD法沉积 N型半导体 层 30、 发光层 40和 P型半导体层 50组成的外延层形成半导体元件。
[0042] 实施例 2
[0043] 参看附图 3， 本实施例与实施例 1的区别在于， 本发明的缓冲层 20为包括厚度为 5〜500埃的 ΑΙχΝ !— J121和厚度为 5〜500埃的 AlyOi— y层 22 (θ<χ<1, 0<y<l) 的超晶格结构层， 且在该超晶格结构层的第一个循环层叠层中 A1XN lx 层 21置于 AlyOi— y层 22与所述衬底 10之间， 所述超晶格结构层的循环次数≥2， A1 XN ^层21的厚度≥A1 yO 层 22厚度。
[0044] 本实施例采取的制备方法与实施例 1的制备方法区别为： S2、 将衬底 10置入 PV D机台腔室， 利用 PVD法先于衬底 10表面沉积厚度为 5〜500埃的 A1XN J121和 厚度为 5〜500埃的 Al yO !_y
层 22 (0<χ<1, 0<y<l) 组成的超晶格结构缓冲层 20， 此步骤中， 先于衬底 1 0表面沉积一 Al XN i J121， 再于 Al XN i J121表面沉积 Al yO y层 22， 依次循环层 叠形成超晶格结构； 超晶格结构的循环次数至少 2个。 试验结果表明， 于衬底 10 表面既可以先沉积 A1XNJ121， 也可以先沉积 AlyOi— y层 22， 此处优先选用在衬
Figure imgf000007_0001
同样， 本实施例制备的缓冲层 20在后续芯片制程 的侧壁腐蚀过程中， 可减小化学溶液的腐蚀程度， 提高芯片良率。
[0045] 实施例 3
[0046] 参看附图 4， 本实施例与实施例 1的区别在于， 在缓冲层 20与 N型半导体层 30之 间沉积非惨杂半导体层 60， 利用该层进一步改善后续外延层的晶体质量， 提升 半导体元件的光电性能。
[0047] 应当理解的是， 上述具体实施方案为本发明的优选实施例， 本发明的范围不限 于该实施例， 凡依本发明所做的任何变更， 皆属本发明的保护范围之内。

Claims

权利要求书
一种半导体元件， 包括： 衬底、 缓冲层、 N型半导体层、 发光层和 P 型半导体层， 其特征在于： 所述缓冲层为包括 A1XNJ1和 AlyC y层
(0<χ<1, 0<y<l) 循环层叠的超晶格结构层。
根据权利要求 1所述的一种半导体元件， 其特征在于： 所述超晶格结 构层的第一个循环中所述 Al yO y层置于所述 Al ΧΝ , Jl之上。
根据权利要求 1所述的一种半导体元件， 其特征在于： 所述超晶格结 构层在芯片制程的侧壁腐蚀过程中， 用于减小化学溶液的腐蚀程度， 提高芯片良率。
根据权利要求 1所述的一种半导体元件， 其特征在于： 所述超晶格结 构层的循环次数≥2。
根据权利要求 1所述的一种半导体元件， 其特征在于： 所述 A1XNJ1 厚度≥A1 yO y层厚度。
根据权利要求 1所述的一种半导体元件， 其特征在于： 所述 A1XNJ1 厚度、 Al yO y层厚度为 5〜500埃。
根据权利要求 1所述的一种半导体元件， 其特征在于： 所述缓冲层与 N型半导体之间包括一非惨杂半导体层。
一种半导体元件的制备方法， 其特征在于， 所述方法包括：
51、 提供一衬底；
52、 利用物理气相沉积法于所述衬底表面沉积包括 Al ΧΝ , Jl和 Al yO y层 （0<χ<1， 0<y<l) 循环层叠的超晶格结构缓冲层， 所述缓冲 层在后续芯片制程的侧壁腐蚀过程中， 用于减小化学溶液的腐蚀程度 ， 提高芯片良率；
53、 利用化学气相沉积法于所述缓冲层表面沉积 N型半导体层、 发光 层和 P型半导体层组成的外延层。
根据权利要求 8所述的一种半导体元件的制备方法， 其特征在于： 所 述步骤 S2中， 利用物理气相沉积法先于衬底表面沉积 AlxNiJl, 再 于所述 A1 ΧΝ , J1表面沉积 Al yO y层， 并依次循环层叠形成超晶格结 构缓冲层。
[权利要求 10] 根据权利要求 9所述的一种半导体元件的制备方法， 其特征在于： 所 述步骤 S3还包括， 于缓冲层表面先沉积一非惨杂半导体层， 再沉积 N 型半导体层。
在此处键入权利要求项 1。
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US20170263822A1 (en) 2017-09-14
CN105261681B (zh) 2019-02-22

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