WO2017041329A1 - 一种液晶显示面板及其阵列基板 - Google Patents

一种液晶显示面板及其阵列基板 Download PDF

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Publication number
WO2017041329A1
WO2017041329A1 PCT/CN2015/090490 CN2015090490W WO2017041329A1 WO 2017041329 A1 WO2017041329 A1 WO 2017041329A1 CN 2015090490 W CN2015090490 W CN 2015090490W WO 2017041329 A1 WO2017041329 A1 WO 2017041329A1
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Prior art keywords
nth
scan line
thin film
film transistor
turned
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PCT/CN2015/090490
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English (en)
French (fr)
Inventor
王金杰
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深圳市华星光电技术有限公司
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Priority to US14/783,862 priority Critical patent/US10013941B2/en
Publication of WO2017041329A1 publication Critical patent/WO2017041329A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N13/30—Image reproducers
    • H04N13/356—Image reproducers having separate monoscopic and stereoscopic modes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N13/30—Image reproducers
    • H04N13/356—Image reproducers having separate monoscopic and stereoscopic modes
    • H04N13/359—Switching between monoscopic and stereoscopic modes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G02F1/134354—Subdivided pixels, e.g. for grey scale or redundancy the sub-pixels being capacitively coupled
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a liquid crystal display panel and an array substrate thereof.
  • a charging sharing design method is usually adopted.
  • the charging sharing function of the liquid crystal display fails due to frame flipping, resulting in a flicker phenomenon in the 3D display screen of the liquid crystal display.
  • the prior art independently controls the pixel charging and pixel sharing functions, and one output terminal of the gate driving chip corresponds to only one charging scanning line or sharing scanning line, but the number of gate driving chips is doubled, resulting in production. The cost is increased.
  • Embodiments of the present invention provide a liquid crystal display panel and an array substrate thereof, which can improve the flicker phenomenon generated in the 3D display mode and avoid an increase in production cost.
  • the present invention provides an array substrate including a substrate, a plurality of scan lines, and a plurality of data lines.
  • the plurality of scan lines and the plurality of data lines are disposed on the substrate to form a plurality of pixel units, and each of the scan lines includes a first a scan line and a second scan line, when the first scan line is turned on, the corresponding pixel unit is charged by the data line; when the second scan line is turned on, the corresponding pixel unit realizes sharing voltage, and the array substrate further includes a switch controller Connected to the first scan line and the second scan line respectively; in the 2D display mode, the switch controller controls the first scan line and the second scan line to be sequentially turned on; in the 3D display mode, the switch controller controls the first scan line Open, control the second scan line to be closed;
  • the Nth pixel unit includes an Nth main pixel unit and an Nth sub-pixel unit
  • the array substrate includes a first thin film transistor, a second thin film transistor, a third thin film transistor, and a shared capacitor corresponding to the Nth pixel unit.
  • the Nth main pixel unit is connected to the drain of the first thin film transistor, the gate of the first thin film transistor is connected to the Nth first scan line, and the source of the first thin film transistor is connected to the Nth data line;
  • N sub-pixel units and second thin film crystal The drain of the tube is connected, the gate of the second thin film transistor is connected to the Nth first scan line, the source of the second thin film transistor is connected to the Nth data line;
  • the gate of the third thin film transistor and the Nth strip a second scan line connection a source of the third thin film transistor is connected to the Nth sub-pixel unit, a drain of the third thin film transistor is connected to the shared capacitor, and N is an integer greater than or equal to 1;
  • the switch controller controls the Nth first scan line to be turned on, the first thin film transistor and the second thin film transistor are turned on, and the Nth main pixel unit and the Nth sub-pixel unit pass the Nth data line Charging; the switch controller controls the Nth second scan line to be turned on, the third thin film transistor is turned on, and the Nth sub-pixel unit shares voltage with the shared capacitor;
  • the switch controller controls the Nth first scan line to be turned on, the Nth second scan line is turned off, the first thin film transistor and the second thin film transistor are turned on, and the third thin film transistor is turned off, the Nth Both the main pixel unit and the Nth sub-pixel unit are charged by the Nth data line.
  • the switch controller includes a plurality of switch units, and the Nth switch unit is connected to the Nth first scan line and the Nth second scan line.
  • the present invention also provides an array substrate including a substrate, a plurality of scan lines, and a plurality of data lines.
  • the plurality of scan lines and the plurality of data lines are disposed on the substrate to form a plurality of pixel units, each of the scan lines including a first scan line and a second scan line, when the first scan line is turned on, the corresponding pixel unit is charged by the data line; when the second scan line is turned on, the corresponding pixel unit realizes sharing voltage, and the array substrate further includes switch control And respectively connected to the first scan line and the second scan line; in the 2D display mode, the switch controller controls the first scan line and the second scan line to be sequentially turned on; in the 3D display mode, the switch controller controls the first scan The line is turned on and the second scan line is controlled to be turned off.
  • the Nth pixel unit includes an Nth main pixel unit and an Nth sub-pixel unit
  • the array substrate includes a first thin film transistor, a second thin film transistor, a third thin film transistor, and a shared capacitor corresponding to the Nth pixel unit.
  • the Nth main pixel unit is connected to the drain of the first thin film transistor, the gate of the first thin film transistor is connected to the Nth first scan line, and the source of the first thin film transistor is connected to the Nth data line;
  • N sub-pixel units are connected to the drain of the second thin film transistor, the gate of the second thin film transistor is connected to the Nth first scan line, the source of the second thin film transistor is connected to the Nth data line, and the third thin film transistor is connected The gate is connected to the Nth second scan line, and the source of the third thin film transistor is connected to the Nth sub-pixel unit, and the third thin
  • the drain of the membrane transistor is connected to the shared capacitor, and N is an integer greater than or equal to one.
  • the switch controller controls the Nth first scan line to be turned on, the first thin film transistor and the second thin film transistor are turned on, and the Nth main pixel unit and the Nth sub-pixel unit pass the Nth The data line is charged; the switch controller controls the Nth second scan line to be turned on, the third thin film transistor is turned on, and the Nth sub-pixel unit shares the voltage with the shared capacitor.
  • the switch controller controls the Nth first scan line to be turned on, the Nth second scan line is controlled to be turned off, the first thin film transistor and the second thin film transistor are turned on, and the third thin film transistor is turned off.
  • the Nth main pixel unit and the Nth sub-pixel unit are each charged by the Nth data line.
  • the switch controller includes a plurality of switch units, and the Nth switch unit is connected to the Nth first scan line and the Nth second scan line.
  • the Nth switch unit includes a first switch tube, a second switch tube, a third switch tube, and a fourth switch tube.
  • the first end of the first switch tube and the first end of the fourth switch tube receive the first control signal.
  • the second end of the first switch tube and the second end of the third switch tube receive the scan line driving signal, and the third end of the first switch tube and the third end of the second switch tube are both connected to the Nth first scan line Connecting, the first end of the second switch tube and the first end of the third switch tube receive the second control signal, the second end of the second switch tube receives the first control signal, and the third end of the third switch tube and the fourth end
  • the third end of the switch tube is connected to the Nth second scan line, and the second end of the fourth switch tube receives the second control signal.
  • the scan line driving signal is at a high level
  • the first control signal is at a high level
  • the second control signal is at a low level
  • the first switch tube and the fourth switch tube are turned on
  • the second The switch tube and the third switch tube are disconnected, the first scan line of the Nth is high level
  • the second scan line of the Nth is low level
  • the second control signal is high
  • the first switch tube and the fourth switch tube are disconnected, the second switch tube and the third switch tube are turned on, the first Nth scan line is at a low level
  • the Nth second scan line is at a high level
  • the scan line driving signal is at a high level
  • the first control signal is at a high level
  • the second control signal is at a low level
  • the first switch tube and the fourth switch tube are turned on
  • the second switch The tube and the third switch are disconnected
  • the first scan line of the Nth is high level
  • the second scan line of the Nth is low level.
  • the switch controller includes a first switch controller and a second switch controller, wherein one end of the first scan line and one end of the second scan line are connected to the first switch controller, and the other of the first scan lines The other end of the terminal and the second scan line are connected to the second switch controller.
  • the present invention also provides a liquid crystal display panel comprising an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate, the array substrate comprising a substrate, a plurality of scan lines, and a plurality of data lines.
  • each of the scan lines includes a first scan line and a second scan line, and when the first scan line is turned on, the corresponding pixel unit passes The data line realizes charging; when the second scan line is turned on, the corresponding pixel unit realizes sharing voltage, and the array substrate further includes a switch controller respectively connected to the first scan line and the second scan line; in the 2D display mode, the switch control The first scanning line and the second scanning line are controlled to be sequentially turned on; in the 3D display mode, the switch controller controls the first scanning line to be turned on to control the second scanning line to be turned off.
  • the Nth pixel unit includes an Nth main pixel unit and an Nth sub-pixel unit
  • the array substrate includes a first thin film transistor, a second thin film transistor, a third thin film transistor, and a shared capacitor corresponding to the Nth pixel unit.
  • the Nth main pixel unit is connected to the drain of the first thin film transistor, the gate of the first thin film transistor is connected to the Nth first scan line, and the source of the first thin film transistor is connected to the Nth data line;
  • N sub-pixel units are connected to the drain of the second thin film transistor, the gate of the second thin film transistor is connected to the Nth first scan line, the source of the second thin film transistor is connected to the Nth data line, and the third thin film transistor is connected The gate is connected to the Nth second scan line, the source of the third thin film transistor is connected to the Nth sub-pixel unit, the drain of the third thin film transistor is connected to the shared capacitor, and N is an integer greater than or equal to 1.
  • the switch controller controls the Nth first scan line to be turned on, the first thin film transistor and the second thin film transistor are turned on, and the Nth main pixel unit and the Nth sub-pixel unit pass the Nth The data line is charged; the switch controller controls the Nth second scan line to be turned on, the third thin film transistor is turned on, and the Nth sub-pixel unit shares the voltage with the shared capacitor.
  • the switch controller controls the Nth first scan line to be turned on, the Nth second scan line is controlled to be turned off, the first thin film transistor and the second thin film transistor are turned on, and the third thin film transistor is turned off.
  • the Nth main pixel unit and the Nth sub-pixel unit are each charged by the Nth data line.
  • the switch controller includes a plurality of switch units, and the Nth switch unit is connected to the Nth first scan line and the Nth second scan line.
  • the Nth switch unit includes a first switch tube, a second switch tube, and a third switch tube.
  • the fourth switch tube, the first end of the first switch tube and the first end of the fourth switch tube receive the first control signal
  • the second end of the first switch tube and the second end of the third switch tube receive the scan line drive a signal
  • a third end of the first switch tube and a third end of the second switch tube are connected to the Nth first scan line
  • the first end of the second switch tube and the first end of the third switch tube receive the second end a control signal
  • the second end of the second switch tube receives the first control signal
  • the third end of the third switch tube and the third end of the fourth switch tube are connected to the Nth second scan line
  • the fourth switch tube The second end receives the second control signal.
  • the scan line driving signal is at a high level
  • the first control signal is at a high level
  • the second control signal is at a low level
  • the first switch tube and the fourth switch tube are turned on
  • the second The switch tube and the third switch tube are disconnected, the first scan line of the Nth is high level
  • the second scan line of the Nth is low level
  • the second control signal is high
  • the first switch tube and the fourth switch tube are disconnected, the second switch tube and the third switch tube are turned on, the first Nth scan line is at a low level
  • the Nth second scan line is at a high level
  • the scan line driving signal is at a high level
  • the first control signal is at a high level
  • the second control signal is at a low level
  • the first switch tube and the fourth switch tube are turned on
  • the second switch The tube and the third switch are disconnected
  • the first scan line of the Nth is high level
  • the second scan line of the Nth is low level.
  • the switch controller includes a first switch controller and a second switch controller. One end of the first scan line and one end of the second scan line are connected to the first switch controller, and the other end of the first scan line and the second scan The other end of the line is connected to the second switch controller.
  • the beneficial effects of the present invention are: when the first scan line is turned on, the corresponding pixel unit is charged by the data line; when the second scan line is turned on, the corresponding pixel unit realizes sharing voltage, and the array substrate is further
  • the switch controller is respectively connected to the first scan line and the second scan line; in the 2D display mode, the switch controller controls the first scan line and the second scan line to be sequentially turned on; in the 3D display mode, the switch controller controls The first scan line is turned on, and the second scan line is controlled to be turned off; since the first scan line is turned on and the second scan line is turned off in the 3D display mode, only the charging function is implemented, which can improve the flicker phenomenon generated in the 3D display mode and avoid Increased production costs.
  • FIG. 1 is a schematic structural view of an array substrate according to a first embodiment of the present invention
  • FIG. 2 is a schematic structural view of an array substrate according to a second embodiment of the present invention.
  • FIG. 3 is a schematic structural view of an array substrate according to a third embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a liquid crystal display panel according to a first embodiment of the present invention.
  • FIG. 1 is a schematic structural view of an array substrate according to a first embodiment of the present invention.
  • the array substrate 10 disclosed in this embodiment includes a 2D (planar) display mode and a 3D (stereoscopic) display mode.
  • the array substrate 10 includes a substrate 11 , a plurality of scan lines 12 , a plurality of data lines 13 , and Switch controller 14.
  • the plurality of scan lines 12 and the plurality of data lines 13 are disposed on the substrate to form a plurality of pixel units 15.
  • Each of the scan lines 12 includes a first scan line 121 and a second scan line 122.
  • the first scan line 121 is turned on, the corresponding pixel unit 15 is charged, that is, the pixel unit 15 connected to the first scan line 121 passes through the data line. 13 to charge.
  • the second scan line 122 is turned on, the corresponding pixel unit 15 realizes the sharing voltage, that is, the pixel unit 15 connected to the second scan line 122 performs the sharing voltage.
  • the switch controller 14 is respectively connected to the first scan line 121 and the second scan line 122.
  • the switch controller 14 controls the first scan line 121 and the second scan line 122 to be sequentially turned on to realize charging and sharing voltage functions.
  • the switch controller 14 controls the first scan line 121 to open, controls the second scan line 122 to be turned off, and only implements the charging function, which can improve the flicker phenomenon generated in the 3D display mode, thereby avoiding an increase in production cost. .
  • N is an integer greater than or equal to 1.
  • the array substrate 10 disclosed in this embodiment further includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, and a correspondingly disposed corresponding to the Nth pixel unit.
  • Capacitor C Capacitor
  • the Nth main pixel unit 151 is connected to the drain of the first thin film transistor T1, the gate of the first thin film transistor T1 is connected to the Nth first scan line 121, and the source and the Nth data of the first thin film transistor T1 are connected.
  • Line 13 is connected.
  • the Nth sub-pixel unit 152 is connected to the drain of the second thin film transistor T2, the gate of the second thin film transistor T2 is connected to the Nth first scan line 121, and the source of the second thin film transistor T2 and the Nth data line 13 connections.
  • the gate of the third thin film transistor T3 is connected to the Nth second scan line 122, the source of the third thin film transistor T3 is connected to the Nth sub-pixel unit 152, and the drain of the third thin film transistor T3 is connected to the shared capacitor C. That is, the drain of the third thin film transistor T3 is grounded through the sharing capacitor C.
  • the output ends of the switch controller 14 are respectively connected to the Nth first scan line 121 and the Nth second scan line 122, and the input end of the switch controller 14 is connected to the scan line drive signal.
  • the switch controller 14 controls the Nth first scan line 121 to be turned on, that is, the scan line drive signal received by the Nth first scan line 121 is at a high level, and the first thin film transistor T1 and the second The thin film transistor T2 is simultaneously turned on, and the Nth main pixel unit 151 and the Nth sub-pixel unit 152 are both connected to the Nth data line 13, and the Nth main pixel unit 151 and the Nth sub-pixel unit 152 pass the Nth strip.
  • the data line 13 is charged to implement a charging function; after the charging of the Nth main pixel unit 151 and the Nth sub-pixel unit 152 is completed, the switch controller 14 controls the Nth second scanning line 122 to be turned on, that is, the Nth second
  • the scanning line driving signal received by the scanning line 122 is at a high level
  • the third thin film transistor T3 is turned on
  • the Nth sub-pixel unit 152 is connected to the sharing capacitor C
  • the Nth sub-pixel unit 152 shares voltage with the sharing capacitor, so that The voltage of the Nth sub-pixel unit 152 is smaller than the voltage of the Nth main pixel unit 151, and the sharing voltage is realized, and the color shift of the large viewing angle can be improved.
  • the switch controller 14 controls the Nth first scan line 121 to be turned on, and controls the Nth second scan line 122 to be turned off, that is, the scan line drive signal received by the Nth first scan line 121 is high.
  • Level the scan line driving signal received by the Nth second scan line 122 is at a low level
  • the first thin film transistor T1 and the second thin film transistor T2 are simultaneously turned on
  • the third thin film transistor T3 is turned off
  • the Nth main The pixel unit 151 and the Nth sub-pixel unit 152 are both connected to the Nth data line 13
  • the Nth main pixel unit 151 and the Nth sub-pixel unit 152 are both charged by the Nth data line 13 to realize a charging function. Therefore, it is possible to improve the flicker phenomenon generated in the 3D display mode without increasing the gate driving chip and avoiding an increase in production cost.
  • the present invention also provides the array substrate of the second embodiment, which is described on the basis of the array substrate 10 disclosed in the first embodiment.
  • the switch controller 14 of the array substrate disclosed in this embodiment includes a plurality of switch units 141, and the Nth switch unit 141 and the Nth first scan line 121 and the Nth second scan line, respectively. 122 connections.
  • the Nth switch unit 141 includes a first switch tube 142, a second switch tube 143, a third switch tube 144, and a fourth switch tube 145.
  • the switch controller 14 further includes a first control signal generating unit 146. And a second control signal generating unit 147.
  • the first end of the first switch tube 142 and the first end of the fourth switch tube 145 are connected to the first control signal generating unit 146 to receive the first control signal CL1; the second end and the third end of the first switch tube 142 The second end of the switch tube 144 receives the scan line driving signal Gn; the third end of the first switch tube 142 and the third end of the second switch tube 143 are both connected to the Nth first scan line 121; the second switch tube 143 The first end of the first switch and the third switch tube 144 are connected to the second control signal generating unit 147, and receive the second control signal CL2. The second end of the second switch tube 143 is connected to the first control signal generating unit 146.
  • the control signal generating unit 147 is connected to receive the second control signal CL2.
  • the first switch tube 142, the second switch tube 143, the third switch tube 144, and the fourth switch tube 145 are thin film transistors, the first end is the gate of the thin film transistor, and the second end is the source of the thin film transistor. The third end is the drain of the thin film transistor.
  • the signal of the Nth first scan line is Gn-main, and the signal of the Nth second scan line is Gn-sub.
  • the scan line driving signal Gn is at a high level
  • the first control signal CL1 generated by the first control signal generating unit 146 is at a high level
  • the second control signal CL2 generated by the second control signal generating unit 147 is low.
  • the first switch tube 142 and the fourth switch tube 145 are turned on, the second switch tube 143 and the third switch tube 144 are turned off, and the signal Gn-main of the Nth first scan line 121 is at a high level, the Nth The signal Gn-sub of the second scanning line 122 is at a low level, the first thin film transistor T1 and the second thin film transistor T2 are simultaneously turned on, and the Nth main pixel unit 151 and the Nth sub-pixel unit 152 are both associated with the Nth The data lines 13 are connected, and the Nth main pixel unit 151 and the Nth sub-pixel unit 152 are all charged by the Nth data line 13 to implement a charging function.
  • the scanning line driving signal Gn is at a high level, and the first control signal generating unit 146
  • the generated first control signal CL1 is at a low level
  • the second control signal CL2 generated by the second control signal generating unit 147 is at a high level
  • the first switch tube 142 and the fourth switch tube 145 are disconnected
  • the second switch tube 143 is turned off.
  • the third switch 144 is turned on, the signal Gn-main of the Nth first scan line 121 is a low level, the signal Gn-sub of the Nth second scan line 122 is a high level, and the third thin film transistor T3 Turning on, the Nth sub-pixel unit 152 is connected to the sharing capacitor C, and the Nth sub-pixel unit 152 shares the voltage with the sharing capacitor, so that the voltage of the Nth sub-pixel unit 152 is smaller than the voltage of the Nth main pixel unit 151. Sharing the voltage can improve the color shift of the large viewing angle.
  • H is high level and L is low level.
  • the scan line driving signal Gn is at a high level
  • the first control signal CL1 generated by the first control signal generating unit 146 is at a high level
  • the second control signal CL2 generated by the second control signal generating unit 147 is low.
  • the first switch tube 142 and the fourth switch tube 145 are turned on, the second switch tube 143 and the third switch tube 144 are turned off, and the signal Gn-main of the Nth first scan line 121 is at a high level, the Nth The signal Gn-sub of the second scanning line 122 is at a low level, the first thin film transistor T1 and the second thin film transistor T2 are simultaneously turned on, and the Nth main pixel unit 151 and the Nth sub-pixel unit 152 are both associated with the Nth The data lines 13 are connected, and the Nth main pixel unit 151 and the Nth sub-pixel unit 152 are all charged by the Nth data line 13 to implement a charging function.
  • the scan line driving signal Gn is at a high level
  • the first control signal CL1 generated by the first control signal generating unit 146 is at a high level
  • the second control signal CL2 generated by the second control signal generating unit 147 is low.
  • the first switch tube 142 and the fourth switch tube 145 are turned on, the second switch tube 143 and the third switch tube 144 are turned off, and the signal Gn-main of the Nth first scan line 121 is at a high level, the Nth The signal Gn-sub of the second scanning line 122 is at a low level
  • the first thin film transistor T1 and the second thin film transistor T2 are simultaneously turned on
  • the Nth main pixel unit 151 and the Nth sub-pixel unit 152 are both associated with the Nth
  • the data lines 13 are connected, the Nth main pixel unit 151 and the Nth Each of the sub-pixel units 152 is charged by the Nth data line 13. Therefore, it is possible to improve the flicker phenomenon generated in the 3D display mode without increasing the gate driving chip
  • H is high level and L is low level.
  • the switch controller disclosed in this embodiment includes a first switch controller 341 and a second switch controller 342, one end of the Nth first scan line 321 and the Nth second scan line 322. One end is connected to the first switch controller 341, and the other end of the Nth first scan line 321 and the other end of the Nth second scan line 322 are connected to the second switch controller 342.
  • the first switch controller 341 and the second switch controller 342 are both the switch controller 14 described in the above embodiments, and are not described herein again.
  • the present invention also provides a liquid crystal display panel which is described on the basis of the array substrate 10 disclosed in the first embodiment.
  • the liquid crystal display panel 40 disclosed in the present embodiment includes an array substrate 41 , a color filter substrate 42 , and a liquid crystal layer 43 disposed between the array substrate 41 and the color filter substrate 42 .
  • the array substrate 41 is preferably the array substrate 10 described above, and will not be described herein.
  • the array substrate further includes a switch controller, respectively Connected to the first scan line and the second scan line; in the 2D display mode, the switch controller controls the first scan line and the second scan line to be sequentially turned on; in the 3D display mode, the switch controller controls the first scan line to be turned on, The second scan line is controlled to be turned off; since the first scan line is turned on and the second scan line is turned off in the 3D display mode, only the charging function is realized, the flicker phenomenon generated in the 3D display mode can be improved, and the production cost can be prevented from being improved.

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Abstract

一种液晶显示面板及其阵列基板（10），该阵列基板（10）包括开关控制器（14），分别与第一扫描线（121）和第二扫描线（122）连接；在2D显示模式下，开关控制器（14）控制第一扫描线（121）和第二扫描线（122）依次打开；在3D显示模式下，开关控制器（14）控制第一扫描线（121）打开，控制第二扫描线（122）关闭。通过以上方式，能够改善在3D显示模式所产生的闪烁现象，避免生产成本的提高。

Description

一种液晶显示面板及其阵列基板 技术领域
本发明涉及液晶显示技术领域，特别是涉及一种液晶显示面板及其阵列基板。
背景技术
为了解决液晶显示面板的色差问题，通常采用充电分享的设计方式。在同时具有2D和3D显示模式的液晶显示器中，当启用3D显示模式时，液晶显示器的充电分享功能由于帧翻转失效，导致液晶显示器的3D显示画面产生闪烁(Flicker)现象。
为了改善闪烁现象，现有技术通过将像素充电和像素分享功能独立控制，栅极驱动芯片的一个输出端仅对应一条充电扫描线或者分享扫描线，但是栅极驱动芯片使用的数目加倍，导致生产成本提高。
发明内容
本发明实施例提供了一种液晶显示面板及其阵列基板，能够改善在3D显示模式所产生的闪烁现象，避免生产成本的提高。
本发明提供一种阵列基板，其包括基板、多条扫描线以及多条数据线，多条扫描线和多条数据线相交设置在基板上，以形成多个像素单元，每条扫描线包括第一扫描线和第二扫描线，在第一扫描线打开时，相应的像素单元通过数据线实现充电；在第二扫描线打开时，相应的像素单元实现分享电压，阵列基板进一步包括开关控制器，分别与第一扫描线和第二扫描线连接；在2D显示模式下，开关控制器控制第一扫描线和第二扫描线依次打开；在3D显示模式下，开关控制器控制第一扫描线打开，控制第二扫描线关闭；
其中，第N个像素单元包括第N个主像素单元和第N个子像素单元，阵列基板包括与第N个像素单元相应设置的第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及分享电容，第N个主像素单元与第一薄膜晶体管的漏极连接，第一薄膜晶体管的栅极与第N条第一扫描线连接，第一薄膜晶体管的源极与第N条数据线连接；第N个子像素单元与第二薄膜晶体 管的漏极连接，第二薄膜晶体管的栅极与第N条第一扫描线连接，第二薄膜晶体管的源极与第N条数据线连接；第三薄膜晶体管的栅极与第N条第二扫描线连接，第三薄膜晶体管的源极与第N个子像素单元连接，第三薄膜晶体管的漏极与分享电容连接，N为大于或等于1的整数；
在2D显示模式下，开关控制器控制第N条第一扫描线打开，第一薄膜晶体管和第二薄膜晶体管导通，第N个主像素单元和第N个子像素单元均通过第N条数据线进行充电；开关控制器控制第N条第二扫描线打开，第三薄膜晶体管导通，第N个子像素单元与分享电容进行分享电压；
在3D显示模式下，开关控制器控制第N条第一扫描线打开，控制第N条第二扫描线关闭，第一薄膜晶体管和第二薄膜晶体管导通，第三薄膜晶体管断开，第N个主像素单元和第N个子像素单元均通过第N条数据线进行充电。
其中，开关控制器包括多个开关单元，第N个开关单元与第N条第一扫描线和第N条第二扫描线连接。
本发明还提供一种阵列基板，其包括基板、多条扫描线以及多条数据线，多条扫描线和多条数据线相交设置在基板上，以形成多个像素单元，每条扫描线包括第一扫描线和第二扫描线，在第一扫描线打开时，相应的像素单元通过数据线实现充电；在第二扫描线打开时，相应的像素单元实现分享电压，阵列基板进一步包括开关控制器，分别与第一扫描线和第二扫描线连接；在2D显示模式下，开关控制器控制第一扫描线和第二扫描线依次打开；在3D显示模式下，开关控制器控制第一扫描线打开，控制第二扫描线关闭。
其中，第N个像素单元包括第N个主像素单元和第N个子像素单元，阵列基板包括与第N个像素单元相应设置的第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及分享电容，第N个主像素单元与第一薄膜晶体管的漏极连接，第一薄膜晶体管的栅极与第N条第一扫描线连接，第一薄膜晶体管的源极与第N条数据线连接；第N个子像素单元与第二薄膜晶体管的漏极连接，第二薄膜晶体管的栅极与第N条第一扫描线连接，第二薄膜晶体管的源极与第N条数据线连接；第三薄膜晶体管的栅极与第N条第二扫描线连接，第三薄膜晶体管的源极与第N个子像素单元连接，第三薄 膜晶体管的漏极与分享电容连接，N为大于或等于1的整数。
其中，在2D显示模式下，开关控制器控制第N条第一扫描线打开，第一薄膜晶体管和第二薄膜晶体管导通，第N个主像素单元和第N个子像素单元均通过第N条数据线进行充电；开关控制器控制第N条第二扫描线打开，第三薄膜晶体管导通，第N个子像素单元与分享电容进行分享电压。
其中，在3D显示模式下，开关控制器控制第N条第一扫描线打开，控制第N条第二扫描线关闭，第一薄膜晶体管和第二薄膜晶体管导通，第三薄膜晶体管断开，第N个主像素单元和第N个子像素单元均通过第N条数据线进行充电。
其中，开关控制器包括多个开关单元，第N个开关单元与第N条第一扫描线和第N条第二扫描线连接。
其中，第N个开关单元包括第一开关管、第二开关管、第三开关管以及第四开关管，第一开关管的第一端和第四开关管的第一端接收第一控制信号，第一开关管的第二端和第三开关管的第二端接收扫描线驱动信号，第一开关管的第三端和第二开关管的第三端均与第N条第一扫描线连接，第二开关管的第一端和第三开关管的第一端接收第二控制信号，第二开关管的第二端接收第一控制信号，第三开关管的第三端和第四开关管的第三端均与第N条第二扫描线连接，第四开关管的第二端接收第二控制信号。
其中，在2D显示模式下，扫描线驱动信号为高电平，当第一控制信号为高电平，第二控制信号为低电平时，第一开关管和第四开关管导通，第二开关管和第三开关管断开，第N条第一扫描线为高电平，第N条第二扫描线为低电平；当第一控制信号为低电平，第二控制信号为高电平时，第一开关管和第四开关管断开，第二开关管和第三开关管导通，第N条第一扫描线为低电平，第N条第二扫描线为高电平。
其中，在3D显示模式下，扫描线驱动信号为高电平，第一控制信号为高电平，第二控制信号为低电平，第一开关管和第四开关管导通，第二开关管和第三开关管断开，第N条第一扫描线为高电平，第N条第二扫描线为低电平。
其中，开关控制器包括第一开关控制器和第二开关控制器，第一扫描线的一端和第二扫描线的一端与第一开关控制器连接，第一扫描线的另一 端和第二扫描线的另一端与第二开关控制器连接。
本发明还提供一种液晶显示面板，液晶显示面板包括阵列基板、彩膜基板以及设置在阵列基板和彩膜基板之间液晶层，该阵列基板包括基板、多条扫描线以及多条数据线，多条扫描线和多条数据线相交设置在基板上，以形成多个像素单元，每条扫描线包括第一扫描线和第二扫描线，在第一扫描线打开时，相应的像素单元通过数据线实现充电；在第二扫描线打开时，相应的像素单元实现分享电压，阵列基板进一步包括开关控制器，分别与第一扫描线和第二扫描线连接；在2D显示模式下，开关控制器控制第一扫描线和第二扫描线依次打开；在3D显示模式下，开关控制器控制第一扫描线打开，控制第二扫描线关闭。
其中，第N个像素单元包括第N个主像素单元和第N个子像素单元，阵列基板包括与第N个像素单元相应设置的第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及分享电容，第N个主像素单元与第一薄膜晶体管的漏极连接，第一薄膜晶体管的栅极与第N条第一扫描线连接，第一薄膜晶体管的源极与第N条数据线连接；第N个子像素单元与第二薄膜晶体管的漏极连接，第二薄膜晶体管的栅极与第N条第一扫描线连接，第二薄膜晶体管的源极与第N条数据线连接；第三薄膜晶体管的栅极与第N条第二扫描线连接，第三薄膜晶体管的源极与第N个子像素单元连接，第三薄膜晶体管的漏极与分享电容连接，N为大于或等于1的整数。
其中，在2D显示模式下，开关控制器控制第N条第一扫描线打开，第一薄膜晶体管和第二薄膜晶体管导通，第N个主像素单元和第N个子像素单元均通过第N条数据线进行充电；开关控制器控制第N条第二扫描线打开，第三薄膜晶体管导通，第N个子像素单元与分享电容进行分享电压。
其中，在3D显示模式下，开关控制器控制第N条第一扫描线打开，控制第N条第二扫描线关闭，第一薄膜晶体管和第二薄膜晶体管导通，第三薄膜晶体管断开，第N个主像素单元和第N个子像素单元均通过第N条数据线进行充电。
其中，开关控制器包括多个开关单元，第N个开关单元与第N条第一扫描线和第N条第二扫描线连接。
其中，第N个开关单元包括第一开关管、第二开关管、第三开关管以 及第四开关管，第一开关管的第一端和第四开关管的第一端接收第一控制信号，第一开关管的第二端和第三开关管的第二端接收扫描线驱动信号，第一开关管的第三端和第二开关管的第三端均与第N条第一扫描线连接，第二开关管的第一端和第三开关管的第一端接收第二控制信号，第二开关管的第二端接收第一控制信号，第三开关管的第三端和第四开关管的第三端均与第N条第二扫描线连接，第四开关管的第二端接收第二控制信号。
其中，在2D显示模式下，扫描线驱动信号为高电平，当第一控制信号为高电平，第二控制信号为低电平时，第一开关管和第四开关管导通，第二开关管和第三开关管断开，第N条第一扫描线为高电平，第N条第二扫描线为低电平；当第一控制信号为低电平，第二控制信号为高电平时，第一开关管和第四开关管断开，第二开关管和第三开关管导通，第N条第一扫描线为低电平，第N条第二扫描线为高电平。
其中，在3D显示模式下，扫描线驱动信号为高电平，第一控制信号为高电平，第二控制信号为低电平，第一开关管和第四开关管导通，第二开关管和第三开关管断开，第N条第一扫描线为高电平，第N条第二扫描线为低电平。
其中，开关控制器包括第一开关控制器和第二开关控制器，第一扫描线的一端和第二扫描线的一端与第一开关控制器连接，第一扫描线的另一端和第二扫描线的另一端与第二开关控制器连接。
通过上述方案，本发明的有益效果是：本发明在第一扫描线打开时，相应的像素单元通过数据线实现充电；在第二扫描线打开时，相应的像素单元实现分享电压，阵列基板进一步包括开关控制器，分别与第一扫描线和第二扫描线连接；在2D显示模式下，开关控制器控制第一扫描线和第二扫描线依次打开；在3D显示模式下，开关控制器控制第一扫描线打开，控制第二扫描线关闭；由于在3D显示模式下，第一扫描线打开，第二扫描线关闭，仅实现充电功能，能够改善在3D显示模式所产生的闪烁现象，避免生产成本的提高。
附图说明
图1是本发明第一实施例的阵列基板的结构示意图；
图2是本发明第二实施例的阵列基板的结构示意图；
图3是本发明第三实施例的阵列基板的结构示意图；
图4是本发明第一实施例的液晶显示面板的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1所示，图1是本发明第一实施例的阵列基板的结构示意图。本实施例所揭示的阵列基板10包括2D(平面)显示模式和3D(立体)显示模式，如图1所示，该阵列基板10包括基板11、多条扫描线12、多条数据线13以及开关控制器14。
其中，多条扫描线12和多条数据线13相交设置在基板上，以形成多个像素单元15。每条扫描线12包括第一扫描线121和第二扫描线122，在第一扫描线121打开时，相应的像素单元15实现充电，即与第一扫描线121连接的像素单元15通过数据线13进行充电。在第二扫描线122打开时，相应的像素单元15实现分享电压，即与第二扫描线122连接的像素单元15进行分享电压。
开关控制器14分别与第一扫描线121和第二扫描线122连接，在2D显示模式下，开关控制器14控制第一扫描线121和第二扫描线122依次打开，实现充电和分享电压功能；在3D显示模式下，开关控制器14控制第一扫描线121打开，控制第二扫描线122断开，仅实现充电功能，能够改善在3D显示模式所产生的闪烁现象，避免生产成本的提高。
以下以第N个像素单元进行详细说明，其中第N个像素单元15包括第N个主像素单元151和第N个子像素单元152，N为大于或等于1的整数。
本实施例所揭示的阵列基板10进一步包括与第N个像素单元相应设置的第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3以及分享 电容C。
第N个主像素单元151与第一薄膜晶体管T1的漏极连接，第一薄膜晶体管T1的栅极与第N条第一扫描线121连接，第一薄膜晶体管T1的源极与第N条数据线13连接。第N个子像素单元152与第二薄膜晶体管T2的漏极连接，第二薄膜晶体管T2的栅极与第N条第一扫描线121连接，第二薄膜晶体管T2的源极与第N条数据线13连接。第三薄膜晶体管T3的栅极与第N条第二扫描线122连接，第三薄膜晶体管T3的源极与第N个子像素单元152连接，第三薄膜晶体管T3的漏极与分享电容C连接，即第三薄膜晶体管T3的漏极通过分享电容C接地。
开关控制器14的输出端分别与第N条第一扫描线121连接和第N条第二扫描线122连接，开关控制器14的输入端与扫描线驱动信号连接。
在2D显示模式下，开关控制器14控制第N条第一扫描线121打开，即第N条第一扫描线121接收到的扫描线驱动信号为高电平，第一薄膜晶体管T1和第二薄膜晶体管T2同时导通，第N个主像素单元151和第N个子像素单元152均与第N条数据线13连接，第N个主像素单元151和第N个子像素单元152均通过第N条数据线13进行充电，实现充电功能；在第N个主像素单元151和第N个子像素单元152充电完成后，开关控制器14控制第N条第二扫描线122打开，即第N条第二扫描线122接收到的扫描线驱动信号为高电平，第三薄膜晶体管T3导通，第N个子像素单元152与分享电容C连接，第N个子像素单元152与分享电容进行分享电压，以使第N个子像素单元152的电压小于第N个主像素单元151的电压，实现分享电压，能够改善大视角的色偏。
在3D显示模式下，开关控制器14控制第N条第一扫描线121打开，控制第N条第二扫描线122关闭，即第N条第一扫描线121接收到的扫描线驱动信号为高电平，第N条第二扫描线122接收到的扫描线驱动信号为低电平，第一薄膜晶体管T1和第二薄膜晶体管T2同时导通，第三薄膜晶体管T3断开，第N个主像素单元151和第N个子像素单元152均与第N条数据线13连接，第N个主像素单元151和第N个子像素单元152均通过第N条数据线13进行充电，实现充电功能。因此能够改善在3D显示模式所产生的闪烁现象，没有增加栅极驱动芯片，避免生产成本的提高。
本发明还提供第二实施例的阵列基板，其在第一实施例所揭示的阵列基板10的基础上进行描述。如图2所示，本实施例所揭示的阵列基板的开关控制器14包括多个开关单元141，第N个开关单元141分别与第N条第一扫描线121和第N条第二扫描线122连接。
在本实施例中，第N个开关单元141包括第一开关管142、第二开关管143、第三开关管144以及第四开关管145，开关控制器14进一步包括第一控制信号生成单元146以及第二控制信号生成单元147。其中，第一开关管142的第一端和第四开关管145的第一端与第一控制信号生成单元146连接，接收第一控制信号CL1；第一开关管142的第二端和第三开关管144的第二端接收扫描线驱动信号Gn；第一开关管142的第三端和第二开关管143的第三端均与第N条第一扫描线121连接；第二开关管143的第一端和第三开关管144的第一端与第二控制信号生成单元147连接，接收第二控制信号CL2；第二开关管143的第二端与第一控制信号生成单元146连接，接收第一控制信号CL1；第三开关管144的第三端和第四开关管145的第三端均与第N条第二扫描线122连接；第四开关管145的第二端与第二控制信号生成单元147连接，接收第二控制信号CL2。
优选地，第一开关管142、第二开关管143、第三开关管144以及第四开关管145均为薄膜晶体管，第一端为薄膜晶体管的栅极，第二端为薄膜晶体管的源极，第三端为薄膜晶体管的漏极。第N条第一扫描线的信号为Gn-main，第N条第二扫描线的信号为Gn-sub。
如表1所示，在2D显示模式下。在时间T1，扫描线驱动信号Gn为高电平，第一控制信号生成单元146产生的第一控制信号CL1为高电平，第二控制信号生成单元147产生的第二控制信号CL2为低电平，第一开关管142和第四开关管145导通，第二开关管143和第三开关管144断开，第N条第一扫描线121的信号Gn-main为高电平，第N条第二扫描线122的信号Gn-sub为低电平，第一薄膜晶体管T1和第二薄膜晶体管T2同时导通，第N个主像素单元151和第N个子像素单元152均与第N条数据线13连接，第N个主像素单元151和第N个子像素单元152均通过第N条数据线13进行充电，实现充电功能。
在时间T2，扫描线驱动信号Gn为高电平，第一控制信号生成单元146 产生的第一控制信号CL1为低电平，第二控制信号生成单元147产生的第二控制信号CL2为高电平，第一开关管142和第四开关管145断开，第二开关管143和第三开关管144导通，第N条第一扫描线121的信号Gn-main为低电平，第N条第二扫描线122的信号Gn-sub为高电平，第三薄膜晶体管T3导通，第N个子像素单元152与分享电容C连接，第N个子像素单元152与分享电容进行分享电压，以使第N个子像素单元152的电压小于第N个主像素单元151的电压，实现分享电压，能够改善大视角的色偏。
表1 阵列基板在2D显示模式下的时序表
  CL1 CL2 Gn Gn+1 Gn-main Gn-sub Gn+1-main Gn+1-sub
T1 H L H L H L L L
T2 L H H L L H L L
T3 H L L H L L H L
T4 L H L H L L L H
其中，H为高电平，L为低电平。
如表2所示，在3D显示模式下。在时间T1，扫描线驱动信号Gn为高电平，第一控制信号生成单元146产生的第一控制信号CL1为高电平，第二控制信号生成单元147产生的第二控制信号CL2为低电平，第一开关管142和第四开关管145导通，第二开关管143和第三开关管144断开，第N条第一扫描线121的信号Gn-main为高电平，第N条第二扫描线122的信号Gn-sub为低电平，第一薄膜晶体管T1和第二薄膜晶体管T2同时导通，第N个主像素单元151和第N个子像素单元152均与第N条数据线13连接，第N个主像素单元151和第N个子像素单元152均通过第N条数据线13进行充电，实现充电功能。
在时间T2，扫描线驱动信号Gn为高电平，第一控制信号生成单元146产生的第一控制信号CL1为高电平，第二控制信号生成单元147产生的第二控制信号CL2为低电平，第一开关管142和第四开关管145导通，第二开关管143和第三开关管144断开，第N条第一扫描线121的信号Gn-main为高电平，第N条第二扫描线122的信号Gn-sub为低电平，第一薄膜晶体管T1和第二薄膜晶体管T2同时导通，第N个主像素单元151和第N个子像素单元152均与第N条数据线13连接，第N个主像素单元151和第N 个子像素单元152均通过第N条数据线13进行充电。因此能够改善在3D显示模式所产生的闪烁现象，没有增加栅极驱动芯片，避免生产成本的提高。
表2 阵列基板在3D显示模式下的时序表
  CL1 CL2 Gn Gn+1 Gn-main Gn-sub Gn+1-main Gn+1-sub
T1 H L H L H L L L
T2 H L H L H L L L
T3 H L L H L L H L
T4 H L L H L L H L
其中，H为高电平，L为低电平。
本发明还提供第三实施例的阵列基板，其在第二实施例所揭示的阵列基板的基础上进行描述。如图3所示，本实施例所揭示的开关控制器包括第一开关控制器341和第二开关控制器342，第N条第一扫描线321的一端和第N条第二扫描线322的一端与第一开关控制器341连接，第N条第一扫描线321的另一端和第N条第二扫描线322的另一端与第二开关控制器342连接。第一开关控制器341和第二开关控制器342均为上述实施例所描述的开关控制器14，在此不再赘述。
本发明还提供一种液晶显示面板，其在第一实施例所揭示的阵列基板10的基础上进行描述。如图4所示，本实施所揭示的液晶显示面板40包括阵列基板41、彩膜基板42以及设置在阵列基板41和彩膜基板42之间液晶层43，其中阵列基板41和彩膜基板42相对设置，阵列基板41优选为上述的阵列基板10，在此不再赘述。
综上所述，本发明在第一扫描线打开时，相应的像素单元通过数据线实现充电；在第二扫描线打开时，相应的像素单元实现分享电压，阵列基板进一步包括开关控制器，分别与第一扫描线和第二扫描线连接；在2D显示模式下，开关控制器控制第一扫描线和第二扫描线依次打开；在3D显示模式下，开关控制器控制第一扫描线打开，控制第二扫描线关闭；由于在3D显示模式下，第一扫描线打开，第二扫描线关闭，仅实现充电功能，能够改善在3D显示模式所产生的闪烁现象，避免生产成本的提高。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡 是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种阵列基板，所述阵列基板包括基板、多条扫描线以及多条数据线，所述多条扫描线和所述多条数据线相交设置在所述基板上，以形成多个像素单元，每条所述扫描线包括第一扫描线和第二扫描线，在所述第一扫描线打开时，相应的所述像素单元通过所述数据线实现充电；在所述第二扫描线打开时，相应的所述像素单元实现分享电压，其中，所述阵列基板进一步包括开关控制器，分别与所述第一扫描线和所述第二扫描线连接；在2D显示模式下，所述开关控制器控制所述第一扫描线和所述第二扫描线依次打开；在3D显示模式下，所述开关控制器控制所述第一扫描线打开，控制所述第二扫描线关闭；
    其中，第N个所述像素单元包括第N个主像素单元和第N个子像素单元，所述阵列基板包括与所述第N个所述像素单元相应设置的第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及分享电容，所述第N个主像素单元与所述第一薄膜晶体管的漏极连接，所述第一薄膜晶体管的栅极与第N条第一扫描线连接，所述第一薄膜晶体管的源极与第N条数据线连接；所述第N个子像素单元与所述第二薄膜晶体管的漏极连接，所述第二薄膜晶体管的栅极与所述第N条第一扫描线连接，所述第二薄膜晶体管的源极与所述第N条数据线连接；所述第三薄膜晶体管的栅极与第N条第二扫描线连接，所述第三薄膜晶体管的源极与所述第N个子像素单元连接，所述第三薄膜晶体管的漏极与所述分享电容连接，N为大于或等于1的整数；
    在所述2D显示模式下，所述开关控制器控制所述第N条第一扫描线打开，所述第一薄膜晶体管和所述第二薄膜晶体管导通，所述第N个主像素单元和第N个子像素单元均通过所述第N条数据线进行充电；所述开关控制器控制所述第N条第二扫描线打开，所述第三薄膜晶体管导通，所述第N个子像素单元与所述分享电容进行分享电压；
    在所述3D显示模式下，所述开关控制器控制所述第N条第一扫描线打开，控制所述第N条第二扫描线关闭，所述第一薄膜晶体管和所述第二薄膜晶体管导通，所述第三薄膜晶体管断开，所述第N个主像素单元和第N个子像素单元均通过所述第N条数据线进行充电。
  2. 根据权利要求1所述的阵列基板，其中，所述开关控制器包括多个开关单元，第N个开关单元与所述第N条第一扫描线和所述第N条第二扫描线连接。
  3. 一种阵列基板，所述阵列基板包括基板、多条扫描线以及多条数据线，所述多条扫描线和所述多条数据线相交设置在所述基板上，以形成多个像素单元，每条所述扫描线包括第一扫描线和第二扫描线，在所述第一扫描线打开时，相应的所述像素单元通过所述数据线实现充电；在所述第二扫描线打开时，相应的所述像素单元实现分享电压，其中，所述阵列基板进一步包括开关控制器，分别与所述第一扫描线和所述第二扫描线连接；在2D显示模式下，所述开关控制器控制所述第一扫描线和所述第二扫描线依次打开；在3D显示模式下，所述开关控制器控制所述第一扫描线打开，控制所述第二扫描线关闭。
  4. 根据权利要求3所述的阵列基板，其中，第N个所述像素单元包括第N个主像素单元和第N个子像素单元，所述阵列基板包括与所述第N个所述像素单元相应设置的第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及分享电容，所述第N个主像素单元与所述第一薄膜晶体管的漏极连接，所述第一薄膜晶体管的栅极与第N条第一扫描线连接，所述第一薄膜晶体管的源极与第N条数据线连接；所述第N个子像素单元与所述第二薄膜晶体管的漏极连接，所述第二薄膜晶体管的栅极与所述第N条第一扫描线连接，所述第二薄膜晶体管的源极与所述第N条数据线连接；所述第三薄膜晶体管的栅极与第N条第二扫描线连接，所述第三薄膜晶体管的源极与所述第N个子像素单元连接，所述第三薄膜晶体管的漏极与所述分享电容连接，N为大于或等于1的整数。
  5. 根据权利要求4所述的阵列基板，其中，在所述2D显示模式下，所述开关控制器控制所述第N条第一扫描线打开，所述第一薄膜晶体管和所述第二薄膜晶体管导通，所述第N个主像素单元和第N个子像素单元均通过所述第N条数据线进行充电；所述开关控制器控制所述第N条第二扫描线打开，所述第三薄膜晶体管导通，所述第N个子像素单元与所述分享电容进行分享电压。
  6. 根据权利要求4所述的阵列基板，其中，在所述3D显示模式下， 所述开关控制器控制所述第N条第一扫描线打开，控制所述第N条第二扫描线关闭，所述第一薄膜晶体管和所述第二薄膜晶体管导通，所述第三薄膜晶体管断开，所述第N个主像素单元和第N个子像素单元均通过所述第N条数据线进行充电。
  7. 根据权利要求4所述的阵列基板，其中，所述开关控制器包括多个开关单元，第N个开关单元与所述第N条第一扫描线和所述第N条第二扫描线连接。
  8. 根据权利要求7所述的阵列基板，其中，所述第N个开关单元包括第一开关管、第二开关管、第三开关管以及第四开关管，所述第一开关管的第一端和所述第四开关管的第一端接收第一控制信号，所述第一开关管的第二端和所述第三开关管的第二端接收扫描线驱动信号，所述第一开关管的第三端和所述第二开关管的第三端均与所述第N条第一扫描线连接，所述第二开关管的第一端和所述第三开关管的第一端接收第二控制信号，所述第二开关管的第二端接收所述第一控制信号，所述第三开关管的第三端和所述第四开关管的第三端均与所述第N条第二扫描线连接，所述第四开关管的第二端接收所述第二控制信号。
  9. 根据权利要求8所述的阵列基板，其中，在所述2D显示模式下，所述扫描线驱动信号为高电平，当所述第一控制信号为高电平，所述第二控制信号为低电平时，所述第一开关管和所述第四开关管导通，所述第二开关管和所述第三开关管断开，所述第N条第一扫描线为高电平，所述第N条第二扫描线为低电平；当所述第一控制信号为低电平，所述第二控制信号为高电平时，所述第一开关管和所述第四开关管断开，所述第二开关管和所述第三开关管导通，所述第N条第一扫描线为低电平，所述第N条第二扫描线为高电平。
  10. 根据权利要求8所述的阵列基板，其中，在所述3D显示模式下，所述扫描线驱动信号为高电平，所述第一控制信号为高电平，所述第二控制信号为低电平，所述第一开关管和所述第四开关管导通，所述第二开关管和所述第三开关管断开，所述第N条第一扫描线为高电平，所述第N条第二扫描线为低电平。
  11. 根据权利要求3所述的阵列基板，其中，所述开关控制器包括第一 开关控制器和第二开关控制器，所述第一扫描线的一端和所述第二扫描线的一端与所述第一开关控制器连接，所述第一扫描线的另一端和所述第二扫描线的另一端与所述第二开关控制器连接。
  12. 一种液晶显示面板，其中，所述液晶显示面板包括阵列基板、彩膜基板以及设置在所述阵列基板和所述彩膜基板之间液晶层，所述阵列基板包括基板、多条扫描线以及多条数据线，所述多条扫描线和所述多条数据线相交设置在所述基板上，以形成多个像素单元，每条所述扫描线包括第一扫描线和第二扫描线，在所述第一扫描线打开时，相应的所述像素单元通过所述数据线实现充电；在所述第二扫描线打开时，相应的所述像素单元实现分享电压，其中，所述阵列基板进一步包括开关控制器，分别与所述第一扫描线和所述第二扫描线连接；在2D显示模式下，所述开关控制器控制所述第一扫描线和所述第二扫描线依次打开；在3D显示模式下，所述开关控制器控制所述第一扫描线打开，控制所述第二扫描线关闭。。
  13. 根据权利要求12所述的液晶显示面板，其中，第N个所述像素单元包括第N个主像素单元和第N个子像素单元，所述阵列基板包括与所述第N个所述像素单元相应设置的第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及分享电容，所述第N个主像素单元与所述第一薄膜晶体管的漏极连接，所述第一薄膜晶体管的栅极与第N条第一扫描线连接，所述第一薄膜晶体管的源极与第N条数据线连接；所述第N个子像素单元与所述第二薄膜晶体管的漏极连接，所述第二薄膜晶体管的栅极与所述第N条第一扫描线连接，所述第二薄膜晶体管的源极与所述第N条数据线连接；所述第三薄膜晶体管的栅极与第N条第二扫描线连接，所述第三薄膜晶体管的源极与所述第N个子像素单元连接，所述第三薄膜晶体管的漏极与所述分享电容连接，N为大于或等于1的整数。
  14. 根据权利要求13所述的液晶显示面板，其中，在所述2D显示模式下，所述开关控制器控制所述第N条第一扫描线打开，所述第一薄膜晶体管和所述第二薄膜晶体管导通，所述第N个主像素单元和第N个子像素单元均通过所述第N条数据线进行充电；所述开关控制器控制所述第N条第二扫描线打开，所述第三薄膜晶体管导通，所述第N个子像素单元与所述分享电容进行分享电压。
  15. 根据权利要求13所述的液晶显示面板，其中，在所述3D显示模式下，所述开关控制器控制所述第N条第一扫描线打开，控制所述第N条第二扫描线关闭，所述第一薄膜晶体管和所述第二薄膜晶体管导通，所述第三薄膜晶体管断开，所述第N个主像素单元和第N个子像素单元均通过所述第N条数据线进行充电。
  16. 根据权利要求13所述的液晶显示面板，其中，所述开关控制器包括多个开关单元，第N个开关单元与所述第N条第一扫描线和所述第N条第二扫描线连接。
  17. 根据权利要求16所述的液晶显示面板，其中，所述第N个开关单元包括第一开关管、第二开关管、第三开关管以及第四开关管，所述第一开关管的第一端和所述第四开关管的第一端接收第一控制信号，所述第一开关管的第二端和所述第三开关管的第二端接收扫描线驱动信号，所述第一开关管的第三端和所述第二开关管的第三端均与所述第N条第一扫描线连接，所述第二开关管的第一端和所述第三开关管的第一端接收第二控制信号，所述第二开关管的第二端接收所述第一控制信号，所述第三开关管的第三端和所述第四开关管的第三端均与所述第N条第二扫描线连接，所述第四开关管的第二端接收所述第二控制信号。
  18. 根据权利要求17所述的液晶显示面板，其中，在所述2D显示模式下，所述扫描线驱动信号为高电平，当所述第一控制信号为高电平，所述第二控制信号为低电平时，所述第一开关管和所述第四开关管导通，所述第二开关管和所述第三开关管断开，所述第N条第一扫描线为高电平，所述第N条第二扫描线为低电平；当所述第一控制信号为低电平，所述第二控制信号为高电平时，所述第一开关管和所述第四开关管断开，所述第二开关管和所述第三开关管导通，所述第N条第一扫描线为低电平，所述第N条第二扫描线为高电平。
  19. 根据权利要求17所述的液晶显示面板，其中，在所述3D显示模式下，所述扫描线驱动信号为高电平，所述第一控制信号为高电平，所述第二控制信号为低电平，所述第一开关管和所述第四开关管导通，所述第二开关管和所述第三开关管断开，所述第N条第一扫描线为高电平，所述第N条第二扫描线为低电平。
  20. 根据权利要求12所述的液晶显示面板，其中，所述开关控制器包括第一开关控制器和第二开关控制器，所述第一扫描线的一端和所述第二扫描线的一端与所述第一开关控制器连接，所述第一扫描线的另一端和所述第二扫描线的另一端与所述第二开关控制器连接。
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