WO2017038448A1 - Élément semi-conducteur au nitrure - Google Patents

Élément semi-conducteur au nitrure Download PDF

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Publication number
WO2017038448A1
WO2017038448A1 PCT/JP2016/073883 JP2016073883W WO2017038448A1 WO 2017038448 A1 WO2017038448 A1 WO 2017038448A1 JP 2016073883 W JP2016073883 W JP 2016073883W WO 2017038448 A1 WO2017038448 A1 WO 2017038448A1
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Prior art keywords
semiconductor layer
layer
dielectric multilayer
substrate
semiconductor
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PCT/JP2016/073883
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English (en)
Japanese (ja)
Inventor
将一郎 泉
統之 風田川
大 倉本
達史 濱口
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ソニー株式会社
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Priority to JP2017537715A priority Critical patent/JP6919565B2/ja
Publication of WO2017038448A1 publication Critical patent/WO2017038448A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
    • H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser

Definitions

  • the present technology relates to, for example, a nitride semiconductor device that emits light in the stacking direction.
  • the semiconductor element which comprises a surface emitting laser etc. is mounted in the submount etc. in order to discharge
  • Solder is generally used at the time of mounting, but it is known that the solder rises due to the wettability of the element. When this rise is large, the solder is in contact with areas other than the desired area, causing a problem of current leakage.
  • a light emitting device such as a surface emitting laser using a nitride semiconductor as a semiconductor material generally has a lower DBR layer (second reflective layer), a lower spacer layer (second compound semiconductor layer), and the like on a substrate.
  • An active layer, an upper spacer layer (first compound semiconductor layer), an upper DBR layer (first reflective layer), and a contact layer (first electrode) are stacked in this order (see, for example, Patent Documents 1 and 2) .
  • Patent Documents 1 and 2 since various characteristics are strongly affected by heat, attempts have been made to improve the heat removal property by covering most of the light emitting element with a solder having high thermal conductivity. For this reason, there has been a problem that a leak failure is likely to occur together with the rise of the solder due to the wettability of the element.
  • a method of suppressing the rising of the solder is considered by providing digging or the like in a member (mounted member) in contact with the nitride semiconductor element such as a submount.
  • a member mounted member
  • the nitride semiconductor element such as a submount.
  • a nitride semiconductor device includes a first semiconductor layer, an active layer provided on the first semiconductor layer, and a second semiconductor layer provided on the active layer. At least one recess or dielectric multilayer film is formed on one of the side surfaces of the first semiconductor layer and the second semiconductor layer.
  • At least one recess or dielectric multilayer film is formed on one of the side surfaces of the first semiconductor layer and the second semiconductor layer in which the active layer is stacked.
  • One is formed.
  • the recess or the dielectric multilayer film is formed on one of the side surfaces of the first semiconductor layer and the second semiconductor layer in which the active layer is stacked.
  • the covering area of the solder used at the time of mounting Therefore, it is possible to suppress the rising of the solder and to reduce the occurrence of the leak failure while enhancing the heat removal efficiency by the coating of the solder.
  • the effects of the present technology are not necessarily limited to the effects described herein, but may be any of the effects described in the present disclosure.
  • FIG. 1 is a cross-sectional view of a surface emitting semiconductor laser according to an embodiment of the present technology. It is a schematic diagram showing the planar shape of the dielectric multilayer of the semiconductor laser shown in FIG. It is a schematic diagram showing an example of the formation position of the dielectric multilayer shown in FIG.
  • FIG. 7 is a cross-sectional view for illustrating the method of manufacturing the semiconductor laser shown in FIG. 1. It is sectional drawing for demonstrating the process of following FIG. 4A. It is sectional drawing for demonstrating the process of following FIG. 4B. It is sectional drawing for demonstrating the process of following FIG. 5A. It is a sectional view of LED concerning a 2nd embodiment of this art.
  • FIG. 1 is a cross-sectional view of a surface emitting semiconductor laser according to an embodiment of the present technology. It is a schematic diagram showing the planar shape of the dielectric multilayer of the semiconductor laser shown in FIG. It is a schematic diagram showing an example of the formation position of the dielectric multilayer shown in FIG.
  • FIG. 18 is an example of a cross-sectional view of a semiconductor laser soldered to a heat sink as an application example 1;
  • FIG. 18 is an example of a cross-sectional view of a semiconductor laser soldered to a heat sink as an application example 1; It is an example of sectional drawing of LED soldered to the heat sink as application example 2.
  • FIG. It is an example of sectional drawing of LED soldered to the heat sink as application example 2.
  • First embodiment semiconductor laser having a dielectric multilayer film and a recess on the side surface of the semiconductor layer on the substrate side
  • Overall configuration 1-2.
  • Manufacturing method 1-3.
  • Action / Effect Second Embodiment LED having dielectric multilayer film and recess on the side surface of the semiconductor layer on the substrate side
  • Application example
  • FIG. 1 illustrates an example of a cross-sectional configuration of a surface-emitting semiconductor device (semiconductor laser 1) according to a first embodiment of the present technology.
  • the semiconductor laser 1 has a substrate 11 and a plurality of dielectric multilayer films 41 in contact with the surface S1 of the substrate 11. A plurality of dielectric multilayer films 41 are provided on the substrate 11 at intervals.
  • the semiconductor laser 1 further has a configuration in which a semiconductor layer 20, an insulating film 24, a transparent electrode 32, and a second reflective layer 42 are stacked in this order.
  • the semiconductor layer 20 has a configuration in which the first semiconductor layer 21, the active layer 22, and the second semiconductor layer 23 are stacked in this order from the substrate 11 side.
  • Each dielectric multilayer film 41 is embedded by the first semiconductor layer 21, and the side surface of the one or more dielectric multilayer films 41 is exposed on the side surface of the first semiconductor layer 21. That is, at least one dielectric multilayer film 41 is formed on the side surface of the first semiconductor layer 21. Furthermore, at least one recess 21A is formed on the side surface of the first semiconductor layer 21.
  • the semiconductor laser 1 has a first electrode 31 in contact with the surface S2 (surface facing the surface S1) of the substrate 11. Note that the semiconductor laser 1 of FIG. 1 is schematically represented and is different from the actual dimensions.
  • the substrate 11 is an element forming substrate used for manufacturing the semiconductor layer 20.
  • the substrate 11 is provided in contact with the semiconductor layer 20 (first semiconductor layer 21).
  • the substrate 11 may use various substrates such as GaN substrate, sapphire substrate, GaAs substrate, SiC substrate, alumina substrate, ZnS substrate, ZnO substrate, LiMgO substrate, LiGaO 2 substrate, MgAl 2 O 4 substrate, InP substrate, for example. it can.
  • an insulating substrate made of AlN or the like, a semiconductor substrate made of Si, SiC, Ge or the like, a metal substrate or an alloy substrate may be used.
  • the thickness in the stacking direction of the substrate 11 (hereinafter simply referred to as thickness), for example, preferably 0.05 mm to 0.5 mm.
  • the semiconductor layer 20 has a configuration in which the first semiconductor layer 21, the active layer 22 and the second semiconductor layer 23 are sequentially stacked from the substrate 11 side.
  • the first semiconductor layer 21 and the second semiconductor layer 23 have different conductivity types.
  • the first semiconductor layer 21 is formed of an n-type compound semiconductor
  • the second semiconductor layer 23 is formed of a p-type compound semiconductor It is formed.
  • the first semiconductor layer 21, the active layer 22 and the second semiconductor layer 23 are each formed of a nitride compound semiconductor.
  • Specific nitride-based compound semiconductors include GaN-based compound semiconductors such as GaN, AlGaN, InGaN, and AlInGaN. Besides these, AlN, AlInN and InN can be mentioned.
  • the active layer 22 preferably has a quantum well structure. Specifically, it may have a single quantum well structure (QW structure) or may have a multiple quantum well structure (MQW structure).
  • the active layer 22 having a quantum well structure has a structure in which the well layer and the barrier layer are stacked in at least one layer, but as a combination of (a compound semiconductor forming the well layer and a compound semiconductor forming the barrier layer), (In y Ga (1-y ) N, GaN), (In y Ga (1-y) N, In z Ga (1-z) N) [ where, y> z], (In y Ga (1- y) N, AlGaN), (AlGaN / GaN), (AlzGa1 - zN / AlyGa1 -yN ) [where y> z] can be mentioned.
  • Each of the first semiconductor layer 21 and the second semiconductor layer 23 may be a layer having a single structure or a layer having a multilayer structure. Also, it may be a layer of a superlattice structure. Furthermore, it may be a layer provided with a composition gradient layer and a concentration gradient layer.
  • the first electrode 31 is provided on the surface opposite to the one surface of the substrate 11 on which the semiconductor layer 20 is formed.
  • the first electrode 31 is made of, for example, gold (Au), silver (Ag), palladium (Pd), platinum (Pt), nickel (Ni), Ti (titanium), vanadium (V), tungsten (W), chromium Cr), Al (aluminum), Cu (copper), Zn (zinc), tin (Sn), and a single layer film or laminated film including at least one metal (including an alloy) of indium (In) Is preferred.
  • a laminated film is mentioned. The layer closer to the “/” in the multilayer film structure is located closer to the active layer 22.
  • the transparent electrode 32 is provided on the semiconductor layer 20.
  • the transparent electrode 32 is provided in contact with the emission window 24 W of the second semiconductor layer 23 for emitting the light emitted from the active layer 22.
  • the transparent electrode 32 is formed of a so-called transparent conductive material having light transparency.
  • transparent conductive materials include, for example, indium-tin oxide (ITO, Indium Tin Oxide, Sn-doped In 2 O 3 , crystalline ITO and amorphous ITO), indium-zinc oxide (IZO, Indium) Zinc Oxide), IFO (F-doped In 2 O 3 ), tin oxide (SnO 2 ), ATO (Sb-doped SnO 2 ), FTO (F-doped SnO 2 ), zinc oxide (ZnO, Al-doped ZnO or B-doped ZnO is included.
  • a transparent conductive film having a gallium oxide, titanium oxide, niobium oxide, nickel oxide or the like as a base layer may be used.
  • the material constituting the transparent electrode 32 depends on the arrangement of the second reflective layer 42 and the transparent electrode 32 described later, but is not limited to the transparent conductive material, and palladium (Pd), platinum (Pt) And metals such as nickel (Ni), gold (Au), cobalt (Co) and rhodium (Rh).
  • the transparent electrode 32 may be made of at least one of these materials.
  • a second electrode 33 for electrically connecting to an external electrode or circuit is provided.
  • the second electrode 33 is, for example, a single layer film including at least one metal of Ti (titanium), aluminum (Al), Pt (platinum), Au (gold), Ni (nickel), and Pd (palladium). Or it is preferable that it is laminated film. Specifically, for example, laminated films of Ti / Pt / Au, Ti / Au, Ti / Pd / Au, Ti / Pd / Au, Ti / Ni / Au, Ti / Ni / Au / Cr / Au, etc. are listed. Be Although not provided here, a pad electrode may be appropriately provided also on the first electrode 31.
  • a cover metal layer (not shown) made of, for example, Ni / TiW / Pd / TiW / Ni is formed on the surface of the first electrode 31
  • a pad electrode made of a multilayer film of, for example, Ti / Ni / Au, Ti / Ni / Au / Cr / Au, etc. is formed on the cover metal layer.
  • a current confinement structure is formed between the semiconductor layer 20 (specifically, the second semiconductor layer 23) and the transparent electrode 32.
  • the current confinement structure is formed of, for example, the insulating film 24 provided on the second semiconductor layer 23.
  • the insulating film 24 has an opening 24A, and this opening becomes a current injection region in the semiconductor layer 20 (second semiconductor layer 23). At this time, the current injection region in the semiconductor layer 20 (second semiconductor layer 23) corresponds to the emission window 24H.
  • the insulating film 24 is formed of, for example, SiO x , SiN x or AlO x .
  • the current confinement structure does not necessarily have to be formed of the insulating film 24.
  • the mesa structure may be formed by etching the second semiconductor layer 23 by a reactive ion etching (RIE) method or the like, or a partial layer of the stacked second semiconductor layer 23 May be partially oxidized laterally to form a current confinement region.
  • an impurity may be ion-implanted into the second semiconductor layer 23 to form a region with reduced conductivity, or these may be combined as appropriate.
  • the transparent electrode 32 needs to be electrically connected to part of the second semiconductor layer 23 through which current flows due to current narrowing.
  • a plurality of dielectric multilayer films 41 are provided, for example, in the plane of the substrate 11, and are embedded in the first semiconductor layer 21.
  • a part of the plurality of dielectric multilayer films 41 provided on the substrate 11 has an end face in the same plane as the end face of the semiconductor layer 20 and is exposed to the side face of the semiconductor laser 1.
  • the dielectric multilayer film 41 is made of, for example, oxides such as Si, Mg, Al, Hf, Nb, Zr, Sc, Ta, Ga, Zn, Y, B, Ti, nitrides (for example, SiN x , AlN x , It is formed of AlGaN, GaN x , BN x or the like) or fluoride or the like.
  • SiO x , TiO x , NbO x , ZrO x , TaO x , ZnO x , AlO x , HfO x , SiN x , AlN x and the like can be mentioned.
  • the first reflective layer 41A functions as a Distributed Bragg Reflector (DBR) layer. It is preferable that the first reflective layer 41A has a configuration in which two or more types of dielectric films made of dielectric materials having different refractive indexes among the above-mentioned dielectric materials are alternately stacked. Thereby, the light reflection effect is obtained. Examples of combinations of two types of dielectric films include SiO x / SiN x , SiO x / NbO x , SiO x / ZrO x , SiO x / AlN x and the like. In order to obtain a desired light reflectance, the material, the film thickness, the number of laminations, etc. constituting each dielectric film may be appropriately selected.
  • DBR Distributed Bragg Reflector
  • each dielectric film can be appropriately adjusted according to the material to be used, etc., and is determined by the light emission wavelength ⁇ 0 and the refractive index n at the light emission wavelength ⁇ 0 of the material used. Specifically, it is preferable to use an odd multiple of ⁇ 0 / (4n).
  • the thickness of each dielectric film is preferably about 40 nm to 70 nm.
  • the number of stacked layers is preferably 5 or more, more preferably 15 or more.
  • the thickness of the entire dielectric multilayer film 41 is preferably, for example, 0.6 ⁇ m to 3.0 ⁇ m.
  • the dielectric multilayer film 41 is preferably arranged or arranged to grow laterally, for example, in the [1120] direction.
  • the planar shape of the dielectric multilayer film 41 is, for example, as shown in FIG. 2, lattice (rectangular) shape (A), polygonal shape including regular hexagon (B), circular shape including ellipse (C), stripe shape D) Or it is formed in island shape.
  • the cross-sectional shape of the dielectric multilayer film 41 may be rectangular as shown in FIG. 1 or may be trapezoidal. Further, as shown in FIG. 3, a part of the dielectric multilayer film 41 may be missing from the substrate 11.
  • the omission of the dielectric multilayer film 41 is caused by cracking or chipping of the dielectric multilayer film 41 at the time of cutting out by cleavage.
  • the dielectric multilayer film 41 is generated by the difference between the linear thermal expansion coefficient of the substrate 11 and the linear thermal expansion coefficient of the dielectric multilayer film 41.
  • a recess 21A is formed on the side face of the semiconductor layer 20.
  • the omission of the dielectric multilayer film 41 may be intentionally formed.
  • the second reflective layer 42 is provided at a position facing the first reflective layer 41A with the semiconductor layer 20 therebetween, and more specifically, provided on the transparent electrode 32. Similar to the dielectric multilayer film 41, the second reflective layer 42 is an oxide such as Si, Mg, Al, Hf, Nb, Zr, Sc, Ta, Ga, Zn, Y, B, Ti, nitride (for example, , SiN x , AlN x , AlGaN, GaN x , BN x, etc.) or fluoride or the like.
  • oxide such as Si, Mg, Al, Hf, Nb, Zr, Sc, Ta, Ga, Zn, Y, B, Ti, nitride (for example, , SiN x , AlN x , AlGaN, GaN x , BN x, etc.) or fluoride or the like.
  • the film thickness, the number of laminations, etc. may be appropriately selected in addition to the material constituting each dielectric film.
  • the thickness of each dielectric film can be appropriately adjusted according to the material to be used, etc., and is determined by the light emission wavelength ⁇ 0 and the refractive index n at the light emission wavelength ⁇ 0 of the material used. Specifically, it is preferable to use an odd multiple of ⁇ 0 / (4n).
  • the thickness of each dielectric film is preferably about 40 nm to 70 nm.
  • the number of layers is 2 or more, preferably 2 to 15.
  • the thickness of the entire dielectric multilayer film 41 is preferably, for example, 0.6 ⁇ m to 3.0 ⁇ m.
  • the semiconductor laser 1 of the present embodiment can be manufactured, for example, as follows.
  • a dielectric multilayer film 41X is formed. Specifically, it is formed by alternately laminating, for example, five layers of SiO x films and SiN x films on the substrate 11 by using any film forming method such as sputtering, CVD and evaporation. Subsequently, as shown in FIG. 4B, the dielectric multilayer film 41X is selectively etched to form a plurality of dielectric multilayer films 41 whose side surfaces are surrounded by the grooves 41H. In the etching step, wet etching with hydrofluoric acid or the like, dry etching using an RIE apparatus, or the like can be used.
  • the semiconductor layer 20 and the insulating film 24 are formed on the substrate 11 and the dielectric multilayer film 41.
  • the dielectric multilayer film 41 is used as a mask for selective growth, and the substrate 11 is placed in a metal organic chemical vapor deposition (MOCVD) apparatus and heated to a desired temperature.
  • MOCVD metal organic chemical vapor deposition
  • the semiconductor layer 20 including the first semiconductor layer 21 made of n-type GaN and the active layer (light emitting layer) 22 such as the second semiconductor layer 23 made of p-type GaN is grown.
  • TMGa trimethylgallium
  • TMAl trimethylaluminum
  • TMIn trimethylindium
  • SiH 4 silane
  • Mg p-type impurity
  • Cyclopentadienyl magnesium (Cp 2 Mg) is used as a raw material for ammonia
  • ammonia gas (NH 3 ) or the like is used as a nitrogen raw material.
  • the first semiconductor layer 21 is grown to 5 ⁇ m
  • the active layer 22 is grown to 80 nm
  • the second semiconductor layer 23 is grown to 100 nm.
  • a SiO 2 film is formed to a thickness of, for example, 200 nm using any film forming method such as sputtering, CVD and evaporation, and then selectively etched to form a current injection region.
  • An insulating film 24 having an opening 24A in which the semiconductor layer 23 is exposed is formed.
  • wet etching with hydrofluoric acid or the like, dry etching using an RIE apparatus, or the like can be used.
  • the area of the current injection region is equal to or less than half of the area of the opposing dielectric multilayer film 41 (first reflective layer 41A), and is, for example, about 25 ⁇ m 2 .
  • the transparent electrode 32, the 2nd electrode 33, and the 2nd reflection layer 42 are formed.
  • an ITO film is formed using any film forming method such as sputtering, CVD and evaporation, and then selectively etched to form a transparent electrode 32 having a desired shape.
  • wet etching using hydrochloric acid or the like, dry etching using a reactive ion etching apparatus, or the like can be used.
  • Au, Pt and Ti are formed in this order using any film forming method such as sputtering, CVD and evaporation, and then selectively etched to form Ti / Pt only in the desired part.
  • the second electrode 33 is formed leaving the / Au film.
  • wet etching with an acid or the like dry etching using a reactive ion etching apparatus or the like, lift-off by a PR method, or the like can be used.
  • a dielectric multilayer film in which, for example, five layers of SiO x films and SiN x films are alternately laminated is formed using any film forming method such as sputtering, CVD and evaporation, for example, selective To form a second reflective layer 42 having a desired shape.
  • wet etching with hydrofluoric acid or the like, dry etching using an RIE apparatus, or the like can be used.
  • the substrate 11 is ground and polished from the back surface side, and then the first electrode 31 is deposited.
  • the element is cut out from the substrate 11 by cleavage or the like. At this time, it cuts out so that the dielectric multilayer film 41 may be traversed. Thereby, the semiconductor laser 1 shown in FIG. 1 is completed.
  • the plurality of dielectric multilayer films 41, the first semiconductor layer 21, the active layer 22, the second semiconductor layer 23, the transparent electrode 32 and the second reflective layer 42 are formed on one surface of the substrate 11.
  • the first electrode 31 is formed on the other surface of the substrate 11 stacked in this order and facing one surface of the substrate 11.
  • a current injection region for enhancing the current injection efficiency to the active layer 22 and reducing the threshold current.
  • a current narrowing structure (an opening 24A of the insulating film 24) is provided to narrow the width.
  • the current injected from the first electrode 31 and the transparent electrode 32 is narrowed by the current narrowing structure and then injected into the active layer 22. This causes light emission due to recombination of electrons and holes. This light is reflected by the first reflection layer 41A and the second reflection layer 42, and laser oscillation occurs at a predetermined wavelength, and is emitted as laser light to the outside through the first reflection layer 41A or the second reflection layer 42. .
  • the exposed surface or the recess 21A of the dielectric multilayer film 41 is provided on the side surface of the first semiconductor layer 21 on the substrate 11.
  • the exposed surface of the dielectric multilayer film 41 provided on the side surface of the first semiconductor layer 21 has a smaller density of dangling bonds than that of the first semiconductor layer 21, and these are stacked in multiple layers to form the side surface of the semiconductor laser 1. And multiple interfaces are formed. Thereby, it becomes possible to control the covering area of the side surface of the semiconductor laser 1 by the solder used at the time of mounting.
  • the recess 21A is formed by a crack or a chip at the time of cutting out by cleavage, or a drop of the dielectric multilayer film 41 due to a difference in linear expansion coefficient between the substrate 11 and the dielectric multilayer film 41. Also by this recess 21A, the covering area of the side surface of the semiconductor laser 1 by the solder used at the time of mounting is controlled, specifically, the rising of the solder is reduced.
  • the semiconductor laser 1 it is possible to suppress the rise of the solder and to reduce the occurrence of the leak failure while enhancing the heat removal efficiency by the coating of the solder.
  • FIG. 6 illustrates an example of a cross-sectional configuration of a surface-emitting semiconductor element (LED 2) according to a second embodiment of the present disclosure.
  • the LED 2 has a substrate 11 and a plurality of dielectric multilayer films 61 in contact with the surface S 1 of the substrate 11. A plurality of dielectric multilayer films 61 are provided on the substrate 11 at intervals.
  • the LED 2 further has a configuration in which the semiconductor layer 20, the transparent electrode 52, and the n-type electrode 53 are stacked in this order.
  • Each dielectric multilayer film 61 is embedded by the first semiconductor layer 21 of the semiconductor layer 20, and the side surface of the one or more dielectric multilayer films 61 is exposed on the side surface of the first semiconductor layer 21.
  • At least one dielectric multilayer film 61 is formed on the side surface of the first semiconductor layer 21. Furthermore, at least one recess 21A is formed on the side surface of the first semiconductor layer 21.
  • the LED 2 has a p-type electrode 51 in contact with the surface S 2 (surface facing the surface S 1) of the substrate 11.
  • the semiconductor laser 1 shown in FIG. 6 is schematically shown, and is different from the actual size.
  • the p-type electrode 51 is provided on the surface opposite to the one surface of the substrate 11 on which the semiconductor layer 20 is formed.
  • the p-type electrode 51 is made of, for example, gold (Au), silver (Ag), palladium (Pd), platinum (Pt), nickel (Ni), Ti (titanium), vanadium (V), tungsten (W), chromium Cr), Al (aluminum), Cu (copper), Zn (zinc), tin (Sn), and a single layer film or laminated film including at least one metal (including an alloy) of indium (In) Is preferred.
  • the laminated film for example, Ti / Au, Ti / Al, Ti / Al / Au, Ti / Pt / Au, Ni / Au, Ni / Au / Pt, Ni / Pt, Pd / Pt, Ag / Pd, etc. It can be mentioned.
  • the transparent electrode 52 is provided, for example, on the upper surface of the semiconductor layer 20 (the surface of the second semiconductor layer 23), and is formed of a so-called transparent conductive material having light transparency.
  • Specific transparent conductive materials include, for example, indium-tin oxide (ITO, Indium Tin Oxide, Sn-doped In 2 O 3 , crystalline ITO and amorphous ITO), indium-zinc oxide (IZO, Indium Zinc Oxide, IFO (F-doped In 2 O 3 ), tin oxide (SnO 2 ), ATO (Sb-doped SnO 2 ), FTO (F-doped SnO 2 ), zinc oxide (ZnO, Al-doped ZnO And B-doped ZnO).
  • a transparent conductive film having a gallium oxide, titanium oxide, niobium oxide, nickel oxide or the like as a base layer may be used.
  • the n-type electrode 53 is provided on a part of the transparent electrode 52.
  • the n-type electrode 53 is, for example, a single layer film including at least one metal of Ti (titanium), aluminum (Al), Pt (platinum), Au (gold), Ni (nickel), and Pd (palladium). Or it is preferable that it is a laminated film.
  • the laminated film include Ti / Pt / Au, Ti / Au, Ti / Pd / Au, Ti / Pd / Au, Ti / Ni / Au, Ti / Ni / Au / Cr / Au, and the like.
  • a plurality of dielectric multilayer films 61 are provided, for example, in the plane of the substrate 11 as in the case of the dielectric multilayer film 41 in the above-described embodiment, and are embedded in the first semiconductor layer 21.
  • the dielectric multilayer film 61 has a function of reflecting the light emitted from the active layer 22 to the transparent electrode 52 side.
  • a part of the plurality of dielectric multilayer films 61 provided on the substrate 11 has the same end face as the semiconductor layer 20 and is exposed to the side face of the LED 2.
  • the dielectric multilayer film 61 is, for example, an oxide or nitride such as Si, Mg, Al, Hf, Nb, Zr, Sc, Ta, Ga, Zn, Y, B, Ti, etc.
  • SiN x , AlN x It is formed of AlGaN, GaN x , BN x or the like
  • fluoride or the like e.g, SiO x , TiO x , NbO x , ZrO x , TaO x , ZnO x , AlO x , HfO x , SiN x , AlN x and the like can be mentioned.
  • the dielectric multilayer film 61 does not necessarily have to alternately laminate two or more types of dielectric films made of dielectric materials having different refractive indexes among the above-mentioned dielectric materials, but, for example, SiN x or TaO x
  • the light extraction efficiency is improved by alternately laminating a high refractive index material and a low refractive index material such as SiO x .
  • Specific combinations of dielectric materials include SiO x / NbO x , SiO x / ZrO x , SiO x / AlN x and the like in addition to SiO x / SiN x .
  • the thickness of each dielectric film is preferably about 40 nm to 70 nm.
  • the number of stacked layers is preferably 5 or more, more preferably 15 or more.
  • the thickness of the entire dielectric multilayer film 61 is preferably, for example, 0.6 ⁇ m to 3.0 ⁇ m.
  • the dielectric multilayer film 61 is preferably arranged or arranged to grow laterally, for example, in the [1120] direction.
  • the planar shape of the dielectric multilayer film 61 is formed, for example, in a lattice (rectangular) shape, a polygonal shape including a regular hexagon, a circular shape including an ellipse, a stripe shape, or an island shape as in the above embodiment.
  • the cross-sectional shape of the dielectric multilayer film 61 may be rectangular as shown in FIG. 6 or may be trapezoidal.
  • the LED 2 can be manufactured, for example, as follows, using a method similar to that of the above embodiment.
  • the dielectric multilayer film 61 and the semiconductor layer 20 are formed on the substrate 11, and then the transparent electrode 52 and the n-type electrode 53 are formed.
  • ITO is formed into a film by any film forming method such as sputtering, CVD and vapor deposition, and then selectively etched to form a transparent electrode 52 having a desired shape.
  • etching step wet etching using hydrochloric acid or the like, dry etching using a reactive ion etching apparatus, or the like can be used.
  • Au, Pt and Ti are formed in this order using any film forming method such as sputtering, CVD and evaporation, and then Ti / Pt / only in desired portions by the PR step and the etching step.
  • An n-type electrode 53 is formed leaving the Au film.
  • wet etching with an acid or the like, dry etching using a reactive ion etching apparatus or the like, lift-off by a PR method, or the like can be used.
  • the substrate 11 is ground and polished from the back surface side, and then the p-type electrode 51 is deposited. Finally, the element is cut out from the substrate 11 by cleavage or the like. At this time, the LED 2 shown in FIG. 6 is completed by cutting out so as to cross the dielectric multilayer film 61.
  • FIGS. 7A and 7B show the semiconductor laser 1 according to the first embodiment mounted on a heat sink.
  • the structure of the semiconductor laser 1 is shown in a simplified manner.
  • the semiconductor laser 1 shown in FIG. 7A is junction-up mounted on the heat sink 101 via the solder 102, and the bonding wire 104 is connected to the second electrode 33 via the solder 103.
  • the semiconductor laser 1 shown in FIG. 7B is junction-down mounted on the heat sink 101 via the solder 102, and the bonding wire 104 is connected to the first electrode 31 via the solder 103.
  • the first electrode 31 is provided with the opening 31A, and the opening 31A serves as an emission window.
  • the ascend of the solder 102 in the junction-up mounting is different from that of the solder 103 in the junction-down mounting. It is possible to prevent by the exposed one or more dielectric multilayer films 41 and the one or more recesses 21A.
  • FIGS. 8A and 8B show the LED 2 of the second embodiment mounted on a heat sink.
  • the LED 2 shown in FIG. 8A is junction-up mounted on the heat sink 101 via the solder 102, and the bonding wire 104 is connected to the second electrode 33 via the solder 103.
  • the LED 2 shown in FIG. 8B is junction-down mounted on the heat sink 101 via the solder 102, and the bonding wire 104 is connected to the p-type electrode 51 via the solder 103.
  • the laser light is emitted from the side of the substrate 11, so the p-type electrode 51 is provided with the opening 51A, and the opening 31A serves as the emission window.
  • the rise of the solder 102 in the junction-up mounting is the junction-down mounting. It is possible to prevent the lowering of the solder 103 by the one or more dielectric multilayer films 61 and the one or more recesses 21A exposed on each side surface of the semiconductor layer 20.
  • both of the dielectric multilayer film 41 (or the dielectric multilayer film 61) and the recess 21A are formed on the side surface of the semiconductor layer 20, respectively.
  • only the recess 21A or only the dielectric multilayer film 41 (or the dielectric multilayer film 61) may be provided.
  • the present technology can also be configured as follows. (1) A first semiconductor layer, An active layer provided on the first semiconductor layer; And a second semiconductor layer provided on the active layer and having an emission window for emitting light emitted from the active layer. A nitride semiconductor device, wherein at least one recess or a first dielectric multilayer film is formed on a side surface of the first semiconductor layer or the second semiconductor layer. (2) The semiconductor device further includes an element formation substrate of the first semiconductor layer provided in contact with the first semiconductor layer, The nitride semiconductor device according to (1), wherein at least one of the recess or the first dielectric multilayer film is formed on a side surface of the first semiconductor layer.
  • the nitride semiconductor device according to (2) wherein one or more of the first dielectric multilayer films are embedded in the first semiconductor layer.
  • a second dielectric provided at a position facing the one first dielectric multilayer film embedded in the first semiconductor layer with the first semiconductor layer, the active layer, and the second semiconductor layer in between.
  • the nitride semiconductor device according to (3) further comprising a body multilayer film.
  • (6) The nitride semiconductor device according to any one of (1) to (5), wherein a plurality of the recesses are formed on each side surface of the first semiconductor layer.
  • the nitride semiconductor device according to any one of (1) to (6), wherein the first semiconductor layer, the active layer, and the second semiconductor layer are made of a GaN-based compound semiconductor.
  • GaN gallium nitride
  • InGaN indium gallium nitride
  • Si silicon

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)
  • Led Device Packages (AREA)

Abstract

Selon un mode de réalisation de l'invention, un élément semi-conducteur au nitrure est équipé : d'une première couche semi-conductrice ; d'une couche active agencée sur la première couche semi-conductrice ; et d'une seconde couche semi-conductrice agencée sur la couche active, et possédant une fenêtre d'émission en sortie par laquelle une lumière générée par la couche active est émise en sortie. Un retrait et/ou un film multicouche diélectrique est formé sur une face latérale de la première ou de la seconde couche semi-conductrice.
PCT/JP2016/073883 2015-09-02 2016-08-16 Élément semi-conducteur au nitrure WO2017038448A1 (fr)

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KR20230117793A (ko) * 2022-02-03 2023-08-10 삼성전기주식회사 적층형 전자 부품

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59145055U (ja) * 1983-03-18 1984-09-28 三洋電機株式会社 半導体レ−ザ用ヒ−トシンク
JP2000022282A (ja) * 1998-07-02 2000-01-21 Fuji Xerox Co Ltd 面発光型発光素子及びその製造方法
JP2002217451A (ja) * 2001-01-18 2002-08-02 Dowa Mining Co Ltd 発光ダイオード及びその製造方法
WO2008018482A1 (fr) * 2006-08-11 2008-02-14 Sanyo Electric Co., Ltd. Élément semi-conducteur et son procédé de fabrication
JP2011520272A (ja) * 2008-05-08 2011-07-14 ウニヴェルズィテート・ウルム 最適化された性質を有する表面実装のための全自動調節された表面放射半導体レーザー
JP2014175565A (ja) * 2013-03-12 2014-09-22 Ushio Inc 半導体レーザ装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59145055U (ja) * 1983-03-18 1984-09-28 三洋電機株式会社 半導体レ−ザ用ヒ−トシンク
JP2000022282A (ja) * 1998-07-02 2000-01-21 Fuji Xerox Co Ltd 面発光型発光素子及びその製造方法
JP2002217451A (ja) * 2001-01-18 2002-08-02 Dowa Mining Co Ltd 発光ダイオード及びその製造方法
WO2008018482A1 (fr) * 2006-08-11 2008-02-14 Sanyo Electric Co., Ltd. Élément semi-conducteur et son procédé de fabrication
JP2011520272A (ja) * 2008-05-08 2011-07-14 ウニヴェルズィテート・ウルム 最適化された性質を有する表面実装のための全自動調節された表面放射半導体レーザー
JP2014175565A (ja) * 2013-03-12 2014-09-22 Ushio Inc 半導体レーザ装置

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