WO2017033950A1 - Substrat de circuit électronique - Google Patents

Substrat de circuit électronique Download PDF

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Publication number
WO2017033950A1
WO2017033950A1 PCT/JP2016/074586 JP2016074586W WO2017033950A1 WO 2017033950 A1 WO2017033950 A1 WO 2017033950A1 JP 2016074586 W JP2016074586 W JP 2016074586W WO 2017033950 A1 WO2017033950 A1 WO 2017033950A1
Authority
WO
WIPO (PCT)
Prior art keywords
inductor
electronic circuit
capacitor
circuit board
closed conductor
Prior art date
Application number
PCT/JP2016/074586
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English (en)
Japanese (ja)
Inventor
達也 福永
Original Assignee
Tdk株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tdk株式会社 filed Critical Tdk株式会社
Priority to JP2017536450A priority Critical patent/JPWO2017033950A1/ja
Publication of WO2017033950A1 publication Critical patent/WO2017033950A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02—Mountings
    • H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components

Definitions

  • the present invention relates to an electronic circuit board.
  • a CPU main processing unit
  • the operating voltage tends to decrease in order to reduce the power consumption.
  • a large current fluctuation noise current
  • a multilayer capacitor as a smoothing capacitor is arranged around the CPU so as to be connected to a power supply, and is frequently used as a countermeasure for stabilizing the power supply.
  • the current is supplied from the multilayer capacitor to the CPU by quick charge / discharge when the current fluctuates at a high speed, thereby suppressing the voltage fluctuation of the power source.
  • ESL Equivalent Series Inductance
  • Patent Document 1 Patent Document 2, or Patent Document 3
  • the internal electrodes and the side terminals are arranged so that the currents flowing in the adjacent terminal electrodes are opposite to each other.
  • a multilayer capacitor has been proposed in which the mutual inductance is made negative, the parasitic inductor component of the capacitor is reduced, and low ESL is realized.
  • an object of the present invention is to provide an electronic circuit board that can reduce an equivalent series inductance that is a parasitic inductance of a capacitor or an inductance of wiring of a mounting board.
  • the electronic circuit board of the present invention includes a mounting board having a DC power supply layer and a ground layer, and a capacitor, and the capacitor is connected to the DC power supply layer and the ground layer via wiring and mounted on the mounting board.
  • a first inductor that is a parasitic inductor component of the capacitor and a second inductor that is an inductor component of the wiring are connected in series, and at least one of the first inductor and the second inductor is magnetically connected. It has a closed conductor loop to be coupled.
  • At least one of the first inductor and the second inductor is magnetically coupled to the closed conductor loop, so that the first inductor and the second inductor can be coupled according to Faraday's law.
  • a counter electromotive force is generated in the closed conductor loop so as to prevent the time fluctuation of the magnetic flux corresponding to at least one of the inductances.
  • the closed conductor loop is configured by a wiring pattern formed inside the mounting board or on the surface of the mounting board.
  • the closed conductor loop is configured by the wiring pattern in the mounting board, thereby mainly preventing the time fluctuation of the magnetic flux corresponding to the inductance of the second inductor which is the inductor component of the wiring.
  • the inductance (equivalent series inductance) of the wiring of the mounting board can be mainly reduced.
  • a part of the closed conductor loop is one of the DC power supply layer and the ground layer.
  • unnecessary wiring can be reduced by using either the DC power supply layer or the ground layer as a part of the closed conductor loop.
  • a component having a conductor pattern is mounted on the mounting board, and at least a part of the closed conductor loop is the conductor pattern.
  • At least a part of the closed conductor loop is a conductor pattern of a component mounted on the mounting board, so that the inductance of the first inductor that is a parasitic inductor component of the capacitor is mainly used. Can be prevented, and the parasitic inductance (equivalent series inductance) of the capacitor can be mainly reduced.
  • the capacitor and the component are integrally formed.
  • the capacitor and the part having the conductor pattern that is at least a part of the closed conductor loop are integrally formed, whereby the first inductor that is the parasitic inductor component of the capacitor is It can be coupled to the closed conductor loop with a magnetically large coupling coefficient.
  • the parasitic inductance (equivalent series inductance) of the capacitor can be greatly reduced.
  • the electronic circuit board of the present invention preferably has a plurality of the closed conductor loops.
  • the electronic circuit board which can reduce the equivalent series inductance of the wiring of a capacitor
  • FIG. 1 is a perspective view of an electronic circuit board according to a first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view taken along line AA in FIG. 9 is a cross-sectional view taken along line BB in FIG. 1 or a cross-sectional view taken along line DD in FIG.
  • FIG. 12 is a cross-sectional view of the part cut along line EE in FIG. 11.
  • FIG. 12 is a cross-sectional view of a part cut along line FF in FIG. 11.
  • FIG. 1 is a perspective view showing a configuration example of an electronic circuit board 1 according to the first embodiment of the present invention
  • FIG. 2 is a cross-sectional view taken along line AA of FIG.
  • FIG. 3 is a sectional view taken along line BB in FIG.
  • the electronic circuit board 1 includes a mounting substrate 111 having a ground layer 101 and a DC power supply layer 102 and a capacitor 104
  • the capacitor 104 includes the ground layer 101 and the DC power supply layer 102.
  • the capacitor 104 includes the ground layer 101 and the DC power supply layer 102.
  • the capacitor 104 has a plurality of first internal electrodes 1041 and a plurality of second internal electrodes 1042, and each first internal electrode 1041 and each second internal electrode 1042 are stacked via a dielectric 1043. ing.
  • the capacitor 104 includes a first terminal electrode 1044 and a second terminal electrode 1045.
  • the plurality of first internal electrodes 1041 are connected to the first terminal electrode 1044, and the plurality of second internal electrodes 1042 are The second terminal electrode 1045 is connected.
  • the first terminal electrode 1044 is connected to the ground layer 101 through the wiring 103a, and the second terminal electrode 1045 is connected to the DC power supply layer 102 through the wiring 103b.
  • the capacitor 104 (capacitance component thereof) and the first inductor 301 that is a parasitic inductor component of the capacitor 104 and the wiring 103a. , 103b, the second inductor 302, which is the inductor component, is connected in series.
  • the first internal electrode 1041 and the second internal electrode 1042 is drawn for short.
  • the electronic circuit board 1 has a wiring pattern 105 formed on the surface of the mounting board 111.
  • the electronic circuit board 1 has a closed conductor loop 110 formed by connecting both ends of the wiring pattern 105 to the DC power supply layer 102 via wirings 103 c and 103 d formed inside the mounting substrate 111.
  • the equivalent circuit of the closed conductor loop 110 is represented by connecting an inductor 303, which is an inductor component of the closed conductor loop 110, and a resistor 304, which is a resistance component, in series in a loop shape.
  • the inductor 303 of the closed conductor loop 110 is mainly composed of the second inductor 302 that is an inductor component of the wirings 103a and 103b. , Coupled through the generated magnetic field. Due to this coupling, a counter electromotive force is generated in the closed conductor loop 110 so as to prevent the time fluctuation of the magnetic flux generated by the noise current passing through the wirings 103a and 103b according to Faraday's law (the closed circuit loop 110 is generated by this counter electromotive force).
  • the magnetic flux generated by the eddy current generated in the circuit is generated so as to prevent the time fluctuation of the magnetic flux generated by the noise current passing through the wirings 103a and 103b).
  • the inductance (equivalent series inductance) of the second inductor 302 that is the inductor component of the wirings 103a and 103b can be mainly reduced.
  • the inductance L is defined by the following formula (1) using the current I, the magnetic flux density B, the area S, and the time t. Considering this definition, the inductance is proportional to the time variation of the magnetic flux B ⁇ dS. Therefore, the inductance can be reduced by suppressing the time variation of the generated magnetic flux.
  • FIG. 4 shows a loop conductor 201 which is a closed conductor.
  • the magnetic flux 202 penetrating the inside of the loop of the loop conductor 201 is generated, an electromotive force is generated in a direction that cancels the generated magnetic flux 202 according to Faraday's law, an eddy current 204 flows in the loop conductor 201, and is opposite to the magnetic flux 202.
  • Directional magnetic flux 203 is generated, and temporal fluctuation of the magnetic flux is suppressed.
  • a closed conductor loop 110 is formed by connecting both ends of the wiring pattern 105 to the DC power supply layer 102 via wirings 103c and 103d.
  • an electromotive force is generated in a direction that prevents an increase in magnetic flux generated by the flow of the noise current 108, and an eddy current 107 opposite to the noise current 108 flows through the closed conductor loop 110. This prevents the time fluctuation of the magnetic flux generated by.
  • the equivalent series inductance of the second inductor 302 that is the inductor component of the wirings 103a and 103b of the mounting substrate 111 is reduced. be able to.
  • the electronic circuit board 1 includes the mounting substrate 111 having the DC power supply layer 102 and the ground layer 101, and the capacitor 104.
  • the first inductor 301 which is the parasitic inductor component of the capacitor 104
  • the second inductor 302 which is the inductor component of the wirings 103a and 103b, are connected in series, and are mounted on the mounting substrate 111. Since the closed conductor loop 110 magnetically coupled to the inductor 302 is provided, the magnetic flux coupling corresponding to the inductance of the second inductor 302 is obtained by Faraday's law by magnetically coupling the second inductor 302 and the closed conductor loop 110. Back electromotive force is generated in closed conductor loop 110 to prevent time fluctuation That. Thereby, the equivalent series inductance which is the inductance of the wirings 103a and 103b of the mounting substrate 111 can be reduced.
  • the closed conductor loop 110 is configured by wiring patterns (wirings 103 c and 103 d, the wiring pattern 105 and the DC power supply layer 102) formed inside the mounting board 111 or on the surface of the mounting board 111. Therefore, the time variation of the magnetic flux corresponding to the inductance of the second inductor 302 which is the inductor component of the wirings 103a and 103b is prevented, and the inductance (equivalent series inductance) of the wirings 103a and 103b of the mounting substrate 111 is mainly used. Can be reduced.
  • a part of the closed conductor loop 110 is the DC power supply layer 102, and therefore, unnecessary wiring can be reduced by using the DC electrode layer 102 as a part of the closed conductor loop 110.
  • FIG. 5 shows an equivalent circuit example of the electronic circuit board 1 when the closed conductor loop 110 and the second inductor 302 by the wirings 103a and 103b are magnetically coupled.
  • This equivalent circuit example is equivalent to a capacitor 104 connected in series between the DC power supply layer 102 and the ground layer 101, a first inductor 301 that is a parasitic inductor of the capacitor 104, and wirings 103 a and 103 b of the mounting substrate 111.
  • This is a resistance component of a closed conductor loop 110 formed by a circuit in which a second inductor 302 that is a series inductor component is connected in series, the wiring pattern 105, the wirings 103c and 103d of the mounting substrate 111, and the DC power supply layer 102.
  • a circuit in which a resistor 304 and an inductor 303 that is an inductor component of the closed conductor loop 110 are connected in series, and the second inductor 302 and the inductor 303 of the closed conductor loop 110 are coupled with a coupling coefficient k. is there.
  • the capacitance of the capacitor 104 is 1 ⁇ F
  • the inductance of the first inductor 301 is 100 pH
  • the inductance of the second inductor 302 is 100 pH
  • the inductance of the inductor 303 of the closed conductor loop 110 is 1 pH
  • the resistance value of the resistor 304 FIG.
  • the wiring pattern 105 formed on the surface of the mounting substrate 111 constitutes a part of the closed conductor loop 110, but the wiring pattern 105 may be formed inside the mounting substrate 111. good.
  • both ends of the wiring pattern 105 are connected to the DC power supply layer 102 via the wirings 103c and 103d to form the closed conductor loop 110.
  • the both ends of 105 may be formed by being connected to the ground layer 101 via wiring formed inside the mounting substrate 111. Even in this case, the same effect as the electronic circuit board 1 of the first embodiment can be obtained. Further, as in the electronic circuit board 2 shown in FIG.
  • the closed conductor loop 110 is configured such that both ends of the wiring pattern 105 are connected to the ground layer 101 and the DC power source via the wirings 103 e and 103 f formed inside the mounting substrate 111. It may be formed by being connected to an independent wiring pattern 109 that is not connected to the layer 102.
  • FIG. 7 is a cross-sectional view of the electronic circuit board 2 corresponding to the cross-sectional view of the electronic circuit board 1 shown in FIG. As long as the closed conductor loop is formed, the eddy current 107 generated by Faraday's law can reduce the equivalent series inductance that is the inductance of the wiring of the mounting board.
  • the electronic circuit board 1 having one closed conductor loop 110 is described. However, even if there are a plurality of closed conductor loops coupled to the second inductor 302 through a generated magnetic field. Good. For example, two closed conductor loops may be formed so as to sandwich a place where the capacitor 104 is mounted. ⁇ Second Embodiment>
  • FIG. 8 is a perspective view showing an overall configuration example of the electronic circuit board 3 according to the second embodiment of the present invention.
  • the electronic circuit board 3 will be described mainly with respect to differences from the electronic device 1 of the first embodiment, and description of common matters will be omitted as appropriate. Elements common to the electronic device 1 of the first embodiment are denoted by the same reference numerals, and description of the common elements is omitted.
  • the electronic circuit board 3 is mounted on the surface of the mounting board 111 with the capacitor 104 connected to the ground layer 101 and the power supply layer 102 via the wirings 103 a and 103 b of the mounting board 111. ing.
  • a component 112 having a conductor pattern 305 is mounted on the surface of the mounting board 111.
  • two components 112 are mounted on the surface of the mounting board 111 with the capacitor 104 interposed therebetween.
  • FIG. 9 is a cross-sectional view taken along the line CC of FIG.
  • the component 112 has a conductor pattern 305 as shown in FIGS.
  • a dielectric 3043 is formed around the conductor pattern 305.
  • the electronic circuit board 3 has a closed conductor loop 310 formed by connecting both ends of the conductor pattern 305 to the DC power supply layer 102 via the wirings 103 g and 103 h of the mounting board 111. Have two.
  • the equivalent circuit of the closed conductor loop 310 is represented by connecting an inductor 313 that is an inductor component of the closed conductor loop 310 and a resistor 304 that is a resistance component in series in a loop shape.
  • the closed conductor loop 310 is generated with the first inductor 301 that is a parasitic inductor of the capacitor 104 and the second inductor 302 that is an equivalent series inductor of the wirings 103 a and 103 b of the mounting substrate 111 connected to the capacitor 104. Coupling through a magnetic field.
  • a cross-sectional view taken along the line DD in FIG. 8 can be represented in FIG. 3 as in the first embodiment.
  • the noise current 108 flows through the capacitor 104 through the wirings 103a and 103b and flows into the ground layer 101.
  • an electromotive force is generated in a direction that prevents an increase in magnetic flux generated by the flow of the noise current 108, and an eddy current 107 opposite to the noise current 108 flows in the closed conductor loop 310. This prevents time fluctuations of the generated magnetic flux.
  • the magnetic flux generated by the eddy current 107 cancels the magnetic flux generated by the noise current 108 inside the capacitor 104 and inside the mounting substrate 111, so that the first inductor 301, which is a parasitic inductor of the capacitor 104, and the wiring of the mounting substrate 111.
  • Both of the equivalent series inductances of the second inductor 302, which are the inductor components 103a and 103b, can be reduced.
  • FIG. 10 shows an equivalent circuit example for the electronic circuit board 3.
  • This equivalent circuit example is equivalent to a capacitor 104 connected in series between the DC power supply layer 102 and the ground layer 101, a first inductor 301 that is a parasitic inductor of the capacitor 104, and wirings 103 a and 103 b of the mounting substrate 111.
  • This is a resistance component of a closed conductor loop 310 formed by a circuit in which a second inductor 302 that is a series inductor component is connected in series, a conductor pattern 305, wirings 103g and 103h of a mounting substrate 111, and a DC power supply layer 102.
  • the electronic circuit board 3 is formed with a plurality of closed conductor loops 310, it is possible to obtain a greater effect of reducing the equivalent series inductance.
  • the larger the coupling coefficient between the closed conductor loop 310 and the first inductor 301 or the second inductor 302 (closer to 1) the more the equivalent series inductance becomes.
  • the effect of reducing becomes large, in reality, it is difficult to set the coupling coefficient to 1.
  • By having the plurality of closed conductor loops 310 even if the coupling coefficient between each closed conductor loop 310 and the first inductor 301 or the second inductor 301 is smaller than 1, it is generated in each closed conductor loop 310. By adding the effects of the back electromotive force, it is possible to obtain a greater reduction effect of the equivalent series inductance.
  • the closed conductor loop 310 may be formed by connecting both ends of the conductor pattern 305 to the ground layer 101 via wiring formed inside the mounting substrate 111.
  • the closed conductor loop 310 is connected at both ends of the conductor pattern 305 to independent wiring patterns that are not connected to the ground layer 101 or the DC power supply layer 102 via wiring formed inside the mounting substrate 111. It may be formed by this.
  • the closed conductor loop 310 is formed by connecting both ends of the wiring pattern 305 to independent wiring patterns that are not connected to the ground layer 101 or the DC power supply layer 102, and the independent wiring patterns are formed on the mounting substrate. It may be formed on the surface of 111 or inside the component 112. In this case, the parasitic inductance (equivalent series inductance) of the capacitor 104 can be mainly reduced.
  • FIG. 11 is a perspective view showing a configuration example of an electronic circuit board 4 according to the third embodiment of the present invention.
  • the electronic circuit board 4 will be described mainly with respect to differences from the electronic circuit board 3 of the second embodiment, and description of common matters will be omitted as appropriate. Elements common to the electronic circuit board 3 of the second embodiment are denoted by the same reference numerals, and description of the common elements is omitted.
  • the component having the conductor pattern 305 and the capacitor 104 are integrally formed in place of the capacitor 104 and the two components 112 having the conductor pattern 305 in the electronic circuit substrate 3 of the second embodiment.
  • the component 411 is mounted on the surface of the mounting substrate 111. In the electronic circuit board 4 shown in FIG. 11, the component 411 shows an example having one conductor pattern 305.
  • FIG. 12 is an exploded perspective view of the part 411
  • FIG. 13 is a sectional view of the part 411 cut along the line EE in FIG. 11
  • FIG. 14 is a part cut along the line FF in FIG. FIG.
  • the first internal electrodes 1041 and the second internal electrodes 1042 are alternately stacked with the dielectric 1043 interposed therebetween, and the conductor pattern 305 is connected to the first internal electrodes via the dielectric 1043.
  • 1041 and the second internal electrode 1042 are arranged apart from each other.
  • the conductor pattern 305 is arranged so that at least a part of the conductor pattern 305 overlaps with the first internal electrode 1041 and the second internal electrode 1042 when viewed from the stacking direction of the first internal electrode 1041 and the second internal electrode 1042. Yes.
  • the other points are the same as those of the electronic circuit board 3 of the second embodiment.
  • the component 411 in which the capacitor 104 and the component having the conductor pattern 305 that is a part of the closed conductor loop 310 are integrally formed is formed on the mounting substrate 111, so that the parasitic inductor of the capacitor 104 is formed.
  • the first inductor 301 as a component can be coupled to the closed conductor loop 310 with a magnetically large coupling coefficient. Thereby, the parasitic inductance (equivalent series inductance) of the capacitor 104 can be greatly reduced.
  • the electronic circuit boards of the first to third embodiments described above may be used as a power supply module board such as a DC-DC converter, or a board used in a set of a smartphone, a PC, a notebook PC, or the like. It may be used as a board such as a graphic board, a microcomputer board, a memory board, and a PCI Express board.
  • a power supply module board such as a DC-DC converter, or a board used in a set of a smartphone, a PC, a notebook PC, or the like. It may be used as a board such as a graphic board, a microcomputer board, a memory board, and a PCI Express board.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

L'invention fournit un substrat de circuit électronique permettant de réduire l'inductance parasite d'un condensateur, ou une inductance série équivalente consistant en l'inductance d'un câble d'un substrat de montage. Le substrat de circuit électronique (1) de l'invention possède un substrat de montage (111) possédant une couche alimentation en courant continu ainsi qu'une couche de mise à la terre, et un condensateur (104). Le condensateur (104) est connecté à la couche alimentation en courant continu et à la couche de mise à la terre par l'intermédiaire de câbles (103a, 103b), et est monté sur le substrat de montage (111). Une première bobine inductrice constituant un composant bobine inductrice parasite du condensateur (104), et une seconde bobine inductrice constituant un composant bobine inductrice des câbles (103a, 103b), sont connectées en série. Enfin, le substrat de circuit électronique (1) est caractéristique en ce qu'il possède une boucle conductrice fermée magnétiquement liée à la première bobine inductrice et/ou la seconde bobine inductrice.
PCT/JP2016/074586 2015-08-26 2016-08-24 Substrat de circuit électronique WO2017033950A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2017536450A JPWO2017033950A1 (ja) 2015-08-26 2016-08-24 電子回路基板

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015166362 2015-08-26
JP2015-166362 2015-08-26

Publications (1)

Publication Number Publication Date
WO2017033950A1 true WO2017033950A1 (fr) 2017-03-02

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PCT/JP2016/074586 WO2017033950A1 (fr) 2015-08-26 2016-08-24 Substrat de circuit électronique

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06349678A (ja) * 1993-06-07 1994-12-22 Tdk Corp 貫通型コンデンサ及びそれを用いた電子装置並びに貫通型コンデンサの実装方法
JP2007115759A (ja) * 2005-10-18 2007-05-10 Tdk Corp 積層コンデンサ、複合コンデンサおよびコンデンサモジュール、ならびにコンデンサの配置方法
JP2009141217A (ja) * 2007-12-07 2009-06-25 Tdk Corp 貫通コンデンサの実装構造
JP2012186251A (ja) * 2011-03-04 2012-09-27 Murata Mfg Co Ltd ３端子コンデンサおよびその実装構造

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06349678A (ja) * 1993-06-07 1994-12-22 Tdk Corp 貫通型コンデンサ及びそれを用いた電子装置並びに貫通型コンデンサの実装方法
JP2007115759A (ja) * 2005-10-18 2007-05-10 Tdk Corp 積層コンデンサ、複合コンデンサおよびコンデンサモジュール、ならびにコンデンサの配置方法
JP2009141217A (ja) * 2007-12-07 2009-06-25 Tdk Corp 貫通コンデンサの実装構造
JP2012186251A (ja) * 2011-03-04 2012-09-27 Murata Mfg Co Ltd ３端子コンデンサおよびその実装構造

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