WO2017024622A1 - 一种液晶显示器及其控制方法 - Google Patents

一种液晶显示器及其控制方法 Download PDF

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Publication number
WO2017024622A1
WO2017024622A1 PCT/CN2015/088027 CN2015088027W WO2017024622A1 WO 2017024622 A1 WO2017024622 A1 WO 2017024622A1 CN 2015088027 W CN2015088027 W CN 2015088027W WO 2017024622 A1 WO2017024622 A1 WO 2017024622A1
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WIPO (PCT)
Prior art keywords
signal
control signal
pixel
scan
switching element
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2015/088027
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English (en)
French (fr)
Inventor
左清成
邹恭华
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Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd, Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/889,917 priority Critical patent/US9818360B2/en
Publication of WO2017024622A1 publication Critical patent/WO2017024622A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of liquid crystals, and in particular to a liquid crystal display and a control method thereof.
  • liquid crystal display Liquid Crystal The development of Display, LCD
  • people have higher and higher requirements on the resolution of LCD, due to the increase of resolution, the data line that needs to be output controlled (source)
  • the number of lines is also increasing.
  • the number of lines output can be sub-pixel charged by the same data line in a MUX controlled manner.
  • control signals MUX_1 and MUX_2 are required to control the switching of the data lines, and two different clock signals CLK_1 and CLK_2 are required to control the output of the scan lines.
  • the control signals MUX_1 and MUX_2 must maintain a certain frequency, and at the same time they need to maintain a certain relationship with the turn-on frequency and timing of the scan lines controlled by the clock signals CLK_1 and CLK_2.
  • control signal MUX_1, the control signal MUX_2, the clock signal CLK_1, and the clock signal CLK_2 are all input signals, which are implemented by separately independent control.
  • the control signal MUX_1, the control signal MUX_2, the clock signal CLK_1, and the clock signal CLK_2 are all input signals, which are implemented by separately independent control.
  • the technical problem to be solved by the present invention is to provide a liquid crystal display and a control method thereof, which can reduce the number of input signals, thereby reducing the time for the relative matching relationship between the timings of debugging input signals, and is advantageous for improving the production efficiency of the liquid crystal display.
  • a technical solution adopted by the present invention is to provide a liquid crystal display including: a plurality of data lines, a plurality of scan lines, and a plurality of pixel units arranged in an array, wherein each of the pixel units includes a first pixel and a second pixel, wherein the first pixel and the second pixel in each pixel unit are connected to the corresponding same data line and the same scan line; the liquid crystal display further includes: a first frequency dividing unit, configured to receive the first a control signal and dividing the first control signal to obtain a first clock signal; a second frequency dividing unit for receiving the second control signal and dividing the second control signal to obtain a second clock signal; the GOA unit And for generating a scan signal according to the first clock signal and the second clock signal; the control circuit is configured to receive the first control signal and the second control signal, and when the scan signal is valid, according to the first control signal and the second control signal Controlling the first pixel and the second pixel corresponding to the scan signal
  • the control circuit includes a plurality of control units in one-to-one correspondence with the plurality of data lines, each control unit includes a first switching element and a second switching element, and the first end of the first switching element and the second switching element correspond to the receiving end a control signal, a second control signal, the second ends of the first switching element and the second switching element are connected to each other and connected to the corresponding same data line, and the third ends of the first switching element and the second switching element are respectively identical
  • the first pixel and the second pixel in the pixel unit are correspondingly connected; wherein, when the scan signal is valid: if the first control signal is valid, the first switching element is turned on to enable the data line to charge the first pixel; if the second control The signal is active and the second switching element is turned on to cause the data line to charge the second pixel.
  • the first switching element and the second switching element are NMOS transistors, and the first end, the second end and the third end of the first switching element and the second switching element correspond to the drain, the source and the gate of the NMOS transistor.
  • the GOA unit is configured to generate a first scan signal and a second scan signal according to the first clock signal and the second clock signal, and output to the Nth scan line and the N+1th scan line, where N is a natural number;
  • the first scan signal and the second scan signal are time-sharing effective.
  • the first control signal and the second control signal have the same frequency and opposite phases
  • the first clock signal and the second clock signal have the same frequency and opposite phases
  • the scan period of the first scan signal and the second scan signal is the first control signal or The reciprocal of the frequency of the second control signal.
  • a liquid crystal display including: a plurality of data lines, a plurality of scan lines, and a plurality of pixel units arranged in an array, wherein each pixel unit The first pixel and the second pixel are connected, and the first pixel and the second pixel in each pixel unit are connected to the corresponding same data line and the same scan line;
  • the liquid crystal display further includes: a first frequency dividing unit, configured to receive a first control signal and dividing the first control signal to obtain a first clock signal; a second frequency dividing unit for receiving the second control signal and dividing the second control signal to obtain a second clock signal;
  • GOA a unit, configured to generate a scan signal according to the first clock signal and the second clock signal;
  • the control circuit is configured to receive the first control signal and the second control signal, and when the scan signal is valid, according to the first control signal and the second control The signal controls charging of the first pixel and the second pixel corresponding to the scan signal in a
  • the first frequency dividing unit is a D flip-flop, and the clock end of the D flip-flop receives the first control signal, the first output end of the D flip-flop is connected with the data input end of the D flip-flop, and the second output end of the D flip-flop is The first clock signal is output such that the frequency of the first clock signal is half the frequency of the first control signal.
  • the second frequency dividing unit includes a first inverter, a D flip-flop and a second inverter; the input end of the first inverter receives the second control signal, and the output of the first inverter and the D flip-flop
  • the clock terminal is connected, the first output end of the D flip-flop is connected to the data input end of the D flip-flop, the second output end of the D flip-flop is connected to the input end of the second inverter, and the output end of the second inverter
  • the second clock signal is output such that the frequency of the second clock signal is half the frequency of the second control signal.
  • the control circuit includes a plurality of control units in one-to-one correspondence with the plurality of data lines, each control unit includes a first switching element and a second switching element, and the first end of the first switching element and the second switching element correspond to the receiving end a control signal, a second control signal, the second ends of the first switching element and the second switching element are connected to each other and connected to the corresponding same data line, and the third ends of the first switching element and the second switching element are respectively identical
  • the first pixel and the second pixel in the pixel unit are correspondingly connected; wherein, when the scan signal is valid: if the first control signal is valid, the first switching element is turned on to enable the data line to charge the first pixel; if the second control The signal is active and the second switching element is turned on to cause the data line to charge the second pixel.
  • the first switching element and the second switching element are NMOS transistors, and the first end, the second end and the third end of the first switching element and the second switching element correspond to the drain, the source and the gate of the NMOS transistor.
  • the GOA unit is configured to generate a first scan signal and a second scan signal according to the first clock signal and the second clock signal, and output to the Nth scan line and the N+1th scan line, where N is a natural number;
  • the first scan signal and the second scan signal are time-sharing effective.
  • the first control signal and the second control signal have the same frequency and opposite phases
  • the first clock signal and the second clock signal have the same frequency and opposite phases
  • the scan period of the first scan signal and the second scan signal is the first control signal or The reciprocal of the frequency of the second control signal.
  • another technical solution adopted by the present invention is to provide a control method for a liquid crystal display, the liquid crystal display comprising: a plurality of data lines, a plurality of scan lines, and a plurality of pixel units arranged according to the array, Each of the pixel units includes a first pixel and a second pixel, and the first pixel and the second pixel of each pixel unit are connected to the corresponding same data line and the same scan line; the method includes: receiving the first control And dividing a first control signal to obtain a first clock signal; receiving a second control signal and dividing the second control signal to obtain a second clock signal; generating a scan according to the first clock signal and the second clock signal a signal; when the scan signal is active, the first control signal and the second control signal control the first pixel and the second pixel corresponding to the scan signal to be time-divisionally charged.
  • the step of generating a scan signal according to the first clock signal and the second clock signal is specifically: generating a first scan signal and a second scan signal according to the first clock signal and the second clock signal, and correspondingly outputting to the Nth scan line and The N+1th scan line, N is a natural number; wherein the first scan signal and the second scan signal are time-sharing effective.
  • the first control signal and the second control signal have the same frequency and opposite phases
  • the first clock signal and the second clock signal have the same frequency and opposite phases
  • the scan period of the first scan signal and the second scan signal is the first control signal or The reciprocal of the frequency of the second control signal.
  • the beneficial effects of the present invention are: the liquid crystal display of the present invention and the control method thereof control the switching of the data lines by the first control signal and the second control signal, and separately divide the first control signal and the second control signal to obtain a corresponding The first clock signal and the second clock signal, in turn, control the output of the scan line in accordance with the first clock signal and the second clock signal.
  • the liquid crystal display of the present invention can reduce the number of input signals, thereby reducing the time for the relative matching relationship between the timings of the debug input signals, and is advantageous for improving the timing debugging efficiency.
  • FIG. 1 is a schematic structural view of a liquid crystal display according to an embodiment of the present invention.
  • Figure 2 is a circuit schematic diagram of the first frequency dividing unit of Figure 1;
  • Figure 3 is a circuit schematic diagram of the second frequency dividing unit of Figure 1;
  • Figure 4 is a timing chart showing the operation of the liquid crystal display shown in Figure 1;
  • FIG. 5 is a flow chart of a control method of the liquid crystal display shown in FIG. 1.
  • the liquid crystal display includes a data line S(N) (N is a natural number), a scanning line G(N) (N is a natural number), a plurality of pixel units 21 arranged in an array, and a first frequency dividing unit 22 , second frequency division unit 23, GOA (Gate Driver On Array unit 24 and control circuit 25.
  • S(N) N is a natural number
  • G(N) N is a natural number
  • GOA Gate Driver On Array unit 24 and control circuit 25.
  • Each pixel unit 21 is connected to its corresponding one of the data lines and one of the scan lines.
  • Each of the pixel units 21 includes a first pixel 21a and a second pixel 21b, and the first pixel 21a and the second pixel 21b of each pixel unit 21 are charged by the corresponding same data line.
  • the first frequency dividing unit 22 is connected to the GOA unit 24 for receiving the first control signal MUX_A and dividing the first control signal MUX_A to obtain a first clock signal CK, and transmitting the first clock signal CK to the GOA unit 24 .
  • FIG. 2 is a circuit schematic diagram of the first frequency dividing unit of FIG. As shown in FIG. 2, the first frequency dividing unit 22 is a D flip-flop 221.
  • the clock terminal CLK of the D flip-flop 221 receives the first control signal MUX_A, the first output of the D flip-flop 221 Connected to the data input terminal D of the D flip-flop 221, the second output terminal Q of the D flip-flop 221 is connected to the GOA unit 24 of FIG. 1 for outputting the first clock signal CK to the GOA unit 24.
  • the frequency of the first clock signal CK is half of the frequency of the first control signal MUX_A.
  • the second frequency dividing unit 23 is connected to the GOA unit 24 for receiving the second control signal MUX_B and dividing the second control signal MUX_B to obtain the second clock signal CKB and transmitting it to the GOA unit 24.
  • FIG. 3 is a circuit schematic diagram of the second frequency dividing unit of FIG.
  • the second frequency dividing unit 23 includes a first inverter 231, a D flip-flop 232, and a second inverter 233.
  • the input end of the first inverter 231 receives the second control signal MUX_B, and the output end of the first inverter 231 is connected to the clock terminal CLK of the D flip-flop 232, and the first output end of the D flip-flop 232 Connected to the data input terminal D of the D flip-flop 231, the second output terminal Q of the D flip-flop is connected to the input terminal of the second inverter 233, and the output terminal of the second inverter 233 is connected to the GOA unit 24 of FIG.
  • the connection is for outputting the second clock signal CKB to the GOA unit 24.
  • the frequency of the second clock signal CKB is half of the frequency of the second control signal MUX_B.
  • the GOA unit 24 is configured to generate a scan signal according to the first clock signal CK and the second clock signal CKB. Specifically, the GOA unit 24 generates the first scan signal Gate(N) and the second scan signal according to the first clock signal CK, the second clock signal CKB, the start pulse signal STV, the high constant voltage source VGH, and the low constant voltage source VGL. Gate (N+1) is correspondingly output to the Nth-th scanning line G(N) and the N+1-th scanning line G(N+1).
  • the start pulse signal STV is used to turn on the scanning operation of the scan line; the high constant voltage source VGH and the low constant voltage source VGL are input constant voltage control signals, the high constant voltage source VGH is high potential, and the low constant voltage source VGL is low. The potential, both are used to provide the high and low potentials in the GOA unit 24.
  • the first control signal MUX_A and the second control signal MUX_B have the same frequency and opposite phases.
  • the duty ratios of the first control signal MUX_A and the second control signal MUX_B are 1:2.
  • the first clock signal CK and the second clock signal CKB have the same frequency and opposite phases.
  • the duty ratio of the first clock signal CK and the second clock signal CKB is 1:2.
  • the scan period of the first scan signal Gate(N) and the second scan signal Gate(N+1) is the reciprocal of the frequency of the first control signal MUX_A or the second control signal MUX_B, the first scan signal Gate(N) and the second The scan signal Gate(N+1) is time-dependent, that is, the first scan signal Gate(N) and the second scan signal Gate(N+1) are time-divided as high-level signals.
  • control circuit 25 includes a plurality of control units 251 that are in one-to-one correspondence with the plurality of data lines S(N), each control unit 251 including a first switching element T1 and a second switching element T2.
  • the first switching element T1 and the second switching element T2 are NMOS transistors, and the first end, the second end, and the third end of the first switching element T1 and the second switching element T2 respectively correspond to the drain and source of the NMOS transistor. Pole and gate.
  • the first ends of the first switching element T1 and the second switching element T2 are respectively connected to the first pixel 21a and the second pixel 21b, and the second ends of the first switching element T1 and the second switching element T2 are connected to each other and corresponding
  • the third data end of the first switching element T1 and the second switching element T2 are corresponding to the first control signal MUX_A and the second control signal MUX_B.
  • FIG. 4 is a timing chart of the operation of the liquid crystal display shown in FIG. 1. As shown in Figure 4:
  • the first control signal MUX_A is a high level signal
  • the second control signal MUX_B is a low level signal, such that the first switching element T1 is turned on, the second switching element T2 is turned off, and the output of the GOA unit 24 is applied to the scan.
  • the first scan signal Gate(N) on the line G(N) is at a high level
  • the second scan signal Gate(N+1) applied to the scan line G(N+1) output by the GOA unit 24 is low.
  • the data line S(N) charges the first pixel 21a of the pixel unit 21 connected to the scanning line G(N).
  • the first control signal MUX_A is a low level signal
  • the second control signal MUX_B is a high level signal, such that the first switching element T1 is turned off, the second switching element T2 is turned on, and the first scanning signal Gate(N) While maintaining the high level, the second scan signal Gate(N+1) is kept at a low level.
  • the data line S(N) is performed on the second pixel 21b in the pixel unit 21 connected to the scan line G(N). Charging.
  • the first control signal MUX_A is a high level signal
  • the second control signal MUX_B is a low level signal, such that the first switching element T1 is turned on, the second switching element T2 is turned off, and the first scan signal Gate(N)
  • the second scan signal Gate(N+1) changes from a low level to a high level.
  • the data line S(N) pair and the scan line G(N+1) The first pixel 21a in the corresponding connected pixel unit 21 is charged.
  • the first control signal MUX_A is a low level signal
  • the second control signal MUX_B is a high level signal, thereby causing the first switching element T1 to be turned off, the second switching element T2 to be turned on, and the first scanning signal Gate (N Keeping a low level, the second scan signal Gate(N+1) remains at a high level, at this time, the data line S(N) is paired with the second of the pixel units 21 correspondingly connected to the scan line G(N+1) The pixel 21b is charged.
  • FIG. 5 is a flow chart of a control method of the liquid crystal display shown in FIG. 1. As shown in FIG. 5, the method includes the steps of:
  • Step S101 Receive a first control signal and divide the first control signal to obtain a first clock signal.
  • the first frequency dividing unit 22 receives the first control signal MUX_A and divides the first control signal MUX_A to obtain a first clock signal CK.
  • the frequency of the first clock signal CK is 1/2 of the frequency of the first control signal MUX_A.
  • Step S102 Receive a second control signal and divide the second control signal to obtain a second clock signal.
  • the second frequency dividing unit 23 receives the second control signal MUX_B and divides the second control signal MUX_B to obtain the second clock signal CKB.
  • the frequency of the second clock signal CKB is 1/2 of the frequency of the second control signal MUX_B.
  • the first control signal MUX_A and the second control signal MUX_B have the same frequency and opposite phases.
  • the duty ratios of the first control signal MUX_A and the second control signal MUX_B are 1:2.
  • the first clock signal CK and the second clock signal CKB have the same frequency and opposite phases.
  • the duty ratio of the first clock signal CK and the second clock signal CKB is 1:2.
  • Step S103 generating a scan signal according to the first clock signal and the second clock signal.
  • step S103 the GOA unit 24 generates a scan signal based on the first clock signal CK and the second clock signal CKB. Specifically, the GOA unit 24 generates the first scan signal Gate(N) and the second scan signal according to the first clock signal CK, the second clock signal CKB, the start pulse signal STV, the high constant voltage source VGH, and the low constant voltage source VGL. Gate (N+1) is correspondingly output to the Nth-th scanning line G(N) and the N+1-th scanning line G(N+1).
  • the first scan signal Gate(N) and the second scan signal Gate(N+1) are time-dependent, that is, the first scan signal Gate(N) and the second scan signal Gate(N+1) are time-sharing high. Flat signal.
  • the scan period of the first scan signal Gate(N) and the second scan signal Gate(N+1) is the reciprocal of the frequency of the first control signal MUX_A or the second control signal MUX_B.
  • Step S104 When the scan signal is valid, the first control signal and the second control signal control the first pixel and the second pixel corresponding to the scan signal to perform charging in a time division manner.
  • step S104 when the first scan signal Gate(N) is active, that is, the first scan signal Gate(N) is high:
  • the first control signal MUX_A is a high level signal
  • the second control signal MUX_B is a low level signal
  • the first switching element T1 is turned on
  • the second switching element T2 is turned off
  • the data line S(N) is paired with the scan line G(N) Charging the first pixel 21a in the corresponding connected pixel unit 21;
  • the first control signal MUX_A is a low level signal
  • the second control signal MUX_B is a high level signal
  • the first switching element T1 is turned off
  • the second switching element T2 is turned on
  • the data line S(N) is paired with the scan line G(N)
  • the second pixel 21b in the corresponding connected pixel unit 21 is charged.
  • the first control signal MUX_A is a high level signal
  • the second control signal MUX_B is a low level signal
  • the first switching element T1 is turned on
  • the second switching element T2 is turned off
  • the data line S(N) is paired with the scan line G(N) +1) charging the first pixel 21a in the corresponding connected pixel unit 21;
  • the first control signal MUX_A is a low level signal
  • the second control signal MUX_B is a high level signal
  • the first switching element T1 is turned off
  • the second switching element T2 is turned on
  • the data line S(N) is paired with the scan line G(N) +1)
  • the second pixel 21b in the corresponding connected pixel unit 21 is charged.
  • the beneficial effects of the present invention are: the liquid crystal display of the present invention and the control method thereof control the switching of the data lines by the first control signal and the second control signal, and separately divide the first control signal and the second control signal to obtain a corresponding The first clock signal and the second clock signal, in turn, control the output of the scan line in accordance with the first clock signal and the second clock signal.
  • the liquid crystal display of the present invention can reduce the number of input signals, thereby reducing the time for the relative matching relationship between the timings of the debug input signals, and is advantageous for improving the timing debugging efficiency.

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Abstract

一种液晶显示器及其控制方法。该液晶显示器包括：第一分频单元（22），用于接收第一控制信号（MUX_A）并对第一控制信号（MUX_A）进行分频以获得第一时钟信号（CK）；第二分频单元（23），用于接收第二控制信号（MUX_B）并对第二控制信号（MUX_B）进行分频以获得第二时钟信号（CKB）；GOA单元（24），用于根据第一时钟信号（CK）和第二时钟信号（CKB）产生扫描信号；控制电路（25），用于接收第一控制信号（MUX_A）和第二控制信号（MUX_B），并在扫描信号有效时，根据第一控制信号（MUX_A）和第二控制信号（MUX_B）控制与扫描信号对应的同一像素单元（21）中的第一像素（21a）和第二像素（21b）分时进行充电。通过上述方式，所述液晶显示器可以减少输入信号的数量，进而可以减少调试输入信号的时序间的相对匹配关系的时间，有利于提高液晶显示器的生产效率。

Description

一种液晶显示器及其控制方法
【技术领域】
本发明涉及液晶领域，特别是涉及一种液晶显示器及其控制方法。
【背景技术】
随着液晶显示器（Liquid Crystal Display，LCD）的发展，人们对LCD的分辨率要求越来越高，由于分辨率的增加，所需要进行输出控制的数据线（source line）的数量也越来越多。为了减少LCD驱动芯片的source line的输出数量，可以采用MUX控制的方式使用同一条数据线分时对子像素（sub-pixel）进行充电。
在现有的1:2MUX模式的液晶显示器中，需要两个不同的控制信号MUX_1和MUX_2控制数据线的切换，同时需要两个不同的时钟信号CLK_1和CLK_2控制扫描线的输出。为使液晶显示器能正常显示，控制信号MUX_1和MUX_2必须保持一定的频率，同时其需要与时钟信号CLK_1和CLK_2控制的扫描线的开启频率及时序保持一定的关系。
由于现有技术中，控制信号MUX_1、控制信号MUX_2、时钟信号CLK_1和时钟信号CLK_2皆为输入信号，其采用分开独立控制的方式实现。为了保证液晶显示器的正常显示，在实际生产时，需要花费大量的时间来调试这四个输入信号的时序间的相对匹配关系，不利于液晶显示器的高效生产。
【发明内容】
本发明主要解决的技术问题是提供一种液晶显示器及其控制方法，能够减少输入信号的数量，进而减少调试输入信号的时序间的相对匹配关系的时间，有利于提高液晶显示器的生产效率。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种液晶显示器，包括：多条数据线、多条扫描线和按照阵列排布的多个像素单元，其中，每一像素单元包括第一像素和第二像素，每一像素单元中的第一像素和第二像素连接对应的同一条数据线和同一条扫描线；该液晶显示器进一步包括：第一分频单元，用于接收第一控制信号并对第一控制信号进行分频以获得第一时钟信号；第二分频单元，用于接收第二控制信号并对第二控制信号进行分频以获得第二时钟信号；GOA单元，用于根据第一时钟信号和第二时钟信号产生扫描信号；控制电路，用于接收第一控制信号和第二控制信号，并在扫描信号有效时，根据第一控制信号和第二控制信号控制与扫描信号对应的第一像素和第二像素分时进行充电；第一分频单元为D触发器，D触发器的时钟端接收第一控制信号，D触发器的第一输出端与D触发器的数据输入端连接，D触发器的第二输出端输出第一时钟信号，以使第一时钟信号的频率为第一控制信号的频率的一半；第二分频单元包括第一反相器、D触发器和第二反相器；第一反相器的输入端接收第二控制信号，第一反相器的输出端与D触发器的时钟端连接，D触发器的第一输出端与D触发器的数据输入端连接，D触发器的第二输出端与第二反相器的输入端连接，第二反相器的输出端输出第二时钟信号，以使第二时钟信号的频率为第二控制信号的频率的一半。
其中，控制电路包括与多个数据线一一对应的多个控制单元，每一控制单元包括第一开关元件和第二开关元件，第一开关元件、第二开关元件的第一端对应接收第一控制信号、第二控制信号，第一开关元件、第二开关元件的第二端相互连接后与对应的同一条数据线连接，第一开关元件、第二开关元件的第三端分别与同一像素单元中的第一像素、第二像素对应连接；其中，当扫描信号有效时：若第一控制信号有效，第一开关元件导通以使数据线对第一像素进行充电；若第二控制信号有效，第二开关元件导通以使数据线对第二像素进行充电。
其中，第一开关元件、第二开关元件为NMOS管，第一开关元件、第二开关元件的第一端、第二端和第三端对应NMOS管的漏极、源极和栅极。
其中，GOA单元用于根据第一时钟信号和第二时钟信号产生第一扫描信号和第二扫描信号并对应输出至第N级扫描线和第N+1级扫描线，N为自然数；其中，第一扫描信号和第二扫描信号分时有效。
其中，第一控制信号和第二控制信号频率相同且相位相反，第一时钟信号和第二时钟信号频率相同且相位相反，第一扫描信号和第二扫描信号的扫描周期为第一控制信号或第二控制信号的频率的倒数。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示器，包括：多条数据线、多条扫描线和按照阵列排布的多个像素单元，其中，每一像素单元包括第一像素和第二像素，每一像素单元中的第一像素和第二像素连接对应的同一条数据线和同一条扫描线；该液晶显示器进一步包括：第一分频单元，用于接收第一控制信号并对第一控制信号进行分频以获得第一时钟信号；第二分频单元，用于接收第二控制信号并对第二控制信号进行分频以获得第二时钟信号；GOA单元，用于根据第一时钟信号和第二时钟信号产生扫描信号；控制电路，用于接收第一控制信号和第二控制信号，并在扫描信号有效时，根据第一控制信号和第二控制信号控制与扫描信号对应的第一像素和第二像素分时进行充电。
其中，第一分频单元为D触发器，D触发器的时钟端接收第一控制信号，D触发器的第一输出端与D触发器的数据输入端连接，D触发器的第二输出端输出第一时钟信号，以使第一时钟信号的频率为第一控制信号的频率的一半。
其中，第二分频单元包括第一反相器、D触发器和第二反相器；第一反相器的输入端接收第二控制信号，第一反相器的输出端与D触发器的时钟端连接，D触发器的第一输出端与D触发器的数据输入端连接，D触发器的第二输出端与第二反相器的输入端连接，第二反相器的输出端输出第二时钟信号，以使第二时钟信号的频率为第二控制信号的频率的一半。
其中，控制电路包括与多个数据线一一对应的多个控制单元，每一控制单元包括第一开关元件和第二开关元件，第一开关元件、第二开关元件的第一端对应接收第一控制信号、第二控制信号，第一开关元件、第二开关元件的第二端相互连接后与对应的同一条数据线连接，第一开关元件、第二开关元件的第三端分别与同一像素单元中的第一像素、第二像素对应连接；其中，当扫描信号有效时：若第一控制信号有效，第一开关元件导通以使数据线对第一像素进行充电；若第二控制信号有效，第二开关元件导通以使数据线对第二像素进行充电。
其中，第一开关元件、第二开关元件为NMOS管，第一开关元件、第二开关元件的第一端、第二端和第三端对应NMOS管的漏极、源极和栅极。
其中，GOA单元用于根据第一时钟信号和第二时钟信号产生第一扫描信号和第二扫描信号并对应输出至第N级扫描线和第N+1级扫描线，N为自然数；其中，第一扫描信号和第二扫描信号分时有效。
其中，第一控制信号和第二控制信号频率相同且相位相反，第一时钟信号和第二时钟信号频率相同且相位相反，第一扫描信号和第二扫描信号的扫描周期为第一控制信号或第二控制信号的频率的倒数。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示器的控制方法，该液晶显示器包括：多条数据线、多条扫描线和按照阵列排布的多个像素单元，其中，每一像素单元包括第一像素和第二像素，每一像素单元中的第一像素和第二像素连接其对应的同一条数据线和同一条扫描线；该方法包括：接收第一控制信号并对第一控制信号进行分频以获得第一时钟信号；接收第二控制信号并对第二控制信号进行分频以获得第二时钟信号；根据第一时钟信号和第二时钟信号产生扫描信号；在扫描信号有效时，第一控制信号和第二控制信号控制与扫描信号对应的第一像素和第二像素分时进行充电。
其中，根据第一时钟信号和第二时钟信号产生扫描信号的步骤具体为：根据第一时钟信号和第二时钟信号产生第一扫描信号和第二扫描信号并对应输出至第N级扫描线和第N+1级扫描线，N为自然数；其中，第一扫描信号和第二扫描信号分时有效。
其中，第一控制信号和第二控制信号频率相同且相位相反，第一时钟信号和第二时钟信号频率相同且相位相反，第一扫描信号和第二扫描信号的扫描周期为第一控制信号或第二控制信号的频率的倒数。
本发明的有益效果是：本发明的液晶显示器及其控制方法通过第一控制信号和第二控制信号控制数据线的切换，以及对第一控制信号和第二控制信号分别进行分频以得到对应的第一时钟信号和第二时钟信号，继而根据第一时钟信号和第二时钟信号控制扫描线的输出。通过上述方式，本发明的液晶显示器可以减少输入信号的数量，进而可以减少调试输入信号的时序间的相对匹配关系的时间，有利于时序调试效率的提高。
【附图说明】
图1是本发明实施例的液晶显示器的结构示意图；
图2是图1中第一分频单元的电路原理图；
图3是图1中第二分频单元的电路原理图；
图4是图1所示液晶显示器的工作时序图；
图5是图1所示液晶显示器的控制方法的流程图。
【具体实施方式】
在说明书及权利要求书当中使用了某些词汇来指称特定的组件，所属领域中的技术人员应可理解，制造商可能会用不同的名词来称呼同样的组件。本说明书及权利要求书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的基准。下面结合附图和实施例对本发明进行详细说明。
图1是本发明实施例的液晶显示器的结构示意图。如图1所示，液晶显示器包括数据线S（N）（N为自然数）、扫描线G（N）（N为自然数）、按照阵列排布的多个像素单元21、第一分频单元22、第二分频单元23、GOA（Gate Driver On Array，阵列基板行扫描驱动）单元24和控制电路25。
每一像素单元21连接其对应的一条数据线和一条扫描线。每一像素单元21包括第一像素21a和第二像素21b，每一像素单元21中第一像素21a和第二像素21b由对应的同一条数据线充电。
第一分频单元22与GOA单元24连接，用于接收第一控制信号MUX_A并对第一控制信号MUX_A进行分频以获得第一时钟信号CK，并将第一时钟信号CK输送至GOA单元24。
请一并参考图2，图2是图1中第一分频单元的电路原理图。如图2所示，第一分频单元22为D触发器221。
D触发器221的时钟端CLK接收第一控制信号MUX_A，D触发器221的第一输出端 与D触发器221的数据输入端D连接，D触发器221的第二输出端Q与图1中的GOA单元24连接，用于向GOA单元24输出第一时钟信号CK。其中，第一时钟信号CK的频率为第一控制信号MUX_A的频率的一半。
请继续参考图1，第二分频单元23与GOA单元24连接，用于接收第二控制信号MUX_B并对第二控制信号MUX_B进行分频以获得第二时钟信号CKB并输送至GOA单元24。
请一并参考图3，图3是图1中第二分频单元的电路原理图。如图3所示，第二分频单元23包括第一反相器231、D触发器232和第二反相器233。
第一反相器231的输入端接收第二控制信号MUX_B，第一反相器231的输出端与D触发器232的时钟端CLK连接，D触发器232的第一输出端 与D触发器231的数据输入端D连接，D触发器的第二输出端Q与第二反相器233的输入端连接，第二反相器233的输出端与图1中的GOA单元24连接，用于向GOA单元24输出第二时钟信号CKB。其中，第二时钟信号CKB的频率为第二控制信号MUX_B的频率的一半。
请继续参考图1，GOA单元24用于根据第一时钟信号CK、第二时钟信号CKB产生扫描信号。具体来说，GOA单元24根据第一时钟信号CK、第二时钟信号CKB配合启动脉冲信号STV、高恒压源VGH和低恒压源VGL产生第一扫描信号Gate（N）和第二扫描信号Gate（N+1）并对应输出至第N级扫描线G（N）和第N+1级扫描线G（N+1）。其中，启动脉冲信号STV用于开启扫描线的扫描动作；高恒压源VGH和低恒压源VGL为输入的恒压控制讯号，高恒压源VGH为高电位，低恒压源VGL为低电位，两者用于提供GOA单元24中的高低电位。
在本实施例中，第一控制信号MUX_A和第二控制信号MUX_B频率相同且相位相反，优选地，第一控制信号MUX_A和第二控制信号MUX_B的占空比为1：2。第一时钟信号CK和第二时钟信号CKB频率相同且相位相反，优选地，第一时钟信号CK和第二时钟信号CKB的占空比为1：2。第一扫描信号Gate（N）和第二扫描信号Gate（N+1）的扫描周期为第一控制信号MUX_A或第二控制信号MUX_B的频率的倒数，第一扫描信号Gate（N）和第二扫描信号Gate（N+1）分时有效也即第一扫描信号Gate（N）和第二扫描信号Gate（N+1）分时为高电平信号。
请继续参考图1，控制电路25包括与多条数据线S（N）一一对应的多个控制单元251，每一控制单元251包括第一开关元件T1和第二开关元件T2。
优选地，第一开关元件T1、第二开关元件T2为NMOS管，第一开关元件T1、第二开关元件T2的第一端、第二端和第三端分别对应NMOS管的漏极、源极和栅极。
第一开关元件T1、第二开关元件T2的第一端分别与第一像素21a和第二像素21b对应连接，第一开关元件T1、第二开关元件T2的第二端相互连接后与对应的同一条数据线连接，第一开关元件T1、第二开关元件T2的第三端对应接收第一控制信号MUX_A、第二控制信号MUX_B。
请一并参考图4，图4是图1所示液晶显示器的工作时序图。如图4所示：
在T1阶段，第一控制信号MUX_A为高电平信号，第二控制信号MUX_B为低电平信号，从而使得第一开关元件T1开启，第二开关元件T2关闭，GOA单元24输出的施加在扫描线G（N）上的第一扫描信号Gate（N）为高电平，GOA单元24输出的施加在扫描线G（N+1）上的第二扫描信号Gate（N+1）为低电平，此时，数据线S（N）对与扫描线G（N）对应连接的像素单元21中的第一像素21a进行充电。
在T2阶段，第一控制信号MUX_A为低电平信号，第二控制信号MUX_B为高电平信号，从而使得第一开关元件T1关闭，第二开关元件T2开启，第一扫描信号Gate（N）保持高电平，第二扫描信号Gate（N+1）保持低电平，此时，数据线S（N）对与扫描线G（N）对应连接的像素单元21中的第二像素21b进行充电。
在T3阶段，第一控制信号MUX_A为高电平信号，第二控制信号MUX_B为低电平信号，从而使得第一开关元件T1开启，第二开关元件T2关闭，第一扫描信号Gate（N）为由高电平变为低电平，第二扫描信号Gate（N+1）由低电平变为高电平，此时，数据线S（N）对与扫描线G（N+1）对应连接的像素单元21中的第一像素21a进行充电。
在T4阶段，第一控制信号MUX_A为低电平信号，第二控制信号MUX_B为高电平信号时，从而使得第一开关元件T1关闭，第二开关元件T2开启，第一扫描信号Gate（N）保持低电平，第二扫描信号Gate（N+1）保持高电平，此时，数据线S（N）对与扫描线G（N+1）对应连接的像素单元21中的第二像素21b进行充电。
在多条扫描线G（N）依次扫描的过程中，重复T1~T4阶段的操作，即可完成液晶显示器中的所有像素单元21的充电。
图5是图1所示液晶显示器的控制方法的流程图。如图5所示，该方法包括步骤：
步骤S101：接收第一控制信号并对第一控制信号进行分频以获得第一时钟信号。
在步骤S101中，第一分频单元22接收第一控制信号MUX_A，并对第一控制信号MUX_A进行分频以获得第一时钟信号CK。优选地，第一时钟信号CK的频率为第一控制信号MUX_A的频率的1/2。
步骤S102：接收第二控制信号并对所述第二控制信号进行分频以获得第二时钟信号。
在步骤S102中，第二分频单元23接收第二控制信号MUX_B，并对第二控制信号MUX_B进行分频以获得第二时钟信号CKB。优选地，第二时钟信号CKB的频率为第二控制信号MUX_B的频率的1/2。
其中，第一控制信号MUX_A和第二控制信号MUX_B频率相同且相位相反，优选地，第一控制信号MUX_A和第二控制信号MUX_B的占空比为1：2。第一时钟信号CK和第二时钟信号CKB频率相同且相位相反，优选地，第一时钟信号CK和第二时钟信号CKB的占空比为1：2。
步骤S103：根据第一时钟信号和第二时钟信号产生扫描信号。
在步骤S103中，GOA单元24根据第一时钟信号CK、第二时钟信号CKB产生扫描信号。具体来说，GOA单元24根据第一时钟信号CK、第二时钟信号CKB配合启动脉冲信号STV、高恒压源VGH和低恒压源VGL产生第一扫描信号Gate（N）和第二扫描信号Gate（N+1）并对应输出至第N级扫描线G（N）和第N+1级扫描线G（N+1）。
其中，第一扫描信号Gate（N）和第二扫描信号Gate（N+1）分时有效也即第一扫描信号Gate（N）和第二扫描信号Gate（N+1）分时为高电平信号。优选地，第一扫描信号Gate（N）和第二扫描信号Gate（N+1）的扫描周期为第一控制信号MUX_A或第二控制信号MUX_B的频率的倒数。
步骤S104：在扫描信号有效时，第一控制信号和第二控制信号控制与扫描信号对应的第一像素和第二像素分时进行充电。
在步骤S104中，当第一扫描信号Gate（N）有效也即第一扫描信号Gate（N）为高电平时：
若第一控制信号MUX_A为高电平信号，第二控制信号MUX_B为低电平信号，第一开关元件T1开启，第二开关元件T2关闭，数据线S（N）对与扫描线G（N）对应连接的像素单元21中的第一像素21a进行充电；
若第一控制信号MUX_A为低电平信号，第二控制信号MUX_B为高电平信号，第一开关元件T1关闭，第二开关元件T2开启，数据线S（N）对与扫描线G（N）对应连接的像素单元21中的第二像素21b进行充电。
当第二扫描信号Gate（N+1）有效也即第二扫描信号Gate（N+1）为高电平时：
若第一控制信号MUX_A为高电平信号，第二控制信号MUX_B为低电平信号，第一开关元件T1开启，第二开关元件T2关闭，数据线S（N）对与扫描线G（N+1）对应连接的像素单元21中的第一像素21a进行充电；
若第一控制信号MUX_A为低电平信号，第二控制信号MUX_B为高电平信号，第一开关元件T1关闭，第二开关元件T2开启，数据线S（N）对与扫描线G（N+1）对应连接的像素单元21中的第二像素21b进行充电。
本发明的有益效果是：本发明的液晶显示器及其控制方法通过第一控制信号和第二控制信号控制数据线的切换，以及对第一控制信号和第二控制信号分别进行分频以得到对应的第一时钟信号和第二时钟信号，继而根据第一时钟信号和第二时钟信号控制扫描线的输出。通过上述方式，本发明的液晶显示器可以减少输入信号的数量，进而可以减少调试输入信号的时序间的相对匹配关系的时间，有利于时序调试效率的提高。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种液晶显示器，其中，包括：多条数据线、多条扫描线和按照阵列排布的多个像素单元，其中，每一所述像素单元包括第一像素和第二像素，每一所述像素单元中的所述第一像素和所述第二像素连接对应的同一条数据线和同一条扫描线；
    所述液晶显示器进一步包括：
    第一分频单元，用于接收第一控制信号并对所述第一控制信号进行分频以获得第一时钟信号；
    第二分频单元，用于接收第二控制信号并对所述第二控制信号进行分频以获得第二时钟信号；
    GOA单元，用于根据所述第一时钟信号和所述第二时钟信号产生扫描信号；
    控制电路，用于接收所述第一控制信号和所述第二控制信号，并在所述扫描信号有效时，根据所述第一控制信号和所述第二控制信号控制与所述扫描信号对应的所述第一像素和所述第二像素分时进行充电；
    其中，所述第一分频单元为D触发器，所述D触发器的时钟端接收所述第一控制信号，所述D触发器的第一输出端与所述D触发器的数据输入端连接，所述D触发器的第二输出端输出所述第一时钟信号，以使所述第一时钟信号的频率为所述第一控制信号的频率的一半；
    其中，所述第二分频单元包括第一反相器、D触发器和第二反相器；
    所述第一反相器的输入端接收所述第二控制信号，所述第一反相器的输出端与所述D触发器的时钟端连接，所述D触发器的第一输出端与所述D触发器的数据输入端连接，所述D触发器的第二输出端与所述第二反相器的输入端连接，所述第二反相器的输出端输出所述第二时钟信号，以使所述第二时钟信号的频率为所述第二控制信号的频率的一半。
  2. 根据权利要求1所述的液晶显示器，其中，所述控制电路包括与多个所述数据线一一对应的多个控制单元，每一所述控制单元包括第一开关元件和第二开关元件，所述第一开关元件、第二开关元件的第一端对应接收所述第一控制信号、第二控制信号，所述第一开关元件、第二开关元件的第二端相互连接后与对应的同一条所述数据线连接，所述第一开关元件、第二开关元件的第三端分别与同一所述像素单元中的所述第一像素、第二像素对应连接；
    其中，当所述扫描信号有效时：
    若所述第一控制信号有效，所述第一开关元件导通以使所述数据线对所述第一像素进行充电；
    若所述第二控制信号有效，所述第二开关元件导通以使所述数据线对所述第二像素进行充电。
  3. 根据权利要求2所述的液晶显示器，其中，所述第一开关元件、第二开关元件为NMOS管，所述第一开关元件、第二开关元件的所述第一端、第二端和第三端对应所述NMOS管的漏极、源极和栅极。
  4. 根据权利要求1所述的液晶显示器，其中，所述GOA单元用于根据所述第一时钟信号和所述第二时钟信号产生第一扫描信号和第二扫描信号并对应输出至第N级所述扫描线和第N+1级所述扫描线，N为自然数；其中，所述第一扫描信号和所述第二扫描信号分时有效。
  5. 根据权利要求4所述的液晶显示器，其中，所述第一控制信号和所述第二控制信号频率相同且相位相反，所述第一时钟信号和所述第二时钟信号频率相同且相位相反，所述第一扫描信号和第二扫描信号的扫描周期为所述第一控制信号或所述第二控制信号的频率的倒数。
  6. 一种液晶显示器，其中，包括：多条数据线、多条扫描线和按照阵列排布的多个像素单元，其中，每一所述像素单元包括第一像素和第二像素，每一所述像素单元中的所述第一像素和所述第二像素连接对应的同一条数据线和同一条扫描线；
    所述液晶显示器进一步包括：
    第一分频单元，用于接收第一控制信号并对所述第一控制信号进行分频以获得第一时钟信号；
    第二分频单元，用于接收第二控制信号并对所述第二控制信号进行分频以获得第二时钟信号；
    GOA单元，用于根据所述第一时钟信号和所述第二时钟信号产生扫描信号；
    控制电路，用于接收所述第一控制信号和所述第二控制信号，并在所述扫描信号有效时，根据所述第一控制信号和所述第二控制信号控制与所述扫描信号对应的所述第一像素和所述第二像素分时进行充电。
  7. 根据权利要求6所述的液晶显示器，其中，所述第一分频单元为D触发器，所述D触发器的时钟端接收所述第一控制信号，所述D触发器的第一输出端与所述D触发器的数据输入端连接，所述D触发器的第二输出端输出所述第一时钟信号，以使所述第一时钟信号的频率为所述第一控制信号的频率的一半。
  8. 根据权利要求6所述的液晶显示器，其中，所述第二分频单元包括第一反相器、D触发器和第二反相器；
    所述第一反相器的输入端接收所述第二控制信号，所述第一反相器的输出端与所述D触发器的时钟端连接，所述D触发器的第一输出端与所述D触发器的数据输入端连接，所述D触发器的第二输出端与所述第二反相器的输入端连接，所述第二反相器的输出端输出所述第二时钟信号，以使所述第二时钟信号的频率为所述第二控制信号的频率的一半。
  9. 根据权利要求6所述的液晶显示器，其中，所述控制电路包括与多个所述数据线一一对应的多个控制单元，每一所述控制单元包括第一开关元件和第二开关元件，所述第一开关元件、第二开关元件的第一端对应接收所述第一控制信号、第二控制信号，所述第一开关元件、第二开关元件的第二端相互连接后与对应的同一条所述数据线连接，所述第一开关元件、第二开关元件的第三端分别与同一所述像素单元中的所述第一像素、第二像素对应连接；
    其中，当所述扫描信号有效时：
    若所述第一控制信号有效，所述第一开关元件导通以使所述数据线对所述第一像素进行充电；
    若所述第二控制信号有效，所述第二开关元件导通以使所述数据线对所述第二像素进行充电。
  10. 根据权利要求9所述的液晶显示器，其中，所述第一开关元件、第二开关元件为NMOS管，所述第一开关元件、第二开关元件的所述第一端、第二端和第三端对应所述NMOS管的漏极、源极和栅极。
  11. 根据权利要求6所述的液晶显示器，其中，所述GOA单元用于根据所述第一时钟信号和所述第二时钟信号产生第一扫描信号和第二扫描信号并对应输出至第N级所述扫描线和第N+1级所述扫描线，N为自然数；其中，所述第一扫描信号和所述第二扫描信号分时有效。
  12. 根据权利要求11所述的液晶显示器，其中，所述第一控制信号和所述第二控制信号频率相同且相位相反，所述第一时钟信号和所述第二时钟信号频率相同且相位相反，所述第一扫描信号和第二扫描信号的扫描周期为所述第一控制信号或所述第二控制信号的频率的倒数。
  13. 一种液晶显示器的控制方法，其中，所述液晶显示器包括：多条数据线、多条扫描线和按照阵列排布的多个像素单元，其中，每一所述像素单元包括第一像素和第二像素，每一所述像素单元中的所述第一像素和所述第二像素连接其对应的同一条数据线和同一条扫描线；
    所述方法包括：
    接收第一控制信号并对所述第一控制信号进行分频以获得第一时钟信号；
    接收第二控制信号并对所述第二控制信号进行分频以获得第二时钟信号；
    根据所述第一时钟信号和所述第二时钟信号产生扫描信号；
    在所述扫描信号有效时，所述第一控制信号和所述第二控制信号控制与所述扫描信号对应的所述第一像素和所述第二像素分时进行充电。
  14. 根据权利要求13所述的控制方法，其中，所述根据所述第一时钟信号和所述第二时钟信号产生扫描信号的步骤具体为：
    根据所述第一时钟信号和所述第二时钟信号产生第一扫描信号和第二扫描信号并对应输出至第N级所述扫描线和第N+1级所述扫描线，N为自然数；其中，所述第一扫描信号和所述第二扫描信号分时有效。
  15. 根据权利要求14所述的控制方法，其中，所述第一控制信号和所述第二控制信号频率相同且相位相反，所述第一时钟信号和所述第二时钟信号频率相同且相位相反，所述第一扫描信号和第二扫描信号的扫描周期为所述第一控制信号或所述第二控制信号的频率的倒数。
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