WO2017024601A2 - 阵列基板行驱动短路保护电路及液晶面板 - Google Patents

阵列基板行驱动短路保护电路及液晶面板 Download PDF

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WO2017024601A2
WO2017024601A2 PCT/CN2015/087077 CN2015087077W WO2017024601A2 WO 2017024601 A2 WO2017024601 A2 WO 2017024601A2 CN 2015087077 W CN2015087077 W CN 2015087077W WO 2017024601 A2 WO2017024601 A2 WO 2017024601A2
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capacitor
diode
module
voltage
high level
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PCT/CN2015/087077
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English (en)
French (fr)
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WO2017024601A3 (zh
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张先明
曹丹
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深圳市华星光电技术有限公司
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Priority to US14/917,017 priority Critical patent/US9841649B2/en
Publication of WO2017024601A2 publication Critical patent/WO2017024601A2/zh
Publication of WO2017024601A3 publication Critical patent/WO2017024601A3/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0826—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in bipolar transistor switches
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G09G2330/045—Protection against panel overheating

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to an array substrate row driving short circuit protection circuit and a liquid crystal panel.
  • the Gate Driver on Array (GOA) technology is a new type of liquid crystal panel driving technology that has been developed in recent years. It directly etches the IC that drives the liquid crystal Gate signal on the liquid crystal panel, eliminating the cost of the Gate Drive IC. And the process of binding the IC to the LCD panel, more importantly, because the Gate Drive IC and the liquid crystal panel are integrated, the product is thinner, higher resolution, better stability and vibration resistance.
  • a level shifting circuit (Level Shifter) is mostly used to generate a CLK_OUT signal for use in the liquid crystal panel.
  • the present invention provides an array substrate row drive short circuit protection circuit to prevent an output current from increasing and burning a liquid crystal panel when a short circuit fault occurs at an output end of the array substrate row drive circuit.
  • the present invention also provides a liquid crystal panel using the array substrate row driving short circuit protection circuit.
  • An array substrate row driving short circuit protection circuit comprises a power module, a first boosting module, a feedback module, a second boosting module and a control module, the power module, the first boosting module, the feedback module and The second boosting module is connected in series, and the control module is electrically connected to the first boosting module, the feedback module, and the second boosting module, where the power module is used to supply a power voltage, and the control module is used by the control module.
  • the control module cuts off the output of the pulse width modulation signal to achieve a short circuit. protection.
  • the control module includes a feedback input, the feedback module includes a transistor, the transistor includes a base, an emitter, and a collector, the base is coupled to the feedback input, the emitter and the The first boosting module is electrically connected, and the collector is electrically connected to the second boosting module.
  • the control module further includes a pulse width modulation signal output end
  • the first boosting module includes a first diode, a second diode, a first capacitor, and a second capacitor, the first diode a positive electrode is connected to the power module, the first diode negative electrode is connected to the second diode positive electrode, and the second diode negative electrode is connected to the emitter;
  • the first diode is connected to the negative pole, and the other end is connected to the pulse width modulation signal output terminal;
  • the second capacitor is connected to the second diode negative terminal and the other end is grounded.
  • the second boosting module includes a third diode, a fourth diode, a third capacitor, a fourth capacitor, and a fifth capacitor, and the third diode anode is connected to the collector.
  • a third diode negative electrode is connected to the fourth diode positive electrode; one end of the third capacitor is connected to the collector, and the other end is grounded; the fourth capacitor end is opposite to the third diode negative electrode Connected, the other end is connected to the pulse width modulation signal output end; the fifth capacitor is connected to the fourth diode negative terminal and the other end is grounded.
  • the pulse width modulation signal includes two states of a high level and a low level, and the high level corresponds to outputting a high level voltage, and the low level corresponds to an output voltage of zero, when the pulse width modulation signal is When the level is low, the first diode, the second diode, the third diode, and the fourth diode are all turned on, and the first capacitor, the second capacitor, the fourth capacitor, and the fourth capacitor The voltage of the fifth capacitor is charged to the power supply voltage.
  • the pulse width modulation signal becomes a high level
  • the voltage of the first capacitor is raised to a high level voltage + a power supply voltage
  • the first diode is turned off
  • the second diode is turned on
  • the voltages of the second capacitor and the third capacitor are charged to a high level voltage + a power supply voltage
  • the third diode and The fourth diode is turned on, and both the fourth capacitor and the fifth capacitor are charged to a high level voltage + a power supply voltage.
  • the pulse width modulation signal changes to a low level again, the first diode is turned on, the voltage of the first capacitor drops to a power supply voltage, and the second diode is turned off, The voltages of the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor maintain a high level voltage + a power supply voltage.
  • the pulse width modulation signal changes to a high level again, the voltage of the first capacitor is charged to a high level voltage + a power supply voltage, then the first diode is turned off, the second diode Turning on, the voltages of the second capacitor and the third capacitor are maintained at a high level voltage + the power supply voltage, and the voltage of the fourth capacitor is charged to the power supply voltage + twice the high level voltage, the third two The pole tube is turned off, the fourth diode is turned on, and the voltage of the fifth capacitor is charged to the power supply voltage + twice the high level voltage.
  • the circuit further includes a level conversion module, the level conversion module includes an input end and an output end, the input end is connected to the fourth diode negative pole, and the level conversion module is used to Converting the driving voltage into a clock driving signal and outputting from the output terminal, causing a current flowing through the first boosting module, the second boosting module, and the level converting module when a short circuit fault occurs at the output terminal
  • the signal is increased, the feedback current is correspondingly increased, and when the control module detects that the feedback current exceeds the preset current threshold, cutting off the output of the pulse width modulation signal to trigger the first boost
  • the module and the second boost module enter a short circuit protection state.
  • a liquid crystal panel comprising an array substrate row driving short circuit protection circuit, the array substrate row driving short circuit protection circuit comprising a power module, a first boosting module, a feedback module, a second boosting module and a control module, the power module,
  • the first boosting module, the feedback module, and the second boosting module are connected in series, and the control module is electrically connected to the first boosting module, the feedback module, and the second boosting module, respectively.
  • the control module is configured to output a pulse width modulation signal to control the first boosting module and the second boosting module to convert the power supply voltage into a driving voltage
  • the feedback module is used to A feedback current is obtained from a current signal flowing through the first boosting module and the second boosting module and fed back to the control module, and when the feedback current exceeds a preset current threshold, the control module cuts off the pulse Wide modulated signal output for short circuit protection.
  • the control module includes a feedback input, the feedback module includes a transistor, the transistor includes a base, an emitter, and a collector, the base is coupled to the feedback input, the emitter and the The first boosting module is electrically connected, and the collector is electrically connected to the second boosting module.
  • the control module further includes a pulse width modulation signal output end
  • the first boosting module includes a first diode, a second diode, a first capacitor, and a second capacitor, the first diode a positive electrode is connected to the power module, the first diode negative electrode is connected to the second diode positive electrode, and the second diode negative electrode is connected to the emitter;
  • the first diode is connected to the negative pole, and the other end is connected to the pulse width modulation signal output terminal;
  • the second capacitor is connected to the second diode negative terminal and the other end is grounded.
  • the second boosting module includes a third diode, a fourth diode, a third capacitor, a fourth capacitor, and a fifth capacitor, and the third diode anode is connected to the collector.
  • a third diode negative electrode is connected to the fourth diode positive electrode; one end of the third capacitor is connected to the collector, and the other end is grounded; the fourth capacitor end is opposite to the third diode negative electrode Connected, the other end is connected to the pulse width modulation signal output end; the fifth capacitor is connected to the fourth diode negative terminal and the other end is grounded.
  • the pulse width modulation signal includes two states of a high level and a low level, and the high level corresponds to outputting a high level voltage, and the low level corresponds to an output voltage of zero, when the pulse width modulation signal is When the level is low, the first diode, the second diode, the third diode, and the fourth diode are all turned on, and the first capacitor, the second capacitor, the fourth capacitor, and the fourth capacitor The voltage of the fifth capacitor is charged to the power supply voltage.
  • the pulse width modulation signal becomes a high level
  • the voltage of the first capacitor is raised to a high level voltage + a power supply voltage
  • the first diode is turned off
  • the second diode is turned on
  • the voltages of the second capacitor and the third capacitor are charged to a high level voltage + a power supply voltage
  • the third diode and the fourth diode are turned on
  • the fourth capacitor and the fifth capacitor are both Charge to high level voltage + supply voltage.
  • the pulse width modulation signal changes to a low level again, the first diode is turned on, the voltage of the first capacitor drops to a power supply voltage, and the second diode is turned off, The voltages of the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor maintain a high level voltage + a power supply voltage.
  • the pulse width modulation signal changes to a high level again, the voltage of the first capacitor is charged to a high level voltage + a power supply voltage, then the first diode is turned off, the second diode Turning on, the voltages of the second capacitor and the third capacitor are maintained at a high level voltage + the power supply voltage, and the voltage of the fourth capacitor is charged to the power supply voltage + twice the high level voltage, the third two The pole tube is turned off, the fourth diode is turned on, and the voltage of the fifth capacitor is charged to the power supply voltage + twice the high level voltage.
  • the array substrate row driving short circuit protection circuit further includes a level conversion module, the level conversion module includes an input end and an output end, and the input end is connected to the fourth diode negative electrode, the level The conversion module is configured to convert the driving voltage into a clock driving signal, and output from the output end, when a short circuit fault occurs at the output end, causing a flow through the first boosting module, the second boosting module, and The current signal of the level conversion module is increased, and the feedback current is correspondingly increased.
  • the control module detects that the feedback current exceeds the preset current threshold, the output of the pulse width modulation signal is cut off to trigger The first boosting module and the second boosting module enter a short circuit protection state.
  • the array substrate row driving short circuit protection circuit connects the transistor in series between the first boosting circuit and the second boosting circuit, and detects a base current of the transistor through the control module, when the electricity When a short circuit occurs at the output end of the flat conversion module to cause an increase in current, the base current exceeds a preset current threshold, thereby triggering the control module to cut off the output of the pulse width modulation signal to achieve short circuit protection, thereby preventing output When the current is short-circuited, the current is increased to burn out the liquid crystal panel, and the stability of the liquid crystal panel is improved.
  • FIG. 1 is a block diagram showing the structure of a row substrate short circuit protection circuit for an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of the row substrate short circuit protection circuit of the array substrate shown in FIG. 1.
  • an embodiment of the present invention provides an array substrate row driving short circuit protection circuit 100 for use in a Gate Driver on Array (GOA) liquid crystal panel to prevent a driving circuit in the GOA liquid crystal panel.
  • GOA Gate Driver on Array
  • the array substrate row driving short circuit protection circuit 100 includes a power module 10, a first boosting module 20, a feedback module 30, a second boosting module 40, and a control module 50, the power module 10, the first boosting module 20, The feedback module 30 and the second boosting module 40 are connected in series, and the control module 50 is electrically connected to the first boosting module 20, the feedback module 30, and the second boosting module 40, respectively.
  • the control module 50 is configured to output a pulse width modulation signal to control the first boosting module 20 and the second boosting module 40 to convert the power supply voltage into a driving voltage
  • the module 30 is configured to obtain a feedback current from a current signal flowing through the first boosting module and the second boosting module, and feed back the control current to the control module 50. When the feedback current exceeds a preset current threshold, the The control module 50 cuts off the output of the pulse width modulated signal to achieve short circuit protection.
  • the power module 10 includes a voltage output terminal 11 for outputting the power voltage VIN.
  • the first boosting module 20 and the second boosting module 40 together form a driving voltage VGH generating circuit to provide an opening voltage for a TFT transistor (not shown) in the liquid crystal panel driving circuit.
  • the control module 50 is a pulse width modulation (Pulse-Width) a Modulation (PWM) chip, which includes a PWM signal output terminal 51 and a feedback input terminal 53 for providing a PWM signal LX1 for controlling the first boosting module 20 and
  • the second boosting module 40 converts the power supply voltage VIN into the driving voltage VGH.
  • the feedback input 53 is configured to receive the feedback current obtained by the feedback module 30.
  • the feedback module 30 is a PNP transistor T1 connected in series between the first boosting module 20 and the second boosting module 40 to flow from the first boosting module 20 and the second The feedback current If is obtained from the current I of the boosting module 40.
  • the transistor T1 includes a base b, an emitter e, and a collector c.
  • the base b is connected to the feedback input terminal 53.
  • the emitter e and the first boosting module 20 are electrically connected.
  • the collector c is electrically connected to the second boosting module 40. It can be understood that the current flowing through the emitter e and the collector c of the transistor T1 is the current I flowing through the first boosting module 20 and the second boosting module 40, flowing through the emitter of the transistor T1.
  • the current of the base b and the base current b is the feedback current If. According to the amplification characteristic of the transistor, if the amplification factor of the transistor T1 is N times, the feedback current If is I/N.
  • the preset current threshold can be set to 1 mA, then When the short circuit fault occurs at the output end of the driving circuit of the GOA liquid crystal panel, the PWM chip detects that the feedback current is 1.5 mA, which is greater than the preset current threshold of 1 mA, thereby triggering the PWM chip to start a short circuit protection mechanism, and cutting off the The output of the pulse width modulation signal is described such that the first boosting module 20 and the second boosting module 40 enter a short circuit protection state. It can be understood that the preset current threshold may be set to a fixed value according to a
  • the first boosting module 20 includes a first diode D1, a second diode D2, a first capacitor C1, and a second capacitor C2.
  • the voltage output end 11 of the power module 10 is connected, the cathode of the first diode D1 is connected to the anode of the second diode D2, and the cathode of the second diode D2 is connected to the emitter e;
  • One end of the first capacitor C1 is connected to the negative pole of the first diode D1, and the other end is connected to the pulse width modulation signal output end 51.
  • One end of the second capacitor C2 is connected to the cathode of the second diode D2, and the other end is grounded.
  • the second boosting module 40 includes a third diode D3, a fourth diode 34, a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5.
  • a cathode of the diode D3 is connected to the collector c
  • a cathode of the third diode D3 is connected to the anode of the fourth diode D4, and one end of the third capacitor C3 is connected to the collector c
  • One end of the fourth capacitor C4 is connected to the negative terminal of the third diode D3, and the other end is connected to the pulse width modulation signal output end 51; one end of the fifth capacitor C5 and the fourth diode Tube D4 is connected to the negative pole and the other end is grounded.
  • the first boosting module 20 and the second boosting module 40 are respectively a first-stage charge pump and a second-stage charge pump of the VGH generating circuit, and the pulse width modulation signal output
  • the terminal 51 outputs a PWM signal LX1 of a specific duty ratio, and the first boosting module 20 and the second boosting module 40 convert the power supply voltage VIN into the driving under the control of the PWM signal LX1.
  • the voltage VGH is such that an opening voltage is supplied to a TFT transistor (not shown) in the liquid crystal panel driving circuit.
  • the high level voltage of the PWM signal LX1 is V1 and the low level voltage is zero
  • the first diode D1 and the second diode are D2
  • the third diode D3 and the fourth diode D4 are both turned on
  • the voltages of the first capacitor C1 to the fifth capacitor C5 are all charged to the power supply voltage VIN;
  • the PWM signal LX1 becomes high
  • the voltage of the first capacitor C1 is raised to V1+VIN
  • the first diode D1 is turned off
  • the second diode D2 is turned on
  • the voltage of the second capacitor C2 and the third capacitor C3 is turned on.
  • the third diode D3 and the fourth diode D4 are turned on, and the fourth capacitor C4 and the fifth capacitor C5 are both charged to V1+VIN; when the PWM When the signal LX1 changes to a low level again, the first diode D1 is turned on, the voltage of the first capacitor C1 is decreased to VIN, and the second diode D2 is turned off, and the second capacitor C2 is turned off.
  • the voltages of the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 are maintained as V1+VIN; when the PWM signal LX1 becomes high again, the voltage of the first capacitor C1 is charged to V1+VIN.
  • the first diode D1 is turned off, the second diode D2 is turned on, the voltages of the second capacitor C2 and the third capacitor C3 are maintained at V1+VIN, and the voltage of the fourth capacitor C4 is Being charged to V1+VIN+V1, the third diode D3 is turned off, the fourth diode D4 is turned on, and the voltage of the fifth capacitor C5 is charged to V1+VIN+V1, thereby obtaining
  • the driving voltage VGH is V1+VIN+V1, and the boosting effect is achieved.
  • the array substrate row drive short circuit protection circuit 100 further includes level shifting The module 60 is connected to the second boosting module 40 to obtain a clock driving signal CLK_OUT from the driving voltage VGH for the liquid crystal panel.
  • the level conversion module 60 includes an input terminal 61 and an output terminal 63.
  • the input terminal 61 is connected to the fourth diode D4, and the level conversion module 60 is configured to obtain the driving voltage VGH.
  • the clock drive signal CLK_OUT is output from the output terminal 63 to be supplied to the liquid crystal panel.
  • the control module 50 detects that the feedback current If exceeds the preset current threshold, the output of the pulse width modulation signal is cut off to trigger the first boosting module 20 and the second boosting module. 40 enters the short-circuit protection state, thereby effectively preventing the output current of the output terminal 63 from being excessively large to burn the liquid crystal panel.
  • the embodiment of the present invention further provides a liquid crystal panel, which comprises an array substrate row driving short circuit protection circuit, which is used to prevent the liquid crystal panel from causing an array substrate row driving circuit due to laminating or other process reasons.
  • a short-circuit fault occurs at the output end, the output current increases and the LCD panel burns out.
  • the specific structure and function of the row substrate short circuit protection circuit of the array substrate can be referred to the description in the embodiment shown in FIG. 1 and FIG. 2 , and details are not described herein again.
  • the array substrate row driving short circuit protection circuit connects the transistor in series between the first boosting circuit and the second boosting circuit, and detects a base current of the transistor through the control module, when the electricity When a short circuit occurs at the output end of the flat conversion module to cause an increase in current, the base current exceeds a preset current threshold, thereby triggering the control module to cut off the output of the pulse width modulation signal to achieve short circuit protection, thereby preventing output When the current is short-circuited, the current is increased to burn out the liquid crystal panel, and the stability of the liquid crystal panel is improved.

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Abstract

本发明提供一种阵列基板行驱动短路保护电路，包括电源模块、第一升压模块、反馈模块、第二升压模块及控制模块，所述电源模块、第一升压模块、反馈模块及第二升压模块依次串联连接，所述控制模块与所述第一升压模块、反馈模块及第二升压模块电性连接，所述电源模块用于提供电源电压，所述控制模块用于输出脉宽调制信号以控制所述第一升压模块和所述第二升压模块将所述电源电压转换为驱动电压，所述反馈模块用于获取反馈电流并反馈给所述控制模块，当所述反馈电流超过预设电流阈值时，所述控制模块切断所述脉宽调制信号的输出。本发明还提供一种液晶面板。所述阵列基板行驱动短路保护电路可实现短路保护，提升所述液晶面板的稳定性。

Description

阵列基板行驱动短路保护电路及液晶面板
本发明要求2015年8月7日递交的发明名称为“阵列基板行驱动短路保护电路及液晶面板”的申请号(201510478474.1)的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种阵列基板行驱动短路保护电路及液晶面板。
背景技术
阵列基板行驱动(Gate Driver on Array，GOA)技术是近年来兴起的一种新型液晶面板驱动技术，其把驱动液晶Gate信号的IC直接刻蚀在液晶面板上，省去了Gate Drive IC的成本和把IC绑定在液晶面板上的工序，更重要的是由于Gate Drive IC与液晶面板为一个整体，使得产品更薄、分辨率更高、稳定性和抗振性更好。目前，在液晶面板的GOA驱动电路中，大都使用电平转换电路(Level Shifter)来产生CLK_OUT信号给液晶面板使用。然而，在现有的GOA驱动电路中，CLK_OUT电流大多数是从PWM芯片产生的Gate Drive IC的开启电压VGH上抽取，由于液晶面板框胶不严或者其他制程原因，易造成Level Shifter的CLK_OUT输出短路，使得CLK_OUT电流增大，最终导致液晶面板烧坏，甚至引起火灾。
发明内容
鉴于现有技术中存在的上述问题，本发明提供一种阵列基板行驱动短路保护电路，以防止在阵列基板行驱动电路的输出端出现短路故障时，导致输出电流增大而烧坏液晶面板。
另，本发明还提供一种应用该阵列基板行驱动短路保护电路的液晶面板。
一种阵列基板行驱动短路保护电路，包括电源模块、第一升压模块、反馈模块、第二升压模块及控制模块，所述电源模块、第一升压模块、反馈模块及 第二升压模块依次串联连接，所述控制模块分别与所述第一升压模块、反馈模块及第二升压模块电性连接，所述电源模块用于提供电源电压，所述控制模块用于输出脉宽调制信号，以控制所述第一升压模块和所述第二升压模块将所述电源电压转换为驱动电压，所述反馈模块用于从流经所述第一升压模块及第二升压模块的电流信号中获取反馈电流并反馈给所述控制模块，当所述反馈电流超过预设电流阈值时，所述控制模块切断所述脉宽调制信号的输出，以实现短路保护。
其中，所述控制模块包括反馈输入端，所述反馈模块包括晶体管，所述晶体管包括基极、发射极和集电极，所述基极与所述反馈输入端连接，所述发射极与所述第一升压模块电性连接，所述集电极与所述第二升压模块电性连接。
其中，所述控制模块还包括脉宽调制信号输出端，所述第一升压模块包括第一二极管、第二二极管、第一电容及第二电容，所述第一二极管正极与所述电源模块连接，所述第一二极管负极与所述第二二极管正极连接，所述第二二极管负极与所述发射极连接；所述第一电容一端与所述第一二极管负极连接，另一端与所述脉宽调制信号输出端连接；所述第二电容一端与所述第二二极管负极连接，另一端接地。
其中，所述第二升压模块包括第三二极管、第四二极管、第三电容、第四电容及第五电容，所述第三二极管正极与所述集电极连接，所述第三二极管负极与所述第四二极管正极连接；所述第三电容一端与所述集电极连接，另一端接地；所述第四电容一端与所述第三二极管负极连接，另一端与所述脉宽调制信号输出端连接；所述第五电容一端与所述第四二极管负极连接，另一端接地。
其中，所述脉宽调制信号包括高电平和低电平两种状态，所述高电平对应输出高电平电压，所述低电平对应输出电压为零，当所述脉宽调制信号为低电平时，所述第一二极管、第二二极管、第三二极管及第四二极管均导通，所述第一电容第二电容、第三电容、第四电容及第五电容的电压均被充电至电源电压。
其中，当所述脉宽调制信号变为高电平时，所述第一电容的电压提升至高电平电压+电源电压，所述第一二极管截止，所述第二二极管导通，所述第二电容及第三电容的电压被充电至高电平电压+电源电压，则所述第三二极管及 第四二极管导通，同时所述第四电容及第五电容均被充电至高电平电压+电源电压。
其中，当所述脉宽调制信号再次变为低电平时，所述第一二极管导通，所述第一电容的电压下降为电源电压，则所述第二二极管截止，所述第二电容、第三电容、第四电容及第五电容的电压维持高电平电压+电源电压不变。
其中，当所述脉宽调制信号再次变为高电平时，所述第一电容的电压被充电至高电平电压+电源电压，则所述第一二极管截止，所述第二二极管导通，所述第二电容、第三电容的电压维持高电平电压+电源电压不变，所述第四电容的电压被充电至电源电压+两倍高电平电压，所述第三二极管截止，所述第四二极管导通，所述第五电容的电压被充电至电源电压+两倍高电平电压。
其中，所述电路还包括电平转换模块，所述电平转换模块包括输入端及输出端，所述输入端与所述第四二极管负极连接，所述电平转换模块用于将所述驱动电压转换为时钟驱动信号，并从所述输出端输出，当所述输出端出现短路故障时，导致流经所述第一升压模块、第二升压模块及电平转换模块的电流信号增大，所述反馈电流对应增大，当所述控制模块检测到所述反馈电流超过所述预设电流阈值时，切断所述脉宽调制信号的输出，以触发所述第一升压模块及第二升压模块进入短路保护状态。
一种液晶面板，包括阵列基板行驱动短路保护电路，所述阵列基板行驱动短路保护电路包括电源模块、第一升压模块、反馈模块、第二升压模块及控制模块，所述电源模块、第一升压模块、反馈模块及第二升压模块依次串联连接，所述控制模块分别与所述第一升压模块、反馈模块及第二升压模块电性连接，所述电源模块用于提供电源电压，所述控制模块用于输出脉宽调制信号，以控制所述第一升压模块和所述第二升压模块将所述电源电压转换为驱动电压，所述反馈模块用于从流经所述第一升压模块及第二升压模块的电流信号中获取反馈电流并反馈给所述控制模块，当所述反馈电流超过预设电流阈值时，所述控制模块切断所述脉宽调制信号的输出，以实现短路保护。
其中，所述控制模块包括反馈输入端，所述反馈模块包括晶体管，所述晶体管包括基极、发射极和集电极，所述基极与所述反馈输入端连接，所述发射极与所述第一升压模块电性连接，所述集电极与所述第二升压模块电性连接。
其中，所述控制模块还包括脉宽调制信号输出端，所述第一升压模块包括第一二极管、第二二极管、第一电容及第二电容，所述第一二极管正极与所述电源模块连接，所述第一二极管负极与所述第二二极管正极连接，所述第二二极管负极与所述发射极连接；所述第一电容一端与所述第一二极管负极连接，另一端与所述脉宽调制信号输出端连接；所述第二电容一端与所述第二二极管负极连接，另一端接地。
其中，所述第二升压模块包括第三二极管、第四二极管、第三电容、第四电容及第五电容，所述第三二极管正极与所述集电极连接，所述第三二极管负极与所述第四二极管正极连接；所述第三电容一端与所述集电极连接，另一端接地；所述第四电容一端与所述第三二极管负极连接，另一端与所述脉宽调制信号输出端连接；所述第五电容一端与所述第四二极管负极连接，另一端接地。
其中，所述脉宽调制信号包括高电平和低电平两种状态，所述高电平对应输出高电平电压，所述低电平对应输出电压为零，当所述脉宽调制信号为低电平时，所述第一二极管、第二二极管、第三二极管及第四二极管均导通，所述第一电容第二电容、第三电容、第四电容及第五电容的电压均被充电至电源电压。
其中，当所述脉宽调制信号变为高电平时，所述第一电容的电压提升至高电平电压+电源电压，所述第一二极管截止，所述第二二极管导通，所述第二电容及第三电容的电压被充电至高电平电压+电源电压，则所述第三二极管及第四二极管导通，同时所述第四电容及第五电容均被充电至高电平电压+电源电压。
其中，当所述脉宽调制信号再次变为低电平时，所述第一二极管导通，所述第一电容的电压下降为电源电压，则所述第二二极管截止，所述第二电容、第三电容、第四电容及第五电容的电压维持高电平电压+电源电压不变。
其中，当所述脉宽调制信号再次变为高电平时，所述第一电容的电压被充电至高电平电压+电源电压，则所述第一二极管截止，所述第二二极管导通，所述第二电容、第三电容的电压维持高电平电压+电源电压不变，所述第四电容的电压被充电至电源电压+两倍高电平电压，所述第三二极管截止，所述第四二极管导通，所述第五电容的电压被充电至电源电压+两倍高电平电压。
其中，所述阵列基板行驱动短路保护电路还包括电平转换模块，所述电平转换模块包括输入端及输出端，所述输入端与所述第四二极管负极连接，所述电平转换模块用于将所述驱动电压转换为时钟驱动信号，并从所述输出端输出，当所述输出端出现短路故障时，导致流经所述第一升压模块、第二升压模块及电平转换模块的电流信号增大，所述反馈电流对应增大，当所述控制模块检测到所述反馈电流超过所述预设电流阈值时，切断所述脉宽调制信号的输出，以触发所述第一升压模块及第二升压模块进入短路保护状态。
所述阵列基板行驱动短路保护电路通过在所述第一升压电路和第二升压电路之间串联所述晶体管，并通过所述控制模块检测所述晶体管的基极电流，当所述电平转换模块的输出端出现短路而导致电流增大时，所述基极电流超过预设电流阈值，从而触发所述控制模块切断所述脉宽调制信号的输出，实现短路保护，从而防止因输出短路时电流增大而烧坏液晶面板，提升所述液晶面板的稳定性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明施例提供的阵列基板行驱动短路保护电路的模块结构示意图。
图2是图1所示阵列基板行驱动短路保护电路的原理图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
可以理解，当一个元件与另一个元件“连接”或“电性连接”时，它可以 一个元件直接连接到另一元件，或者可以存在居间元件。可以理解，这里所用的术语仅是为了描述特定实施例，并非要限制本发明。在这里使用时，除非上下文另有明确表述，否则单数形式“一”和“该”也旨在包括复数形式。进一步地，当在本说明书中使用时，术语“包括”和/或“包含”表明所述特征、整体、步骤、操作、元件和/或组件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、组件和/或其组合的存在或增加。
除非另行定义，这里使用的所有术语(包括技术术语和科学术语)都具有本发明所属领域内的普通技术人员所通常理解的相同含义，即，诸如通用词典中所定义的术语，应当被解释为具有与它们在相关领域的语境中的含义相一致的含义，而不应被解释为理想化或过度形式化的意义，除非在说明书中有明确地另行定义。
请参阅图1，本发明施例提供一种阵列基板行驱动短路保护电路100，应用与阵列基板行驱动(Gate Driver on Array，GOA)液晶面板中，以防止在所述GOA液晶面板的驱动电路输出端出现短路故障时，导致输出电流增大而烧坏所述液晶面板，提升液晶面板的稳定性。
所述阵列基板行驱动短路保护电路100包括电源模块10、第一升压模块20、反馈模块30、第二升压模块40及控制模块50，所述电源模块10、第一升压模块20、反馈模块30及第二升压模块40依次串联连接，所述控制模块50分别与所述第一升压模块20、反馈模块30及第二升压模块40电性连接，所述电源模块10用于提供电源电压，所述控制模块50用于输出脉宽调制信号，以控制所述第一升压模块20和所述第二升压模块40将所述电源电压转换为驱动电压，所述反馈模块30用于从流经所述第一升压模块及第二升压模块的电流信号中获取反馈电流并反馈给所述控制模块50，当所述反馈电流超过预设电流阈值时，所述控制模块50切断所述脉宽调制信号的输出，以实现短路保护。
请一并参阅图2，在本实施例中，所述电源模块10包括电压输出端11，用于输出所述电源电压VIN。所述第一升压模块20及第二升压模块40共同形成一个驱动电压VGH产生电路，以为所述液晶面板驱动电路中的TFT晶体管(图未示)提供开启电压。所述控制模块50为一脉宽调制(Pulse-Width  Modulation，PWM)芯片，其包括PWM信号输出端51及反馈输入端53，所述PWM信号输出端51用于提供PWM信号LX1，所述PWM信号LX1用于控制所述第一升压模块20和所述第二升压模块40将所述电源电压VIN转换为所述驱动电压VGH。所述反馈输入端53用于接收所述反馈模块30获取的反馈电流。所述反馈模块30为一PNP型晶体管T1，其串联于所述第一升压模块20和所述第二升压模块40之间，以从流经所述第一升压模块20及第二升压模块40的电流I中获取反馈电流If。
具体地，所述晶体管T1包括基极b、发射极e和集电极c，所述基极b与所述反馈输入端53连接，所述发射极e与所述第一升压模块20电性连接，所述集电极c与所述第二升压模块40电性连接。可以理解，流经所述晶体管T1发射极e和集电极c的电流即为流经所述第一升压模块20及第二升压模块40的电流I，流经所述晶体管T1发射极e和基极b的电流即为所述反馈电流If。根据所述晶体管的放大特性，若所述晶体管T1的放大倍数为N倍，则所述反馈电流If即为I/N。
在本实施例中，假设所述晶体管T1的放大倍数为100倍，所述VGH产生电路的正常输出电流为50mA，则对应的反馈电流为0.5mA；假设所述GOA液晶面板的驱动电路输出端出现短路故障时，所述VGH产生电路的输出电流增大为150mA，则对应的反馈电流为1.5mA；因此，在所述假设条件下，可设置所述预设电流阈值为1mA，则当所述GOA液晶面板的驱动电路输出端出现短路故障时，所述PWM芯片检测到所述反馈电流为1.5mA，大于所述预设电流阈值1mA，从而触发所述PWM芯片启动短路保护机制，切断所述脉宽调制信号的输出，以使所述第一升压模块20及第二升压模块40进入短路保护状态。可以理解，所述预设电流阈值可根据所述液晶面板的驱动特性设置为固定值，也可通过寄存器来调整大小。
在可选实施例中，所述第一升压模块20包括第一二极管D1、第二二极管D2、第一电容C1及第二电容C2，所述第一二极管D1正极与所述电源模块10的电压输出端11连接，所述第一二极管D1负极与所述第二二极管D2正极连接，所述第二二极管D2负极与所述发射极e连接；所述第一电容C1一端与所述第一二极管D1负极连接，另一端与所述脉宽调制信号输出端51连 接；所述第二电容C2一端与所述第二二极管D2负极连接，另一端接地。
在可选实施例中，所述第二升压模块40包括第三二极管D3、第四二极管34、第三电容C3、第四电容C4及第五电容C5，所述第三二极管D3正极与所述集电极c连接，所述第三二极管D3负极与所述第四二极管D4正极连接；所述第三电容C3一端与所述集电c极连接，另一端接地；所述第四电容C4一端与所述第三二极管D3负极连接，另一端与所述脉宽调制信号输出端51连接；所述第五电容C5一端与所述第四二极管D4负极连接，另一端接地。
在本实施例中，所述第一升压模块20及所述第二升压模块40分别为所述VGH产生电路的第一级电荷泵及第二级电荷泵，所述脉宽调制信号输出端51输出特定占空比的PWM信号LX1，所述第一升压模块20及所述第二升压模块40在所述PWM信号LX1的控制下，将所述电源电压VIN转换为所述驱动电压VGH，以为所述液晶面板驱动电路中的TFT晶体管(图未示)提供开启电压。具体地，假设所述PWM信号LX1的高电平电压为V1，低电平电压为零，则当所述PWM信号LX1为低电平时，所述第一二极管D1、第二二极管D2、第三二极管D3及第四二极管D4均导通，所述第一电容C1至第五电容C5的电压均被充电至电源电压VIN；当所述PWM信号LX1变为高电平时，所述第一电容C1的电压提升至V1+VIN，所述第一二极管D1截止，所述第二二极管D2导通，所述第二电容C2及第三电容C3的电压被充电至V1+VIN，则所述第三二极管D3及第四二极管D4导通，同时所述第四电容C4及第五电容C5均被充电至V1+VIN；当所述PWM信号LX1再次变为低电平时，所述第一二极管D1导通，所述第一电容C1的电压下降为VIN，则所述第二二极管D2截止，所述第二电容C2、第三电容C3、第四电容C4及第五电容C5的电压维持V1+VIN不变；当所述PWM信号LX1再次变为高电平时，所述第一电容C1的电压被充电至V1+VIN，则所述第一二极管D1截止，所述第二二极管D2导通，所述第二电容C2、第三电容C3的电压维持V1+VIN不变，所述第四电容C4的电压被充电至V1+VIN+V1，所述第三二极管D3截止，所述第四二极管D4导通，所述第五电容C5的电压被充电至V1+VIN+V1，从而得到所述驱动电压VGH为V1+VIN+V1，达到升压效果。
在可选实施例中，所述阵列基板行驱动短路保护电路100还包括电平转换 模块60，所述电平转换模块60与所述第二升压模块40连接，以从所述驱动电压VGH中获取时钟驱动信号CLK_OUT提供给所述液晶面板。
所述电平转换模块60包括输入端61及输出端63，所述输入端61与所述第四二极管D4负极连接，所述电平转换模块60用于从所述驱动电压VGH中获取时钟驱动信号CLK_OUT，并从所述输出端63输出，以提供给所述液晶面板。当所述输出端63出现短路故障时，会导致流经所述第一升压模块20、第二升压模块40及电平转换模块60的电流I增大，则所述反馈电流If对应增大，当所述控制模块50检测到所述反馈电流If超过所述预设电流阈值时，切断所述脉宽调制信号的输出，以触发所述第一升压模块20及第二升压模块40进入短路保护状态，从而有效防止所述输出端63输出电流过大而烧毁所述液晶面板。
另，本发明实施例还提供一种液晶面板，所述液晶面板包括阵列基板行驱动短路保护电路，用于防止在所述液晶面板因框胶不严或者其他制程原因而使得阵列基板行驱动电路的输出端出现短路故障时，导致输出电流增大而烧坏液晶面板。其中，所述阵列基板行驱动短路保护电路的具体结构及功能可参考所述如图1和图2所示实施例中的描述，此处不再赘述。
所述阵列基板行驱动短路保护电路通过在所述第一升压电路和第二升压电路之间串联所述晶体管，并通过所述控制模块检测所述晶体管的基极电流，当所述电平转换模块的输出端出现短路而导致电流增大时，所述基极电流超过预设电流阈值，从而触发所述控制模块切断所述脉宽调制信号的输出，实现短路保护，从而防止因输出短路时电流增大而烧坏液晶面板，提升所述液晶面板的稳定性。
以上所揭露的仅为本发明的较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (18)

  1. 一种阵列基板行驱动短路保护电路，其中，所述电路包括电源模块、第一升压模块、反馈模块、第二升压模块及控制模块，所述电源模块、第一升压模块、反馈模块及第二升压模块依次串联连接，所述控制模块分别与所述第一升压模块、反馈模块及第二升压模块电性连接，所述电源模块用于提供电源电压，所述控制模块用于输出脉宽调制信号，以控制所述第一升压模块和所述第二升压模块将所述电源电压转换为驱动电压，所述反馈模块用于从流经所述第一升压模块及第二升压模块的电流信号中获取反馈电流并反馈给所述控制模块，当所述反馈电流超过预设电流阈值时，所述控制模块切断所述脉宽调制信号的输出，以实现短路保护。
  2. 如权利要求1所述的阵列基板行驱动短路保护电路，其中，所述控制模块包括反馈输入端，所述反馈模块包括晶体管，所述晶体管包括基极、发射极和集电极，所述基极与所述反馈输入端连接，所述发射极与所述第一升压模块电性连接，所述集电极与所述第二升压模块电性连接。
  3. 如权利要求2所述的阵列基板行驱动短路保护电路，其中，所述控制模块还包括脉宽调制信号输出端，所述第一升压模块包括第一二极管、第二二极管、第一电容及第二电容，所述第一二极管正极与所述电源模块连接，所述第一二极管负极与所述第二二极管正极连接，所述第二二极管负极与所述发射极连接；所述第一电容一端与所述第一二极管负极连接，另一端与所述脉宽调制信号输出端连接；所述第二电容一端与所述第二二极管负极连接，另一端接地。
  4. 如权利要求3所述的阵列基板行驱动短路保护电路，其中，所述第二升压模块包括第三二极管、第四二极管、第三电容、第四电容及第五电容，所述第三二极管正极与所述集电极连接，所述第三二极管负极与所述第四二极管正极连接；所述第三电容一端与所述集电极连接，另一端接地；所述第四电容一端与所述第三二极管负极连接，另一端与所述脉宽调制信号输出端连接；所述第五电容一端与所述第四二极管负极连接，另一端接地。
  5. 如权利要求4所述的阵列基板行驱动短路保护电路，其中，所述脉宽 调制信号包括高电平和低电平两种状态，所述高电平对应输出高电平电压，所述低电平对应输出电压为零，当所述脉宽调制信号为低电平时，所述第一二极管、第二二极管、第三二极管及第四二极管均导通，所述第一电容第二电容、第三电容、第四电容及第五电容的电压均被充电至电源电压。
  6. 如权利要求5所述的阵列基板行驱动短路保护电路，其中，当所述脉宽调制信号变为高电平时，所述第一电容的电压提升至高电平电压+电源电压，所述第一二极管截止，所述第二二极管导通，所述第二电容及第三电容的电压被充电至高电平电压+电源电压，则所述第三二极管及第四二极管导通，同时所述第四电容及第五电容均被充电至高电平电压+电源电压。
  7. 如权利要求6所述的阵列基板行驱动短路保护电路，其中，当所述脉宽调制信号再次变为低电平时，所述第一二极管导通，所述第一电容的电压下降为电源电压，则所述第二二极管截止，所述第二电容、第三电容、第四电容及第五电容的电压维持高电平电压+电源电压不变。
  8. 如权利要求7所述的阵列基板行驱动短路保护电路，其中，当所述脉宽调制信号再次变为高电平时，所述第一电容的电压被充电至高电平电压+电源电压，则所述第一二极管截止，所述第二二极管导通，所述第二电容、第三电容的电压维持高电平电压+电源电压不变，所述第四电容的电压被充电至电源电压+两倍高电平电压，所述第三二极管截止，所述第四二极管导通，所述第五电容的电压被充电至电源电压+两倍高电平电压。
  9. 如权利要求4所述的阵列基板行驱动短路保护电路，其中，所述电路还包括电平转换模块，所述电平转换模块包括输入端及输出端，所述输入端与所述第四二极管负极连接，所述电平转换模块用于将所述驱动电压转换为时钟驱动信号，并从所述输出端输出，当所述输出端出现短路故障时，导致流经所述第一升压模块、第二升压模块及电平转换模块的电流信号增大，所述反馈电流对应增大，当所述控制模块检测到所述反馈电流超过所述预设电流阈值时，切断所述脉宽调制信号的输出，以触发所述第一升压模块及第二升压模块进入短路保护状态。
  10. 一种液晶面板，其中，所述液晶面板包括阵列基板行驱动短路保护电路，所述阵列基板行驱动短路保护电路包括电源模块、第一升压模块、反馈模 块、第二升压模块及控制模块，所述电源模块、第一升压模块、反馈模块及第二升压模块依次串联连接，所述控制模块分别与所述第一升压模块、反馈模块及第二升压模块电性连接，所述电源模块用于提供电源电压，所述控制模块用于输出脉宽调制信号，以控制所述第一升压模块和所述第二升压模块将所述电源电压转换为驱动电压，所述反馈模块用于从流经所述第一升压模块及第二升压模块的电流信号中获取反馈电流并反馈给所述控制模块，当所述反馈电流超过预设电流阈值时，所述控制模块切断所述脉宽调制信号的输出，以实现短路保护。
  11. 如权利要求10所述的液晶面板，其中，所述控制模块包括反馈输入端，所述反馈模块包括晶体管，所述晶体管包括基极、发射极和集电极，所述基极与所述反馈输入端连接，所述发射极与所述第一升压模块电性连接，所述集电极与所述第二升压模块电性连接。
  12. 如权利要求11所述的液晶面板，其中，所述控制模块还包括脉宽调制信号输出端，所述第一升压模块包括第一二极管、第二二极管、第一电容及第二电容，所述第一二极管正极与所述电源模块连接，所述第一二极管负极与所述第二二极管正极连接，所述第二二极管负极与所述发射极连接；所述第一电容一端与所述第一二极管负极连接，另一端与所述脉宽调制信号输出端连接；所述第二电容一端与所述第二二极管负极连接，另一端接地。
  13. 如权利要求12所述的液晶面板，其中，所述第二升压模块包括第三二极管、第四二极管、第三电容、第四电容及第五电容，所述第三二极管正极与所述集电极连接，所述第三二极管负极与所述第四二极管正极连接；所述第三电容一端与所述集电极连接，另一端接地；所述第四电容一端与所述第三二极管负极连接，另一端与所述脉宽调制信号输出端连接；所述第五电容一端与所述第四二极管负极连接，另一端接地。
  14. 如权利要求13所述的液晶面板，其中，所述脉宽调制信号包括高电平和低电平两种状态，所述高电平对应输出高电平电压，所述低电平对应输出电压为零，当所述脉宽调制信号为低电平时，所述第一二极管、第二二极管、第三二极管及第四二极管均导通，所述第一电容第二电容、第三电容、第四电容及第五电容的电压均被充电至电源电压。
  15. 如权利要求14所述的液晶面板，其中，当所述脉宽调制信号变为高电平时，所述第一电容的电压提升至高电平电压+电源电压，所述第一二极管截止，所述第二二极管导通，所述第二电容及第三电容的电压被充电至高电平电压+电源电压，则所述第三二极管及第四二极管导通，同时所述第四电容及第五电容均被充电至高电平电压+电源电压。
  16. 如权利要求15所述的液晶面板，其中，当所述脉宽调制信号再次变为低电平时，所述第一二极管导通，所述第一电容的电压下降为电源电压，则所述第二二极管截止，所述第二电容、第三电容、第四电容及第五电容的电压维持高电平电压+电源电压不变。
  17. 如权利要求16所述的液晶面板，其中，当所述脉宽调制信号再次变为高电平时，所述第一电容的电压被充电至高电平电压+电源电压，则所述第一二极管截止，所述第二二极管导通，所述第二电容、第三电容的电压维持高电平电压+电源电压不变，所述第四电容的电压被充电至电源电压+两倍高电平电压，所述第三二极管截止，所述第四二极管导通，所述第五电容的电压被充电至电源电压+两倍高电平电压。
  18. 如权利要求13所述的液晶面板，其中，所述阵列基板行驱动短路保护电路还包括电平转换模块，所述电平转换模块包括输入端及输出端，所述输入端与所述第四二极管负极连接，所述电平转换模块用于将所述驱动电压转换为时钟驱动信号，并从所述输出端输出，当所述输出端出现短路故障时，导致流经所述第一升压模块、第二升压模块及电平转换模块的电流信号增大，所述反馈电流对应增大，当所述控制模块检测到所述反馈电流超过所述预设电流阈值时，切断所述脉宽调制信号的输出，以触发所述第一升压模块及第二升压模块进入短路保护状态。
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