WO2017020590A1 - 一种芯片验证方法和装置、设备、存储介质 - Google Patents

一种芯片验证方法和装置、设备、存储介质 Download PDF

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WO2017020590A1
WO2017020590A1 PCT/CN2016/076547 CN2016076547W WO2017020590A1 WO 2017020590 A1 WO2017020590 A1 WO 2017020590A1 CN 2016076547 W CN2016076547 W CN 2016076547W WO 2017020590 A1 WO2017020590 A1 WO 2017020590A1
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vector
output vector
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任庆昆
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深圳市中兴微电子技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software

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  • the present invention relates to a chip verification technology, and in particular, to a chip verification method and apparatus, device, and storage medium.
  • the chip verification work needs to ensure the integrity of the verification test scenario coverage.
  • the commonly used chip verification schemes use random seeds and custom constraint rules to generate massive, continuous, batch-by-batch random excitation vectors. Then, the random excitation vectors are respectively input into the object to be verified and the standard model, respectively Corresponding to the response vector of the object to be verified and the output vector of the standard model; comparing the response vector with the output vector to determine whether an abnormality has occurred.
  • the random seed is re-entered into the object to be verified, and the entire verification process is repeated again to implement the abnormal reproduction.
  • the embodiments of the present invention are expected to provide a chip verification method and device, device, and storage medium, which improve the accuracy and efficiency of the chip verification solution.
  • an embodiment of the present invention provides a chip verification method, where the method includes:
  • excitation vectors generated according to the preset generation mechanism are respectively input to the object to be verified and the standard model, and the corresponding output vector to be verified and the reference output vector are obtained;
  • the object to be verified is determined to be abnormal, and the excitation vector is re-inputted to the object to be verified for abnormal scene reproduction.
  • the excitation vector generated according to the preset generation mechanism includes: an excitation vector generated to represent the scene data according to a preset random seed and a constraint rule.
  • the method further includes:
  • the method when the comparing the to-be-verified output vector and the reference output vector, the method further comprises: saving the excitation vector.
  • an embodiment of the present invention provides a chip verification apparatus, where the apparatus includes: a generating unit, an input unit, an object to be verified, a standard model unit, a comparing unit, and a feedback unit;
  • the generating unit is configured to generate an excitation vector according to a preset generation mechanism, and transmit the signal to the input unit;
  • An input unit configured to input an excitation vector transmitted by the generating unit to the object to be verified and the standard model unit, respectively;
  • the object to be verified is configured to generate a corresponding output vector to be verified according to the excitation vector
  • the standard model unit is configured to generate a corresponding reference output vector according to the excitation vector
  • the comparing unit is configured to compare the output vector to be verified with the reference output vector; and trigger the feedback unit when the output vector to be verified is inconsistent with the reference output vector;
  • the feedback unit is configured to determine that the object to be verified is abnormal, and retransmit the excitation vector to the input unit;
  • the input unit is further configured to re-enter the excitation vector re-entered by the feedback unit to the object to be verified to perform an abnormal scene reproduction.
  • the generating unit is configured to generate an excitation vector for characterizing the scene data according to a preset random seed and a constraint rule.
  • the device further includes a discarding unit
  • the comparing unit is further configured to trigger the discarding unit when the output vector to be verified and the reference output vector are consistent;
  • the discarding unit is configured to determine that the object to be verified is normal, and discard the excitation vector.
  • the apparatus further comprises a saving unit configured to save the excitation vector.
  • an embodiment of the present invention provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the chip verification method described in the foregoing first embodiment.
  • an embodiment of the present invention provides a chip verification device, where the chip verification device includes:
  • a storage medium configured to store computer executable instructions
  • a processor configured to execute computer executable instructions stored on the storage medium, the computer executable instructions comprising: inputting an excitation vector generated according to a preset generation mechanism to an object to be verified and a standard model, respectively, to obtain a corresponding Output vector and reference output to be verified Comparing the output vector to be verified with the reference output vector; when the output vector to be verified is inconsistent with the reference output vector, determining an abnormality of the object to be verified, and re-entering the excitation vector The object to be verified is reproduced for the abnormal scene.
  • the embodiment of the invention provides a chip verification method and device, device and storage medium, which can save the random seed by saving the excitation vector generated by the random seed, so that the verification can be performed when the abnormality is verified.
  • the vector performs the recurrence of the abnormal scene, which improves the accuracy and efficiency of the chip verification scheme.
  • FIG. 1 is a schematic flowchart of a chip verification method according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a chip verification apparatus according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of another chip verification apparatus according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a UVM architecture for chip verification according to an embodiment of the present invention.
  • the basic idea of the embodiment of the present invention is to save the random seed by saving the excitation vector generated by the random seed in the chip verification process, so that the abnormality scene can be performed by the excitation vector when the abnormality is verified. Recurrence avoids the inaccuracy and inefficiency caused by scene replay by random seeds.
  • a chip verification method according to an embodiment of the present invention is provided.
  • the method is applied to a chip verification device, and the chip verification device can be any electronic device with computing capability.
  • the chip verification device may be implemented as a personal computer (PC), an integrated server, or the like.
  • the functions implemented by the method can be implemented by the processor calling program code in the chip verification device.
  • the program code can be saved in a computer storage medium.
  • the chip verification device includes at least a processor and a storage medium.
  • the method can include:
  • S101 input the excitation vectors generated according to the preset generation mechanism to the object to be verified and the standard model, respectively, and obtain a corresponding output vector to be verified and a reference output vector;
  • the excitation vector generated according to the preset generation mechanism includes: an excitation vector generated to represent the scene data according to a preset random seed and a constraint rule; specifically, may be specified according to a verification engineer or automatically generated by the system.
  • the random seed and the verification rules customized by the verification engineer generate a massive, continuous, batch-based random excitation vector, and generate a packaging unit corresponding to the random excitation vector, thereby enabling the packaging unit to characterize a completely independent verification scenario.
  • the excitation vector may also be saved for subsequent re Enter or discard the processing.
  • the encapsulation unit corresponding to the random excitation vector may be saved as a snapshot file by a file write operation for subsequent operations; correspondingly, when the output vector to be verified is inconsistent with the reference output vector, the file read operation may be performed. , reading the snapshot file, and restoring the snapshot file to a package unit corresponding to the corresponding random excitation vector and re-entering, thereby implementing the scenario Precise reproduction.
  • the embodiment of the present invention may continue to execute S101: input the excitation vector generated according to the preset generation mechanism to the object to be verified and the standard model respectively, and obtain Corresponding output vector to be verified and reference output vector; thus performing a subsequent verification process.
  • the random excitation vector that is snapshotted can be re-entered, and it is not necessary to follow the constraint rule to consume the lengthy simulation time to perform the reproduction according to the random seed. Since the excitation vector itself is saved instead of the excitation vector generation mechanism, such as random seed and constraint mechanism, the uniqueness and certainty of scene reproduction can be realized in different simulation server environments.
  • the embodiment of the invention provides a chip verification method, which saves the random seed by saving the excitation vector generated by the random seed, so that the abnormal scene can be reproduced by the excitation vector when the abnormality is verified. Improve the accuracy and efficiency of the chip verification solution.
  • the apparatus 20 includes: a generating unit 201, an input unit 202, an object to be verified 203, and a standard. Model unit 204, comparison unit 205, feedback unit 206; wherein
  • the generating unit 201 is configured to generate an excitation vector according to a preset generation mechanism, and transmit the signal to the input unit 202;
  • the input unit 202 is configured to input the excitation vectors transmitted by the generating unit 201 to the object to be verified 203 and the standard model unit 204, respectively;
  • the object to be verified 203 is configured to generate a corresponding output vector to be verified according to the excitation vector
  • a standard model unit 204 configured to generate a corresponding reference output vector according to the excitation vector
  • the comparing unit 205 is configured to compare the output vector to be verified with the reference output vector; and when the output vector to be verified is inconsistent with the reference output vector, the feedback unit 206 is triggered;
  • the feedback unit 206 is configured to determine that the object to be verified 203 is abnormal, and retransmit the excitation vector to the input unit 202;
  • the input unit 202 is further configured to re-enter the excitation vector re-inputted by the feedback unit 206 to the object to be verified 203 for abnormal scene reproduction.
  • the generating unit 201 is configured to generate an excitation vector for characterizing the scene data according to a preset random seed and constraint rule.
  • the device 20 further includes a discarding unit 207;
  • the comparing unit 205 is further configured to trigger the discarding unit 207 when the output vector to be verified and the reference output vector are consistent;
  • the discarding unit 207 is configured to determine that the object to be verified 203 is normal, and discard the excitation vector.
  • apparatus 30 further includes a save unit 208 configured to save the excitation vector.
  • FIG. 4 is a schematic diagram of a UVM architecture for chip verification according to an embodiment of the present invention. It can be understood that FIG. 4 is only used to explain the technical solutions of the embodiments of the present invention, and those skilled in the art can obtain more different UVM architecture diagrams according to the embodiment of the present invention and the enlightenment of FIG. 4, which is implemented by the present invention. For example, as shown in FIG.
  • the UVM architecture may include: a random excitation vector generator (random_uvm_sequence), a recurring vector generator (debug_uvm_sequence), a switch, a vector driver (uvm_driver), Validation object (DUV, Design Under Verification), DUV input interface, DUV output interface, input sampler (uvm_monitor for input), output sampler (uvm_monitor for output), standard reference Model (reference_model) and anomaly detector (uvm_scoreboard).
  • the UVM architecture is installed on a personal computer. During the verification process of the chip, the chip verification engineer calls the modules provided by the above UVM architecture to verify the chip by writing program code.
  • random_uvm_sequence can generate a large number of random excitation vectors according to the generation mechanism of random seed + constraint rules
  • Debug_uvm_sequence is connected to uvm_scoreboard, and the excitation vector that causes the exception is obtained from uvm_scoreboard;
  • the switch configuration determines whether to select debug_uvm_sequence to achieve rapid recurrence of the scene, or select random_uvm_sequence to complete the normal verification process;
  • Uvm_driver is configured to push the excitation vector of random_uvm_sequence or debug_uvm_sequence to the DUV through the DUV input interface;
  • Uvm_monitor for input obtains the excitation vector pushed into the DUV through the DUV input interface, and transmits the excitation vector to the reference_model and uvm_scoreboard respectively;
  • Uvm_monitor for output obtains the output vector to be verified generated by DUV according to the excitation vector through the DUV output interface, and transmits the output vector to be verified to uvm_scoreboard;
  • the reference_model is configured to generate a standard output vector from the standard reference model and the excitation vector; and transmit the standard output vector to the uvm_scoreboard;
  • Uvm_scoreboard is configured to compare the output vector to be verified with the standard output vector. When the two are consistent, it is determined that no abnormality occurs, and the excitation vector transmitted by uvm_monitor for input is discarded, and the switch is set to select random_uvm_sequence to complete the normal verification process; When the two are inconsistent, it is determined that an abnormality occurs, and the excitation vector transmitted by uvm_monitor for input is transmitted to debug_uvm_sequence, and the switch is set to select debug_uvm_sequence to realize rapid scene recurrence.
  • the embodiment of the present invention provides a chip verification apparatus 20, which saves the random seed by saving the excitation vector generated by the random seed, so that the abnormal scene can be reproduced by the excitation vector when the abnormality is verified. Improve the accuracy and efficiency of the chip verification solution.
  • Each unit included in the chip verification apparatus in the embodiment of the present invention may be implemented by a processor in the chip verification device.
  • the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA). )Wait.
  • the chip verification method described above is implemented in the form of a software function module and sold or used as a stand-alone product, it may also be stored in a computer readable storage medium.
  • the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions.
  • a computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk.
  • program codes such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk.
  • an embodiment of the present invention further provides a computer storage medium, where the computer stores Computer-executable instructions are stored in the medium for executing the chip verification method in the embodiments of the present invention.
  • an embodiment of the present invention provides a chip verification device, where the device includes:
  • a storage medium configured to store computer executable instructions
  • a processor configured to execute computer executable instructions stored on the storage medium, the computer executable instructions comprising: inputting an excitation vector generated according to a preset generation mechanism to an object to be verified and a standard model, respectively, to obtain a corresponding An output vector to be verified and a reference output vector; comparing the output vector to be verified with the reference output vector; when the output vector to be verified is inconsistent with the reference output vector, determining that the object to be verified is abnormal, and The excitation vector is re-inputted to the object to be verified for abnormal scene reproduction.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • These computer program instructions can also be stored in a bootable computer or other programmable data processing
  • the apparatus is readable in a computer readable memory in a particular manner such that instructions stored in the computer readable memory produce an article of manufacture comprising instruction means implemented in one or more flows and/or block diagrams of the flowchart The function specified in the box or in multiple boxes.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

一种芯片验证方法和装置、设备、存储介质，该方法可以包括：将按照预设生成机制生成的激励矢量分别输入至待验证对象和标准模型，获取对应的待验证输出矢量和参照输出矢量（S101）；将所述待验证输出矢量和所述参照输出矢量进行比较（S102）；当所述待验证输出矢量与参照输出矢量之间不一致时，确定所述待验证对象异常，并将所述激励矢量重新输入至待验证对象进行异常场景复现（S103）。

Description

一种芯片验证方法和装置、设备、存储介质 技术领域
本发明涉及芯片验证技术，尤其涉及一种芯片验证方法和装置、设备、存储介质。
背景技术
芯片验证工作需要保证验证测试场景覆盖的完整性。目前常用的芯片验证方案均采用随机种子以及定制的约束规则来生成海量的、连续不断的、分批次的随机激励矢量，随后，将该随机激励矢量分别输入待验证对象和标准模型，从而分别对应得到待验证对象的响应矢量和标准模型的输出矢量；将响应矢量和输出矢量进行比较，来确定是否出现异常。当出现异常时，将随机种子重新输入待验证对象，将整个验证过程重新再进行一遍，来实现异常复现。
对于上述的验证方案，需要说明的是，相同的随机种子在不同的仿真环境下进行异常复现的场景就有可能会不同，可能会出现场景丢失的风险；而且，如果异常场景是仿真进行了很长时间，比如几天、几周甚至几个月才出现时，那么采用随机种子重新输入的方法来实现异常复现往往也需要消耗相同的时间，比如几天、几周甚至几个月。因此，目前的芯片验证方案的准确性不高，并且效率较低。
发明内容
为解决上述技术问题，本发明实施例期望提供一种芯片验证方法和装置、设备、存储介质，提高了芯片验证方案的准确性和效率。
本发明实施例的技术方案是这样实现的：
第一方面，本发明实施例提供了一种芯片验证方法，所述方法包括：
将按照预设生成机制生成的激励矢量分别输入至待验证对象和标准模型，获取对应的待验证输出矢量和参照输出矢量；
将所述待验证输出矢量和所述参照输出矢量进行比较；
当所述待验证输出矢量与参照输出矢量之间不一致时，确定所述待验证对象异常，并将所述激励矢量重新输入至待验证对象进行异常场景复现。
在本发明的一种实施例中，所述按照预设生成机制生成的激励矢量，包括：按照预设的随机种子及约束规则所生成的用于表征场景数据的激励矢量。
在本发明的一种实施例中，所述方法还包括：
当所述待验证输出矢量与参照输出矢量之间一致时，确定所述待验证对象正常，并丢弃所述激励矢量。
在本发明的一种实施例中，所述将所述待验证输出矢量和所述参照输出矢量进行比较时，所述方法还包括：将所述激励矢量进行保存。
第二方面，本发明实施例提供了一种芯片验证装置，所述装置包括：生成单元、输入单元、待验证对象单元、标准模型单元、比较单元、反馈单元；其中，
所述生成单元，配置为按照预设生成机制生成激励矢量，传输至所述输入单元；
输入单元，配置为将所述生成单元传输的激励矢量分别输入至所述待验证对象单元和所述标准模型单元；
所述待验证对象单元，配置为根据所述激励矢量生成对应的待验证输出矢量；
所述标准模型单元，配置为根据所述激励矢量生成对应的参照输出矢量；
所述比较单元，配置为将所述待验证输出矢量和所述参照输出矢量进行比较；并且当所述待验证输出矢量与参照输出矢量之间不一致时，触发所述反馈单元；
所述反馈单元，配置为确定所述待验证对象单元异常，并将所述激励矢量重新传输至输入单元；
所述输入单元，还配置为将所述反馈单元重新输入的所述激励矢量重新输入至所述待验证对象单元进行异常场景复现。
在本发明的一种实施例中，所述生成单元，配置为按照预设的随机种子及约束规则所生成的用于表征场景数据的激励矢量。
在本发明的一种实施例中，所述装置还包括丢弃单元；
所述比较单元，还配置为当所述待验证输出矢量与参照输出矢量之间一致时，触发所述丢弃单元；
所述丢弃单元，配置为确定所述待验证对象单元正常，并丢弃所述激励矢量。
在本发明的一种实施例中，所述装置还包括保存单元，配置为将所述激励矢量进行保存。
第三方面，本发明实施例提供一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，该计算机可执行指令用于执行上述第一方面实施例所述的芯片验证方法。
第四方面，本发明实施例提供一种芯片验证设备，所述芯片验证设备包括：
存储介质，配置为存储计算机可执行指令；
处理器，配置为执行存储在所述存储介质上的计算机可执行指令，所述计算机可执行指令包括：将按照预设生成机制生成的激励矢量分别输入至待验证对象和标准模型，获取对应的待验证输出矢量和参照输出 矢量；将所述待验证输出矢量和所述参照输出矢量进行比较；当所述待验证输出矢量与参照输出矢量之间不一致时，确定所述待验证对象异常，并将所述激励矢量重新输入至待验证对象进行异常场景复现。
本发明实施例提供了一种芯片验证方法和装置、设备、存储介质，通过对随机种子生成的激励矢量进行保存来取代目前验证方案中对随机种子进行保存，从而能够在验证异常时，通过激励矢量进行异常场景复现，提高了芯片验证方案的准确性和效率。
附图说明
图1为本发明实施例提供的一种芯片验证方法的流程示意图；
图2为本发明实施例提供的一种芯片验证装置的结构示意图；
图3为本发明实施例提供的另一种芯片验证装置的结构示意图；
图4为本发明实施例提出的一种芯片验证的UVM架构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
本发明实施例的基本思想是：在芯片验证过程中，通过对随机种子生成的激励矢量进行保存来取代目前验证方案中对随机种子进行保存，从而能够在验证异常时，通过激励矢量进行异常场景复现，避免了通过随机种子进行场景复现所导致的准确性不高，效率低下的情况出现。
基于上述基本思想，通过以下几个实施例对本发明实施例的技术方案进行说明。
实施例一
参见图1，其示出了本发明实施例提供的一种芯片验证方法，该方法应用于芯片验证设备，所述芯片验证设备可以为任何具有计算能力的电子设 备，在具体实现的过程中，所述芯片验证设备可以为个人计算机(PC)、集成的服务器等来实现。该方法所实现的功能可以通过芯片验证设备中的处理器调用程序代码来实现，当然程序代码可以保存在计算机存储介质中，可见，该芯片验证设备至少包括处理器和存储介质。
该方法可以包括：
S101：将按照预设生成机制生成的激励矢量分别输入至待验证对象和标准模型，获取对应的待验证输出矢量和参照输出矢量；
S102：将待验证输出矢量和参照输出矢量进行比较；
S103：当待验证输出矢量与参照输出矢量之间不一致时，确定待验证对象异常，并将激励矢量重新输入至待验证对象进行异常场景复现；
需要说明的是，当待验证输出矢量与参照输出矢量之间一致时，确定待验证对象正常，并丢弃该激励矢量。
示例性地，按照预设生成机制生成的激励矢量，包括：按照预设的随机种子及约束规则所生成的用于表征场景数据的激励矢量；具体地，可以根据由验证工程师指定或者系统自动生成随机种子以及验证工程师定制的约束规则生成海量的、连续不断的、分批次的随机激励矢量，并且对应随机激励矢量生成封装单元，从而使得封装单元能够表征完整独立的验证场景。
示例性地，为了能够将激励矢量重新输入至待验证对象进行异常场景复现，在将待验证输出矢量和所述参照输出矢量进行比较时，还可以将激励矢量进行保存，以备后续的重新输入或者丢弃处理。
具体地，可以将随机激励矢量对应的封装单元，通过文件写操作，保存为一个快照文件以备后续操作；相应地，当待验证输出矢量与参照输出矢量之间不一致时，可以通过文件读操作，读取该快照文件，并将该快照文件还原成相应随机激励矢量对应的封装单元并重新输入，从而实现场景 精确复现。
还需要说明的是，当确定待验证对象正常，并丢弃该激励矢量之后，本发明实施例可以继续执行S101：将按照预设生成机制生成的激励矢量分别输入至待验证对象和标准模型，获取对应的待验证输出矢量和参照输出矢量；从而进行后续的验证过程。
可以理解地，本实施例在需要复现异常场景的时候，将快照下来的随机激励矢量重新输入即可，不需要再根据随机种子，按照约束规则，去消耗冗长的仿真时间来进行复现，由于保存的是激励矢量本身而不是激励矢量的生成机制，例如随机种子和约束机制，从而能够在不同的仿真服务器环境下实现了场景复现的唯一性和确定性。
本发明实施例提供了一种芯片验证方法，通过对随机种子生成的激励矢量进行保存来取代目前验证方案中对随机种子进行保存，从而能够在验证异常时，通过激励矢量进行异常场景复现，提高了芯片验证方案的准确性和效率。
实施例二
基于前述实施例相同的技术构思，参见图2，其示出了本发明实施例提供的一种芯片验证装置20，该装置20包括：生成单元201、输入单元202、待验证对象单元203、标准模型单元204、比较单元205、反馈单元206；其中，
生成单元201，配置为按照预设生成机制生成激励矢量，传输至输入单元202；
输入单元202，配置为将生成单元201传输的激励矢量分别输入至待验证对象单元203和标准模型单元204；
待验证对象单元203，配置为根据激励矢量生成对应的待验证输出矢量；
标准模型单元204，配置为根据激励矢量生成对应的参照输出矢量；
比较单元205，配置为将待验证输出矢量和参照输出矢量进行比较；并且当待验证输出矢量与参照输出矢量之间不一致时，触发反馈单元206；
反馈单元206，配置为确定待验证对象单元203异常，并将激励矢量重新传输至输入单元202；
输入单元202，还配置为将反馈单元206重新输入的激励矢量重新输入至待验证对象单元203进行异常场景复现。
示例性地，生成单元201，配置为按照预设的随机种子及约束规则所生成的用于表征场景数据的激励矢量。
示例性地，参见图3，装置20还包括丢弃单元207；
比较单元205，还配置为当待验证输出矢量与参照输出矢量之间一致时，触发丢弃单元207；
丢弃单元207，配置为确定待验证对象单元203正常，并丢弃激励矢量。
示例性地，参见图3，装置30还包括保存单元208，配置为将激励矢量进行保存。
具体地，结合通用验证方法学(UVM，Universal Verification Methodology)的工程实例及图2或图3所示的芯片验证装置，参见图4，为本发明实施例提出的一种芯片验证的UVM架构示意图，可以理解地，图4仅用于说明本发明实施例的技术方案，本领域技术人员可以根据本发明实施例跌技术方案以及图4的启示，得到更多不同的UVM架构图，本发明实施例对此不作具体限定，参见图4，该UVM架构可以包括：随机激励矢量生成器(random_uvm_sequence)、复现矢量生成器(debug_uvm_sequence)、二选一开关(switch)、矢量驱动器(uvm_driver)、待验证对象(DUV，Design Under Verification)、DUV输入接口、DUV输出接口、输入采样器(uvm_monitor for input)、输出采样器(uvm_monitor for output)、标准参考 模型(reference_model)以及异常检测器(uvm_scoreboard)。一般来说，UVM架构安装在个人计算机上，在对芯片进行验证的过程中，芯片验证工程师通过编写程序代码调用上述UVM架构所提供的各模组对芯片进行验证。
其中，random_uvm_sequence可以根据随机种子+约束规则的生成机制，来生成海量的随机激励矢量；
debug_uvm_sequence与uvm_scoreboard连接，从uvm_scoreboard获取导致异常的激励矢量；
switch配置为决定选择debug_uvm_sequence去实现场景快速复现、还是选择random_uvm_sequence去完成正常的验证流程；
uvm_driver配置为将random_uvm_sequence或者debug_uvm_sequence的激励矢量通过DUV输入接口推入至DUV；
uvm_monitor for input通过DUV输入接口获取推入至DUV的激励矢量，并将激励矢量分别传输至reference_model和uvm_scoreboard；
uvm_monitor for output通过DUV输出接口获取由DUV根据激励矢量所生成的待验证输出矢量，并将待验证输出矢量传输至uvm_scoreboard；
reference_model配置为根据标准参考模型和激励矢量生成标准输出矢量；并将标准输出矢量传输至uvm_scoreboard；
uvm_scoreboard配置为将待验证输出矢量与标准输出矢量进行比较，当两者一致时，确定没有异常发生，并丢弃由uvm_monitor for input传输的激励矢量，将switch设置为选择random_uvm_sequence去完成正常的验证流程；当两者不一致时，确定发生异常，并将由uvm_monitor for input传输的激励矢量传输至debug_uvm_sequence，将switch设置为选择debug_uvm_sequence去实现场景快速复现。
可以理解地，图4所示的架构示意图中，为了能够清楚地说明技术方 案，对于与本发明实施例技术方案无关的接口、缓存器等部件进行了省略，本领域技术人员可以根据图4所示的架构示意图来完成完整详细的架构图；并且本领域技术人员可以将上述架构中的组成部分与图2或图3所示的装置结构中的组成部分进行对应，从而实现本发明实施例的技术方案，本实施例对此不作赘述。
本发明实施例提供了一种芯片验证装置20，通过对随机种子生成的激励矢量进行保存来取代目前验证方案中对随机种子进行保存，从而能够在验证异常时，通过激励矢量进行异常场景复现，提高了芯片验证方案的准确性和效率。
本发明实施例中芯片验证装置所包括的各单元，例如生成单元、输入单元、待验证对象单元、标准模型单元、比较单元、反馈单元等单元，都可以通过芯片验证设备中处理器来实现，当然还可以通过逻辑电路来实现，在一个实施例的过程中，处理器可以为中央处理器(CPU)、微处理器(MPU)、数字信号处理器(DSP)或现场可编程门阵列(FPGA)等。
需要说明的是，本发明实施例中，如果以软件功能模块的形式实现上述的芯片验证方法，并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机、服务器、或者网络设备等)执行本发明各个实施例所述方法的全部或部分。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read Only Memory)、磁碟或者光盘等各种可以存储程序代码的介质。这样，本发明实施例不限制于任何特定的硬件和软件结合。
相应地，本发明实施例再提供一种计算机存储介质，所述计算机存储 介质中存储有计算机可执行指令，该计算机可执行指令用于执行本发明实施例中的芯片验证方法。
基于前述的实施例，本发明实施例提供一种芯片验证设备，所述设备包括：
存储介质，配置为存储计算机可执行指令；
处理器，配置为执行存储在所述存储介质上的计算机可执行指令，所述计算机可执行指令包括：将按照预设生成机制生成的激励矢量分别输入至待验证对象和标准模型，获取对应的待验证输出矢量和参照输出矢量；将所述待验证输出矢量和所述参照输出矢量进行比较；当所述待验证输出矢量与参照输出矢量之间不一致时，确定所述待验证对象异常，并将所述激励矢量重新输入至待验证对象进行异常场景复现。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理 设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。

Claims (10)

  1. 一种芯片验证方法，所述方法包括：
    将按照预设生成机制生成的激励矢量分别输入至待验证对象和标准模型，获取对应的待验证输出矢量和参照输出矢量；
    将所述待验证输出矢量和所述参照输出矢量进行比较；
    当所述待验证输出矢量与参照输出矢量之间不一致时，确定所述待验证对象异常，并将所述激励矢量重新输入至待验证对象进行异常场景复现。
  2. 根据权利要求1所述的方法，其中，所述按照预设生成机制生成的激励矢量，包括：按照预设的随机种子及约束规则所生成的用于表征场景数据的激励矢量。
  3. 根据权利要求1所述的方法，其中，所述方法还包括：
    当所述待验证输出矢量与参照输出矢量之间一致时，确定所述待验证对象正常，并丢弃所述激励矢量。
  4. 根据权利要求1所述的方法，其中，所述将所述待验证输出矢量和所述参照输出矢量进行比较时，所述方法还包括：将所述激励矢量进行保存。
  5. 一种芯片验证装置，所述装置包括：生成单元、输入单元、待验证对象单元、标准模型单元、比较单元、反馈单元；其中，
    所述生成单元，配置为按照预设生成机制生成激励矢量，传输至所述输入单元；
    输入单元，配置为将所述生成单元传输的激励矢量分别输入至所述待验证对象单元和所述标准模型单元；
    所述待验证对象单元，配置为根据所述激励矢量生成对应的待验证输出矢量；
    所述标准模型单元，配置为根据所述激励矢量生成对应的参照输出矢量；
    所述比较单元，配置为将所述待验证输出矢量和所述参照输出矢量进行比较；并且当所述待验证输出矢量与参照输出矢量之间不一致时，触发所述反馈单元；
    所述反馈单元，配置为确定所述待验证对象单元异常，并将所述激励矢量重新传输至输入单元；
    所述输入单元，还配置为将所述反馈单元重新输入的所述激励矢量重新输入至所述待验证对象单元进行异常场景复现。
  6. 根据权利要求5所述的装置，其中，所述生成单元，配置为按照预设的随机种子及约束规则所生成的用于表征场景数据的激励矢量。
  7. 根据权利要求5所述的装置，其中，所述装置还包括丢弃单元；
    所述比较单元，还配置为当所述待验证输出矢量与参照输出矢量之间一致时，触发所述丢弃单元；
    所述丢弃单元，配置为确定所述待验证对象单元正常，并丢弃所述激励矢量。
  8. 根据权利要求5所述的装置，其中，所述装置还包括保存单元，配置为将所述激励矢量进行保存。
  9. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，该计算机可执行指令用于执行权利要求1至4任一项所述的芯片验证方法。
  10. 一种计算设备，所述计算设备包括：
    存储介质，配置为存储计算机可执行指令；
    处理器，配置为执行存储在所述存储介质上的计算机可执行指令，所述计算机可执行指令包括：将按照预设生成机制生成的激励矢量分别 输入至待验证对象和标准模型，获取对应的待验证输出矢量和参照输出矢量；将所述待验证输出矢量和所述参照输出矢量进行比较；当所述待验证输出矢量与参照输出矢量之间不一致时，确定所述待验证对象异常，并将所述激励矢量重新输入至待验证对象进行异常场景复现。
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CN109670246A (zh) * 2018-12-21 2019-04-23 天津国芯科技有限公司 一种测试数据通路的uvm验证系统
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CN111796975A (zh) * 2020-07-07 2020-10-20 云知声智能科技股份有限公司 芯片的随机化验证方法及装置
CN111796975B (zh) * 2020-07-07 2024-01-30 云知声智能科技股份有限公司 芯片的随机化验证方法及装置
CN112433900B (zh) * 2020-12-03 2023-03-14 海光信息技术股份有限公司 用于芯片验证的方法、系统、设备以及存储介质
CN112433900A (zh) * 2020-12-03 2021-03-02 海光信息技术股份有限公司 用于芯片验证的方法、系统、设备以及存储介质
CN112464499A (zh) * 2020-12-24 2021-03-09 深圳市芯天下技术有限公司 非易失芯片擦写数据检查方法、装置、存储介质和终端
CN112464499B (zh) * 2020-12-24 2023-05-26 芯天下技术股份有限公司 非易失芯片擦写数据检查方法、装置、存储介质和终端
CN112949231A (zh) * 2021-02-26 2021-06-11 浪潮电子信息产业股份有限公司 一种基于uvm验证平台的模块验证系统、方法及设备
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CN117454823B (zh) * 2023-12-22 2024-04-19 深圳鲲云信息科技有限公司 一种芯片验证多端口激励控制方法、代理器、设备及介质

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