WO2017016274A1 - 开关控制电路 - Google Patents

开关控制电路 Download PDF

Info

Publication number
WO2017016274A1
WO2017016274A1 PCT/CN2016/081685 CN2016081685W WO2017016274A1 WO 2017016274 A1 WO2017016274 A1 WO 2017016274A1 CN 2016081685 W CN2016081685 W CN 2016081685W WO 2017016274 A1 WO2017016274 A1 WO 2017016274A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
mos transistor
control signal
switch
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/081685
Other languages
English (en)
French (fr)
Other versions
WO2017016274A9 (zh
Inventor
骆川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
Original Assignee
CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSMC Technologies Fab1 Co Ltd, CSMC Technologies Fab2 Co Ltd filed Critical CSMC Technologies Fab1 Co Ltd
Priority to US15/748,156 priority Critical patent/US10236876B2/en
Publication of WO2017016274A1 publication Critical patent/WO2017016274A1/zh
Anticipated expiration legal-status Critical
Publication of WO2017016274A9 publication Critical patent/WO2017016274A9/zh
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017545—Coupling arrangements; Impedance matching circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/10—Modifications for increasing the maximum permissible switched voltage
    • H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0054—Gating switches, e.g. pass gates
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/94—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00 characterised by the way in which the control signal is generated

Definitions

  • the present invention relates to the field of circuit control, and more particularly to a switch control circuit.
  • analog signals need to be implemented by some switches during the process of acquisition and transmission.
  • Switch control circuits are used to control the on and off of these switches.
  • the higher the voltage of the driving switch is the smaller the on-resistance of the switch is.
  • the smaller the on-resistance can make the speed of the analog signal pass through the switch faster and the distortion of the analog signal is reduced. small.
  • the traditional switch control circuit can increase the driving voltage, but when the system power supply voltage is too high or the voltage range of the sampled analog signal is large, the driving voltage on the sampling switch is too high, which may cause the sampling switch to be broken down. Low reliability.
  • a switch control circuit for controlling on-off of a switch circuit; comprising: a clock circuit for generating a first clock control signal and a second clock control signal; a voltage boosting circuit, respectively, and the clock circuit, a power supply connection of the switch control circuit; the voltage boost circuit is configured to receive the second clock control signal and an operating voltage output by the power supply, and perform the operation under the control of the second clock control signal Forming a switch control signal after the voltage is raised by a preset value; and an inverter circuit respectively connected to the clock circuit and the voltage boost circuit; the inverter circuit is configured to receive the first clock control signal and the switch control signal, And controlling whether to output the switch control signal to the switch circuit according to the first clock control signal to control on and off of the switch circuit.
  • the voltage boosting circuit can increase the operating voltage of the power supply output by a preset value, form a switch control signal, and output the signal to the inverter circuit. Inverting circuit can be based on the first time
  • the clock control signal controls whether the switch control signal is output to the switch circuit, thereby implementing control of the switch circuit on and off. Since the voltage boosting value of the switch control signal is a preset value, the voltage boosting amount is controllable and does not change according to external factors, so that the internal resistance of the switching circuit is reduced without causing the switching tube in the switching circuit to be broken down. Hidden dangers, the reliability of the circuit is high.
  • FIG. 1 is a schematic block diagram of a switch control circuit in an embodiment
  • FIG. 2 is a circuit schematic diagram of a switch control circuit in an embodiment
  • FIG. 3 is a schematic diagram of two clock control signals generated in the switch control circuit of FIG. 2;
  • FIG. 4 is a circuit schematic diagram of a switching circuit controlled by the switch control circuit of FIG. 2;
  • FIG. 5 is a circuit schematic diagram of a switch control circuit in another embodiment
  • FIG. 6 is a circuit schematic diagram of a switching circuit controlled by the switch control circuit of FIG. 5.
  • the switch control circuit is used to control the on and off of the switch circuit.
  • the switch control circuit includes a clock circuit 110, a voltage boost circuit 120, and an inverter circuit 130.
  • the clock circuit 110 is connected to the voltage boosting circuit 120 and the inverter circuit 130 respectively.
  • the inverter circuit 130 is connected to the voltage boosting circuit 120 and is also connected to the switching circuit.
  • the clock circuit 110 is configured to generate two clock control signals, which are respectively output to the voltage boosting circuit 120 and the inverter circuit 130.
  • the generated two clock control signals are a first clock control signal CLK1 and a second clock control signal CLK2, respectively.
  • the phases of the first clock control signal CLK1 and the second clock control signal CLK2 are complementary and do not overlap each other.
  • the voltage boosting circuit 120 is connected to the clock circuit 110 and the power supply VDD of the switch control circuit, respectively, for receiving the second clock control signal CLK2 output by the clock circuit 110 and the operating voltage V DD output by the power supply VDD.
  • the voltage boosting circuit 120 increases the operating voltage V DD by a preset value under the control of the second clock control signal CLK2 to form a switch control signal H1, and outputs the switch control signal H1 to the inverter circuit 130.
  • the inverter circuit 130 is configured to receive the first clock control signal CLK1 and the switch control signal H1 output by the clock circuit 110, and control whether to output the switch control signal H1 to the switch circuit according to the level of the first clock control signal CLK1 high/low. .
  • the voltage boosting circuit 120 in the switch control circuit can increase the operating voltage V DD outputted by the power supply VDD by a preset value, form a switch control signal H1, and output the same to the inverter circuit 130.
  • the inverter circuit 130 can control whether to output the switch control signal H1 to the switch circuit according to the first clock control signal CLK1, thereby implementing control of the switch circuit on and off. Since the voltage boosting value of the switch control signal H1 is a preset value, the voltage boosting amount is controllable and does not change with external factors, so that the internal resistance of the switching circuit is reduced without causing the switching tube in the switching circuit to be broken down. The hidden danger is that the reliability of the circuit is high.
  • FIG. 2 is a circuit schematic diagram of a switch control circuit in an embodiment (clock circuit not shown)
  • FIG. 3 is a schematic diagram of two clock control signals generated by the switch control circuit of FIG. 2
  • FIG. 4 is a diagram of FIG.
  • the phases of the first clock control signal CLK1 and the second clock control signal CLK2 generated by the clock circuit are complementary and do not overlap each other to ensure that the phases do not appear the same, as shown in FIG.
  • the inverter circuit includes a first inverting unit and a second inverting unit.
  • the first inverting unit and the second inverting unit are both CMOS inverters.
  • the first inverting unit includes the first The MOS transistor M1 and the second MOS transistor M2
  • the second inverting unit includes a third MOS transistor M3 and a fourth MOS transistor M4.
  • the first MOS transistor M1 and the third MOS transistor M3 are PMOS transistors
  • the second MOS transistor M2 and the fourth MOS transistor M4 are NMOS transistors.
  • the gate of the first MOS transistor M1 is connected to the gate of the second MOS transistor M2 and is connected to the output terminal of the first clock control signal CLK1 in the clock circuit for receiving the first clock control signal CLK1 of its output.
  • the source of the first MOS transistor M1 is connected to the power supply VDD, and the drain thereof is connected to the drain of the second MOS transistor M2 and then connected to the gate of the third MOS transistor M3.
  • the gate of the third MOS transistor M3 is connected to the gate of the fourth MOS transistor M4.
  • the source of the third MOS transistor M3 is connected to the voltage boosting circuit.
  • the drain of the third MOS transistor M3 is connected to the drain of the fourth MOS transistor M4 as an output terminal for outputting the switching control signal H1.
  • the source of the second MOS transistor M2 and the drain of the fourth MOS transistor M4 are connected to each other and grounded.
  • the voltage boosting circuit includes a fourth inverting unit, a first switching transistor T1, a second switching transistor T2, and a bootstrap capacitor C.
  • the fourth inverting unit is a CMOS inverter including a fifth MOS transistor M5 and a sixth MOS transistor M6.
  • the fifth MOS transistor M5 is a PMOS transistor
  • the sixth MOS transistor is an NMOS transistor.
  • the first switch tube T1 and the second switch tube T2 are both NPN type transistors, that is, the input end of the switch tube is the collector of the NPN type transistor; the base of the switch tube is the control end of the NPN type transistor; the output end of the switch tube is The emitter of an NPN transistor.
  • the gate of the fifth MOS transistor M5 is connected to the gate of the sixth MOS transistor M6, and is connected to the output terminal of the second clock control signal CLK2 of the clock circuit for receiving the second clock control signal CLK2 of its output.
  • the source of the fifth MOS transistor M5 is connected to the power supply VDD, the drain thereof is connected to the drain of the sixth MOS transistor M6, and is connected to the negative plate of the bootstrap capacitor C.
  • the positive electrode of the bootstrap capacitor C is connected to the emitter of the first switching transistor T1, the collector of the second switching transistor T2, and the source of the third MOS transistor M3, respectively. After the collector of the first switching transistor T1 is connected to its base, it is connected to the power supply VDD. The emitter of the second switching transistor T2 is connected to the power supply VDD. The base of the second switching transistor T2 is connected to its collector.
  • the switch circuit includes a switch tube M7.
  • the switch M7 is an NMOS transistor, and its source is connected to the sampling end for receiving the sampling analog signal VIN.
  • the drain of the switch M7 is the output terminal VOUT, which is also connected to the sampling capacitor CL and grounded.
  • the first MOS transistor M1 When the first clock control signal CLK1 is at a low level, the first MOS transistor M1 is turned on, and the second MOS transistor M2 is turned off, thereby controlling the third MOS transistor to be turned off, the fourth MOS transistor to be turned on, and the output signal of the output terminal being a low level.
  • the switch tube M7 is turned off. Therefore, the switching circuit remains off in the control of the output signal that is low.
  • the first clock control signal CLK1 When the first clock control signal CLK1 is at a low level, the second clock control signal is at a high level. Therefore, the fifth MOS transistor M5 is turned off, and the sixth MOS transistor M6 is turned on, so that the voltage of the negative plate of the bootstrap capacitor C is zero.
  • the first switch T1 is turned on, and the second switch T2 is turned off, so that the positive plate voltage of the bootstrap capacitor C is (V DD - V be ), and V be is the forward voltage of the first switch T1. In this embodiment, V be is around 0.7V.
  • the fifth MOS transistor M5 is turned on, the sixth MOS transistor M6 is turned off, and the negative plate voltage of the bootstrap capacitor C becomes V DD .
  • the positive plate voltage of the bootstrap capacitor C becomes (2V DD - V be ).
  • the positive plate voltage of the bootstrap capacitor C is greater than V DD , so the second switch T2 is forward biased, and the first switch T1 is reverse biased.
  • the charge of the bootstrap capacitor C is discharged through the second switching transistor T2, and its positive plate voltage is finally stabilized at (V DD + V be ).
  • the formed switch control signal H1 is used as the control signal of the switch tube M7, and the on-resistance of the switch tube can be significantly reduced, and the voltage increment of the switch control signal H1 is fixed, which is the positive of the second switch tube T2.
  • the conduction voltage is about 0.7V. Therefore, the incremental voltage is not too high, and the switch is not broken down, which improves the reliability of the circuit while reducing the internal resistance of the switching circuit.
  • the switch control circuit in the present case has a simple circuit structure and is flexible in use, and can be widely applied to various process platforms. The above switch control circuit can avoid the possibility of excessive voltage in the circuit node and improve the reliability of the circuit.
  • the switch control circuit occupies a small layout area, which can satisfy most occasions requiring high-speed and high-precision sampling of analog signals.
  • FIG. 5 is a circuit schematic diagram of a switch control circuit in another embodiment
  • FIG. 6 is a circuit schematic diagram of a switch circuit corresponding to the switch control circuit of FIG. 5.
  • a switch pair formed by the MOS transistor M8 and the MOS transistor M9 is included.
  • the MOS transistor M8 is an NMOS transistor
  • the MOS transistor M9 is a PMOS transistor.
  • the inverter circuit in the switch control circuit further includes a third inverting unit and a delay circuit based on the inverting circuit in the embodiment shown in FIG. 2.
  • the switch circuit includes the MOS transistor M8 and the MOS transistor M9, and therefore two control signals are required to separately control the MOS transistor M8 and the MOS transistor M9.
  • the aforementioned switch control signal H1 is the first control signal and is output to the gate of the MOS transistor M8.
  • the third inverting unit is configured to generate the second control signal N1 and output it to the gate of the MOS transistor M9, thereby controlling the on and off of the MOS transistor M9.
  • the second control signal N1 and the first control signal H1 are mutually inverted.
  • the third inverting unit includes three inverters INV1, INV2, and INV3 connected in series. The output of the inverter INV3 outputs a second control signal H1.
  • the delay circuit includes a third switching transistor T3.
  • the input end of the third switching transistor T3 is connected to the control terminal and connected to the source of the second MOS transistor M2.
  • the output end of the third switching transistor T3 is grounded.
  • the third switching transistor T3 is an NPN transistor. In this embodiment, the input end of the third switching transistor T3 is the collector of the NPN transistor; the control terminal of the third switching transistor T3 is the base of the NPN transistor; the output terminal of the third switching transistor T3 is the NPN transistor.
  • the third switching transistor T3 may also be an N-channel MOS transistor. Therefore, the delay circuit and the first inverting unit and the second inverting unit form a three-stage delay, so that the complementary signals of the first control signal H1 and the second control signal H2 are synchronized as much as possible in timing, thereby ensuring The MOS transistor M8 and the MOS transistor M9 can be simultaneously opened and closed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)

Abstract

一种开关控制电路包括：时钟电路(110)，用于生成第一时钟控制信号(CLK1)和第二时钟控制信号(CLK2)；电压提升电路(120)，用于接收第二时钟控制信号(CLK2)以及供电电源(VDD)输出的工作电压，并在第二时钟控制信号(CLK2)的控制下将工作电压提升预设值后形成开关控制信号(H1)；以及反相电路(130)，用于接收第一时钟控制信号(CLK1)以及开关控制信号(H1)，并根据第一时钟控制信号(CLK1)控制是否将开关控制信号(H1)输出给开关电路，以对开关电路的通断进行控制。

Description

开关控制电路 技术领域
本发明涉及电路控制领域，特别是涉及开关控制电路。
背景技术
在一些高速高精度的信号处理以及转换电路里面，模拟信号在被采集和传输的过程中需要通过一些开关来实现。开关控制电路用来控制这些开关的通断。在构成开关的晶体管本身的特性不变的前提下，驱动开关的电压越高开关的导通电阻就越小，导通电阻减小可以使得模拟信号通过开关时的速度加快且模拟信号的失真减小。传统的开关控制电路能够提升驱动电压，但是系统供电电压过高或者采样的模拟信号的电压范围较大时，容易导致采样开关上的驱动电压过高进而导致采样开关存在被击穿的危险，电路可靠性较低。
发明内容
基于此，有必要提供一种可靠性较高的开关控制电路。
一种开关控制电路，用于对开关电路的通断进行控制；包括：时钟电路，用于生成第一时钟控制信号和第二时钟控制信号；电压提升电路，分别与所述时钟电路、所述开关控制电路的供电电源连接；所述电压提升电路用于接收所述第二时钟控制信号以及所述供电电源输出的工作电压，并在所述第二时钟控制信号的控制下，将所述工作电压提升预设值后形成开关控制信号；以及反相电路，分别与所述时钟电路、电压提升电路连接；所述反相电路用于接收所述第一时钟控制信号以及所述开关控制信号，并根据所述第一时钟控制信号控制是否将所述开关控制信号输出给所述开关电路，以对所述开关电路的通断进行控制。
上述开关控制电路中，电压提升电路能够将供电电源输出的工作电压提升预设值，形成开关控制信号后输出给反相电路。反相电路能够根据第一时 钟控制信号控制是否输出该开关控制信号给开关电路，从而实现对开关电路通断的控制。由于开关控制信号的电压提升值为预设值，电压提升量可控，不会随外界因素变化而变化，因此在降低开关电路内阻的同时不会造成开关电路中的开关管被击穿的隐患，电路的可靠性较高。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例中的开关控制电路的原理框图；
图2为一实施例中的开关控制电路的电路原理图；
图3为图2中的开关控制电路中产生的两路时钟控制信号的示意图；
图4为图2中的开关控制电路所控制的开关电路的电路原理图；
图5为另一实施例中的开关控制电路的电路原理图；
图6为图5中的开关控制电路所控制的开关电路的电路原理图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的较佳实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。
图1为一实施例中的开关控制电路的原理框图。该开关控制电路用于对开关电路的通断进行控制。在本实施例中，该开关控制电路包括时钟电路110、电压提升电路120以及反相电路130。其中，时钟电路110分别与电压提升电路120、反相电路130连接，反相电路130与电压提升电路120连接，且还用于与开关电路连接。
时钟电路110用于生成两路时钟控制信号，分别输出给电压提升电路120以及反相电路130。具体地，生成的两路时钟控制信号分别为第一时钟控制信号CLK1和第二时钟控制信号CLK2。在本实施例中，第一时钟控制信号CLK1和第二时钟控制信号CLK2的相位互补且互不交叠。
电压提升电路120分别与时钟电路110以及开关控制电路的供电电源VDD连接，用于接收时钟电路110输出的第二时钟控制信号CLK2以及供电电源VDD输出的工作电压VDD。电压提升电路120在第二时钟控制信号CLK2的控制下，将工作电压VDD提升预设值后形成开关控制信号H1，并输出给反相电路130。
反相电路130用于接收时钟电路110输出的第一时钟控制信号CLK1以及开关控制信号H1，并根据第一时钟控制信号CLK1的电平高/低，控制是否将开关控制信号H1输出给开关电路。
上述开关控制电路中电压提升电路120能够将供电电源VDD输出的工作电压VDD提升预设值，形成开关控制信号H1后输出给反相电路130。反相电路130能够根据第一时钟控制信号CLK1控制是否输出该开关控制信号H1给开关电路，从而实现对开关电路通断的控制。由于开关控制信号H1的电压提升值为预设值，电压提升量可控，不会随外界因素变化而变化，因此在降低开关电路内阻的同时不会造成开关电路中的开关管被击穿的隐患，电路的可靠性较高。
图2为一实施例中的开关控制电路的电路原理图(时钟电路未示)，图3为图2中的开关控制电路产生的两路时钟控制信号的示意图；图4则为图2中的开关控制电路所对应的开关电路的电路原理图。下面结合图2、图3以及图4，对本实施例中的开关控制电路的电路结构及其工作过程做详细说明。
时钟电路产生的第一时钟控制信号CLK1和第二时钟控制信号CLK2的相位互补且互不交叠，以确保二者不会出现相位相同的情况，如图3所示。
反相电路包括第一反相单元和第二反相单元。在本实施例中，第一反相单元和第二反相单元均为CMOS反相器。具体地，第一反相单元包括第一 MOS管M1和第二MOS管M2，第二反相单元则包括第三MOS管M3和第四MOS管M4。其中，第一MOS管M1和第三MOS管M3为PMOS管，第二MOS管M2和第四MOS管M4则为NMOS管。具体地，第一MOS管M1的栅极与第二MOS管M2的栅极连接并与时钟电路中第一时钟控制信号CLK1的输出端连接，用于接收其输出的第一时钟控制信号CLK1。第一MOS管M1的源极与供电电源VDD连接，其漏极与第二MOS管M2的漏极连接后连接于第三MOS管M3的栅极。第三MOS管M3的栅极与第四MOS管M4的栅极连接。第三MOS管M3的源极与电压提升电路连接。第三MOS管M3的漏极与第四MOS管M4的漏极连接后作为输出端，用于输出开关控制信号H1。第二MOS管M2的源极和第四MOS管M4的漏极连接后接地。
电压提升电路包括第四反相单元、第一开关管T1、第二开关管T2以及自举电容C。第四反相单元为CMOS反相器，其包括第五MOS管M5和第六MOS管M6。其中，第五MOS管M5为PMOS管，第六MOS管为NMOS管。第一开关管T1和第二开关管T2均为NPN型晶体管，即：开关管的输入端为NPN型晶体管的集电极；开关管的基极为NPN型晶体管的控制端；开关管的输出端为NPN型晶体管的发射极。第五MOS管M5的栅极与第六MOS管M6的栅极连接，并与时钟电路的第二时钟控制信号CLK2的输出端连接，用于接收其输出的第二时钟控制信号CLK2。第五MOS管M5的源极与供电电源VDD连接，其漏极与第六MOS管M6的漏极连接，并与自举电容C的负极板连接。自举电容C的正极板分别与第一开关管T1的发射极、第二开关管T2的集电极以及第三MOS管M3的源极连接。第一开关管T1的集电极与其基极连接后，与供电电源VDD连接。第二开关管T2的发射极与供电电源VDD连接。第二开关管T2基极则与其集电极连接。
在本实施例中，开关电路包括开关管M7。开关管M7为NMOS管，其源极与采样端连接，用于接收采样模拟信号VIN。开关管M7的漏极为输出端VOUT，其还与采样电容CL连接后接地。
上述开关控制电路的工作过程具体如下：
当第一时钟控制信号CLK1为低电平时，第一MOS管M1导通、第二MOS管M2截止，从而控制第三MOS管截止、第四MOS管导通，输出端的输出信号为低电平，开关管M7截止。故，开关电路在为低电平的输出信号的控制下保持断开状态。当第一时钟控制信号CLK1为低电平时，第二时钟控制信号为高电平。因此，第五MOS管M5截止，第六MOS管M6导通，使得自举电容C的负极板电压为0。第一开关管T1导通，第二开关管T2截止，从而使得自举电容C的正极板电压为(VDD-Vbe)，Vbe为第一开关管T1的正向导通电压。在本实施例中，Vbe在0.7V左右。
当第二时钟控制信号CLK2变为高电平后，第五MOS管M5导通，第六MOS管M6截止，自举电容C的负极板电压变为VDD。根据电荷守恒原理，自举电容C的正极板电压变为(2VDD-Vbe)。此时，自举电容C的正极板电压大于VDD，故第二开关管T2正向偏置，第一开关管T1反向偏置。自举电容C的电荷通过第二开关管T2泄放，其正极板电压最终稳定在(VDD+Vbe)上。当CLK1变为高电平时，第一MOS管M1截止，第二MOS管M2导通，从而使得第三MOS管M3导通，第四MOS管M4截止，输出端输出电压为(VDD+Vbe)的开关控制信号H1。开关控制信号H1控制开关管M7导通，从而使得开关电路导通，实现对模拟信号VIN的采样。
在本实施例中，形成的开关控制信号H1作为开关管M7的控制信号，可以明显减小开关管的导通电阻，且开关控制信号H1的电压增量固定，为第二开关管T2的正向导通电压，其值在0.7V左右。因此，增量电压不会过高，不会导致开关被击穿，在降低开关电路内阻的同时，提高了电路的可靠性。并且，本案中的开关控制电路的电路结构简单，使用灵活，可以广泛应用于各种工艺平台。上述开关控制电路能够避免在电路节点中出现过高电压的可能，提高了电路的可靠性。另外，上述开关控制电路占用的版图面积也较小，能够满足需要对模拟信号进行高速高精度采样的大部分场合。
图5为另一实施例中的开关控制电路的电路原理图，图6则为图5中的开关控制电路所对应的开关电路的电路原理图。本实施例中开关电路中包括了由MOS管M8和MOS管M9形成的开关对。具体地，MOS管M8为NMOS管，MOS管M9为PMOS管。开关控制电路中的反相电路在图2所示实施例中的反相电路的基础上还包括了第三反相单元和延时电路。
在本实施例中，开关电路包括MOS管M8和MOS管M9，因此需要两路控制信号来对MOS管M8和MOS管M9分别进行控制。前述提及的开关控制信号H1为第一控制信号，输出给MOS管M8的栅极。第三反相单元则用于生成第二控制信号N1并输出给MOS管M9的栅极，从而控制MOS管M9的通断。第二控制信号N1和第一控制信号H1互为反相。具体地，第三反相单元包括三个顺次串联的反相器INV1、INV2以及INV3。反相器INV3的输出端输出第二控制信号H1。
由于第一时钟控制信号CLK1经过三级反相器的延时，因此为保证第一控制信号H1和第二控制信号H2这一对互补信号在时序上尽量同步，在反相电路中设置延时电路。延时电路包括第三开关管T3。第三开关管T3的输入端和控制端连接后与第二MOS管M2的源极连接。第三开关管T3的输出端接地。第三开关管T3为NPN型晶体管。在本实施例中，第三开关管T3的输入端为NPN型晶体管的集电极；第三开关管T3的控制端为NPN型晶体管的基极；第三开关管T3的输出端为NPN型晶体管的发射极。在其他的实施例中，第三开关管T3还可以为N沟道MOS管。因此，通过延时电路以及第一反相单元、第二反相单元形成三级延时，可以保证第一控制信号H1和第二控制信号H2这一对互补信号在时序上尽量同步，从而保证MOS管M8和MOS管M9能同时断开和闭合。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详 细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (11)

  1. 一种开关控制电路，包括：
    时钟电路，用于生成第一时钟控制信号和第二时钟控制信号；
    电压提升电路，分别与所述时钟电路、所述开关控制电路的供电电源连接；所述电压提升电路用于接收所述第二时钟控制信号以及所述供电电源输出的工作电压，并在所述第二时钟控制信号的控制下，将所述工作电压提升预设值后形成开关控制信号；以及
    反相电路，分别与所述时钟电路、电压提升电路连接；所述反相电路用于接收所述第一时钟控制信号以及所述开关控制信号，并根据所述第一时钟控制信号控制是否将所述开关控制信号输出给所述开关电路，以对所述开关电路的通断进行控制。
  2. 根据权利要求1所述的开关控制电路，其特征在于，所述第一时钟控制信号和所述第二时钟控制信号为互补的不交叠时钟信号。
  3. 根据权利要求1所述的开关控制电路，其特征在于，所述反相电路包括第一反相单元和第二反相单元；所述第一反相单元和所述第二反相单元均为CMOS反相器；所述第一反相单元包括第一MOS管和第二MOS管；所述第二反相单元包括第三MOS管和第四MOS管；所述第一MOS管和所述第三MOS管为PMOS管，所述第二MOS管和所述第四MOS管为NMOS管；
    所述第一MOS管的栅极与所述第二MOS管的栅极连接后与所述时钟电路连接，用于接收所述第一时钟控制信号；所述第一MOS管的源极与所述供电电源连接；所述第一MOS管的漏极与所述第二MOS管的漏极连接后，与所述第三MOS管的栅极连接；所述第三MOS管的栅极与所述第四MOS管的栅极连接；所述第三MOS管的源极与所述电压提升电路连接；所述第三MOS管的漏极和所述第四MOS管的漏极连接后作为输出端，用于输出所述开关控制信号；所述第二MOS管的源极和所述第四MOS管的源极连接后接地。
  4. 根据权利要求3所述的开关控制电路，其特征在于，所述开关电路包 括两个开关管；所述开关控制信号为第一控制信号；所述反相电路还包括第三反相单元，与所述时钟电路连接，用于接收所述第一时钟控制信号并对所述第一时钟控制信号进行反相，形成第二控制信号后输出给所述开关电路；所述第一控制信号和所述第二控制信号分别对所述开关电路中的两个开关管的通断进行控制。
  5. 根据权利要求4所述的开关控制电路，其特征在于，所述反相电路还包括延时电路；所述延时电路连接于所述第二MOS管的源极与地之间，用于延迟所述第一控制信号的输出，使得所述第一控制信号和所述第二控制信号同步输出。
  6. 根据权利要求5所述的开关控制电路，其特征在于，所述延时电路包括第三开关管；所述第三开关管的输入端与所述第二MOS管的源极连接，所述第三开关管的输出端接地；所述第三开关管的控制端与所述第三开关管的输入端连接。
  7. 根据权利要求6所述的开关控制电路，其特征在于，所述第三开关管为NPN型晶体管。
  8. 根据权利要求4所述的开关控制电路，其特征在于，所述第三反相单元包括三个依次串联的反相器。
  9. 根据权利要求1所述的开关控制电路，其特征在于，所述电压提升电路包括第四反相单元、第一开关管、第二开关管以及自举电容；所述第四反相单元分别与所述供电电源、所述时钟电路以及所述自举电容的负极板连接；所述第一开关管的输入端与所述供电电源连接，所述第一开关管的输出端分别与所述自举电容的正极板、所述反相电路连接；所述第二开关管的输入端分别与所述自举电容的正极板、所述反相电路连接；所述第二开关管的输出端与所述供电电源连接；所述预设值为所述第二开关管的正向导通电压。
  10. 根据权利要求9所述的开关控制电路，其特征在于，所述第四反相单元为CMOS反相器，包括第五MOS管和第六MOS管；所述第五MOS管为PMOS管，所述第六MOS管为NMOS管；所述第五MOS管的栅极与所 述第六MOS管的栅极连接后与所述时钟电路连接，用于接收所述第二时钟控制信号；所述第五MOS管的源极与所述供电电源连接；所述第五MOS管的漏极与所述第六MOS管的漏极连接后与所述自举电容的负极板连接；所述第六MOS管的源极接地。
  11. 根据权利要求9所述的开关控制电路，其特征在于，所述第一开关管和所述第二开关管均为NPN型晶体管。
PCT/CN2016/081685 2015-07-28 2016-05-11 开关控制电路 Ceased WO2017016274A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/748,156 US10236876B2 (en) 2015-07-28 2016-05-11 Switch control circuit with booster

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510452720.6A CN106411302B (zh) 2015-07-28 2015-07-28 开关控制电路
CN201510452720.6 2015-07-28

Publications (2)

Publication Number Publication Date
WO2017016274A1 true WO2017016274A1 (zh) 2017-02-02
WO2017016274A9 WO2017016274A9 (zh) 2018-02-01

Family

ID=57884067

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/081685 Ceased WO2017016274A1 (zh) 2015-07-28 2016-05-11 开关控制电路

Country Status (3)

Country Link
US (1) US10236876B2 (zh)
CN (1) CN106411302B (zh)
WO (1) WO2017016274A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109228360B (zh) * 2018-10-31 2020-12-15 安徽省春谷3D打印智能装备产业技术研究院有限公司 3d打印机皮带松紧调节装置
CN114375084B (zh) * 2020-10-16 2025-07-18 格科微电子（上海）有限公司 Cmos开关触发电路
CN113570998B (zh) 2021-07-30 2022-05-10 惠科股份有限公司 显示面板的控制电路和显示装置
CN114566877A (zh) * 2021-11-12 2022-05-31 杭州耐立电气有限公司 一种用于高压开关柜的安全监测系统
CN115729302A (zh) * 2022-12-09 2023-03-03 浙江地芯引力科技有限公司 电压产生电路及带隙基准装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009017640A (ja) * 2007-07-03 2009-01-22 Nec Electronics Corp 昇圧回路、およびその昇圧回路を備える集積回路
CN101540600A (zh) * 2009-04-09 2009-09-23 复旦大学 一种应用于开关电容电路的双自举开关
CN102270981A (zh) * 2011-06-28 2011-12-07 上海宏力半导体制造有限公司 采样开关电路
CN102545862A (zh) * 2010-12-23 2012-07-04 无锡华润上华半导体有限公司 开关电路
CN103326700A (zh) * 2013-05-23 2013-09-25 苏州苏尔达信息科技有限公司 一种自举采样开关电路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5808502A (en) * 1995-06-05 1998-09-15 Hewlett-Packard Co. Parallel micro-relay bus switch for computer network communication with reduced crosstalk and low on-resistance using charge pumps
JP4354056B2 (ja) * 1999-10-12 2009-10-28 株式会社 沖マイクロデザイン 半導体集積回路
US6404237B1 (en) * 2000-12-29 2002-06-11 Intel Corporation Boosted multiplexer transmission gate
US6693479B1 (en) * 2002-06-06 2004-02-17 Analog Devices, Inc. Boost structures for switched-capacitor systems
US20070046359A1 (en) * 2005-08-29 2007-03-01 Texas Instruments Incorporated Apparatus and method for effecting switching of an input signal by a switching transistor
CN101977046B (zh) * 2010-09-25 2012-07-04 西安电子科技大学 自举采样开关电路和自举电路
US8624663B2 (en) * 2012-03-02 2014-01-07 Fairchild Semiconductor Corporation Methods and apparatus related to an improved complementary MOSFET switch
US8525574B1 (en) * 2012-05-15 2013-09-03 Lsi Corporation Bootstrap switch circuit with over-voltage prevention
CN103762986A (zh) * 2014-01-16 2014-04-30 四川和芯微电子股份有限公司 采样保持开关电路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009017640A (ja) * 2007-07-03 2009-01-22 Nec Electronics Corp 昇圧回路、およびその昇圧回路を備える集積回路
CN101540600A (zh) * 2009-04-09 2009-09-23 复旦大学 一种应用于开关电容电路的双自举开关
CN102545862A (zh) * 2010-12-23 2012-07-04 无锡华润上华半导体有限公司 开关电路
CN102270981A (zh) * 2011-06-28 2011-12-07 上海宏力半导体制造有限公司 采样开关电路
CN103326700A (zh) * 2013-05-23 2013-09-25 苏州苏尔达信息科技有限公司 一种自举采样开关电路

Also Published As

Publication number Publication date
WO2017016274A9 (zh) 2018-02-01
CN106411302B (zh) 2019-03-15
US10236876B2 (en) 2019-03-19
CN106411302A (zh) 2017-02-15
US20180262191A1 (en) 2018-09-13

Similar Documents

Publication Publication Date Title
US10714155B2 (en) Charge pump circuit with low reverse current and low peak current
US10546519B2 (en) Gate driving circuits and display panels
US10140910B2 (en) Shift register, a gate line driving circuit, an array substrate and a display apparatus
WO2015109769A1 (zh) 移位寄存器单元、栅极驱动电路及其驱动方法、显示装置
JP6601667B2 (ja) シフトレジスタ回路及びゲートドライバ並びに表示装置
WO2017016274A1 (zh) 开关控制电路
CN107094012B (zh) 一种电平转换电路及方法
CN102904565A (zh) 一种用于dc-dc驱动的超低静态电流的电平移位电路
JPH0282713A (ja) スイッチング補助回路
WO2022057366A1 (zh) 一种负压电平转换控制电路和方法
CN107786187B (zh) 时钟电压提升电路
CN104991113B (zh) 应用于高频开关电源中的过零检测电路
WO2016115797A1 (zh) 触控电路、触控面板及显示装置
CN104917359A (zh) 一种上开关管驱动电路及应用其的同步boost电路
CN112769430B (zh) 一种信号沿检测延时电路、电器及信号沿检测延时装置
WO2017020506A1 (zh) 触控驱动电极的驱动单元、方法、电路和触控显示面板
JP2020532199A (ja) 電位変換回路及び表示パネル
CN104917492A (zh) 一种cmos振荡器
CN104935302A (zh) 直流电压产生电路及其脉冲产生电路
CN108809285A (zh) 一种隔离高压输入的传输门电路
CN107104663B (zh) 用于信道选择开关的自举电路
CN107517045B (zh) 一种环形振荡器
TWI601385B (zh) 延遲電路
CN105991126A (zh) 一种反相器
CN204103893U (zh) 一种电平转换电路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16829641

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 15748156

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16829641

Country of ref document: EP

Kind code of ref document: A1