WO2017015985A1 - 一种像素单元、coa基板和液晶显示面板 - Google Patents

一种像素单元、coa基板和液晶显示面板 Download PDF

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Publication number
WO2017015985A1
WO2017015985A1 PCT/CN2015/086376 CN2015086376W WO2017015985A1 WO 2017015985 A1 WO2017015985 A1 WO 2017015985A1 CN 2015086376 W CN2015086376 W CN 2015086376W WO 2017015985 A1 WO2017015985 A1 WO 2017015985A1
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Prior art keywords
bridge
pixel unit
adjacent
holes
color resist
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English (en)
French (fr)
Inventor
熊源
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/779,689 priority Critical patent/US10217770B2/en
Publication of WO2017015985A1 publication Critical patent/WO2017015985A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a pixel unit, a COA substrate, and a liquid crystal display panel.
  • COA Color filter On Array
  • the color film layer is directly formed on the array substrate.
  • M1 first metal layer
  • M2 second metal layer
  • M1/ITO indium tin oxide layer
  • M1/ITO indium tin oxide layer
  • M2/ITO electrical conduction of the conductive layer
  • the prior art needs to separately set a color resistance opening for each bridge hole, and the space occupied by the single color resistance opening is large; therefore, in the TFT layout design, the color resistance opening takes up a lot of space and reduces The space utilization and aperture ratio of the TFT (Thin Film Transistor) region.
  • the pixel unit includes: a color resist layer 10 and a pixel electrode 11 .
  • the first bridge hole 101 and the second bridge hole 102 need to be separately in the color resist layer.
  • the upper 10 is provided with two corresponding color resist openings, the first color resist opening 103 and the second color resist opening 104; and at the same time, since the edge of each color resist opening is away from the edge of the bridge hole (ie, the color resistance is open)
  • the spacing between the hole and the bridge hole has a certain requirement, that is, the distance d1 between the first color resist opening 103 and the first bridge hole 101 in FIG. 1 , the second color resist opening 104 and the second bridge hole
  • the spacing d2 between 102 has certain requirements; thus, the color resist opening in the pixel unit takes up a lot of space, which reduces the space utilization and aperture ratio of the TFT region.
  • An embodiment of the present invention provides a pixel unit, including:
  • a thin film transistor for controlling whether to transmit a data signal to a corresponding one of the pixel electrodes through a drain of the thin film transistor according to a scan signal
  • a color resist layer having an actual color resist opening, the color resist layer being used to form a color filter
  • each of the bridge holes corresponding to a conventional pitch, wherein the conventional pitch is a conventional color resist opening corresponding to the bridge hole, and a spacing between the bridge holes;
  • the plurality of bridge holes are all included in the actual color resist opening
  • the spacing between adjacent two bridge holes is less than the sum of the respective normal spacings of the adjacent two bridge holes.
  • the sum of the respective conventional pitches of the adjacent two bridge holes is greater than 14 um, and the spacing between the adjacent two of the bridge holes is less than 14 um.
  • the thin film transistor includes:
  • a semiconductor layer disposed on the gate insulating layer for forming a channel of the thin film transistor
  • a source and a drain respectively located on both sides of the semiconductor layer
  • the color resist layer is disposed on the drain and the gate insulating layer.
  • the pixel unit includes a first bridge hole and a second bridge hole, the first bridge hole being adjacent to the second bridge hole;
  • the spacing between the first bridging aperture and the second bridging aperture is less than the sum of the conventional spacing of the first bridging aperture and the corresponding spacing of the second bridging aperture.
  • the spacing between the adjacent two of the bridge holes is less than 14 um and greater than 7 um.
  • Embodiments of the present invention also provide a COA substrate, including:
  • the data line is configured to transmit a data signal
  • the scan line is configured to transmit a scan signal
  • the first pixel unit is configured to perform screen display according to the data signal line, and includes:
  • a thin film transistor for controlling whether to transmit a data signal to a corresponding one of the pixel electrodes through a drain of the thin film transistor according to a scan signal
  • a color resist layer having an actual color resist opening, the color resist layer being used to form a color filter
  • each of the bridge holes corresponding to a common pitch, wherein the normal pitch is a spacing between a conventional color resist opening corresponding to the bridge hole and the bridge hole;
  • a pixel electrode disposed on the color resist layer and electrically connected to a drain of the thin film transistor through one of the bridge holes; the pixel is configured to control a corresponding liquid crystal molecule according to the data signal;
  • a plurality of bridge holes in the first pixel unit are included in the actual color resist opening
  • the spacing between adjacent two bridge holes is less than the sum of the respective normal spacings of the adjacent two bridge holes.
  • a second pixel unit is further formed on the substrate substrate;
  • the second pixel unit is configured to perform screen display according to the data signal, the second pixel unit is adjacent to the first pixel unit, and has at least one of the bridge holes;
  • At least one of the bridge holes of the second pixel unit is included in the actual color resist opening
  • the actual color resistance openings belong to different pixel units, and the spacing between the adjacent two bridge holes is smaller than the sum of the corresponding common spacings of the adjacent two bridge holes.
  • the second pixel unit has a bridge hole located in the actual color resist opening and adjacent to a bridge hole belonging to the first pixel unit.
  • the sum of the corresponding common pitches of the adjacent two bridge holes is greater than 14 um, and the spacing between the adjacent two of the bridge holes is less than 14 um.
  • the thin film transistor includes:
  • a semiconductor layer disposed on the gate insulating layer for forming a channel of the thin film transistor
  • a source and a drain respectively located on both sides of the semiconductor layer
  • the color resist layer is disposed on the drain and the gate insulating layer.
  • the first pixel unit includes a first bridge hole and a second bridge hole, and the first bridge hole is adjacent to the second bridge hole;
  • the spacing between the first bridging aperture and the second bridging aperture is less than the sum of the conventional spacing of the first bridging aperture and the corresponding spacing of the second bridging aperture.
  • the second pixel unit has two adjacent bridge holes, the two adjacent bridge holes are located in the actual color resist opening, and the two adjacent bridge holes One of the bridge holes is adjacent to a bridge hole belonging to the first pixel unit.
  • the spacing between the adjacent two of the bridge holes is less than 14 um and greater than 7 um.
  • An embodiment of the present invention further provides a liquid crystal display panel comprising: a COA substrate, a glass substrate, and a liquid crystal layer disposed between the COA substrate and the glass substrate;
  • COA substrate comprises:
  • the data line is configured to transmit a data signal
  • the scan line is configured to transmit a scan signal
  • the first pixel unit is configured to perform screen display according to the data signal line, and includes:
  • a thin film transistor for controlling whether to transmit a data signal to a corresponding one of the pixel electrodes through a drain of the thin film transistor according to a scan signal
  • a color resist layer having an actual color resist opening, the color resist layer being used to form a color filter
  • each of the bridge holes corresponding to a conventional pitch, wherein the conventional pitch is a conventional color resist opening corresponding to the bridge hole, and a spacing between the bridge holes;
  • a pixel electrode disposed on the color resist layer and electrically connected to a drain of the thin film transistor through one of the bridge holes; the pixel is configured to control a corresponding liquid crystal molecule according to the data signal;
  • a plurality of bridge holes in the first pixel unit are included in the actual color resist opening
  • the spacing between adjacent two bridge holes is less than the sum of the respective normal spacings of the adjacent two bridge holes.
  • a second pixel unit is further formed on the substrate substrate;
  • the second pixel unit is configured to perform screen display according to the data signal, the second pixel unit is adjacent to the first pixel unit, and has at least one of the bridge holes;
  • At least one of the bridge holes of the second pixel unit is included in the actual color resist opening
  • the actual color resistance openings belong to different pixel units, and the spacing between the adjacent two bridge holes is smaller than the sum of the corresponding common spacings of the adjacent two bridge holes.
  • the second pixel unit has a bridge hole located in the actual color resist opening and adjacent to a bridge hole belonging to the first pixel unit.
  • the sum of the respective conventional pitches of the adjacent two bridge holes is greater than 14 um, and the spacing between the adjacent two of the bridge holes is less than 14 um.
  • the spacing between the adjacent two of the bridge holes is less than 14 um and greater than 7 um.
  • the thin film transistor includes:
  • a semiconductor layer disposed on the gate insulating layer for forming a channel of the thin film transistor
  • a source and a drain respectively located on both sides of the semiconductor layer
  • the color resist layer is disposed on the drain and the gate insulating layer.
  • the first pixel unit includes a first bridge hole and a second bridge hole, and the first bridge hole is adjacent to the second bridge hole;
  • a spacing between the first bridging aperture and the second bridging aperture is less than a sum of a conventional spacing of the first bridging aperture and a corresponding spacing of the second bridging aperture.
  • the present invention provides a pixel unit, a COA substrate, and a liquid crystal display panel.
  • the plurality of bridge holes in the pixel unit of the present invention are all included in an actual color resist opening, and the spacing between adjacent two bridge holes is smaller than the The sum of the corresponding common spacings of the two adjacent bridge holes; it can be seen that the plurality of bridge holes in the pixel unit of the present invention can share one color resist opening, and the spacing between adjacent two bridge holes is smaller than the adjacent two The sum of the corresponding spacings of the respective bridge holes, so that the shared color resist opening occupies less space than the space occupied by the conventional color resist opening corresponding to the plurality of bridge holes, compared with the prior art.
  • the space occupied by the color resist opening can be reduced, thereby improving the space utilization ratio of the TFT region and increasing the aperture ratio.
  • 1 is a schematic view of a conventional design color resist opening
  • FIG. 2 is a schematic diagram of a color-blocking opening in a pixel unit according to Embodiment 1 of the present invention
  • FIG. 3 is a schematic diagram showing the design of a color resistance opening in a pixel unit according to Embodiment 2 of the present invention.
  • FIG. 4 is a schematic structural diagram of a liquid crystal display panel according to Embodiment 3 of the present invention.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • this embodiment provides a pixel unit, including:
  • a thin film transistor (not shown) for controlling whether a data signal is transmitted to a corresponding one of the pixel electrodes through a drain of the thin film transistor according to a scan signal;
  • the thin film transistor includes a gate formed by a first metal layer, a gate insulating layer, a semiconductor layer, a source and a drain formed by the second metal layer, a gate receiving a scan signal transmitted by the scan line, and a source receiving the data line for transmitting Data signal
  • a gate insulating layer disposed on the gate; a semiconductor layer disposed on the gate insulating layer for forming a channel of the thin film transistor;
  • a source and a drain are respectively located on both sides of the semiconductor layer
  • the color resist layer 20 has an actual color resist opening 201, and the color resist layer 201 is used to form a color filter; in particular, the color resist layer 201 may be disposed on the drain and the gate insulating layer;
  • the actual color resist opening 201 in the embodiment may be a rectangle, and the bridge hole may be a rectangle;
  • the two bridge holes are the first bridge hole 22 and the second bridge hole 23, wherein the first bridge hole 22 can be a bridge hole for electrically connecting the pixel electrode 21 and the drain of the thin film transistor.
  • the second bridge hole 23 may be a bridge hole for electrically connecting the drain or source of the thin film transistor to other layers, other electrodes or other traces;
  • the pixel unit may have three, four or more bridge holes, and the number of the specific bridge holes is set according to actual needs;
  • each bridge hole corresponds to a conventional color resistance opening
  • the conventional color resistance opening refers to a color resistance opening with a certain distance between the edge and the edge of the bridge hole, that is, the distance from the bridge hole reaches a preset spacing.
  • a pixel electrode 21 disposed on the color resist layer 20 and electrically connected to the drain of the thin film transistor through one of the bridge holes (the bridge hole 22 in FIG. 2); the pixel electrode is used according to the The data signal controls the corresponding liquid crystal molecules;
  • the plurality of bridge holes are all included in the actual color resist opening, and the first bridge hole 22 and the second bridge hole 23 in FIG. 2 are all included in the actual color resist opening 201;
  • the spacing between adjacent two bridge holes is smaller than the sum of the corresponding common spacings of the adjacent two bridge holes; specifically, referring to FIG. 1, the first spacing of the first bridge holes 22 may be d1, the second bridge hole 23 corresponding to the conventional spacing may be d2; Referring to Figure 2, the distance between the first bridging hole 22 and the second bridging hole 23 is d3;
  • d1+d2 will generally be greater than 14um, so d3 is less than 14um.
  • the first bridging hole 22 and the second bridging hole 23 share an actual color resisting hole 201, and d3 ⁇ d1+d2; the area occupied by d1 and d2 can be compressed into the area occupied by d3, thereby reducing the color.
  • the space occupied by the hole is blocked, the space utilization ratio of the TFT area is improved, and the aperture ratio is improved.
  • the space occupied by the color resist opening can also be reduced, the space utilization ratio of the TFT region can be improved, and the aperture ratio can be improved.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • This embodiment provides a COA substrate, including:
  • the data line is configured to transmit a data signal
  • the scan line is configured to transmit a scan signal
  • the first pixel unit is configured to perform screen display according to the data signal line, and includes:
  • a thin film transistor for controlling whether to transmit a data signal to a corresponding one of the pixel electrodes through a drain of the thin film transistor according to a scan signal
  • the color resist layer 20 has an actual color resist opening 201, and the color resist layer 20 is used to form a color filter;
  • each of the bridge holes corresponding to a common pitch, wherein the normal pitch is a spacing between a conventional color resist opening corresponding to the bridge hole and the bridge hole;
  • the two bridging holes are taken as an example, the first bridging hole 22 and the second bridging hole 23, wherein the first bridging hole 22 can be a bridging hole for electrically connecting the pixel electrode 21 and the drain of the thin film transistor.
  • the second bridge hole 23 may be a bridge hole for electrically connecting the drain or the source of the thin film transistor to other layers, other electrodes or other traces;
  • a pixel electrode 21 disposed on the color resist layer 20 and electrically connected to the drain of the thin film transistor through one of the bridge holes (the bridge hole 22 in FIG. 2); the pixel electrode is used according to the The data signal controls the corresponding liquid crystal molecules;
  • the plurality of bridge holes are all included in the actual color resist opening, and the first bridge hole 22 and the second bridge hole 23 in FIG. 2 are all included in the actual color resist opening 201;
  • the spacing between two adjacent bridge holes is smaller than the sum of the respective normal spacings of the adjacent two bridge holes, that is, d3 ⁇ d1 + d2.
  • the design of the color-resistance opening in the first pixel unit in this embodiment may refer to the color-resistance opening design of the pixel unit of FIG. 2; in this embodiment, the pixel unit bridge hole shares a color by adjusting the position of the pixel unit bridge hole. The hole is blocked to reduce the space occupied by the color resistance opening and increase the aperture ratio.
  • the bridging holes of the adjacent two pixel units may share a color resist opening; specifically, as shown in FIG. 3, the COA substrate in this embodiment is Forming a second pixel unit on the substrate;
  • the second pixel unit is configured to perform screen display according to the data signal, the second pixel unit is adjacent to the first pixel unit, and has at least one of the bridge holes;
  • the second pixel unit includes: a color resist layer 30 and a pixel electrode 31; the second pixel unit has one or more bridge holes; as shown in FIG. 3, a third bridge hole 32 is taken as an example;
  • At least one of the bridge holes of the second pixel unit is included in the actual color resist opening, and the third bridge hole 32 of the specific map 3 is included in the actual color resist opening 201;
  • first The bridge hole 22, the second bridge hole 23 and the third bridge hole 32 are sequentially adjacent, and are all included in the actual color resistance opening 201;
  • the spacing between the second bridging hole 23 and the third bridging hole 32 in the actual color resisting opening 201 is d4;
  • the bridge holes of adjacent pixel units can share a color resist opening, and the area occupied by d1 and d2 can be compressed into d3.
  • the occupied area compresses the area occupied by d2 and d5 into the area occupied by d4, further reducing the space occupied by the color resist opening and increasing the aperture ratio.
  • d2+d5 is generally greater than 14um, so d4 is less than 14um.
  • the first pixel unit has two bridge holes, but the second pixel unit has one bridge hole, and the first pixel unit has a plurality of bridge holes, and the second pixel unit has a plurality of bridge holes.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • the present embodiment provides a liquid crystal display panel comprising: a COA substrate 401, a glass substrate 403, and a liquid crystal layer 402 disposed between the COA substrate 401 and the glass substrate 403;
  • the COA substrate 403 includes:
  • the data line is configured to transmit a data signal
  • the scan line is configured to transmit a scan signal
  • the first pixel unit is configured to perform screen display according to the data signal line, and includes:
  • a thin film transistor (not shown) for controlling whether a data signal is transmitted to a corresponding one of the pixel electrodes through a drain of the thin film transistor according to a scan signal;
  • the color resist layer 20 has an actual color resist opening 201 for forming a color filter
  • a plurality of bridging holes for electrical connection that is, a first bridging hole 22 and a second bridging hole 23, each of the bridging holes corresponding to a regular spacing, the conventional spacing being a conventional color resistance corresponding to the bridging hole a spacing between the opening and the bridging hole;
  • the pixel electrode 21 is disposed on the color resist layer 20 and electrically connected to the drain of the thin film transistor through a first bridge hole 22; the pixel is configured to control corresponding liquid crystal molecules according to the data signal;
  • the first bridge hole 22 and the second bridge hole 23 in the first pixel unit are all included in the actual color resist opening 201;
  • the spacing between two adjacent bridge holes is smaller than the sum of the respective normal spacings of the adjacent two bridge holes, that is, d3 ⁇ d1 + d2.
  • a second pixel unit is further formed on the substrate substrate;
  • the second pixel unit is configured to perform screen display according to the data signal, the second pixel unit is adjacent to the first pixel unit, and has at least one of the bridge holes;
  • At least one of the bridge holes of the second pixel unit is included in the actual color resist opening
  • the actual color resistance opening 201 belongs to different pixel units, and the spacing between the adjacent two bridge holes is smaller than the sum of the corresponding common spacings of the adjacent two bridge holes, that is, d4 ⁇ d2+d5.
  • the liquid crystal display panel of the embodiment can reduce the space occupied by the color resist opening, improve the space utilization ratio of the TFT region, and improve the aperture ratio.

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  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
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Abstract

一种像素单元、COA基板和液晶显示面板，像素单元中多个桥接孔（22、23）可共用一个色阻开孔（201），且相邻两个桥接孔（22、23）之间的间距小于该相邻两个桥接孔（22、23）各自对应的常规间距之和；与现有技术相比，应用所述的像素单元，可以降低色阻开孔占用的空间，进而提高TFT区域的空间利用率，提高开口率。

Description

一种像素单元、COA基板和液晶显示面板 技术领域
本发明涉及液晶显示器技术领域，特别是涉及一种像素单元、COA基板和液晶显示面板。
 背景技术
COA（Color filter On Array，彩膜层直接形成在阵列基板上）架构中为了保证M1（第一金属层）/M2（第二金属层），M1/ITO（铟锡氧化物层），M1/ITO等两个不同导电层的电性连接，需要在对应的导电层设置桥接孔；进一步为了确保桥接孔不被色阻覆盖或者方便导电层的电性导通（例如M2/ITO的电性导通），对于每个桥接孔需要在色阻层上与桥接孔对应的区域单独设置色阻开孔。
然而，由于不同导电层的制程不同，以及桥接孔与色阻开孔的制程不同；为了能够保证导电层上的桥接孔与色阻层上的色阻开孔的重合度在一定范围内，所以需要色阻开孔的孔径远大于桥接孔的孔径单个色阻开孔占用的空间较大。
可见，现有技术对于每个桥接孔需要单独设置一个色阻开孔，且单个色阻开孔占用的空间较大；因此，在TFT版图设计时，色阻开孔都会占用大量的空间，降低了TFT（薄膜晶体管）区域的空间利用率和开口率。
例如，如图1所示，像素单元包括：色阻层10和像素电极11，当像素单元中存在两个桥接孔，第一桥接孔101和第二桥接孔102时，需要单独在色阻层上10上设置2个对应的色阻开孔，级第一色阻开孔103和第二色阻开孔104；同时由于每个色阻开孔的边缘距离桥接孔边缘（也即色阻开孔与桥接孔之间的间距）都有一定的要求，即图1中第一色阻开孔103与第一桥接孔101之间的间距d1，第二色阻开孔104与第二桥接孔102之间的间距d2均有一定的要求；这样在像素单元中色阻开孔会占用大量的空间，降低了TFT区域的空间利用率和开口率。
 技术问题
本发明的目的在于提供一种像素单元、COA基板和液晶显示面板，以解决现有技术中色阻开孔占用大量空间，从而降低TFT区域的空间利用率和开口率的技术问题。
 技术解决方案
本发明的实施例提供了一种像素单元，包括：
薄膜晶体管，用于根据扫描信号控制是否将数据信号通过该薄膜晶体管的漏极传输给对应的所述像素电极；
色阻层，具有一实际色阻开孔，所述色阻层用于形成彩色滤光片；
多个用于电性连接的桥接孔，每个所述桥接孔对应一个常规间距，所述常规间距为与所述桥接孔对应的常规色阻开孔、与该桥接孔之间的间距；
像素电极，设置在所述色阻层上，并通过一个所述桥接孔与所述薄膜晶体管的漏极电性连接；所述像素电极用于根据所述数据信号控制对应的液晶分子；以及
所述多个桥接孔均包含在所述实际色阻开孔内；
相邻两个桥接孔之间的间距小于该相邻两个桥接孔各自对应的常规间距之和。
在本发明的像素单元中，所述相邻两个桥接孔各自对应的常规间距之和大于14um，所述相邻两个所述桥接孔之间的间距小于14um。
在本发明的像素单元中，所述薄膜晶体管包括：
栅极；
栅极绝缘层，设置在所述栅极上
半导体层，设置在所述栅极绝缘层上，用于形成所述薄膜晶体管的沟道；
源极和漏极，分别位于所述半导体层的两侧；以及
所述色阻层设置所述漏极和所述栅极绝缘层上。
在本发明的像素单元中，所述像素单元包括第一桥接孔和第二桥接孔，所述第一桥接孔与所述第二桥接孔相邻；
所述第一桥接孔与所述第二桥接孔之间的间距小于，第一桥接孔对应的常规间距和第二桥接孔对应的常规间距之和。
在本发明的像素单元中，所述相邻两个所述桥接孔之间的间距小于14um，且大于7um。
本发明的实施例还提供出了一种COA基板，包括：
基板衬底；
在基板衬底上形成的扫描线、数据线和第一像素单元；
所述数据线，用于传输数据信号；
所述扫描线，用于传输扫描信号；
所述第一像素单元，用于根据所述数据信号线进行画面显示，其包括：
薄膜晶体管，用于根据扫描信号控制是否将数据信号通过该薄膜晶体管的漏极传输给对应的所述像素电极；
色阻层，具有一实际色阻开孔，所述色阻层用于形成彩色滤光片；
多个用于电性连接的桥接孔，每个所述桥接孔对应一个常规间距，所述常规间距为与所述桥接孔对应的常规色阻开孔与该桥接孔之间的间距；
像素电极，设置在所述色阻层上，并通过一个所述桥接孔与所述薄膜晶体管的漏极电性连接；所述像素用于根据所述数据信号控制对应的液晶分子；
所述第一像素单元中的多个桥接孔均包含在所述实际色阻开孔内；
相邻两个桥接孔之间的间距小于该相邻两个桥接孔各自对应的常规间距之和。
在本发明的COA基板中，所述基板衬底上还形成有第二像素单元；
所述第二像素单元，用于根据所述数据信号进行画面显示，所述第二像素单元与所述第一像素单元相邻，且具有至少一个所述桥接孔；
所述第二像素单元中至少一个所述桥接孔包含在所述实际色阻开孔内；以及
所述实际色阻开孔内属于不同像素单元，且相邻的两个桥接孔之间的间距小于该相邻两个桥接孔各自对应的常规间距之和。
在本发明的COA基板中，所述第二像素单元具有一个桥接孔，该桥接孔位于所述实际色阻开孔内，且与一属于第一像素单元的桥接孔相邻。
在本发明的COA基板中，所述相邻两个桥接孔各自对应的常规间距之和大于14um，所述相邻两个所述桥接孔之间的间距小于14um。
在本发明的COA基板，所述薄膜晶体管包括：
栅极；
栅极绝缘层，设置在所述栅极上
半导体层，设置在所述栅极绝缘层上，用于形成所述薄膜晶体管的沟道；
源极和漏极，分别位于所述半导体层的两侧；以及
所述色阻层设置所述漏极和所述栅极绝缘层上。
在本发明的COA基板中，所述第一像素单元包括第一桥接孔和第二桥接孔，所述第一桥接孔与所述第二桥接孔相邻；
所述第一桥接孔与所述第二桥接孔之间的间距小于，第一桥接孔对应的常规间距和第二桥接孔对应的常规间距之和。
在本发明的COA基板中，所述第二像素单元具有两个相邻的桥接孔，该两个相邻的桥接孔位于所述实际色阻开孔内，且该两个相邻的桥接孔中的一个桥接孔与一属于第一像素单元的桥接孔相邻。
在本发明的COA基板，所述相邻两个所述桥接孔之间的间距小于14um，且大于7um。
本发明的实施例还提供了一种液晶显示面板，包括：COA基板、玻璃基板和设置在所述COA基板和所述玻璃基板之间的液晶层；
其中所述COA基板包括：
基板衬底；
在基板衬底上形成的扫描线、数据线和第一像素单元；
所述数据线，用于传输数据信号；
所述扫描线，用于传输扫描信号；
所述第一像素单元，用于根据所述数据信号线进行画面显示，其包括：
薄膜晶体管，用于根据扫描信号控制是否将数据信号通过该薄膜晶体管的漏极传输给对应的所述像素电极；
色阻层，具有一实际色阻开孔，所述色阻层用于形成彩色滤光片；
多个用于电性连接的桥接孔，每个所述桥接孔对应一个常规间距，所述常规间距为与所述桥接孔对应的常规色阻开孔、与该桥接孔之间的间距；
像素电极，设置在所述色阻层上，并通过一个所述桥接孔与所述薄膜晶体管的漏极电性连接；所述像素用于根据所述数据信号控制对应的液晶分子；
所述第一像素单元中的多个桥接孔均包含在所述实际色阻开孔内；以及
相邻两个桥接孔之间的间距小于该相邻两个桥接孔各自对应的常规间距之和。
在本发明的液晶显示面板中，所述基板衬底上还形成有第二像素单元；
所述第二像素单元，用于根据所述数据信号进行画面显示，所述第二像素单元与所述第一像素单元相邻，且具有至少一个所述桥接孔；
所述第二像素单元中至少一个所述桥接孔包含在所述实际色阻开孔内；
所述实际色阻开孔内属于不同像素单元，且相邻的两个桥接孔之间的间距小于该相邻两个桥接孔各自对应的常规间距之和。
在本发明的液晶显示面板中，所述第二像素单元具有一个桥接孔，该桥接孔位于所述实际色阻开孔内，且与一属于第一像素单元的桥接孔相邻。
在本发明的液晶显示面板中，所述相邻两个桥接孔各自对应的常规间距之和大于14um，所述相邻两个所述桥接孔之间的间距小于14um。
在本发明的液晶显示面板中，所述相邻两个所述桥接孔之间的间距小于14um，且大于7um。
在本发明的液晶显示面板中，所述薄膜晶体管包括：
栅极；
栅极绝缘层，设置在所述栅极上
半导体层，设置在所述栅极绝缘层上，用于形成所述薄膜晶体管的沟道；
源极和漏极，分别位于所述半导体层的两侧；以及
所述色阻层设置所述漏极和所述栅极绝缘层上。
在本发明的液晶显示面板中，所述第一像素单元包括第一桥接孔和第二桥接孔，所述第一桥接孔与所述第二桥接孔相邻；
所述第一桥接孔与所述第二桥接孔之间的间距小于，所述第一桥接孔对应的常规间距和所述第二桥接孔对应的常规间距之和。
 有益效果
本发明提供了一种像素单元、COA基板和液晶显示面板；本发明的像素单元中多个桥接孔均包含在一个实际色阻开孔内，且相邻两个桥接孔之间的间距小于该相邻两个桥接孔各自对应的常规间距之和；可见本发明像素单元中的多个桥接孔可以共用一个色阻开孔，且由于相邻两个桥接孔之间的间距小于该相邻两个桥接孔各自对应的常规间距之和，因此，该共用的色阻开孔占用的空间比多个桥接孔对应的常规色阻开孔所占用的空间之和小，与现有技术相比，应用本发明的像素单元，可以降低色阻开孔占用的空间，进而提高TFT区域的空间利用率，提高开口率。
 附图说明
图1为现有设计色阻开孔的示意图；
图2为本发明实施例一提供的像素单元中色阻开孔的设计示意图；
图3为本发明实施例二提供的像素单元中色阻开孔的设计示意图；
图4为本发明实施例三提供的一种液晶显示面板的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
实施例一：
如图2所示本实施例提供了一种像素单元，包括：
薄膜晶体管（图中未示意出），用于根据扫描信号控制是否将数据信号通过该薄膜晶体管的漏极传输给对应的所述像素电极；
薄膜晶体管包括由第一金属层形成栅极，栅极绝缘层、半导体层、由第二金属层形成的源极和漏极，栅极接收扫描线传输的扫描信号，源极接收数据线传输的数据信号；
栅极绝缘层，设置在所述栅极上；半导体层，设置在所述栅极绝缘层上，用于形成所述薄膜晶体管的沟道；
源极和漏极，分别位于所述半导体层的两侧；
色阻层20，具有一实际色阻开孔201，所述色阻层201用于形成彩色滤光片；具体地色阻层201可以设置所述漏极和所述栅极绝缘层上；优选地，本实施例中实际色阻开孔201可以为矩形，桥接孔可以为矩形；
多个用于电性连接的桥接孔，每个所述桥接孔对应一个常规间距，所述常规间距为与所述桥接孔对应的常规色阻开孔与该桥接孔之间的间距；本实施例以两个桥接孔为例，第一桥接孔22和第二桥接孔23，其中第一桥接孔22可以为用于像素电极21与所述薄膜晶体管的漏极电性连接的桥接孔，第二桥接孔23可以为用于薄膜晶体管的漏极或者源极与其他层、其他电极或者其他走线电性连接的桥接孔；
应当理解的是，在其他实施例中像素单元可以具有3个、4个或者4个以上的桥接孔，具体桥接孔的数量根据实际需求进行设定；
本实施例中每个桥接孔对应一个常规色阻开孔，常规色阻开孔指的是边缘与桥接孔边缘的距离达到一定要求的色阻开孔，即与桥接孔的间距达到预设间距的色阻开孔；其中该预设间距即为常规间距；
像素电极21，设置在所述色阻层20上，并通过一个所述桥接孔（图2中通过桥接孔22）与所述薄膜晶体管的漏极电性连接；所述像素电极用于根据所述数据信号控制对应的液晶分子；以及
所述多个桥接孔均包含在所述实际色阻开孔内，图2中第一桥接孔22和第二桥接孔23均包含在实际色阻开孔201内；
相邻两个桥接孔之间的间距小于该相邻两个桥接孔各自对应的常规间距之和；具体地，参考图1，第一桥接孔22对应的常规间距可以为d1，第二桥接孔23对应的常规间距可以为d2；参考图2，第一桥接孔22与第二桥接孔23之间的间距为d3；
其中d3＜d1+d2，在实际应用中，d1+d2一般会大于14um，因此d3小于14um。
优选地，为便于走线的布局和TFT版图的设计，本实施例中7um＜d3＜14um。
本实施例中第一桥接孔22和第二桥接孔23共用一个实际色阻孔201，且d3＜d1+d2；可以将d1，d2所占区域压缩成d3所占的区域，因此可以降低色阻开孔占用的空间，提高TFT区域的空间利用率，提高开口率。
同理，在其他实施例中像素单元包括3个、4个或者4个以上的桥接孔的情况下，同样可以降低色阻开孔占用的空间，提高TFT区域的空间利用率，提高开口率。
实施例二：
本实施例提供了一种COA基板，包括：
基板衬底；
在基板衬底上形成的扫描线、数据线和第一像素单元；
所述数据线，用于传输数据信号；
所述扫描线，用于传输扫描信号；
参考图2，所述第一像素单元，用于根据所述数据信号线进行画面显示，其包括：
薄膜晶体管，用于根据扫描信号控制是否将数据信号通过该薄膜晶体管的漏极传输给对应的所述像素电极；
色阻层20，具有一实际色阻开孔201，所述色阻层20用于形成彩色滤光片；
多个用于电性连接的桥接孔，每个所述桥接孔对应一个常规间距，所述常规间距为与所述桥接孔对应的常规色阻开孔与该桥接孔之间的间距；
本实施例以两个桥接孔为例，第一桥接孔22和第二桥接孔23，其中第一桥接孔22可以为用于像素电极21与所述薄膜晶体管的漏极电性连接的桥接孔，第二桥接孔23可以为用于薄膜晶体管的漏极或者源极与其他层、其他电极或者其他走线电性连接的桥接孔；
像素电极21，设置在所述色阻层20上，并通过一个所述桥接孔（图2中通过桥接孔22）与所述薄膜晶体管的漏极电性连接；所述像素电极用于根据所述数据信号控制对应的液晶分子；以及
所述多个桥接孔均包含在所述实际色阻开孔内，图2中第一桥接孔22和第二桥接孔23均包含在实际色阻开孔201内；
相邻两个桥接孔之间的间距小于该相邻两个桥接孔各自对应的常规间距之和，即d3＜d1+d2。
本实施例中第一像素单元中色阻开孔的设计可以参考图2种像素单元的色阻开孔设计；本实施例通过对像素单元桥接孔的位置调整，使像素单元桥接孔共用一个色阻孔，以减少色阻开孔占用的空间，提高开口率。
为能够进一步降低色阻开孔占用空间以提高开口率，可以使相邻两个像素单元的桥接孔共用一个色阻开孔；具体地，如图3所示，本实施例中COA基板在所述基板衬底上还形成有第二像素单元；
所述第二像素单元，用于根据所述数据信号进行画面显示，所述第二像素单元与所述第一像素单元相邻，且具有至少一个所述桥接孔；
所述第二像素单元包括：色阻层30和像素电极31；所述第二像素单元具有一个或者多个桥接孔；图3所示，以具有一个第三桥接孔32为例；
所述第二像素单元中至少一个所述桥接孔包含在所述实际色阻开孔内，具体地图3中第三桥接孔32包含在实际色阻开孔201内；
所述实际色阻开孔内，属于不同像素单元，且相邻的两个桥接孔之间的间距小于该相邻两个桥接孔各自对应的常规间距之和，具体到图3中，第一桥接孔22、第二桥接孔23和第三桥接孔32依次相邻，且均包含在实际色阻开孔201内；
设置第三桥接孔32对应的常规间距为d5，实际色阻开孔201内第二桥接孔23与第三桥接孔32之间的间距为d4；
在本实施例中，d3＜d1+d2，d4＜d2+d5；因此，本实施例中相邻像素单元的桥接孔可以共用一个色阻开孔，可以将d1，d2所占区域压缩成d3所占区域，将d2和d5所占区域压缩成d4所占的区域，进一步减少了色阻开孔所占空间，提高了开口率。
在实际应用中，d2+d5一般会大于14um，因此d4小于14um。
优选地，为便于走线的布局和TFT版图的设计，本实施例中7um＜d4＜14um。
本实施例中不仅限于第一像素单元具有两个桥接孔、第二像素单元具有一个桥接孔，还可以是第一像素单元具有多个桥接孔，所述第二像素单元具有多个桥接孔。
实施例三：
如图4所示，本实施例提供了一种液晶显示面板，包括：COA基板401、玻璃基板403和设置在所述COA基板401和所述玻璃基板403之间的液晶层402；其中，所述COA基板403包括：
基板衬底；
在基板衬底上形成的扫描线、数据线和第一像素单元；
所述数据线，用于传输数据信号；
所述扫描线，用于传输扫描信号；
参考图2，所述第一像素单元，用于根据所述数据信号线进行画面显示，其包括：
薄膜晶体管(未示出)，用于根据扫描信号控制是否将数据信号通过该薄膜晶体管的漏极传输给对应的所述像素电极；
色阻层20，具有一实际色阻开孔201，所述色阻层用于形成彩色滤光片；
多个用于电性连接的桥接孔，即第一桥接孔22和第二桥接孔23，每个所述桥接孔对应一个常规间距，所述常规间距为与所述桥接孔对应的常规色阻开孔与该桥接孔之间的间距；
像素电极21，设置在所述色阻层20上，并通过一个第一桥接孔22与所述薄膜晶体管的漏极电性连接；所述像素用于根据所述数据信号控制对应的液晶分子；
所述第一像素单元中的第一桥接孔22和第二桥接孔23均包含在所述实际色阻开孔201内；
相邻两个桥接孔之间的间距小于该相邻两个桥接孔各自对应的常规间距之和，即d3＜d1+d2。
优选地，参考图3，所述基板衬底上还形成有第二像素单元；
所述第二像素单元，用于根据所述数据信号进行画面显示，所述第二像素单元与所述第一像素单元相邻，且具有至少一个所述桥接孔；
所述第二像素单元中至少一个所述桥接孔包含在所述实际色阻开孔内；
所述实际色阻开孔201内，属于不同像素单元，且相邻的两个桥接孔之间的间距小于该相邻两个桥接孔各自对应的常规间距之和，即d4＜d2+d5。
应用本实施例的液晶显示面板可以降低色阻开孔占用的空间，提高TFT区域的空间利用率，提高开口率。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种像素单元，其包括：
    薄膜晶体管，用于根据扫描信号控制是否将数据信号通过该薄膜晶体管的漏极传输给对应的所述像素电极；
    色阻层，具有一实际色阻开孔，所述色阻层用于形成彩色滤光片；
    多个用于电性连接的桥接孔，每个所述桥接孔对应一个常规间距，所述常规间距为与所述桥接孔对应的常规色阻开孔、与该桥接孔之间的间距；
    像素电极，设置在所述色阻层上，并通过一个所述桥接孔与所述薄膜晶体管的漏极电性连接；所述像素电极用于根据所述数据信号控制对应的液晶分子；以及
    所述多个桥接孔均包含在所述实际色阻开孔内；
    相邻两个桥接孔之间的间距小于该相邻两个桥接孔各自对应的常规间距之和。
  2. 如权利要求1所述的像素单元，其中所述相邻两个桥接孔各自对应的常规间距之和大于14um，所述相邻两个所述桥接孔之间的间距小于14um。
  3. 如权利要求1所述的像素单元，其中
    所述薄膜晶体管包括：
    栅极；
    栅极绝缘层，设置在所述栅极上
    半导体层，设置在所述栅极绝缘层上，用于形成所述薄膜晶体管的沟道；
    源极和漏极，分别位于所述半导体层的两侧；以及
    所述色阻层设置所述漏极和所述栅极绝缘层上。
  4. 如权利要求1所述的像素单元，其中所述像素单元包括第一桥接孔和第二桥接孔，所述第一桥接孔与所述第二桥接孔相邻；
    所述第一桥接孔与所述第二桥接孔之间的间距小于，第一桥接孔对应的常规间距和第二桥接孔对应的常规间距之和。
  5. 如权利要求2所述的像素单元，其中所述相邻两个所述桥接孔之间的间距小于14um，且大于7um。
  6. 一种COA基板，其包括：
    基板衬底；
    在基板衬底上形成的扫描线、数据线和第一像素单元；
    所述数据线，用于传输数据信号；
    所述扫描线，用于传输扫描信号；
    所述第一像素单元，用于根据所述数据信号线进行画面显示，其包括：
    薄膜晶体管，用于根据扫描信号控制是否将数据信号通过该薄膜晶体管的漏极传输给对应的所述像素电极；
    色阻层，具有一实际色阻开孔，所述色阻层用于形成彩色滤光片；
    多个用于电性连接的桥接孔，每个所述桥接孔对应一个常规间距，所述常规间距为与所述桥接孔对应的常规色阻开孔与该桥接孔之间的间距；
    像素电极，设置在所述色阻层上，并通过一个所述桥接孔与所述薄膜晶体管的漏极电性连接；所述像素用于根据所述数据信号控制对应的液晶分子；
    所述第一像素单元中的多个桥接孔均包含在所述实际色阻开孔内；以及
    相邻两个桥接孔之间的间距小于该相邻两个桥接孔各自对应的常规间距之和。
  7. 如权利要求6所述的COA基板，其中
    所述基板衬底上还形成有第二像素单元；
    所述第二像素单元，用于根据所述数据信号进行画面显示，所述第二像素单元与所述第一像素单元相邻，且具有至少一个所述桥接孔；
    所述第二像素单元中至少一个所述桥接孔包含在所述实际色阻开孔内；
    所述实际色阻开孔内属于不同像素单元，且相邻的两个桥接孔之间的间距小于该相邻两个桥接孔各自对应的常规间距之和。
  8. 如权利要求7所述的COA基板，其中所述第二像素单元具有一个桥接孔，该桥接孔位于所述实际色阻开孔内，且与一属于第一像素单元的桥接孔相邻。
  9. 如权利要求6所述的COA基板，其中所述相邻两个桥接孔各自对应的常规间距之和大于14um，所述相邻两个所述桥接孔之间的间距小于14um。
  10. 如权利要求6所述的COA基板，其中所述薄膜晶体管包括：
    栅极；
    栅极绝缘层，设置在所述栅极上
    半导体层，设置在所述栅极绝缘层上，用于形成所述薄膜晶体管的沟道；
    源极和漏极，分别位于所述半导体层的两侧；以及
    所述色阻层设置所述漏极和所述栅极绝缘层上。
  11. 如权利要求6所述的COA基板，其中所述第一像素单元包括第一桥接孔和第二桥接孔，所述第一桥接孔与所述第二桥接孔相邻；
    所述第一桥接孔与所述第二桥接孔之间的间距小于，第一桥接孔对应的常规间距和第二桥接孔对应的常规间距之和。
  12. 如权利要求7所述的COA基板，其中所述第二像素单元具有两个相邻的桥接孔，该两个相邻的桥接孔位于所述实际色阻开孔内，且该两个相邻的桥接孔中的一个桥接孔与一属于第一像素单元的桥接孔相邻。
  13. 如权利要求9所述的COA基板，其中所述相邻两个所述桥接孔之间的间距小于14um，且大于7um。
  14. 一种液晶显示面板，其包括：COA基板、玻璃基板和设置在所述COA基板和所述玻璃基板之间的液晶层；其中所述COA基板包括：
    基板衬底；
    在基板衬底上形成的扫描线、数据线和第一像素单元；
    所述数据线，用于传输数据信号；
    所述扫描线，用于传输扫描信号；
    所述第一像素单元，用于根据所述数据信号线进行画面显示，其包括：
    薄膜晶体管，用于根据扫描信号控制是否将数据信号通过该薄膜晶体管的漏极传输给对应的所述像素电极；
    色阻层，具有一实际色阻开孔，所述色阻层用于形成彩色滤光片；
    多个用于电性连接的桥接孔，每个所述桥接孔对应一个常规间距，所述常规间距为与所述桥接孔对应的常规色阻开孔、与该桥接孔之间的间距；
    像素电极，设置在所述色阻层上，并通过一个所述桥接孔与所述薄膜晶体管的漏极电性连接；所述像素用于根据所述数据信号控制对应的液晶分子；
    所述第一像素单元中的多个桥接孔均包含在所述实际色阻开孔内；以及
    相邻两个桥接孔之间的间距小于该相邻两个桥接孔各自对应的常规间距之和。
  15. 如权利要求14所述的液晶显示面板，其中所述基板衬底上还形成有第二像素单元；
    所述第二像素单元，用于根据所述数据信号进行画面显示，所述第二像素单元与所述第一像素单元相邻，且具有至少一个所述桥接孔；
    所述第二像素单元中至少一个所述桥接孔包含在所述实际色阻开孔内；
    所述实际色阻开孔内属于不同像素单元，且相邻的两个桥接孔之间的间距小于该相邻两个桥接孔各自对应的常规间距之和。
  16. 如权利要求15所述的液晶显示面板，其中所述第二像素单元具有一个桥接孔，该桥接孔位于所述实际色阻开孔内，且与一属于第一像素单元的桥接孔相邻。
  17. 如权利要求14所述的液晶显示面板，其中所述相邻两个桥接孔各自对应的常规间距之和大于14um，所述相邻两个所述桥接孔之间的间距小于14um。
  18. 如权利要求17所述的液晶显示面板，其中所述相邻两个所述桥接孔之间的间距小于14um，且大于7um。
  19. 如权利要求14所述的液晶显示面板，其中所述薄膜晶体管包括：
    栅极；
    栅极绝缘层，设置在所述栅极上
    半导体层，设置在所述栅极绝缘层上，用于形成所述薄膜晶体管的沟道；
    源极和漏极，分别位于所述半导体层的两侧；以及
    所述色阻层设置所述漏极和所述栅极绝缘层上。
  20. 如权利要求14所述的液晶显示面板，其中所述第一像素单元包括第一桥接孔和第二桥接孔，所述第一桥接孔与所述第二桥接孔相邻；
    所述第一桥接孔与所述第二桥接孔之间的间距小于，所述第一桥接孔对应的常规间距和所述第二桥接孔对应的常规间距之和。
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