WO2017014254A1 - メモリセル、半導体集積回路装置、および半導体集積回路装置の製造方法 - Google Patents
メモリセル、半導体集積回路装置、および半導体集積回路装置の製造方法 Download PDFInfo
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- WO2017014254A1 WO2017014254A1 PCT/JP2016/071351 JP2016071351W WO2017014254A1 WO 2017014254 A1 WO2017014254 A1 WO 2017014254A1 JP 2016071351 W JP2016071351 W JP 2016071351W WO 2017014254 A1 WO2017014254 A1 WO 2017014254A1
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Definitions
- the present invention relates to a memory cell, a semiconductor integrated circuit device, and a method for manufacturing a semiconductor integrated circuit device.
- Patent Document 1 discloses a memory cell in which a memory gate structure is disposed between two select gate structures (see Patent Document 1 and FIG. 15).
- this memory cell comprises a drain region to which a bit line is connected and a source region to which a source line is connected, and a first select gate structure on a semiconductor substrate between the drain region and the source region, A memory gate structure and a second selection gate structure are arranged and formed in order.
- a charge storage layer is provided in the memory gate structure, and data is written by injecting charges into the charge storage layer, or charges in the charge storage layer are extracted. Data may be erased.
- the low voltage bit voltage from the bit line is reduced while the voltage is cut off by the second selection gate structure connected to the source line.
- the voltage is applied to the channel layer of the memory gate structure via the first select gate structure.
- a high memory gate voltage is applied to the memory gate electrode in the memory gate structure, and charges can be injected into the charge storage layer by a quantum tunnel effect caused by a voltage difference between the bit voltage and the memory gate voltage.
- a peripheral circuit of a MOS (Metal-Oxide-Semiconductor) transistor structure for driving such a memory cell when a logic gate electrode formed of polysilicon doped with impurities is applied, for example, a voltage is applied to the logic gate electrode. Is applied, a depletion layer is formed in the logic gate electrode. Therefore, in such a peripheral circuit, the parasitic capacitance for the depletion layer is connected in series with the gate capacitance. Therefore, even if a very thin gate insulating film is formed, only the depletion layer is effective. There is a problem that the gate insulating film thickness becomes thick. Therefore, in recent years, a peripheral circuit in which the logic gate electrode is formed of a metal material is used in order to prevent the formation of a depletion layer in the logic gate electrode.
- MOS Metal-Oxide-Semiconductor
- a memory cell using polysilicon for each electrode of the memory gate structure, the first selection gate structure, and the second selection gate structure is the same as a peripheral circuit having a metal logic gate electrode formed of a metal material.
- a manufacturing process for forming a memory cell is required separately from a manufacturing process for forming a peripheral circuit because members used for the memory cell and the peripheral circuit are different.
- the present invention has been made in consideration of the above points, and a memory cell, a semiconductor integrated circuit device, and a semiconductor integrated circuit that can be formed in a series of manufacturing steps for forming a metal logic gate electrode made of a metal material on a semiconductor substrate. It aims at proposing the manufacturing method of a circuit device.
- a memory cell of the present invention is a memory cell formed on the same semiconductor substrate as a peripheral circuit having a metal logic gate electrode containing a metal material, and is formed on the surface of the semiconductor substrate, and is a bit line.
- a drain region connected to each other, a source region formed on the surface of the semiconductor substrate and connected to a source line, and formed between the drain region and the source region, a lower memory gate insulating film, a charge storage layer, an upper memory
- a metal first selection gate electrode containing the metal material is formed via the selection gate insulating film, and the memory gate structure is formed.
- a first select gate structure adjacent to one side wall of the body via a side wall spacer, and a second select gate insulating film on the semiconductor substrate between the source region and the memory gate structure,
- a metal second select gate electrode including a metal material is formed, and the second select gate structure is provided adjacent to the other side wall of the memory gate structure via another side wall spacer.
- the one side wall spacer is formed along one side wall insulating film formed along one side wall of the memory gate structure, the side wall of the first select gate structure, and the first select gate.
- the first selection gate sidewall insulating film is formed integrally with the insulating film.
- the other side wall spacer is formed along the other side wall insulating film formed along the other side wall of the memory gate structure, along the side wall of the second selection gate structure, and the second selection gate.
- the second select gate sidewall insulating film is formed integrally with the insulating film.
- the first select gate sidewall insulating film and the second select gate sidewall insulating film are formed of an insulating material different from an insulating material of the sidewall insulating film, and the sidewall insulating film is formed of the first select gate sidewall insulating film.
- the insulating film has a relative dielectric constant smaller than that of the film and the second selection gate sidewall insulating film.
- one memory gate side wall insulating film formed along the side wall spacer and integrally formed with the upper memory gate insulating film is provided. Yes.
- another memory gate side wall insulating film formed along the side wall spacer and integrally formed with the upper memory gate insulating film is provided. Yes.
- the semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device in which memory cells to which bit lines and source lines are connected are arranged in a matrix, wherein the memory cells are the memory cells described above, and the memory A peripheral circuit region in which the peripheral circuit is provided is provided around the memory circuit region in which the cells are arranged.
- a memory cell is formed in which a memory gate structure is disposed between a first selection gate structure and a second selection gate structure.
- a method for manufacturing a semiconductor integrated circuit device comprising a memory circuit region and a peripheral circuit region in which a peripheral circuit having a logic gate structure is formed, wherein the lower memory gate layered on the semiconductor substrate of the memory circuit region After sequentially forming the insulating film and the charge storage layer, a layered first insulating film and a logic dummy electrode layer are sequentially stacked on the charge storage layer in the memory circuit region and on the semiconductor substrate in the peripheral circuit region.
- the logic dummy electrode layer in the memory circuit region, the first insulating film, and the electrode By patterning the storage layer and the lower memory gate insulating film, the patterned lower memory gate insulating film, the charge storage layer, the upper memory gate insulating film, and the dummy memory gate electrode are sequentially stacked.
- a layered memory dummy electrode layer is formed on the second insulating film, and the memory dummy in the peripheral circuit region is formed using a patterned resist.
- a second dummy electrode layer forming step of removing the electrode layer and the second insulating film in order to leave the second insulating film and the memory dummy electrode layer in the memory circuit region; and another patterned resist The dummy logic gate electrode and the first insulating film in the peripheral circuit region are patterned to form dummy logic in which dummy logic gate electrodes are sequentially stacked on the semiconductor substrate via the logic gate insulating film; By etching back the memory dummy electrode layer and the second insulating film in the memory circuit region while forming a gate structure, A sidewall-shaped dummy first selection gate electrode is formed along the sidewall spacer of one of the dummy memory gate structures, and the second insulating film is left below the dummy first selection gate electrode.
- the leading ends of the dummy memory gate electrode, the dummy first selection gate electrode, the dummy second selection gate electrode, and the dummy logic gate electrode are connected to the interlayer insulation.
- An electrode exposing step of exposing to the outside from the edge layer; and after removing the dummy memory gate electrode, the dummy first selection gate electrode, the dummy second selection gate electrode, and the dummy logic gate electrode, the dummy memory gate electrode A metal memory gate electrode containing a metal material, a metal first selection gate electrode, in an electrode formation space where the dummy first selection gate electrode, the dummy second selection gate electrode, and the dummy logic gate electrode were formed, And a metal gate electrode forming step of forming a metal second select gate electrode and a metal logic gate electrode.
- a memory cell in which a memory gate structure is disposed between the first selection gate structure and the second selection gate structure is formed.
- a method for manufacturing a semiconductor integrated circuit device comprising a memory circuit region and a peripheral circuit region in which a peripheral circuit having a logic gate structure is formed, wherein the patterned lower memory gate insulating film, charge storage layer, upper part
- a dummy memory gate structure in which a memory gate insulating film and a dummy memory gate electrode are sequentially stacked on a semiconductor substrate is provided in the memory circuit region, and then sidewalls are formed along opposing sidewalls of the dummy memory gate structure.
- a dummy first selection gate electrode is formed, and the dummy first selection gate electrode is formed.
- a first selection gate insulating film is formed by leaving the insulating film under the pole, and a sidewall-shaped dummy second selection gate electrode is formed along the other side wall spacer of the dummy memory gate structure.
- An electrode exposing step for exposing the dummy memory gate electrode, the dummy first selection gate electrode, the dummy second selection gate electrode, and the dummy After removing the logic gate electrode, the dummy memory gate electrode, the dummy first selection gate electrode, the dummy second selection gate electrode, and the electrode formation space in which the dummy logic gate electrode is formed include a metal material.
- a memory cell in which a memory gate structure is arranged between the first selection gate structure and the second selection gate structure is formed.
- a method for manufacturing a semiconductor integrated circuit device comprising a memory circuit region and a peripheral circuit region in which a peripheral circuit having a logic gate structure is formed, wherein the lower memory gate layered on the semiconductor substrate of the memory circuit region After forming an insulating film and a charge storage layer in order, a first dummy electrode layer for forming a layered logic dummy electrode layer on the charge storage layer in the memory circuit region and on the semiconductor substrate in the peripheral circuit region And forming the logic dummy electrode layer, the charge storage layer, and the lower memory gate in the memory circuit region using a patterned resist and a patterned resist.
- a dummy memory gate structure in which the patterned lower memory gate insulating film, the charge storage layer, and the dummy memory gate electrode are sequentially stacked is formed in the memory circuit region, and the resist
- the dummy logic gate electrode While forming the dummy logic gate electrode on the semiconductor substrate by patterning the dummy electrode layer for logic in the peripheral circuit region by utilizing the second dummy electrode layer forming step and another patterned resist, Etching back the memory dummy electrode layer in the memory circuit region to form a sidewall-shaped dummy first selection gate electrode along the sidewall insulating film of one of the dummy memory gate structures, and Forming a dummy second selection gate electrode in the form of a sidewall along the other sidewall insulating film of the dummy memory gate structure, and forming an interlayer insulating layer in the memory circuit region and the peripheral circuit region Thereafter, the interlayer insulating layer is processed, the dummy memory gate electrode, the dummy first selection gate An electrode exposing step of exposing each end of the electrode, the dummy second selection gate electrode, and the dummy logic gate electrode from the interlayer insulating layer, the dummy memory gate electrode, the dummy first selection gate electrode, and the dummy After
- a metal memory gate electrode containing a metal material, a metal first selection gate electrode, and a metal second selection are formed in an electrode formation space surrounded by the insulating film in each space
- a metal gate electrode forming step for forming a gate electrode and a metal logic gate electrode is
- a memory cell is formed in which a memory gate structure is disposed between a first selection gate structure and a second selection gate structure.
- a method for manufacturing a semiconductor integrated circuit device comprising a memory circuit region and a peripheral circuit region in which a peripheral circuit having a logic gate structure is formed, comprising a patterned lower memory gate insulating film, a charge storage layer, and Side walls forming a side wall insulating film along the opposing side walls of the dummy memory gate structure after a dummy memory gate structure in which dummy memory gate electrodes are sequentially stacked on the semiconductor substrate is provided in the memory circuit region.
- Insulating film forming step, and dummy electrode layer formation for forming a layered logic dummy electrode layer in the memory circuit region and the peripheral circuit region Then, using the patterned resist, the logic dummy electrode layer in the peripheral circuit region is patterned to form a dummy logic gate electrode on the semiconductor substrate, while the logic in the memory circuit region is formed.
- Etching back the dummy electrode layer for forming a sidewall-shaped dummy first selection gate electrode along the sidewall insulating film of one of the dummy memory gate structures, and the other of the dummy memory gate structures A dummy gate electrode forming step of forming a sidewall-shaped dummy second selection gate electrode along the side wall insulating film, and after forming an interlayer insulating layer in the memory circuit region and the peripheral circuit region, the interlayer insulating layer To process the dummy memory gate electrode, the dummy first selection gate electrode, and the dummy second selection.
- a metal memory gate electrode including a metal material, a metal first selection gate electrode, a metal second selection gate electrode, and a metal logic gate in an electrode formation space surrounded by the insulating film in each of the spaces And a metal gate electrode forming step for forming an electrode.
- the memory circuit region includes the lower memory gate insulating film, the charge storage layer, the upper memory gate insulating film, and the metal memory gate electrode in this order on the semiconductor substrate.
- the memory gate structure formed in a stacked manner, the metal first selection gate electrode formed on the semiconductor substrate via the first selection gate insulating film, and one side wall on one side of the memory gate structure
- the memory cell including the second selection gate structure adjacent to another side wall through the other side wall spacer is formed, and the peripheral circuit region includes the metal Logic gate electrode logic gate structure formed on said semiconductor substrate through said logic gate insulating film is formed.
- the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode are made of the same metal material as the metal logic gate electrode. Since it can be formed, it is possible to provide a memory cell that can be formed in a series of manufacturing steps in which a metal logic gate electrode made of a metal material is formed on a semiconductor substrate.
- FIG. 1 is a schematic diagram showing a cross-sectional configuration of a memory cell according to a first embodiment.
- 1 is a schematic diagram showing a cross-sectional configuration of a semiconductor integrated circuit device according to a first embodiment.
- 3A is a schematic diagram showing a manufacturing process (1) of the semiconductor integrated circuit device shown in FIG. 2, and
- FIG. 3B is a schematic diagram showing a manufacturing process (2) of the semiconductor integrated circuit device shown in FIG.
- FIG. 3C is a schematic view showing a manufacturing process (3) of the semiconductor integrated circuit device shown in FIG. 4A is a schematic diagram showing a manufacturing process (4) of the semiconductor integrated circuit device shown in FIG. 2, and
- FIG. 4B is a schematic diagram showing a manufacturing process (5) of the semiconductor integrated circuit device shown in FIG.
- FIG. 4C is a schematic view showing a manufacturing process (6) of the semiconductor integrated circuit device shown in FIG.
- FIG. 5A is a schematic diagram showing a manufacturing process (7) of the semiconductor integrated circuit device shown in FIG. 2
- FIG. 6B is a schematic diagram showing a manufacturing process (10) of the semiconductor integrated circuit device shown in FIG.
- FIG. 5 is a schematic diagram showing a cross-sectional configuration of a semiconductor integrated circuit device according to a second embodiment.
- 8A is a schematic diagram showing a manufacturing process (1) of the semiconductor integrated circuit device shown in FIG. 7, and FIG.
- FIG. 8B is a schematic diagram showing a manufacturing process (2) of the semiconductor integrated circuit device shown in FIG.
- FIG. 5 is a schematic diagram showing a cross-sectional configuration of a memory cell according to a third embodiment.
- FIG. 5 is a schematic diagram showing a cross-sectional configuration of a semiconductor integrated circuit device according to a third embodiment.
- 11A is a schematic diagram showing a manufacturing process (1) of the semiconductor integrated circuit device shown in FIG. 10
- FIG. 11B is a schematic diagram showing a manufacturing process (2) of the semiconductor integrated circuit device shown in FIG.
- FIG. 11C is a schematic view showing a manufacturing step (3) of the semiconductor integrated circuit device shown in FIG. 12A is a schematic diagram showing a manufacturing process (4) of the semiconductor integrated circuit device shown in FIG. 10, and FIG.
- FIG. 12B is a schematic diagram showing a manufacturing process (5) of the semiconductor integrated circuit device shown in FIG. 12C is a schematic view showing a manufacturing process (6) of the semiconductor integrated circuit device shown in FIG. 13A is a schematic diagram showing a manufacturing process (7) of the semiconductor integrated circuit device shown in FIG. 10, and FIG. 13B is a schematic diagram showing a manufacturing process (8) of the semiconductor integrated circuit device shown in FIG.
- FIG. 10 is a schematic diagram showing a cross-sectional configuration of a semiconductor integrated circuit device according to a fourth embodiment.
- 15A is a schematic diagram showing a manufacturing process (1) of the semiconductor integrated circuit device shown in FIG. 14, and FIG. 15B is a schematic diagram showing a manufacturing process (2) of the semiconductor integrated circuit device shown in FIG.
- First Embodiment> 1-1 Configuration of memory cell according to first embodiment 1-2.
- Data writing method 1-2-1 First writing method 1-2-2.
- Second writing method 1-3 Other operations 1-4.
- Configuration of Semiconductor Integrated Circuit Device According to First Embodiment 1-5 Manufacturing method of semiconductor integrated circuit device according to first embodiment 1-6. Action and effect ⁇ 2.
- Third Embodiment> 3-1 Configuration of Memory Cell According to Third Embodiment 3-2.
- the memory cell 1 includes, for example, a memory gate structure 2 that forms an N-type transistor structure on a semiconductor substrate W into which a P-type impurity is implanted, a first selection gate structure 3 that forms an N-type MOS transistor structure, and Similarly, a second select gate structure 4 that forms an N-type MOS transistor structure is formed.
- a drain region 6a at one end of the first selection gate structure 3 and a source region 6b at one end of the second selection gate structure 4 are formed with a predetermined distance therebetween, A bit line BL is connected to the drain region 6a, and a source line SL is connected to the source region 6b.
- a low concentration drain region is formed in the drain region 6a on the surface of the semiconductor substrate W, and a sidewall 17a formed along the side wall of the first selection gate structure 3 is formed on the low concentration drain region. Can be placed. Further, on the surface of the semiconductor substrate W, a low concentration source region is also formed in the source region 6b, and a sidewall 17b formed along the side wall of the second selection gate structure 4 is formed on the low concentration source region. Can be arranged.
- a silicide layer SC is formed on each surface of the drain region 6a and the source region 6b.
- the sidewalls 17a and 17b are formed of, for example, SiN or the like, and the metal memory gate electrode MG of the memory gate structure 2 or the first one is formed by a planarization process such as CMP (Chemical Mechanical Polishing) performed in the manufacturing process.
- CMP Chemical Mechanical Polishing
- the tips are flattened together with the tips of the metal first select gate electrode DG of the select gate structure 3 and the metal second select gate electrode SG of the second select gate structure 4.
- the low concentration drain region in the drain region 6a and the low concentration source region in the source region 6b are selected to have an impurity concentration exceeding 1.0E19 / cm 3
- the semiconductor substrate W immediately below the side wall spacers 8a and 8b, which will be described later, has the same surface region as the surface region where the channel layer is formed immediately below the memory gate structure 2 (for example, the region from the surface to 50 [nm])
- the concentration is selected to be 1.0E19 / cm 3 or less, preferably 3.0E18 / cm 3 or less.
- the memory gate structure 2 includes a lower memory gate insulating film 10 made of an insulating material such as SiO 2 on the semiconductor substrate W between the low concentration drain region of the drain region 6a and the low concentration source region of the source region 6b. And has a charge storage layer EC made of, for example, silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), alumina (Al 2 O 3 ), hafnia (HfO 2), etc.
- Metal is placed on the storage layer EC via an upper memory gate insulating film 11 made of an insulating material different from the lower memory gate insulating film 10 (for example, high-k such as hafnium oxide (HfO2) or hafnium nitride silicate (HfSiON)). It has a memory gate electrode MG.
- the memory gate structure 2 has a configuration in which the charge storage layer EC is insulated from the semiconductor substrate W and the metal memory gate electrode MG by the lower memory gate insulating film 10 and the upper memory gate insulating film 11.
- the metal memory gate electrode MG is formed of a metal material for N-type MOS such as aluminum (AL), titanium aluminum (TiAL), tantalum carbide (TaC), silicon tantalum nitride (TaSiN), and the like.
- the tip is flattened by a flattening process such as CMP performed in the manufacturing process to form a flat tip surface 2a.
- a memory gate line MGL is connected to the metal memory gate electrode MG, and a predetermined voltage can be applied from the memory gate line MGL.
- a side wall spacer 8a made of an insulating material is formed along one side wall of the memory gate structure 2, and the first selection gate structure 3 is adjacent to the memory gate structure 2 via the side wall spacer 8a.
- the sidewall spacer 8a formed between the memory gate structure 2 and the first selection gate structure 3 is formed with a predetermined film thickness, and the memory gate structure 2, the first selection gate structure 3, Can be insulated.
- the side wall spacer 8a is formed along the side wall of the memory gate structure 2 and is made of an insulating material such as SiO 2 and between the side wall insulating film 13a and the first selection gate structure 3.
- a first selection gate sidewall insulating film 16a made of an insulating material (for example, High-k) formed in a different process from the sidewall insulating film 13a.
- the side wall when a predetermined voltage is applied to the metal memory gate electrode MG and the metal first selection gate electrode DG when the space between the memory gate structure 2 and the first selection gate structure 3 exceeds 40 [nm], there is a possibility that a breakdown voltage failure may occur in the spacer 8a, and the metal memory gate electrode MG and the metal first selection gate electrode DG.
- the resistance in the semiconductor substrate W for example, a region (surface region) from the surface to 50 [nm]
- a read current is generated between the memory gate structure 2 and the first selection gate structure 3 during data reading. It becomes difficult to occur.
- the side wall spacer 8a between the memory gate structure 2 and the first selection gate structure 3 is selected to have a width of 5 [nm] or more and 40 [nm] or less.
- the sidewall insulating film 13a is desirably formed of an insulating material having a relative dielectric constant smaller than that of the first select gate sidewall insulating film 16a. In this case, the capacity between the first selection gate structure 3 and the memory gate structure 2 is reduced, and the access speed can be increased.
- the first select gate structure 3 is integrally formed with the lower end side wall of the wall-shaped first select gate side wall insulating film 16a on the semiconductor substrate W between the side wall spacer 8a and the drain region 6a, and the first select gate side wall insulation.
- the first select gate insulating film 15a is formed of the same insulating material (for example, High-k) as the film 16a. In this case, the thickness of the first selection gate insulating film 15a is 9 [nm] or less, preferably 3 [nm] or less, and the metal first selection gate electrode DG is formed on the first selection gate insulating film 15a. Has been.
- the metal first selection gate electrode DG is the same metal material for N-type MOS as the metal memory gate electrode MG (for example, aluminum (AL), titanium aluminum (TiAL), tantalum carbide (TaC), silicon tantalum nitride (TaSiN) Etc.), and the tip is flattened by a flattening process such as CMP performed in the manufacturing process to form the tip flat surface 3a.
- a first selection gate line DGL is connected to the metal first selection gate electrode DG, and a predetermined voltage can be applied from the first selection gate line DGL.
- sidewall spacers 8b made of an insulating material are also formed on the other sidewalls of the memory gate structure 2, and the second selection gate structures 4 are adjacent to each other through the sidewall spacers 8b.
- the side wall spacer 8b formed between the memory gate structure 2 and the second selection gate structure 4 is also formed to have the same film thickness as the one side wall spacer 8a.
- the gate structure 4 can be insulated.
- the side wall spacer 8b is formed along the side wall of the memory gate structure 2 and is made of an insulating material such as SiO 2 and between the side wall insulating film 13b and the second selection gate structure 4.
- the side wall spacer 8b may have a breakdown voltage failure, and the metal memory gate electrode MG and the metal second selection gate The resistance on the semiconductor substrate W increases between the electrodes SG, and a read current hardly occurs between the memory gate structure 2 and the second select gate structure 4 at the time of data reading.
- the sidewall spacer 8b between the memory gate structure 2 and the second selection gate structure 4 is also selected to have a width of 5 [nm] or more and 40 [nm] or less.
- the sidewall insulating film 13b is preferably formed of an insulating material having a relative dielectric constant smaller than that of the second select gate sidewall insulating film 16b. In this case, the capacity between the second selection gate structure 4 and the memory gate structure 2 is reduced, and the access speed can be increased.
- the second select gate structure 4 is integrally formed with the lower end side wall of the wall-shaped second select gate side wall insulating film 16b on the semiconductor substrate W between the side wall spacer 8b and the source region 6b, and the second select gate side wall insulation.
- the second selection gate insulating film 15b is formed of the same insulating material (for example, High-k) as the film 16b. In this case, the thickness of the second selection gate insulating film 15b is 9 [nm] or less, preferably 3 [nm] or less, and the metal second selection gate electrode SG is formed on the second selection gate insulating film 15b. Has been.
- the metal second select gate electrode SG is the same metal material for N-type MOS as the metal memory gate electrode MG (for example, aluminum (AL), titanium aluminum (TiAL), tantalum carbide (TaC), silicon tantalum nitride (TaSiN) Etc.), and the tip is flattened by the flattening process such as CMP performed in the manufacturing process to form the tip flat surface 4a. Further, the second selection gate line SGL is connected to the metal second selection gate electrode SG, and a predetermined voltage can be applied from the second selection gate line SGL.
- AL aluminum
- TiAL titanium aluminum
- TaC tantalum carbide
- TaSiN silicon tantalum nitride
- the tip flat surface 3a of the metal first select gate electrode DG, the tip flat surface 4a of the metal second select gate electrode SG, the tip flat surface 2a of the metal memory gate electrode MG, and a sidewall spacer are all aligned at the same height, and the projecting region is not formed, so that the size can be reduced.
- the memory cell 1 since the memory cell 1 includes the metal memory gate electrode MG, the metal first selection gate electrode DG, and the metal second selection gate electrode SG using a metal material, the metal logic of the peripheral circuit When forming a gate electrode (not shown) on the same semiconductor substrate W, the metal material forming the metal logic gate electrode is diverted to the metal memory gate electrode MG, the metal first selection gate electrode DG, and the metal.
- the second select gate electrode SG can also be formed.
- the metal memory gate electrode MG, the metal first selection gate electrode DG, and the metal second selection gate electrode SG are formed of a predetermined metal material, the metal memory gate electrode MG Further, it is possible to prevent the depletion layer from being formed in the metal first selection gate electrode DG and the metal second selection gate electrode SG.
- the semiconductor cell W facing the metal memory gate electrode MG The carrier is excluded from the region where the carrier forming the channel layer exists (hereinafter referred to as the channel layer forming carrier region) (this operation is hereinafter referred to as carrier exclusion operation), and then the data write operation is executed.
- the data writing operation is performed by either of the first writing method and (ii) the second writing method of performing the data writing operation without performing the carrier exclusion operation.
- the first select gate structure 3 when performing the carrier removal operation, is connected to, for example, the metal from the first select gate line DGL.
- a first selection gate voltage of 1.5 [V] can be applied to one selection gate electrode DG, and a bit voltage of 0 [V] can be applied from the bit line BL to the drain region 6a.
- the first selection gate structure 3 becomes conductive on the surface of the semiconductor substrate W facing the metal first selection gate electrode DG, and faces the drain region 6a to which the bit line BL is connected and the memory gate structure 2.
- the channel layer forming carrier region of the semiconductor substrate W can be electrically connected.
- a second selection gate voltage of 1.5 [V] is applied to the second selection gate structure 4 from the second selection gate line SGL to the metal second selection gate electrode SG, and the source A source voltage of 0 [V] can be applied from the line SL to the source region 6b.
- the second select gate structure 4 becomes conductive on the surface of the semiconductor substrate W facing the metal second select gate electrode SG, and faces the source region 6b to which the source line SL is connected, and the memory gate structure 2.
- the channel layer forming carrier region of the semiconductor substrate W can be electrically connected.
- a carrier exclusion voltage of ⁇ 2 [V] can be applied to the electrode MG.
- the carrier exclusion voltage applied to the metal memory gate electrode MG is defined based on the threshold voltage (Vth) at which the channel layer is formed in the semiconductor substrate W facing the memory gate structure 2.
- the carrier exclusion voltage is a voltage value outside the range of the threshold voltage (Vth) that is displaced between the data writing state and the data erasing state, and is applied to the metal memory gate electrode MG. In this case, the voltage value is selected so that the channel layer is not formed.
- the memory cell 1 carriers (in this case, electrons) induced in the channel layer forming carrier region by the carrier exclusion voltage applied to the metal memory gate electrode MG are drained from the channel layer forming carrier region.
- the carrier is guided to the region 6a and / or the source region 6b so that carriers can be expelled from the channel layer forming carrier region.
- the channel layer is not formed on the semiconductor substrate W immediately below the memory gate structure 2, and the minority carriers can be depleted.
- the carrier exclusion voltage lower (shallow) than the lower (shallow) threshold voltage when electrons are not stored in the charge storage layer EC (or holes are stored) is metal. Even if the memory cell 1 is in a depleted state by being applied to the memory gate electrode MG, carriers induced in the channel layer forming carrier region of the semiconductor substrate W immediately below the memory gate structure 2 are transferred to the channel layer. Excluding from the formed carrier region, a minority carrier may be depleted without forming the channel layer.
- a charge storage gate voltage of 12 [V] can be applied from the memory gate line MGL to the metal memory gate electrode MG of the memory gate structure 2.
- a gate off voltage of 0 [V] is applied to the second selection gate structure 4 from the second selection gate line SGL to the metal second selection gate electrode SG, and 0 [V] from the source line SL to the source region 6b.
- the source-off voltage is applied to the source region 6b to which the source line SL is connected and the channel layer forming carrier region of the memory gate structure 2 is disconnected, and the memory gate structure is disconnected from the source line SL. Application of voltage to the two channel layer forming carrier regions can be prevented.
- a first selection gate voltage of 1.5 [V] is applied from the first selection gate line DGL to the metal first selection gate electrode DG, and 0 to the drain region 6a from the bit line BL.
- the drain region 6a to which the charge storage bit voltage of [V] is applied and the bit line BL is connected and the channel layer forming carrier region of the memory gate structure 2 can be electrically connected.
- the same substrate voltage of 0 [V] as the charge storage bit voltage can be applied to the semiconductor substrate W.
- carriers are induced in the channel layer forming carrier region by electrically connecting the channel layer forming carrier region of the semiconductor substrate W to the drain region 6a, and 0 [V] which is the same as the charge storage bit voltage Can be formed on the surface of the semiconductor substrate W by carriers.
- a large voltage difference (12 [V]) of 12 [V] is generated between the metal memory gate electrode MG and the channel layer, and a charge is generated in the charge storage layer EC due to a quantum tunnel effect generated thereby. Can be injected and data can be written.
- a high voltage charge storage gate voltage is applied to the metal memory gate electrode MG, if the charge is not injected into the charge storage layer EC of the memory cell 1, a high voltage charge storage gate is used as in the prior art. There is no need to apply a high bit voltage to the bit line BL according to the voltage, and the channel region forming carrier region of the semiconductor substrate W immediately below the bit line BL and the memory gate structure 2 by the first selection gate structure 3 And the second selection gate structure 4 simply cuts off the electrical connection between the source line SL and the channel layer forming carrier region immediately below the memory gate structure 2. Charge injection into the charge storage layer EC of the memory gate structure 2 can be prevented.
- a first selection gate voltage of 1.5 [V] is applied from the first selection gate line DGL to the metal first selection gate electrode DG, and the drain region 6a is transmitted from the bit line BL.
- An off-voltage of 1.5 [V] can be applied.
- the first select gate structure 3 is turned off (off state), and the drain region 6a to which the bit line BL is connected and the channel layer forming carrier region of the semiconductor substrate W immediately below the memory gate structure 2 The electrical connection can be cut off.
- a gate-off voltage of 0 [V] is applied from the second selection gate line SGL to the metal second selection gate electrode SG, and the source line SL to the source region 6b.
- a source off voltage of 0 [V] can be applied.
- the second selection gate structure 4 is turned off (off state), and the source region 6b to which the source line SL is connected and the channel layer forming carrier region of the semiconductor substrate W immediately below the memory gate structure 2 The electrical connection can be cut off.
- a substrate voltage of 0 [V] which is the same as the charge storage bit voltage, is applied to the semiconductor substrate W.
- the voltage drops in the three layers of the upper memory gate insulating film 11, the charge storage layer EC, and the lower memory gate insulating film 10, and the metal memory gate electrode MG and the semiconductor substrate A voltage difference is generated on the W surface, and the voltage value decreases in a depletion layer formed from the surface of the semiconductor substrate W to a predetermined depth, so that a substrate voltage of 0 [V] can be finally obtained.
- the metal memory gate electrode MG and the surface of the semiconductor substrate W are about 3.5 [V] (for example, the flat band voltage Vfb is 0 [V], the memory gate voltage Vg is 12 [V], the acceptor concentration Na of the semiconductor substrate W is 2.0E17 [cm ⁇ 3 ], and the upper memory gate insulating film 11 Of the charge storage layer EC is 12 [nm] and the thickness of the lower memory gate insulating film is 2 [nm]), the metal memory gate electrode MG and the surface of the semiconductor substrate W A large voltage difference necessary for the occurrence of the quantum tunnel effect does not occur between them, and charge injection into the charge storage layer EC can be prevented.
- the impurity diffusion region having a high impurity concentration is not formed in the region of the semiconductor substrate W between the memory gate structure 2 and the first selection gate structure 3
- a depletion layer can be reliably formed in the semiconductor substrate W between the memory gate structure 2 and the first selection gate structure 3, and the depletion layer causes the potential on the surface of the semiconductor substrate W immediately below the memory gate structure 2 to be the first selection. Reaching the gate insulating film 15a can be prevented, and the dielectric breakdown of the first selection gate insulating film 15a due to the potential of the surface of the semiconductor substrate W can be prevented.
- the memory gate structure A depletion layer can be reliably formed in the semiconductor substrate W between the body 2 and the second selection gate structure 4, and the depletion layer causes the potential of the surface of the semiconductor substrate W immediately below the memory gate structure 2 to be the second selection gate insulating film. Reaching to 15b can be prevented, and the dielectric breakdown of the second select gate insulating film 15b due to the potential of the surface of the semiconductor substrate W can be prevented.
- the electrical connection between the channel layer forming carrier region and the source region 6b is interrupted by the second selection gate structure 4, and the carriers in the channel layer forming carrier region are drained. Transmitting to the region 6a, or blocking the electrical connection between the channel layer forming carrier region and the drain region 6a by the first selection gate structure 3, and transmitting carriers in the channel layer forming carrier region to the source region 6b By doing so, carriers may be excluded from the channel layer forming carrier region.
- (1-2-2) Second Write Method when data is written to the memory cell 1, the above-mentioned “(1-2-1) First write” is performed except that the carrier exclusion operation is not performed. Since it is the same as the “method”, its description is omitted.
- a high voltage charge storage gate voltage is applied to the metal memory gate electrode MG, if no charge is injected into the charge storage layer EC of the memory cell 1, the memory gate line MGL is transferred to the metal memory gate electrode MG. Since the charge storage gate voltage of 12 [V] is applied, the charge storage gate voltage is transmitted to the semiconductor substrate W, and a channel layer can be formed along the surface of the semiconductor substrate W facing the metal memory gate electrode MG. .
- a gate off voltage of 0 [V] is applied from the second selection gate line SGL to the metal second selection gate electrode SG, and the source region 6b is supplied from the source line SL.
- a source-off voltage of 0 [V] may be applied to the gate.
- the second select gate structure 4 becomes non-conductive at the semiconductor substrate W facing the metal second select gate electrode SG, and the source region 6b to which the source line SL is connected and the channel of the memory gate structure 2
- the electrical connection with the layer can be interrupted.
- the first selection gate structure 3 of the memory cell 1 has, for example, a first selection gate voltage of 1.5 [V] from the first selection gate line DGL to the metal first selection gate electrode DG.
- the off voltage of 1.5 [V] can be applied from the bit line BL to the drain region 6a.
- the first select gate structure 3 is configured such that the semiconductor substrate W facing the metal first select gate electrode DG is in a non-conductive state, the drain region 6a to which the bit line BL is connected, and the memory gate structure 2
- the electrical connection with the channel layer can be interrupted.
- the metal memory gate electrode formed on the surface of the semiconductor substrate W by MG is in a state where the electrical connection with the drain region 6a and the source region 6b is cut off, and a depletion layer can be formed around the channel layer.
- a capacitance obtained by a three-layer configuration of the upper memory gate insulating film 11, the charge storage layer EC, and the lower memory gate insulating film 10, and a channel layer formed in the semiconductor substrate W
- the capacity of the depletion layer surrounding the depletion layer (depletion layer capacity) can be regarded as a configuration in which the gate insulating film capacity and the depletion layer capacity are connected in series.
- the gate insulating film capacity is three times the depletion layer capacity. Assuming that it is a capacitance, the channel potential of the channel layer is 9 [V].
- the channel potential of the channel layer surrounded by the depletion layer in the semiconductor substrate W is 9 [V Therefore, the voltage difference between the metal memory gate electrode MG and the channel layer is reduced to 3 [V], and as a result, it is possible to prevent charge injection into the charge storage layer EC without generating a quantum tunnel effect. .
- the channel potential at the time when the operation is started may change depending on the charge accumulation state in the memory cell 1. Therefore, before the data write operation, the potential of the bit line BL or the source line SL is set to, for example, 0 [V], the metal first selection gate electrode DG or the metal second selection gate electrode SG is set to, for example, 1.5 [V], and the metal More preferably, the memory gate electrode MG is set to 1.5 [V], for example, and an operation of aligning the channel potential of the memory cell 1 with the potential of the bit line BL or the source line SL is added. In this case, after the channel potentials are made uniform, the metal first selection gate electrode DG or the metal second selection gate electrode SG is returned to the gate-off voltage of 0 [V] and then the write operation is started.
- the bit line BL connected to the memory cell 1 to be read is precharged to 1.5 [V], for example, and the source line SL is set to 0 [V].
- the potential of the bit line BL that changes depending on whether or not current flows through the memory cell 1 it can be determined whether or not charge is stored in the charge storage layer EC.
- the data is not detected on the semiconductor substrate W immediately below the memory gate structure 2.
- the conductive state is established, and the electrical connection between the drain region 6a and the source region 6b can be cut off. Thereby, in the memory cell 1 from which data is read, the read voltage of 1.5 [V] on the bit line BL connected to the drain region 6a adjacent to the first select gate structure 3 can be maintained as it is.
- the semiconductor substrate W immediately below the memory gate structure 2 is in a conductive state.
- the drain region 6a and the source region 6b are electrically connected.
- the 0 [V] source line SL and the 1.5 [V] bit line BL are electrically connected via the memory cell 1.
- the read voltage of the bit line BL is applied to the source line SL of 0 [V], so that the read voltage of 1.5 [V] applied to the bit line BL is increased. descend.
- a memory gate voltage of ⁇ 12 [V] is applied from the memory gate line MGL to the metal memory gate electrode MG.
- Data in the charge storage layer EC is extracted toward the semiconductor substrate W of [V], and data can be erased.
- FIG. 2 is a schematic diagram showing a cross-sectional configuration of the semiconductor integrated circuit device 20 in a region where, for example, one memory cell 1 and two peripheral circuits L1 and L2 are provided.
- the semiconductor integrated circuit device 20 includes a memory circuit region ER1 in which the memory cell 1 is provided, and a peripheral circuit region ER3 in which the peripheral circuits L1 and L2 are provided.
- the memory circuit region ER1 and the peripheral circuit The region ER3 is separated by the boundary region ER2.
- the peripheral circuit region ER3 for example, an NMOS peripheral circuit region ER4 in which a peripheral circuit L1 having an N-type MOS transistor structure is formed, and a PMOS peripheral circuit region ER5 in which a peripheral circuit L2 having a P-type MOS transistor structure is formed.
- the element isolation layer IL2 is formed on the surface of the semiconductor substrate W between the NMOS peripheral circuit region ER4 and the PMOS peripheral circuit region ER5.
- one impurity diffusion region is in contact with the element isolation layer IL2 between the NMOS peripheral circuit region ER4 and the PMOS peripheral circuit region ER5 on the surface of the semiconductor substrate W of the NMOS peripheral circuit region ER4 provided in the peripheral circuit region ER3.
- 23a is formed, and another impurity diffusion region 23b is formed in contact with the element isolation layer IL1 in the boundary region ER2.
- N-type impurities are added to the impurity diffusion regions 23a and 23b that are formed apart from the surface of the semiconductor substrate W, and the semiconductor between the impurity diffusion regions 23a and 23b.
- a logic gate structure 21a is formed on the surface of the substrate W.
- a metal logic gate electrode LG1 is formed on a semiconductor substrate W via a logic gate insulating film 25a.
- the logic gate insulating film 25a is made of, for example, the same insulating material (in this case, High-k) as the upper memory gate insulating film 11 of the memory cell 1, and has a thickness of 9 [nm. ], Preferably 3 [nm] or less.
- the metal logic gate electrode LG1 is formed of the same metal material as the metal memory gate electrode MG, the metal first selection gate electrode DG, and the metal second selection gate electrode SG, for example, CMP performed in the manufacturing process, etc.
- the tip is flattened by this flattening process, and the tip flat surface L1a is formed at the same height as the tip flat surfaces 2a, 3a, 4a of the memory cell 1.
- the metal memory gate electrode MG, the metal first selection gate electrode DG, and the metal second selection gate electrode SG provided in the memory circuit region ER1 are N-type MOS.
- Metal logic for example, aluminum (AL), titanium aluminum (TiAL), tantalum carbide (TaC), silicon tantalum nitride (TaSiN)), and metal logic provided in the NMOS peripheral circuit region ER4
- the gate electrode LG1 is also formed of a metal material for N-type MOS.
- peripheral circuit L1 sidewalls 26 made of, for example, SiN are formed on the opposing sidewalls of the logic gate structure 21a, respectively, and the impurity diffusion regions 23a and 23b have a low concentration immediately below the sidewalls 26. Each region is formed.
- silicide layers SC are formed on the surfaces of the impurity diffusion regions 23a and 23b, respectively. Note that the tip of the side wall 26 is also flattened by a flattening process such as CMP performed in the manufacturing process, similarly to the metal logic gate electrode LG1.
- one impurity diffusion region 23c is formed so as to be in contact with the predetermined element isolation layer IL3, and the NMOS peripheral circuit region ER4 and Another impurity diffusion region 23d is formed in contact with the element isolation layer IL2 between the PMOS peripheral circuit regions ER5.
- P-type impurities are added to the impurity diffusion regions 23c and 23d formed on the surface of the semiconductor substrate W so as to be separated from each other, and between the impurity diffusion regions 23c and 23d.
- a logic gate structure 21b is formed on the surface of the semiconductor substrate W.
- a metal logic gate electrode LG2 is formed on the semiconductor substrate W via a logic gate insulating film 25b.
- the logic gate insulating film 25b is formed of, for example, the same insulating material (in this case, High-k) as the upper memory gate insulating film 11, and the film thickness is 9 [nm] or less, preferably It is formed below 3 [nm].
- the metal logic gate electrode LG2 is formed of a metal material having a work function different from that of the metal memory gate electrode MG, the metal first selection gate electrode DG, and the metal second selection gate electrode SG, for example.
- the tip is flattened by a flattening process such as CMP, and a flat tip surface L2a is formed.
- the metal logic gate electrode LG2 provided in the PMOS peripheral circuit region ER5 is a metal memory gate electrode MG or a metal first selection gate electrode DG formed of a metal material for N-type MOS.
- the metal selection gate electrode SG2 is formed of a metal material for P-type MOS (for example, aluminum (AL), titanium nitride (TiN), etc.).
- side walls 27 made of, for example, SiN are formed on the opposing side walls of the logic gate structure 21b, respectively.
- low-concentration regions of impurity diffusion regions 23c and 23d are formed, respectively.
- Silicide layers SC are also formed on the surfaces of the impurity diffusion regions 23c and 23d. Note that the tip of the side wall 27 is flattened by a flattening process such as CMP performed in the manufacturing process, similarly to the metal logic gate electrode LG2.
- the boundary region ER2 there are remaining portions 29 remaining in the manufacturing process of manufacturing the memory gate structure 2, the first selection gate structure 3, the second selection gate structure 4, and the logic gate structures 21a and 21b. It is formed on the element isolation layer IL1.
- the remaining portion 29 remains when the first selection gate insulating film 15a and the second selection gate insulating film 15b are formed, and the same insulation as the first selection gate insulating film 15a and the second selection gate insulating film 15b.
- a residual insulating film 31 having an L-shaped cross section made of a material (in this case, High-k) is provided.
- the remaining insulating layer 31 is provided with a bottom 31a formed on the element isolation layer IL1, and a wall 31b standing on the element isolation layer IL1 from a terminal side surface of the bottom 31a.
- One remaining metal layer MS2 is formed on the bottom 31a along one surface.
- a sidewall 34a made of, for example, SiN is formed along the side wall of the bottom portion 31a of the remaining insulating film 31 and the remaining metal layer MS2 on the bottom portion 31a.
- the remaining portion 29 is provided with a wall-shaped remaining sidewall insulating film 30 along the other surface of the wall portion 31b of the remaining insulating film 31.
- the remaining sidewall insulating film 30 is left when the sidewall insulating films 13a and 13b of the memory cell 1 are formed, and is formed of the same insulating material (for example, SiO 2 or the like) as the sidewall insulating films 13a and 13b. Yes.
- a remaining insulating film 33 is formed on the element isolation layer IL1 so as to be adjacent to the remaining sidewall insulating film 30.
- This remaining insulating film 33 remains when the upper memory gate insulating film 11 and the logic gate insulating films 25a and 25b are formed, and is the same insulating material as the upper memory gate insulating film 11 and the logic gate insulating films 25a and 25b. (In this case, high-k).
- the remaining portion 29 is flattened by CMP or the like performed at the front ends of the sidewalls 34a and 34b, the remaining metal layers MS1 and MS2, the remaining insulating film 31, and the remaining sidewall insulating film 30 in the manufacturing process. Each tip is flattened by processing.
- the semiconductor integrated circuit device 20 is an interlayer in which the periphery of the memory cell 1 in the memory circuit region ER1, the remaining portion 29 in the boundary region ER2, and the peripheral circuits L1 and L2 in the peripheral circuit region ER3 are made of an insulating material such as SiO 2 The structure is covered with an insulating layer ILD and insulated from each other.
- the semiconductor integrated circuit device 20 having the configuration as described above is manufactured in the peripheral circuit region ER3 in the N-type by manufacturing according to the following manufacturing process.
- the memory cell 1 can be formed in the memory circuit region ER1.
- a plurality of element isolation layers IL1 made of an insulating material such as SiO 2 are formed at a predetermined position on the surface of the semiconductor substrate W made of Si by an STI (Shallow Trench Isolation) method or the like.
- IL2 and IL3 are formed at predetermined intervals.
- a P-type impurity is added to the semiconductor substrate W in the NMOS peripheral circuit region ER4 between the element isolation layer layers IL1 and IL2.
- an N-type impurity can be implanted into the semiconductor substrate W in the PMOS peripheral circuit region ER5 between the element isolation layer layers IL2 and IL3.
- a resist is patterned using photolithography technology, and from a partial region of the element isolation layer IL1 formed in the boundary region ER2 between the memory circuit region ER1 and the peripheral circuit region ER3 to the semiconductor substrate W in the peripheral circuit region ER3
- a formation planned region hereinafter also referred to as a memory gate electrode formation planned region
- Impurities such as B (boron), P (phosphorus), and As (arsenic) are implanted into the semiconductor substrate W in the memory circuit region ER1.
- a lower memory gate insulating film made of layered SiO 2 or the like and a charge storage layer made of SiN or the like are sequentially stacked over the memory circuit region ER1, the boundary region ER2, and the peripheral circuit region ER3.
- the resist is patterned by using the photolithography technique, and the part from the memory circuit region ER1 to a partial region of the boundary region ER2 as shown in FIG. Covering with the resist M2, the lower memory gate insulating film and the charge storage layer in the boundary region ER2 and the peripheral circuit region ER3 exposed from the resist M2 are removed.
- the layered lower memory gate insulating film 10a and the charge storage layer ECa are formed only in a part of the boundary region ER2 from the memory circuit region ER1.
- the charge accumulation layer ECa in the memory circuit region ER1 passes through the element isolation layer IL1 in the boundary region ER2.
- a layered first insulating film 11a made of an insulating material (for example, High-k) different from the lower memory gate insulating film 10a is formed over the semiconductor substrate W in the peripheral circuit region ER3, and then a layered type made of polysilicon or the like is formed.
- a logic dummy electrode layer 37 is stacked on the first insulating film 11a (first dummy electrode layer forming step).
- the hard mask layer is patterned with resists M3a and M3b patterned using a photolithography technique.
- the resist M3a can be formed in the memory gate electrode formation scheduled region of the memory circuit region ER1
- the other resist M3b can be formed so as to cover the entire surface of the peripheral circuit region ER3.
- the hard mask layer HM1a is left in the memory gate electrode formation scheduled region in the memory circuit region ER1, and the hard mask layer is also formed on the entire peripheral circuit region ER3.
- Layer HM1b is left.
- the logic dummy electrode layer 37 in the memory circuit region ER1 and the boundary region ER2 the first insulating film 11a, the charge storage layer ECa, and the lower part
- the memory gate insulating film 10a is removed in order, and a lower memory gate insulating film is formed in the memory gate electrode formation planned area of the memory circuit area ER1 as shown in FIG. 10.
- a dummy memory gate structure D2 is formed in which the charge storage layer EC, the upper memory gate insulating film 11, and the dummy memory gate electrode DMG are sequentially stacked.
- the upper memory gate insulating film 11 can be formed by processing the first insulating film 11a in the memory circuit region ER1.
- the first insulating film 11a and the logic dummy electrode layer 37 are left as they are in the peripheral circuit region ER3 by the hard mask layer HM1b (dummy memory gate structure forming step).
- the logic dummy electrode layer 37 provided for forming dummy logic gate electrodes DLG1 and DLG2 (FIG. 5B), which will be described later, is diverted in the memory circuit region.
- a dummy memory gate electrode DMG can also be formed on ER1.
- a layered insulating film made of SiO 2 or the like is formed over the memory circuit region ER1, the boundary region ER2, and the peripheral circuit region ER3, and then etched back, thereby forming the memory circuit region ER1 as shown in FIG. 4A.
- Side wall insulating films 13a, 13b are formed along the opposing side walls of the dummy memory gate structure D2 (side wall insulating film forming step). At this time, the insulating film also remains on the side walls of the logic dummy electrode layer 37 and the first insulating film 11a disposed in the boundary region ER2, and the side wall-like remaining side wall insulating film 30 can be formed.
- a semiconductor substrate W in a region where a metal first selection gate electrode DG and a metal second selection gate electrode SG (FIG. 2) to be formed in a later manufacturing process are formed (hereinafter also referred to as a selection gate electrode formation scheduled region)
- B (boron) or P (P) is applied to the semiconductor substrate W in the memory circuit region ER1 not covered with the hard mask layers HM1a, HM1b and the sidewall insulating films 13a, 13b, 30 by ion implantation or the like. Impurities such as phosphorus) and As (arsenic) are implanted.
- the same insulating material as that of the upper memory gate insulating film 11 is formed over the memory circuit region ER1, the boundary region ER2, and the peripheral circuit region ER3 as shown in FIG.
- a layered memory dummy electrode layer 38 made of, eg, polysilicon is formed on the second insulating film 15.
- the second insulating film 15 is provided in a wall shape along the side wall insulating film 13a on one side wall to form the first selection gate side wall insulating film 16a,
- the second insulating film 15 is also provided in a wall shape on the side wall insulating film 13b on the other side wall to form the second select gate side wall insulating film 16b.
- one sidewall spacer 8a composed of the sidewall insulating film 13a and the first select gate sidewall insulating film 16a is formed on one sidewall, and the sidewall insulating film 13b and the second select gate sidewall are formed.
- Another sidewall spacer 8b made of the insulating film 16b can be formed on the other sidewall.
- FIG. 4C in which the same reference numerals are given to the corresponding parts to FIG. 4B, from the memory circuit region ER1 to a partial region of the boundary region ER2 by the resist M4 patterned using photolithography technology.
- the memory dummy electrode layer 38 and the second insulating film 15 formed in the peripheral circuit region ER3 and the other partial region ER2 that are not covered with the resist M4 are removed. Thereby, the layered memory dummy electrode layer 38 and the second insulating film 15 are left in the memory circuit region ER1 and the partial region of the boundary region ER2 covered with the resist M4 (second dummy electrode layer forming step). .
- a new layered resist is formed over the memory circuit region ER1, the boundary region ER2, and the peripheral circuit region ER3.
- the resist is patterned using photolithography technology, and the metal logic formed in the subsequent manufacturing process in the peripheral circuit region ER3 as shown in FIG.
- Resist M5a and M5b are formed so as to cover the regions where gate electrodes LG1 and LG2 (FIG. 2) are to be formed (hereinafter also referred to as logic gate electrode formation regions), and peripheral circuit region ER3 is formed using resists M5a and M5b.
- the hard mask layer HM1b FIG. 4C
- the remaining hard mask layers HM1d and HM1e are used as a mask to cover the memory dummy electrode layer 38 in the memory circuit region ER1 and the boundary region ER2, and the memory dummy electrode layer 38.
- the etched second insulating film 15, the logic dummy electrode layer 37 in the boundary region ER2 and the peripheral circuit region ER3, and the first insulating film 11a covered with the logic dummy electrode layer 37 are etched back.
- the memory circuit region ER1 has a memory space along the side wall spacer 8a on one side wall of the dummy memory gate structure D2.
- the dummy electrode layer 38 remains in a sidewall shape to form the dummy first selection gate electrode DDG, and further, the second insulating film 15 remains below the dummy first selection gate electrode DDG to form the first selection gate insulation.
- the film 15a is formed, and the dummy first selection gate structure D3 having the sidewall-shaped dummy first selection gate electrode DDG on the first selection gate insulating film 15a can be formed.
- the memory dummy electrode layer 38 remains in a sidewall shape along the side wall spacer 8b on the other side wall of the dummy memory gate structure D2, and the dummy second selection gate electrode
- the SDG is formed, and further, the second insulating film 15 is left under the dummy second selecting gate electrode SDG to form the second selecting gate insulating film 15b, and the sidewalls are formed on the second selecting gate insulating film 15b.
- a dummy second selection gate structure D4 having a dummy second selection gate electrode DSG may be formed.
- the dummy logic gate electrodes DGL1 and DGL2 are formed by leaving the logic dummy electrode layer 37 in the logic gate electrode formation planned region by the hard mask layers HM1d and HM1e.
- the first insulating film 11a is left below the dummy logic gate electrodes DLG1 and DLG2 to form logic gate insulating films 25a and 25b.
- the logic gate insulating film 25a, Dummy logic gate structures DL1 and DL2 in which dummy logic gate electrodes DLG1 and DLG2 are stacked can be formed via 25b (dummy gate electrode formation step).
- the dummy first selection gate electrode DDG and the dummy second selection gate electrode DSG formed in the dummy gate electrode formation step are the films of the memory dummy electrode layer 38 formed in the second dummy electrode layer formation step described above.
- a desired width can be formed by adjusting the thickness.
- the hard mask layer HM1c remains in the region covered with the memory dummy electrode layer 38 and the second insulating film 15 (FIG. 5A). ).
- the first insulating film 15, the second insulating layer 11a, the logic dummy electrode layer 37, and the memory dummy electrode layer 38 remain around the remaining sidewall insulating film 30.
- a dummy remaining portion D29 can be formed.
- the second insulating film 15 remains in an L-shaped cross section along the element isolation layer IL1 from one surface of the wall-shaped residual sidewall insulating film 30, and the residual insulating film 31 is formed.
- the memory dummy electrode layer 39b can be formed by leaving the memory dummy electrode layer 38 in a sidewall shape on the bottom 31a and along the wall 31b of the remaining insulating film 31.
- the logic dummy electrode layer 37 remains in the region adjacent to the other surface of the remaining sidewall insulating film 30 and covered with the hard mask layer HM1c, and the logic dummy electrode remaining portion 39a is formed.
- the first insulating film 11a remains in the region covered with the logic dummy electrode remaining portion 39a, and the remaining insulating film 33 can be formed on the element isolation layer IL1.
- the memory circuit region ER1 and the peripheral circuit region are formed using a resist (not shown) patterned for N-type or P-type.
- a low concentration N-type impurity or P-type impurity is implanted into ER3 by an ion implantation method or the like, and a drain region 6a and a source region 6b are formed on the surface of the semiconductor substrate W in the memory circuit region ER1.
- Impurity diffusion regions 23a, 23b, 23c, and 23d can be formed on the surface of the semiconductor substrate W.
- the insulating layer is etched back.
- the insulating layers remain on the sidewalls of the dummy first selection gate structure D3 and the dummy second selection gate structure D4 to form the sidewalls 17a and 17b, and the dummy logic gate structures DL1 and DL2 are opposed to each other.
- Side walls 26 and 27 are formed with the insulating layer remaining on the side walls.
- the insulating layers remain around the logic dummy electrode remaining portion 39a and the memory dummy electrode remaining portion 39b to form the sidewalls 34a and 34b.
- a high concentration N-type impurity or P-type impurity is implanted into a necessary portion of the semiconductor substrate W by an ion implantation method or the like, so that the drain region 6a and the source region 6b of the memory circuit region ER1 and the peripheral circuit
- the interlayer insulating layer ILD is formed so as to cover the dummy memory gate structure D2, the dummy first selection gate structure D3, the dummy second selection gate structure D4, the dummy logic gate structures DL1 and DL2, the dummy remaining portion D29, etc.
- the process of forming is performed in order.
- the surface of the interlayer insulating layer ILD is polished and planarized, and further exposed to the outside from the tip of the interlayer insulating layer ILD, hard mask layers HM1a, HM1c, HM1d, HM1e,
- the surfaces of the dummy memory gate structure D2, the dummy first selection gate structure D3, the dummy second selection gate structure D4, the dummy logic gate structures DL1 and DL2, and the dummy remaining portion D29 are also polished and flattened.
- the dummy memory gate electrode DMG and the dummy first selection gate electrode are formed from the surface of the flattened interlayer insulating layer ILD as shown in FIG.
- the flattened tips of the DDG, the dummy second selection gate electrode DSG, the dummy logic gate electrodes DLG1 and DLG2, the logic dummy electrode remaining portion 39a, and the memory dummy electrode remaining portion 39b are exposed to the outside.
- the PMOS peripheral circuit region ER5 is covered with a resist, and the other memory circuit region ER1, the boundary region ER2, and the NMOS peripheral circuit region ER4 are exposed to the outside, and dry etching using carbon tetrafluoride (CF 4 ) or the like is performed.
- CF 4 carbon tetrafluoride
- Dummy memory gate electrode DMG exposed from the surface of interlayer insulating layer ILD, dummy first selection gate electrode DDG, dummy second selection gate electrode DSG, dummy logic gate electrode DLG1, logic dummy electrode remaining portion 39a, and memory
- the resist in the PMOS peripheral circuit region ER5 is removed.
- a metal electrode layer made of a metal material for N-type MOS such as aluminum (AL), titanium aluminum (TiAL), tantalum carbide (TaC), silicon tantalum nitride (TaSiN), etc. is formed on the surface of the interlayer insulating layer ILD.
- the dummy memory gate electrode DMG, the dummy first selection gate electrode DDG, the dummy second selection gate electrode DSG, the dummy logic gate electrode DLG1, the logic dummy electrode remaining portion 39a, and the memory dummy electrode remaining portion 39b are removed.
- the surface of the metal electrode layer is polished by a planarization process such as CMP, and the surface of the metal electrode layer is aligned with the surface of the interlayer insulating layer ILD. Flatten.
- the dummy logic gate electrode DLG2 is formed without being removed, so that the metal electrodes on the dummy logic gate electrode DLG2 and the interlayer insulating layer ILD The layer is removed by this planarization process.
- the metal electrode layer is embedded in the electrode formation space where the dummy memory gate electrode DMG was formed, thereby forming the metal memory gate electrode MG.
- the metal electrode layer is buried in the electrode formation space where the selection gate electrode DDG was formed to form the metal first selection gate electrode DG, and the metal electrode is formed in the electrode formation space where the dummy second selection gate electrode DSG was formed.
- the layer may be embedded to form the metal second select gate electrode SG.
- a metal electrode layer is embedded in the electrode formation space where the dummy logic gate electrode DLG1 is formed in the NMOS peripheral circuit region ER4 of the peripheral circuit region ER3, and is made of a metal material for N-type MOS.
- a metal logic gate electrode LG1 is formed (metal gate electrode forming step).
- a metal electrode layer is buried also in the boundary region ER2 in the electrode formation space from which the logic dummy electrode remaining portion 39a and the memory dummy electrode remaining portion 39b are removed, and is made of a metal material for N-type MOS.
- the remaining metal layers MS1 and MS2 are formed.
- the metal memory gate electrode MG, the metal first selection gate electrode DG, the metal second selection gate electrode SG, and the metal logic gate electrode LG1 are formed by the same manufacturing process using the same layer (the same metal electrode layer). Can be done.
- the memory circuit region ER1, the boundary region ER2, and the NMOS peripheral circuit region ER4 are covered with a resist, the PMOS peripheral circuit region ER5 is exposed to the outside, and the interlayer is formed by dry etching using carbon tetrafluoride (CF 4 ) or the like.
- the resist is removed.
- another metal electrode layer made of a metal material for P-type MOS such as aluminum (AL) or titanium nitride (TiN) is formed on the surface of the interlayer insulating layer ILD, and the dummy logic gate electrode DLG2 is removed.
- the surface of the metal electrode layer is polished by a planarization process such as CMP, and the surface of the metal electrode layer is aligned with the surface of the interlayer insulating layer ILD. Flatten.
- the metal electrode layer for P-type MOS is embedded in the electrode formation space where the dummy logic gate electrode DLG2 was formed.
- a metal logic gate electrode LG2 made of a metal material for P-type MOS is formed.
- a semiconductor integrated circuit is formed through a process of forming various contacts such as a first selection gate contact, a second selection gate contact, and a memory gate contact not shown in FIG. Device 20 may be manufactured.
- the lower memory gate insulating film 10 the charge storage layer EC, and the upper memory gate insulating film are formed on the semiconductor substrate W between the drain region 6a and the source region 6b.
- the second selection gate structure 4 is formed along the side wall of the side wall spacer 8b provided on the other side wall of the memory gate structure 2.
- the first selection gate structure 3 has a first selection on the semiconductor substrate W between the drain region 6a to which the bit line BL is connected and one sidewall spacer 8a provided on the sidewall of the memory gate structure 2.
- a metal first selection gate electrode DG is provided via the gate insulating film 15a.
- the second select gate structure 4 includes a first region on the semiconductor substrate W between the source region 6b to which the source line SL is connected and the other side wall spacer 8b provided on the side wall of the memory gate structure 2.
- a metal second selection gate electrode SG is provided via the two selection gate insulating film 15b.
- the metal memory gate electrode MG, the metal first selection gate electrode DG, and the metal second selection gate electrode SG can be formed of the same metal material as the metal logic gate electrode LG1 of the peripheral circuit L1, predetermined
- the metal memory gate electrode MG, the metal first selection gate electrode DG, and the metal second selection gate electrode SG can also be formed in a series of manufacturing steps in which the metal logic gate electrode LG1 made of the above metal material is formed on the semiconductor substrate W.
- the tip flat surface 3a of the metal first select gate electrode DG, the tip flat surface 4a of the metal second select gate electrode SG, and the tip flat surface 2a of the metal memory gate electrode MG are in the manufacturing process. Since the planarization is performed by the same planarization process, the heights of the memory gate structure 2, the first selection gate structure 3, and the second selection gate structure 4 can be made uniform, and the metal memory gate electrode MG is made of metal. Since the first selection gate electrode DG and the metal second selection gate electrode SG do not protrude, the overall size can be reduced.
- the charge storage layer EC is used by using the first writing method.
- the first select gate structure in a state in which carriers induced in the channel layer forming carrier region of the semiconductor substrate W facing the metal memory gate electrode MG are excluded from the channel layer forming carrier region
- the body 3 cuts off the electrical connection between the semiconductor substrate W in the region facing the metal memory gate electrode MG and the drain region 6a, and faces the metal memory gate electrode MG by the second selection gate structure 4 The electrical connection between the semiconductor substrate W in the region and the source region 6b was cut off.
- a channel layer is not formed in the channel layer forming carrier region, but a depletion layer is formed, and the potential of the surface of the semiconductor substrate W rises based on the charge storage gate voltage, and the metal memory gate
- the voltage difference between the electrode MG and the surface of the semiconductor substrate W is reduced, so that charge injection into the charge storage layer EC can be prevented.
- Reaching the selection gate insulating film 15a and the second selection gate insulating film 15b can be prevented.
- the semiconductor in the region facing the metal memory gate electrode MG is not restrained by the high voltage charge storage gate voltage necessary for injecting charges into the charge storage layer EC by the quantum tunnel effect.
- the voltage value required to cut off the electrical connection between the substrate W and the bit line BL by the first selection gate structure 3, the semiconductor substrate W in the region facing the metal memory gate electrode MG, and the source line SL The voltage value of the bit line BL and the source line SL can be lowered to a voltage value necessary to cut off the electrical connection with the second selection gate structure 4.
- the thickness of the first selection gate insulating film 15a of the first selection gate structure 3 and the second selection gate structure 4 are adjusted in accordance with the voltage reduction in the bit line BL and the source line SL.
- the film thickness of the second select gate insulating film 15b can be reduced, and high speed operation can be realized correspondingly.
- the charge storage gate voltage necessary for the charge injection into the charge storage layer EC is applied to the metal memory gate electrode MG. Even if a channel layer is formed on the surface of the semiconductor substrate W facing the metal memory gate electrode MG, the first selection gate structure 3 blocks the electrical connection between the drain region 6a and the channel layer, and the second selection. The gate structure 4 also cuts off the electrical connection between the source region 6b and the channel layer.
- a depletion layer is formed around the channel layer of the semiconductor substrate W facing the memory gate structure 2, and the channel potential of the channel layer rises based on the charge storage gate voltage.
- the voltage difference between the gate electrode MG and the channel layer is reduced, preventing charge injection into the charge storage layer EC, and the depletion layer from the channel layer to the first selection gate insulating film 15a and the second selection gate insulating film 15b. Voltage application can be cut off.
- the first selection gate structure 3 and the second selection gate are not constrained by the high voltage charge storage gate voltage necessary for injecting charges into the charge storage layer EC by the quantum tunnel effect.
- the voltage of bit line BL and source line SL is reduced to the voltage required to cut off the electrical connection between bit line BL and the channel layer, and the electrical connection between source line SL and the channel layer. The value can be lowered.
- the thickness of the first selection gate insulating film 15a of the first selection gate structure 3 and the second selection gate structure 4 are adjusted in accordance with the voltage reduction in the bit line BL and the source line SL.
- the film thickness of the second select gate insulating film 15b can be reduced, and high speed operation can be realized correspondingly.
- the logic dummy electrode layer 37 in the memory circuit region ER1 and the first resist are used by using the patterned resists M3a and M3b.
- the patterned lower memory gate insulating film 10, charge storage layer EC, upper memory gate insulating film 11, and dummy memory gate electrode DMG are formed in the memory circuit region ER1, and the first insulating film 11a and the logic dummy electrode layer 37 remain as they are in the peripheral circuit region ER3 using the resist M3b.
- the sidewall insulating films 13a and 13b and the second insulating film 15 are formed along the opposing sidewalls of the dummy memory gate structure D2 in the memory circuit region ER1.
- the second insulating film 15 and the memory dummy electrode layer 38 formed in the memory circuit region ER1, and the logic circuit formed in the peripheral circuit region ER3 are used.
- the dummy logic gate electrode DLG1 is formed on the semiconductor substrate W via the logic gate insulating films 25a and 25b.
- DLG2 are sequentially stacked, the dummy logic gate structures DL1 and DL2, and the dummy first gate electrode DDG and the first selection gate insulating film 15a disposed along one sidewall spacer 8a of the dummy memory gate structure D2.
- Dummy and second select gate structure D4 that can be formed simultaneously in the same manufacturing process.
- the interlayer insulating layer ILD formed in the memory circuit region ER1 and the peripheral circuit region ER3 is planarized by a planarization process, and the dummy memory gate electrode DMG exposed to the outside from the interlayer insulating layer ILD, the dummy After removing the first selection gate electrode DDG, the dummy second selection gate electrode DSG, and the dummy logic gate electrode DLG1, the dummy memory gate electrode DMG, the dummy first selection gate electrode DDG, the dummy second selection gate electrode DSG, and By forming a metal electrode layer in each electrode formation space where the dummy logic gate electrode DLG1 was formed, a metal memory gate electrode MG, a metal first selection gate electrode DG, a metal second selection gate electrode SG, and a metal logic gate
- the electrode LG1 can be formed in a batch in the same manufacturing process.
- the same metal material as the metal logic gate electrode LG1 is used.
- the metal memory gate electrode MG, the metal first selection gate electrode DG, and the metal second selection gate electrode SG can be formed simultaneously with the metal logic gate electrode LG1.
- the semiconductor integrated circuit device according to the embodiment is shown, and only the configuration of the boundary region ER2 is different from the semiconductor integrated circuit device 20 according to the first embodiment described above.
- this semiconductor integrated circuit device 46 is not formed with the remaining portion 29 (FIG. 2) of the semiconductor integrated circuit device 20 according to the first embodiment described above in the boundary region ER2, but on the element isolation layer IL1.
- the interlayer insulating layer ILD is formed.
- Such a semiconductor integrated circuit device 46 can simplify the entire configuration because the remaining portion 29 (FIG. 2) is not formed in the boundary region ER2.
- the configurations of the memory circuit region ER1 and the peripheral circuit region ER3 other than the boundary region ER2 are the same as those of the semiconductor integrated circuit device 20 according to the first embodiment described above. Therefore, the description of the memory circuit region ER1 and the peripheral circuit region ER3 is omitted here.
- the data write operation to the memory cell 1 and the data write prevention operation in the semiconductor integrated circuit device 46 are the same as the above-mentioned “(1-2) Data write method”.
- the operation of reading data 1 and the operation of erasing data are also the same as “(1-3) Other operations” described above, and thus the description thereof is omitted here.
- the semiconductor integrated circuit device 46 having the above-described configuration is made of a metal material by being manufactured according to the following manufacturing process.
- the metal logic gate electrodes LG1 and LG2 for example, in a series of manufacturing steps in which the metal logic gate electrode LG1 formed of a metal material for N-type MOS is formed on the semiconductor substrate W, the remaining portion 29 (FIG. 2) is formed in the boundary region ER2. ),
- the metal memory gate electrode MG, the metal first selection gate electrode DG, and the metal second selection gate electrode SG are formed simultaneously with the metal logic gate electrode LG1 using the same metal material as the metal logic gate electrode LG1. Can do.
- a plurality of element isolation layers IL1, IL2, made of an insulating material such as SiO 2 are formed at predetermined positions on the surface of a semiconductor substrate W made of Si, for example, by STI (Shallow Trench Isolation) method.
- IL3 is formed at predetermined intervals.
- a P-type impurity is added to the semiconductor substrate W in the NMOS peripheral circuit region ER4 between the element isolation layer layers IL1 and IL2.
- an N-type impurity can be implanted into the semiconductor substrate W in the PMOS peripheral circuit region ER5 between the element isolation layer layers IL2 and IL3.
- a patterned lower memory gate insulating film 10 and a charge storage layer EC are formed by a hard mask layer HM1a formed in the memory circuit region ER1 using a patterned resist (not shown).
- a dummy memory gate structure D2 in which the upper memory gate insulating film 11 and the dummy memory gate electrode DMG are sequentially stacked on the semiconductor substrate W is formed in the memory gate electrode formation planned region of the memory circuit region ER1.
- the dummy memory gate electrode DMG can be formed by leaving a layered memory dummy electrode layer in the memory gate electrode formation scheduled region by the hard mask layer HM1a.
- a layered insulating film (not shown) made of SiO 2 or the like is formed over the memory circuit region ER1, the boundary region ER2, and the peripheral circuit region ER3, and then etched back, thereby providing a dummy in the memory circuit region ER1.
- Side wall insulating films 13a and 13b are formed along the opposing side walls of the memory gate structure D2 (side wall insulating film forming step).
- the peripheral circuit region ER3 is covered with the resist, and the metal first selection gate electrode DG and the metal second selection gate electrode SG ( 7) Impurities such as B (boron), P (phosphorus), and As (arsenic) by ion implantation or the like in order to adjust the threshold voltage of the semiconductor substrate W in the formation planned region (selection gate electrode formation planned region). Is injected into the semiconductor substrate W in the memory circuit region ER1.
- a layered insulating film 48 made of the same insulating material (for example, High-k) as the upper memory gate insulating film 11 is formed across the memory circuit region ER1, the boundary region ER2, and the peripheral circuit region ER3.
- a layered logic dummy electrode layer 49 made of polysilicon or the like is formed on the insulating film 48 (dummy electrode layer forming step).
- an insulating film 48 is provided in a wall shape along the side wall insulating film 13a on one side wall to form the first selection gate side wall insulating film 16a, and the other
- the second selection gate sidewall insulating film 16b may be formed by providing the sidewall insulating film 13b on the sidewall also with the insulating film 48 in a wall shape.
- one sidewall spacer 8a composed of the sidewall insulating film 13a and the first select gate sidewall insulating film 16a is formed on one sidewall, and the sidewall insulating film 13b and the second select gate sidewall are formed.
- Another sidewall spacer 8b made of the insulating film 16b can be formed on the other sidewall.
- resists M6a and M6b covering the formation planned region (logic gate electrode formation planned region) of the metal logic gate electrodes LG1 and LG2 (FIG. 7) formed in a later manufacturing process are formed.
- a hard mask layer (not shown) made of SiO 2 or the like using the resists M6a and M6b, the hard mask layers HM2a and HM2b covering the logic gate electrode formation scheduled region are changed to the logic dummy electrode layer 49. Form on top.
- the logic dummy electrode layer 49 in the memory circuit region ER1, the boundary region ER2, and the peripheral circuit region ER3, and the logic dummy The insulating film 48 covered with the electrode layer 49 is etched back.
- the logic dummy electrode layer 49 remains in the logic gate electrode formation scheduled region of the peripheral circuit region ER3 by the hard mask layers HM2a and HM2b.
- the dummy logic gate electrodes DLG1 and DLG2 are formed, and the insulating film 48 is left below the dummy logic gate electrodes DLG1 and DLG2, respectively, thereby forming the logic gate insulating films 25a and 25b.
- dummy logic gate structures DL1 and DL2 in which dummy logic gate electrodes DLG1 and DLG2 are laminated on the semiconductor substrate W via the logic gate insulating films 25a and 25b can be formed in the peripheral circuit region ER3.
- the logic dummy electrode layer 49 remains in a sidewall shape along the side wall spacer 3a on one side wall of the dummy memory gate structure D2, and the dummy first selection gate electrode DDG is formed.
- the insulating film 48 is left below the dummy first selection gate electrode DDG to form the first selection gate insulating film 15a.
- the dummy first selection gate electrode DDG having a sidewall shape is formed on the first selection gate insulating film 15a along one sidewall spacer 8a on one sidewall of the dummy memory gate structure D2.
- a dummy first selection gate structure D3 having the following can be formed.
- the logic dummy electrode layer 49 remains in a sidewall shape along the side wall spacer 8b on the other side wall of the dummy memory gate structure D2, and the dummy second selection gate electrode The SDG is formed, and the insulating film 48 is left below the dummy second selection gate electrode SDG to form the second selection gate insulating film 15b.
- the dummy second selection gate electrode DSG having a sidewall shape on the second selection gate insulating film 15b along the other sidewall spacer 8b on the other sidewall of the dummy memory gate structure D2.
- the dummy second selection gate structure D4 having the above can be formed (dummy gate electrode forming step).
- the logic first dummy electrode layer 49 provided for forming the dummy logic gate electrodes DLG1 and DLG2 is diverted to use the dummy first selection gate electrode DDG and the dummy in the memory circuit region ER1.
- a second selection gate electrode SDG can also be formed.
- the peripheral circuit region ER3 to the boundary region ER2 The dummy first selection gate electrode DDG and the dummy second selection gate electrode DSG exposed in the memory circuit region ER1 are removed by dry etching while covering a part of the region with the resist M7, thereby achieving a desired width.
- a dummy first selection gate electrode DDG and a dummy second selection gate electrode DSG are formed.
- the dummy first selection gate electrode DDG and the dummy second selection gate formed in the memory circuit region ER1 while forming the dummy logic gate electrodes DLG1 and DLG2 having a desired width in the peripheral circuit region ER3. Since the electrode DSG can be separately formed in a desired width, the dummy first selection gate electrode DDG and the dummy second selection gate electrode DSG having a very small width can be realized.
- the sidewall insulating film 30 when forming the dummy first selection gate electrode DDG, the dummy second selection gate electrode DSG, and the dummy logic gate electrode DMG, the sidewall insulating film 30 Alternatively, the first insulating film 15, the second insulating layer 11a, the logic dummy electrode layer 49, and the memory dummy electrode layer may not be left in the boundary region ER2, and the entire surface of the element isolation layer IL1 may be exposed to the outside. it can.
- N-type impurities or P-type impurities are implanted into the memory circuit region ER1 and the peripheral circuit region ER3 by ion implantation or the like using a resist (not shown) patterned for N-type or P-type.
- the drain region 6a and the source region 6b are formed on the surface of the semiconductor substrate W in the memory circuit region ER1
- the impurity diffusion regions 23a, 23b, 23c are formed on the surface of the semiconductor substrate W in the peripheral circuit region ER3. 23d can be formed.
- the insulating layer is etched back.
- the insulating layers remain on the sidewalls of the dummy first selection gate structure D3 and the dummy second selection gate structure D4 to form the sidewalls 17a and 17b, and the dummy logic gate structures DL1 and DL2 are opposed to each other.
- Side walls 26 and 27 are formed with the insulating layer remaining on the side walls.
- the surface of the interlayer insulating layer ILD is polished and planarized by a planarization process such as CMP, and the dummy memory gate electrode DMG, the dummy first selection gate electrode DDG, and the dummy second are started from the surface of the interlayer insulating layer ILD.
- the planarized tips of the selection gate electrode DSG and the dummy logic gate electrodes DLG1 and DLG2b are exposed (electrode exposure process).
- the PMOS peripheral circuit region ER5 is covered with a resist, and the other memory circuit region ER1, the boundary region ER2, and the NMOS peripheral circuit region ER4 are exposed to the outside, and dry etching using carbon tetrafluoride (CF 4 ) or the like is performed.
- CF 4 carbon tetrafluoride
- the PMOS peripheral circuit region Remove ER5 resist.
- a metal electrode layer made of a metal material for N-type MOS such as aluminum (AL), titanium aluminum (TiAL), tantalum carbide (TaC), silicon tantalum nitride (TaSiN), etc. is formed on the surface of the interlayer insulating layer ILD.
- a metal electrode layer made of a metal material for N-type MOS such as aluminum (AL), titanium aluminum (TiAL), tantalum carbide (TaC), silicon tantalum nitride (TaSiN), etc. is formed on the surface of the interlayer insulating layer ILD.
- the dummy logic gate electrode DLG2 is formed without being removed, so that the metal electrodes on the dummy logic gate electrode DLG2 and the interlayer insulating layer ILD The layer is removed by this planarization process.
- the metal electrode layer is embedded in the electrode formation space where the dummy memory gate electrode DMG was formed, thereby forming the metal memory gate electrode MG.
- the metal electrode layer is buried in the electrode formation space where the selection gate electrode DDG was formed to form the metal first selection gate electrode DG, and the metal electrode is formed in the electrode formation space where the dummy second selection gate electrode DSG was formed.
- the metal second selection gate electrode SG can be formed by embedding the layer.
- a metal electrode layer is embedded in the electrode formation space where the dummy logic gate electrode DLG1 is formed in the NMOS peripheral circuit region ER4 of the peripheral circuit region ER3, and is made of a metal material for N-type MOS.
- a metal logic gate electrode LG1 is formed (metal gate electrode forming step). Thereby, the metal memory gate electrode MG, the metal first selection gate electrode DG, the metal second selection gate electrode SG, and the metal logic gate electrode LG1 can be formed of the same layer (the same metal electrode layer).
- the metal logic gate electrode LG2 made of a metal material for P-type MOS as shown in FIG. 7 is also formed in the PMOS peripheral circuit region ER5 of the peripheral circuit region ER3.
- a process of forming various contacts such as a first selection gate contact, a second selection gate contact, and a memory gate contact not shown in FIG. 7 at a predetermined position of the interlayer insulating layer ILD, etc.
- the semiconductor integrated circuit device 46 can be manufactured.
- the patterned lower memory gate insulating film 10, charge storage layer EC, upper memory gate insulating film 11, and dummy memory gate electrode After the dummy memory gate structure D2 in which the DMGs are sequentially stacked on the semiconductor substrate W is provided in the memory circuit region ER1, the side wall insulating films 13a and 13b and the insulation are formed along the opposite side walls of the dummy memory gate structure D2. Side wall spacers 8a and 8b made of the film 48 are formed.
- the insulating film 48 and the logic dummy electrode layer 49 formed over the memory circuit region ER1 and the peripheral circuit region ER3 are patterned by using the patterned resists M6a and M6b.
- 8B dummy logic gate structures DL1 and DL2 in which dummy logic gate electrodes DLG1 and DLG2 are sequentially stacked on a semiconductor substrate W through logic gate insulating films 25a and 25b, and a dummy memory gate structure.
- a dummy first selection gate structure D3 composed of a dummy first selection gate electrode DDG and a first selection gate insulating film 15a disposed along one side wall spacer 8a of the body D2, and another dummy memory gate structure D2.
- the dummy second select gate structure D4 including the dummy second select gate electrode DSG and the second select gate insulating film 15b arranged along the sidewall spacer 8b is collectively processed in the same manufacturing process. It can be formed.
- the interlayer insulating layer ILD formed in the memory circuit region ER1 and the peripheral circuit region ER3 is planarized by the planarization process, and the dummy memory gate electrode DMG exposed to the outside from the interlayer insulating layer ILD, the dummy After removing the first selection gate electrode DDG, the dummy second selection gate electrode DSG, and the dummy logic gate electrode DLG1, the dummy memory gate electrode DMG, the dummy first selection gate electrode DDG, the dummy second selection gate electrode DSG, and By forming a metal electrode layer in each electrode formation space where the dummy logic gate electrode DLG1 was formed, a metal memory gate electrode MG, a metal first selection gate electrode DG, a metal second selection gate electrode SG, and a metal logic gate
- the electrode LG1 can be formed in a batch in the same manufacturing process.
- the metal logic gate electrode LG1 made of a metal material for N-type MOS on the semiconductor substrate W
- the metal logic The metal memory gate electrode MG, the metal first selection gate electrode DG, and the metal second selection gate electrode SG made of the same metal material as the gate electrode LG1 can be formed simultaneously with the metal logic gate electrode LG1.
- the memory cell 51 includes a memory gate side wall insulating film 57a, 57b provided in the metal memory gate electrode MG of the memory gate structure 52, and the memory cell 51 includes a first metal selection of the first selection gate structure 53.
- the opposing side wall insulating film 56a is formed in the gate electrode DG, and the opposing side wall insulating film 56b is formed in the metal second selection gate electrode SG of the second selection gate structure 54. This is different from the memory cell 1 according to the embodiment.
- one memory gate side wall insulating film 57a having a wall shape is formed along one side wall insulating film 13a, and the other side wall insulating film 13b is formed on the other side wall insulating film 13b.
- Another memory gate side wall insulating film 57b having a wall shape is formed.
- the memory gate side wall insulating films 57a and 57b are formed of the same insulating material (for example, High-k) as the upper memory gate insulating film 11, and are integrally formed at the end of the upper memory gate insulating film 11 to form a charge storage layer. It is formed to stand on EC.
- the metal memory gate electrode MG can be formed in a concave region surrounded by the memory gate sidewall insulating films 57a and 57b and the upper memory gate insulating film 11.
- the wall is formed along the sidewall 17a so as to be opposed to the first selection gate sidewall insulating film 16a.
- An opposing sidewall insulating film 56a is provided.
- the opposing side wall insulating film 56a is formed of the same insulating material (for example, High-k) as the first selection gate insulating film 15a, and is integrally formed at the end of the first selection gate insulating film 15a. It is erected on the semiconductor substrate W.
- the metal first selection gate electrode DG is formed in the concave region surrounded by the first selection gate sidewall insulating film 16a, the first selection gate insulating film 15a, and the opposing sidewall insulating film 56a. Can be done.
- the opposing side wall having a wall shape formed along the side wall 17b so as to be opposed to the second selection gate side wall insulating film 16b.
- An insulating film 56b is provided.
- the opposing sidewall insulating film 56b is also formed of the same insulating material (for example, High-k) as the second selection gate insulating film 15b, and is integrally formed at the end of the second selection gate insulating film 15b. It stands on the top.
- the metal second selection gate electrode SG is formed in the concave region surrounded by the second selection gate sidewall insulating film 16b, the second selection gate insulating film 15b, and the opposing sidewall insulating film 56b. Can be done.
- the same metal material as the metal logic gate electrode (not shown) of the peripheral circuit formed on the same semiconductor substrate W is used, and the metal memory gate electrode MG and the metal first Since the selection gate electrode DG and the metal second selection gate electrode SG are formed, when the metal logic gate electrode of the peripheral circuit is formed on the semiconductor substrate W, the metal memory gate electrode MG and the metal first selection are selected.
- the gate electrode DG and the metal second selection gate electrode SG can also be formed on the semiconductor substrate W.
- the memory cell 51 includes a metal memory gate electrode MG, a metal first selection gate electrode DG, and a metal second selection gate electrode SG formed of a predetermined metal material. Further, it is possible to prevent the depletion layer from being formed in the metal first selection gate electrode DG and the metal second selection gate electrode SG.
- the tip flat surface 3a of the metal first select gate electrode DG, the tip flat surface 4a of the metal second select gate electrode SG, and the tip flat surface 2a of the metal memory gate electrode MG are manufactured.
- the height of the memory gate structure 52, the first selection gate structure 53, and the second selection gate structure 54 can be made uniform, and the metal memory gate electrode MG Since the metal first select gate electrode DG and the metal second select gate electrode SG do not protrude, the overall size can be reduced.
- the data write operation and the data write prevention operation to the memory cell 51 according to the third embodiment are the same as the “(1-2) Data write method” described above, and the memory cell
- the data read operation 51 and the data erase operation are also the same as the “(1-3) Other operations” described above, and the description thereof is omitted here.
- FIG. 10 showing the same reference numerals as those in FIG. 2 indicates the semiconductor integrated circuit device according to the third embodiment, and the semiconductor integrated circuit device 20 according to the first embodiment described above.
- Memory gate side wall insulating films 57a and 57b and opposing side wall insulating films 56a and 56b are formed in the memory circuit region ER1, insulating films 63 and 64 having a concave cross section are formed in the boundary region ER2, and side wall insulation is further formed in the peripheral circuit region ER3.
- films 73a, 73b, 74a, and 74b are formed. Since the memory cell 51 formed in the memory circuit region ER1 has been described with reference to FIG. 9, the description of the memory circuit region ER1 is omitted here, and the boundary region ER2 and the peripheral circuit region ER3 Is described below.
- an N-type MOS transistor structure peripheral circuit L3 is provided in the NMOS peripheral circuit region ER4, and a P-type MOS transistor structure peripheral circuit L4 is provided in the PMOS peripheral circuit region ER5. Yes.
- a logic gate structure 21a having a metal logic gate electrode LG1 on the logic gate insulating film 25a is formed on the surface of the semiconductor substrate W between the impurity diffusion regions 23a and 23b.
- the logic gate insulating film 25a is formed of the same insulating material (for example, High-k), and A wall-shaped side wall insulating film 73a is formed standing on the semiconductor substrate W from one end of the logic gate insulating film 25a. Further, between the side wall 26 formed on the other impurity diffusion region 23a and the logic gate structure 21a, the other side of the logic gate insulating film 25a is formed of the same insulating material as the logic gate insulating film 25a. A wall-like side wall insulating film 73b is formed standing on the semiconductor substrate W from the end thereof.
- insulating material for example, High-k
- a metal logic gate electrode LG1 made of a metal material for N-type MOS can be formed in an electrode forming space having a concave cross section surrounded by the side wall insulating films 73a and 73b and the logic gate insulating film 25a.
- a logic gate structure 21b having a metal logic gate electrode LG2 on the logic gate insulating film 25b is formed on the surface of the semiconductor substrate W between the impurity diffusion regions 23c and 23d. Further, between the sidewall 27 formed on the one impurity diffusion region 23c and the logic gate structure 21b, the same insulating material as the logic gate insulating film 25b (for example, High-k) is formed, and A wall-shaped side wall insulating film 74a standing on the semiconductor substrate W from one end of the logic gate insulating film 25b is formed.
- the other side of the logic gate insulating film 25b is formed of the same insulating material as the logic gate insulating film 25b.
- a wall-shaped side wall insulating film 74b standing on the semiconductor substrate W from the end thereof is formed.
- a metal logic gate electrode LG2 made of a metal material for P-type MOS can be formed in an electrode forming space having a concave cross section surrounded by the sidewall insulating films 74a and 74b and the logic gate insulating film 25b.
- an insulating film 63 having a concave cross section is formed on the element isolation layer IL1 between the remaining insulating film 30 and the one sidewall 34a.
- a residual metal layer MS1 made of the same metal material for N-type MOS as the metal gate memory electrode MG and the like is formed in an electrode formation space surrounded by the insulating film 63.
- an insulating film 64 having a concave cross section is formed on the element isolation layer IL1 between the remaining insulating film 30 and the other sidewall 34b.
- a metal gate memory electrode MG or the like The remaining metal layer MS2 made of the same metal material for the N-type MOS is formed in the electrode forming space surrounded by the insulating film 64.
- the semiconductor integrated circuit device 60 having the configuration as described above is made of a metal material by being manufactured according to the following manufacturing process.
- the metal logic gate electrodes LG1, LG2 for example, in a series of manufacturing processes for forming the metal logic gate electrode LG1 formed of a metal material for N-type MOS on the semiconductor substrate W, the same metal material as the metal logic gate electrode LG1
- the metal memory gate electrode MG, the metal first selection gate electrode DG, and the metal second selection gate electrode SG can be formed simultaneously with the metal logic gate electrode LG1.
- a plurality of element isolation layers IL1, IL2, and IL3 made of an insulating material such as SiO 2 are formed at predetermined intervals by a STI method or the like at a predetermined position on the surface of a semiconductor substrate W made of Si, for example.
- a P-type impurity is added to the semiconductor substrate W in the NMOS peripheral circuit region ER4 between the element isolation layer layers IL1 and IL2.
- an N-type impurity can be implanted into the semiconductor substrate W in the PMOS peripheral circuit region ER5 between the element isolation layer layers IL2 and IL3.
- a resist is patterned using photolithography technology, and from a partial region of the element isolation layer IL1 formed in the boundary region ER2 between the memory circuit region ER1 and the peripheral circuit region ER3 to the semiconductor substrate W in the peripheral circuit region ER3
- B Impurities such as boron
- P phosphorus
- As arsenic
- a lower memory gate insulating film made of layered SiO 2 or the like and a charge storage layer made of SiN or the like are sequentially stacked over the memory circuit region ER1, the boundary region ER2, and the peripheral circuit region ER3.
- the resist is patterned by using the photolithography technique, and the part from the memory circuit region ER1 to a partial region of the boundary region ER2 as shown in FIG. Covering with the resist M2, the lower memory gate insulating film and the charge storage layer in the boundary region ER2 and the peripheral circuit region ER3 exposed from the resist M2 are removed.
- the layered lower memory gate insulating film 10a and the charge storage layer ECa are formed only in a part of the boundary region ER2 from the memory circuit region ER1.
- the charge accumulation layer ECa in the memory circuit region ER1 passes through the element isolation layer IL1 in the boundary region ER2.
- a layered logic dummy electrode layer 77 made of polysilicon or the like is formed over the semiconductor substrate W in the peripheral circuit region ER3 (first dummy electrode layer forming step).
- the hard mask layer is patterned with resists M3a and M3b patterned using a photolithography technique.
- the resist M3a can be formed in the memory gate electrode formation scheduled region of the memory circuit region ER1, and the other resist M3b can be formed so as to cover the entire surface of the peripheral circuit region ER3. Then, by removing the hard mask layer exposed from the resists M3a and M3b, the hard mask layer HM1a is left in the memory gate electrode formation scheduled region in the memory circuit region ER1, and the hard mask layer is also formed on the entire peripheral circuit region ER3. Layer HM1b is left.
- the logic dummy electrode layer 77, the charge storage layer ECa, and the lower memory gate insulating film 10a in the memory circuit region ER1 and the boundary region ER2 are formed.
- the portions corresponding to FIG. 11A are assigned the same reference numerals, and the memory gate electrode formation planned region of the memory circuit region ER1 is formed in the lower memory gate insulating film 10 and the charge storage layer EC.
- the logic dummy electrode layer 77 is left as it is in the peripheral circuit region ER3 by the hard mask layer HM1b (dummy memory gate structure forming step).
- the logic dummy electrode layer 77 provided for forming dummy logic gate electrodes DLG1 and DLG2 (FIG. 12C), which will be described later, is diverted in the memory circuit region.
- a dummy memory gate electrode DMG can also be formed on ER1.
- a layered insulating film (not shown) made of SiO 2 or the like is formed over the memory circuit region ER1, the boundary region ER2, and the peripheral circuit region ER3, and then etched back to form a dummy in the memory circuit region ER1.
- Side wall insulating films 13a and 13b are formed along the opposing side walls of the memory gate structure D22 (side wall insulating film forming step). At this time, the insulating film also remains on the side wall of the logic dummy electrode layer 77 disposed in the boundary region ER2, and the side wall-like remaining side wall insulating film 30 can be formed.
- the threshold voltage of the semiconductor substrate W in the formation planned region (selection gate electrode formation planned region) of the metal first selection gate electrode DG and the metal second selection gate electrode SG (FIG. 10) to be formed in a later manufacturing process is adjusted.
- B (boron), P (phosphorus), As, etc. are applied to the semiconductor substrate W in the memory circuit region ER1 not covered with the hard mask layers HM1a, HM1b and the sidewall insulating films 13a, 13b, 30 by ion implantation or the like. Impurities such as (arsenic) are implanted.
- the parts corresponding to FIG. 11B are given the same reference numerals, and the memory circuit area ER1, the boundary area ER2, and the peripheral circuit area ER3 are covered with a layered memory made of, for example, polysilicon.
- a dummy electrode layer 78 is formed.
- FIG. 12A in which the same reference numerals are assigned to the corresponding parts to FIG. 11C, the memory circuit region ER1 and the partial region of the boundary region ER2 are formed by the resist M4 patterned using the photolithography technique.
- the memory dummy electrode layer 78 formed in the peripheral circuit region ER3 not covered with the resist M4 and the other partial region of the boundary region ER2 is removed. Thereby, the layered memory dummy electrode layer 78 is left over the memory circuit region ER1 covered with the resist M4 and a partial region of the boundary region ER2 (second dummy electrode layer forming step).
- a new layered resist is formed over the memory circuit region ER1, the boundary region ER2, and the peripheral circuit region ER3.
- the resist is patterned using photolithography technology, and the metal logic formed in the subsequent manufacturing process in the peripheral circuit region ER3 as shown in FIG.
- Resist M5a and M5b are formed to cover the formation regions (logic gate electrode formation planned region) of gate electrodes LG1 and LG2 (FIG. 10), and peripheral circuit region ER3 and boundary region ER2 are formed using the resists M5a and M5b.
- the hard mask layer HM1b FIG. 12A
- hard mask layers HM1d and HM1e that cover the logic gate electrode formation scheduled region are formed.
- the remaining hard mask layers HM1d and HM1e are used as masks, the memory dummy electrode layers 78 in the memory circuit region ER1 and the boundary region ER2, and the boundary regions ER2 and the peripheral circuit region ER3.
- the logic dummy electrode layer 77 is etched back.
- the memory circuit region ER1 has a memory space along the side wall spacer 8a on one side wall of the dummy memory gate structure D22.
- the dummy electrode layer 78 remains in a sidewall shape, and the dummy first selection gate electrode DDG is formed on the semiconductor substrate W, and for the memory along the side wall spacer 8b on the other side wall of the dummy memory gate structure D22.
- the dummy electrode layer 78 remains in a sidewall shape, and the dummy second selection gate electrode SDG is formed on the semiconductor substrate W.
- the dummy logic gate electrodes DGL1 and DGL2 are formed by leaving the logic dummy electrode layer 77 in the logic gate electrode formation scheduled region by the hard mask layers HM1d and HM1e. (Dummy gate electrode forming step).
- the dummy first selection gate electrode DDG and the dummy second selection gate electrode DSG formed in the dummy gate electrode formation step are the films of the memory dummy electrode layer 78 formed in the above-described second dummy electrode layer formation step.
- a desired width can be formed by adjusting the thickness.
- the hard mask layer HM1c remains in the region covered with the memory dummy electrode layer 78 (FIG. 12B).
- the logic dummy electrode layer 77 and the memory dummy electrode layer 78 may remain around the remaining sidewall insulating film 30 to form a dummy remaining portion D61.
- the memory dummy electrode layer 78 remains in a sidewall shape from one surface of the wall-shaped remaining sidewall insulating film 30 along the element isolation layer IL1, and the memory dummy electrode remaining portion 39b is formed. Can be formed.
- the logic dummy electrode layer 77 remains in the region adjacent to the other surface of the remaining sidewall insulating film 30 and covered with the hard mask layer HM1c, and the logic dummy electrode remaining portion 39a It can be formed on the separation layer IL1.
- the memory circuit region ER1 and the peripheral circuit region are formed using a resist (not shown) patterned for N-type or P-type.
- a low concentration N-type impurity or P-type impurity is implanted into ER3 by an ion implantation method or the like to form a drain region 6a and a source region 6b on the surface of the semiconductor substrate W in the memory circuit region ER1, and in the peripheral circuit region ER3.
- Impurity diffusion regions 23a, 23b, 23c, and 23d can be formed on the surface of the semiconductor substrate W.
- the insulating layer is etched back.
- the insulating layers remain on the sidewalls of the dummy first selection gate electrode DDG and the dummy second selection gate electrode DSG to form the sidewalls 17a and 17b, and on the opposite sidewalls of the dummy logic gate electrodes DLG1 and DLG2.
- the sidewalls 26 and 27 are formed with the insulating layer remaining.
- an insulating layer remains around the logic dummy electrode remaining portion 39a and the memory dummy electrode remaining portion 39b, thereby forming the sidewall 34.
- a high concentration N-type impurity or P-type impurity is implanted into a necessary portion of the semiconductor substrate W by an ion implantation method or the like, so that the drain region 6a and the source region 6b of the memory circuit region ER1 and peripheral circuits
- a step of forming a high concentration impurity region in the impurity diffusion regions 23a, 23b, 23c, and 23d of the region ER3, and a step of forming a silicide SC in the drain region 6a, the source region 6b, and the impurity diffusion regions 23a, 23b, 23c, and 23d Forming the interlayer insulating layer ILD so as to cover the dummy memory gate structure D22, the dummy first selection gate electrode DDG, the dummy second selection gate electrode DSG, the dummy logic gate electrodes DLG1 and DLG2, the dummy remaining portion D61, etc. Repeat in order.
- the surface of the interlayer insulating layer ILD is polished and planarized, and further exposed to the outside from the tip of the interlayer insulating layer ILD, hard mask layers HM1a, HM1c, HM1d, HM1e,
- the surfaces of the dummy memory gate structure D22, the dummy first selection gate electrode DDG, the dummy second selection gate electrode DSG, the dummy logic gate electrodes DLG1 and DLG2, and the dummy remaining portion D61 are also polished and flattened. In this way, as shown in FIG. 13B in which the same reference numerals are given to the corresponding parts to FIG.
- the dummy memory gate electrode DMG and the dummy first selection gate electrode DDG are formed from the surface of the flattened interlayer insulating layer ILD. Then, the flattened tips of the dummy second selection gate electrode DSG, the dummy logic gate electrodes DLG1 and DLG2, the logic dummy electrode remaining portion 39a, and the memory dummy electrode remaining portion 39b are exposed (electrode exposing step).
- the PMOS peripheral circuit region ER5 is covered with a resist, and the other memory circuit region ER1, the boundary region ER2, and the NMOS peripheral circuit region ER4 are exposed to the outside, and dry etching using carbon tetrafluoride (CF 4 ) or the like is performed.
- CF 4 carbon tetrafluoride
- Dummy memory gate electrode DMG exposed from the surface of interlayer insulating layer ILD, dummy first selection gate electrode DDG, dummy second selection gate electrode DSG, dummy logic gate electrode DLG1, logic dummy electrode remaining portion 39a, and memory
- the resist in the PMOS peripheral circuit region ER5 is removed.
- a layered insulating film is formed with an insulating material (for example, High-k) different from that of the lower memory gate insulating film 10 over the memory circuit region ER1 and the peripheral circuit region ER3, and the dummy memory gate electrode DMG and the dummy first
- a layered insulating film is also formed in each space from which the selection gate electrode DDG, dummy second selection gate electrode DSG, dummy logic gate electrode DLG1, logic dummy electrode remaining portion 39a, and memory dummy electrode remaining portion 39b are removed.
- the upper memory gate insulating film 11 is formed on the charge storage layer EC between the side wall insulating films 13a and 13b by the insulating film, and the side wall insulation is performed.
- Wall-like memory gate sidewall insulating films 57a and 57b are formed along the films 13a and 13b.
- the first selection gate insulating film 15a is formed on the semiconductor substrate W between the sidewall insulating film 13a and the sidewall 17a by the insulating film, and the sidewall insulating film 13a
- a wall-shaped first select gate sidewall insulating film 16a is formed along the sidewalls
- a wall-shaped opposing sidewall insulating film 56a is formed along the sidewall 17a.
- the second selection gate insulating film 15b is formed on the semiconductor substrate W between the sidewall insulating film 13b and the sidewall 17b by the insulating film, and the sidewall insulating film 13b
- a wall-shaped second select gate sidewall insulating film 16b is formed along the sidewalls, and a wall-shaped opposing sidewall insulating film 56b is formed along the sidewall 17b.
- another sidewall spacer 8b composed of the sidewall insulating film 13b and the second select gate sidewall insulating film 16b is formed in the memory circuit region ER1.
- a logic gate insulating film 25a is formed on the semiconductor substrate W between the opposing sidewalls 26 by an insulating film, and a wall-like shape is formed along each sidewall 26.
- Sidewall insulating films 73a and 73b may be formed.
- an insulating film 63 having a concave cross section is formed on the element isolation layer IL1 between the one sidewall 34a and the remaining insulating film 30, and the other sidewall 34b and the remaining insulating film are formed.
- An insulating film 64 having a concave cross section is formed on the element isolation layer IL1 between 30 and 30.
- a metal electrode layer made of a metal material for N-type MOS such as aluminum (AL), titanium aluminum (TiAL), tantalum carbide (TaC), silicon tantalum nitride (TaSiN), and the surface of the interlayer insulating layer ILD
- the dummy memory gate electrode DMG, the dummy first selection gate electrode DDG, the dummy second selection gate electrode DSG, the dummy logic gate electrode DLG1, the logic dummy electrode remaining portion 39a, and the memory dummy electrode remaining portion 39b are removed.
- the metal electrode layer and the insulating film are polished by a planarization process such as CMP, and the interlayer insulating layer ILD
- the surface of the metal electrode layer and the insulating film is flattened in accordance with the surface.
- the dummy logic gate electrode DLG2 remains formed without being removed, so that the metal on the dummy logic gate electrode DLG2 and on the interlayer insulating layer ILD
- the electrode layer and the insulating film are removed by this planarization process.
- the memory circuit region ER1 is surrounded by the upper memory gate insulating film 11 and the memory gate side wall insulating films 57a and 57b in the space where the dummy memory gate electrode DMG is formed.
- a metal electrode layer is embedded in the electrode forming space to form a metal memory gate electrode MG.
- the first selection gate insulating film 15a, the first selection gate sidewall insulating film 16a, and the opposing sidewall insulating film 56a A metal electrode layer is buried in the electrode formation space surrounded by the metal first selection gate electrode DG.
- the first selection gate structure 53 in which the metal first selection gate electrode DG is provided on the first selection gate insulating film 15a is formed.
- the second selection gate insulating film 15b, the second selection gate sidewall insulating film 16b, and the opposing sidewall insulating film 56b A metal electrode layer is buried in the electrode forming space surrounded by the metal to form the metal second select gate electrode SG.
- the second selection gate structure 54 in which the metal second selection gate electrode SG is provided on the second selection gate insulating film 15b is formed.
- the metal memory gate electrode MG, the metal first selection gate electrode DG, the metal second selection gate electrode SG, and the metal logic gate electrode LG1 can be formed of the same layer (the same metal electrode layer).
- the remaining metal layers MS1 and MS2 are also formed in the boundary region ER2 by embedding the metal electrode layers in the electrode formation spaces surrounded by the insulating films 63 and 64 having a concave cross section, thereby separating the elements. Residual portion 61 is formed on layer IL1.
- the memory circuit region ER1, the boundary region ER2, and the NMOS peripheral circuit region ER4 are covered with a resist, the PMOS peripheral circuit region ER5 is exposed to the outside, and the interlayer is formed by dry etching using carbon tetrafluoride (CF 4 ) or the like.
- the resist is removed.
- a layered insulating film made of an insulating material (for example, High-k) other than the insulating material of the lower memory gate insulating film 10 is formed, and a layered insulating film is also formed in the space from which the dummy logic gate electrode DLG2 is removed. To do.
- the logic gate insulating film 25a is formed on the semiconductor substrate W between the opposing sidewalls 27, and a wall-like shape is formed along each sidewall 26.
- Sidewall insulating films 73a and 73b may be formed.
- a metal electrode layer made of a metal material for P-type MOS such as aluminum (AL) or titanium nitride (TiN) is formed on the surface of the interlayer insulating layer ILD, and the space from which the dummy logic gate electrode DLG2 is removed
- the metal electrode layer embedded in the electrode formation space surrounded by the logic gate insulating film 25a and the side wall insulating films 73a and 73b the metal electrode layer for P-type MOS by the planarization process such as CMP, and The insulating film is polished, and the surfaces of the metal electrode layer and the insulating film are planarized according to the surface of the interlayer insulating layer ILD.
- the metal logic gate electrode LG2 is formed in the electrode formation space surrounded by the logic gate insulating film 25a and the side wall insulating films 73a and 73b, and the P-type MOS is formed on the logic gate insulating film 25b.
- a logic gate structure 21b provided with a metal logic gate electrode LG2 made of a metal material is formed.
- the semiconductor integrated circuit is formed through a process of forming various contacts such as a first selection gate contact, a second selection gate contact, and a memory gate contact not shown in FIG. Device 60 may be manufactured.
- the dummy memory gate structure D22 in which the patterned lower memory gate insulating film 10, the charge storage layer EC, and the dummy memory gate electrode DMG are sequentially stacked is stored in the memory.
- the logic dummy electrode layer 77 is left as it is in the peripheral circuit region ER3 with the resist M3b while being formed in the circuit region ER1, and then sidewall insulation is performed along the opposite sidewall of the dummy memory gate structure D22 in the memory circuit region ER1. Films 13a and 13b are formed.
- the memory dummy electrode layer 78 formed in the memory circuit region ER1 and the logic dummy electrode layer 77 formed in the peripheral circuit region ER3 are provided.
- the dummy logic gate electrodes DLG1 and DLG2 disposed on the semiconductor substrate W in the peripheral circuit region ER3 and one sidewall insulation of the dummy memory gate structure D22 A dummy first selection gate electrode DDG disposed on the semiconductor substrate W along the film 13a and a dummy second selection disposed on the semiconductor substrate W along the other sidewall insulating film 13b along the dummy memory gate structure D22
- the gate electrode DSG can be collectively formed in the same manufacturing process.
- the interlayer insulating layer ILD formed in the memory circuit region ER1 and the peripheral circuit region ER3 is planarized by a planarization process, and the dummy memory gate electrode DMG exposed to the outside from the interlayer insulating layer ILD, the dummy After removing the first selection gate electrode DDG, the dummy second selection gate electrode DSG, and the dummy logic gate electrode DLG1, the dummy memory gate electrode DMG, the dummy first selection gate electrode DDG, the dummy second selection gate electrode DSG, and An insulating film and a metal electrode layer are sequentially formed in each space where the dummy logic gate electrode DLG1 has been formed.
- the upper memory gate insulating film 11 in the space from which the dummy memory gate electrode DMG, the dummy first selection gate electrode DDG, the dummy second selection gate electrode DSG, and the dummy logic gate electrode DLG1 are removed.
- the first selection gate insulating film 15a, the second selection gate insulating film 15b, and the logic gate insulating film 25a can be collectively formed in the same manufacturing process, and the metal memory gate electrode MG, the metal first selection gate electrode DG, and the metal The same applies to the second select gate electrode SG and the metal logic gate electrode LG1 on the corresponding upper memory gate insulating film 11, first select gate insulating film 15a, second select gate insulating film 15b, and logic gate insulating film 25a, respectively. It can be formed at a time in the manufacturing process.
- the metal logic gate electrode LG1 made of a metal material for N-type MOS, for example, is formed in a series of manufacturing steps on the semiconductor substrate W.
- the metal memory gate electrode MG, the metal first selection gate electrode DG, and the metal second selection gate electrode SG made of the same metal material as the gate electrode LG1 can be formed simultaneously with the metal logic gate electrode LG1.
- the semiconductor integrated circuit device 80 according to the fourth embodiment has the same configuration of the memory circuit region ER1 and the peripheral circuit region ER3 other than the boundary region ER2 as the semiconductor integrated circuit device 60 according to the third embodiment described above. Therefore, the description of the memory circuit region ER1 and the peripheral circuit region ER3 is omitted here. Also, the data write operation to the memory cell 51 and the data write prevention operation in the semiconductor integrated circuit device 80 are the same as the above-mentioned “(1-2) Data write method”. The data read operation 51 and the data erase operation are also the same as the “(1-3) Other operations” described above, and the description thereof is omitted here.
- the semiconductor integrated circuit device 80 having the configuration as described above is made of a metal material by being manufactured according to the following manufacturing process.
- the metal logic gate electrodes LG1 and LG2 for example, in a series of manufacturing steps in which the metal logic gate electrode LG1 formed of a metal material for N-type MOS is formed on the semiconductor substrate W, the remaining portion 61 (see FIG. 10) is formed in the boundary region ER2.
- the metal memory gate electrode MG, the metal first selection gate electrode DG, and the metal second selection gate electrode SG are formed simultaneously with the metal logic gate electrode LG1 using the same metal material as the metal logic gate electrode LG1. Can do.
- a plurality of element isolation layers IL1, IL2, and IL3 made of an insulating material such as SiO 2 are formed at predetermined intervals on a surface of a semiconductor substrate W made of Si, for example, by an STI method or the like.
- a P-type impurity is added to the semiconductor substrate W in the NMOS peripheral circuit region ER4 between the element isolation layer layers IL1 and IL2.
- an N-type impurity can be implanted into the semiconductor substrate W in the PMOS peripheral circuit region ER5 between the element isolation layer layers IL2 and IL3.
- a resist is patterned using photolithography technology, and from a partial region of the element isolation layer IL1 formed in the boundary region ER2 between the memory circuit region ER1 and the peripheral circuit region ER3 to the semiconductor substrate W in the peripheral circuit region ER3
- P phosphorus
- As arsenic
- a lower memory gate insulating film made of layered SiO 2 or the like and a charge storage layer made of SiN or the like are sequentially stacked over the memory circuit region ER1, the boundary region ER2, and the peripheral circuit region ER3.
- the resist is patterned by using the photolithography technique, and the part from the memory circuit region ER1 to a partial region of the boundary region ER2 as shown in FIG. Covering with the resist M2, the lower memory gate insulating film and the charge storage layer in the boundary region ER2 and the peripheral circuit region ER3 exposed from the resist M2 are removed.
- the layered lower memory gate insulating film 10a and the charge storage layer ECa are formed only in a part of the boundary region ER2 from the memory circuit region ER1.
- a layered memory made of polysilicon or the like extends from the charge storage layer ECa in the memory circuit region ER1 to the semiconductor substrate W in the peripheral circuit region ER3 through the element isolation layer IL1 in the boundary region ER2.
- a dummy electrode layer (not shown) is formed.
- the memory dummy electrode layer (not shown), the charge storage layer ECa and the lower memory gate insulating film 10a are patterned by the hard mask layer HM1a, and the memory gate electrode formation planned region of the memory circuit region ER1
- a dummy memory gate structure D22 is formed in which the memory gate insulating film 10, the charge storage layer EC, and the dummy memory gate electrode DMG are sequentially stacked.
- the dummy memory gate electrode DMG can be formed by processing a memory dummy electrode layer (not shown) in the memory circuit region ER1.
- a layered insulating film (not shown) made of SiO 2 or the like is formed over the memory circuit region ER1, the boundary region ER2, and the peripheral circuit region ER3, and then etched back, thereby providing a dummy in the memory circuit region ER1.
- Side wall insulating films 13a and 13b are formed along the opposing side walls of the memory gate structure D22 (side wall insulating film forming step).
- the peripheral circuit region ER3 is covered with the resist, and the metal first selection gate electrode DG and the metal second selection gate electrode SG ( 7) Impurities such as B (boron), P (phosphorus), and As (arsenic) by ion implantation or the like in order to adjust the threshold voltage of the semiconductor substrate W in the formation planned region (selection gate electrode formation planned region). Is injected into the semiconductor substrate W in the memory circuit region ER1.
- a layered logic dummy electrode layer 49 made of polysilicon or the like is formed over the memory circuit region ER1, the boundary region ER2, and the peripheral circuit region ER3 (dummy electrode layer forming step).
- resists M6a and M6b are formed so as to cover formation planned regions (logic gate electrode formation planned regions) of the metal logic gate electrodes LG1 and LG2 (FIG. 14) formed in a later manufacturing process.
- a hard mask layer (not shown) made of SiO 2 or the like using the resists M6a and M6b, the hard mask layers HM2a and HM2b covering the logic gate electrode formation scheduled region are changed to the logic dummy electrode layer 49. Form on top.
- the logic dummy electrode layer 49 in the memory circuit region ER1, the boundary region ER2, and the peripheral circuit region ER3 is etched back using the remaining hard mask layers HM2a and HM2b as a mask.
- the logic dummy electrode layer 49 remains in the logic gate electrode formation scheduled region of the peripheral circuit region ER3 by the hard mask layers HM2a and HM2b.
- dummy logic gate electrodes DLG1 and DLG2 are formed.
- the logic dummy electrode layer 49 remains in a sidewall shape along the side wall insulating film 13a on one side wall of the dummy memory gate structure D22, and the dummy first selection gate electrode DDG And the logic dummy electrode layer 49 remains in a sidewall shape along the side wall insulating film 13b on the other side wall of the dummy memory gate structure D22 to form the dummy second selection gate electrode SDG.
- the logic first dummy electrode layer 49 provided for forming the dummy logic gate electrodes DLG1 and DLG2 is diverted to use the dummy first selection gate electrode DDG and the dummy in the memory circuit region ER1.
- a second selection gate electrode SDG can also be formed.
- the peripheral circuit region ER3 to the boundary region ER2 The dummy first selection gate electrode DDG and the dummy second selection gate electrode DSG exposed in the memory circuit region ER1 are removed by dry etching while covering a part of the region with the resist M7, thereby achieving a desired width.
- a dummy first selection gate electrode DDG and a dummy second selection gate electrode DSG are formed.
- the dummy first selection gate electrode DDG and the dummy second selection gate formed in the memory circuit region ER1 while forming the dummy logic gate electrodes DLG1 and DLG2 having a desired width in the peripheral circuit region ER3. Since the electrode DSG can be separately formed in a desired width, the dummy first selection gate electrode DDG and the dummy second selection gate electrode DSG having a very small width can be realized.
- the sidewall insulating film 30 is formed when the dummy first selection gate electrode DDG, the dummy second selection gate electrode DSG, and the dummy logic gate electrode DMG are formed.
- the entire surface of the element isolation layer IL1 can be exposed to the outside without the memory dummy electrode layer and the logic dummy electrode layer 49 remaining in the boundary region ER2.
- N-type impurities or P-type impurities are implanted into the memory circuit region ER1 and the peripheral circuit region ER3 by ion implantation or the like using a resist (not shown) patterned for N-type or P-type.
- the drain region 6a and the source region 6b are formed on the surface of the semiconductor substrate W in the memory circuit region ER1
- the impurity diffusion regions 23a, 23b, 23c are formed on the surface of the semiconductor substrate W in the peripheral circuit region ER3. 23d can be formed.
- the insulating layer is etched back.
- the insulating layers remain on the sidewalls of the dummy first selection gate electrode DDG and the dummy second selection gate electrode DSG to form the sidewalls 17a and 17b, and on the opposite sidewalls of the dummy logic gate electrodes DLG1 and DLG2.
- the sidewalls 26 and 27 are formed with the insulating layer remaining.
- the surface of the interlayer insulating layer ILD is polished and planarized by a planarization process such as CMP, and the dummy memory gate electrode DMG, the dummy first selection gate electrode DDG, and the dummy second are started from the surface of the interlayer insulating layer ILD.
- the planarized tips of the selection gate electrode DSG and the dummy logic gate electrodes DLG1 and DLG2b are exposed (electrode exposure process).
- the PMOS peripheral circuit region ER5 is covered with a resist, and the other memory circuit region ER1, the boundary region ER2, and the NMOS peripheral circuit region ER4 are exposed to the outside, and dry etching using carbon tetrafluoride (CF 4 ) or the like is performed.
- CF 4 carbon tetrafluoride
- the PMOS peripheral circuit region Remove ER5 resist.
- a layered insulating film is formed with an insulating material (for example, High-k) different from that of the lower memory gate insulating film 10 over the memory circuit region ER1 and the peripheral circuit region ER3, and the dummy memory gate electrode DMG and the dummy first
- a layered insulating film is also formed in each space from which the selection gate electrode DDG, dummy second selection gate electrode DSG, dummy logic gate electrode DLG1, logic dummy electrode remaining portion 39a, and memory dummy electrode remaining portion 39b are removed.
- the upper memory gate insulating film 11 is formed on the charge storage layer EC between the side wall insulating films 13a and 13b by the insulating film, and the side wall insulation is performed.
- Wall-like memory gate sidewall insulating films 57a and 57b are formed along the films 13a and 13b.
- the first selection gate insulating film 15a is formed on the semiconductor substrate W between the sidewall insulating film 13a and the sidewall 17a by the insulating film, and the sidewall insulating film 13a
- a wall-shaped first select gate sidewall insulating film 16a is formed along the sidewalls
- a wall-shaped opposing sidewall insulating film 56a is formed along the sidewall 17a.
- the second selection gate insulating film 15b is formed on the semiconductor substrate W between the sidewall insulating film 13b and the sidewall 17b by the insulating film, and the sidewall insulating film 13b
- a wall-shaped second select gate sidewall insulating film 16b is formed along the sidewalls, and a wall-shaped opposing sidewall insulating film 56b is formed along the sidewall 17b.
- another sidewall spacer 8b composed of the sidewall insulating film 13b and the second select gate sidewall insulating film 16b is formed in the memory circuit region ER1.
- a logic gate insulating film 25a is formed on the semiconductor substrate W between the opposing sidewalls 26 by an insulating film, and a wall-like shape is formed along each sidewall 26.
- Sidewall insulating films 73a and 73b may be formed.
- a metal electrode layer made of a metal material for N-type MOS such as aluminum (AL), titanium aluminum (TiAL), tantalum carbide (TaC), silicon tantalum nitride (TaSiN), etc. is formed on the surface of the interlayer insulating layer ILD.
- a metal material for N-type MOS such as aluminum (AL), titanium aluminum (TiAL), tantalum carbide (TaC), silicon tantalum nitride (TaSiN), etc.
- the dummy memory gate electrode DMG, the dummy first selection gate electrode DDG, the dummy second selection gate electrode DSG and the dummy logic gate electrode DLG1 are removed, and each electrode formation space surrounded by a layered insulating material is formed, After embedding the metal electrode layer, the metal electrode layer and the insulating film are polished by a planarization process such as CMP, and the surfaces of the metal electrode layer and the insulating film are planarized according to the surface of the interlayer insulating layer ILD.
- the dummy logic gate electrode DLG2 remains formed without being removed, so that the metal on the dummy logic gate electrode DLG2 and on the interlayer insulating layer ILD The electrode layer and the insulating film are removed by this planarization process.
- the memory circuit region ER1 is surrounded by the upper memory gate insulating film 11 and the memory gate sidewall insulating films 57a and 57b in the space where the dummy memory gate electrode DMG is formed.
- a metal electrode layer is embedded in the electrode forming space to form a metal memory gate electrode MG.
- the first selection gate insulating film 15a, the first selection gate sidewall insulating film 16a, and the opposing sidewall insulating film 56a A metal electrode layer is buried in the electrode formation space surrounded by the metal first selection gate electrode DG.
- the first selection gate structure 53 in which the metal first selection gate electrode DG is provided on the first selection gate insulating film 15a is formed.
- the second selection gate insulating film 15b, the second selection gate sidewall insulating film 16b, and the opposing sidewall insulating film 56b A metal electrode layer is buried in the electrode forming space surrounded by the metal to form the metal second select gate electrode SG.
- the second selection gate structure 54 in which the metal second selection gate electrode SG is provided on the second selection gate insulating film 15b is formed.
- the metal logic gate electrode LG1 is formed by embedding the metal electrode layer.
- the logic gate structure 21a in which the metal logic gate electrode LG1 is provided on the logic gate insulating film 25a is formed (metal gate electrode forming step).
- the metal memory gate electrode MG, the metal first selection gate electrode DG, the metal second selection gate electrode SG, and the metal logic gate electrode LG1 can be formed of the same layer (the same metal electrode layer).
- the metal logic gate electrode LG2 made of a metal material for P-type MOS as shown in FIG. 14 is also formed in the PMOS peripheral circuit region ER5 of the peripheral circuit region ER3.
- a process of forming various contacts such as a first selection gate contact, a second selection gate contact, and a memory gate contact, which are not illustrated in FIG.
- the semiconductor integrated circuit device 80 can be manufactured.
- the patterned lower memory gate insulating film 10, charge storage layer EC, and dummy memory gate electrode DMG are formed of a semiconductor.
- the dummy memory gate structure D22 laminated in order on the substrate W is provided in the memory circuit region ER1, side wall insulating films 13a and 13b are formed along the opposite side walls of the dummy memory gate structure D22.
- the logic dummy electrode layer 49 formed over the memory circuit region ER1 and the peripheral circuit region ER3 is patterned by using the patterned resists M6a and M6b, as shown in FIG. 15B.
- the dummy logic gate electrodes DLG1 and DLG2 disposed on the semiconductor substrate W, the dummy first selection gate electrode DDG disposed along the side wall insulating film 13a of the dummy memory gate structure D22, and the dummy The dummy second select gate electrode DSG disposed along the other side wall insulating film 13b of the memory gate structure D22 can be collectively formed in the same manufacturing process.
- the interlayer insulating layer ILD formed in the memory circuit region ER1 and the peripheral circuit region ER3 is planarized by a planarization process, and the dummy memory gate electrode DMG exposed to the outside from the interlayer insulating layer ILD, the dummy After removing the first selection gate electrode DDG, the dummy second selection gate electrode DSG, and the dummy logic gate electrode DLG1, the dummy memory gate electrode DMG, the dummy first selection gate electrode DDG, the dummy second selection gate electrode DSG, and An insulating film and a metal electrode layer are sequentially formed in each space where the dummy logic gate electrode DLG1 has been formed.
- the upper memory gate insulating film 11 in the space from which the dummy memory gate electrode DMG, the dummy first selection gate electrode DDG, the dummy second selection gate electrode DSG, and the dummy logic gate electrode DLG1 are removed.
- the first selection gate insulating film 15a, the second selection gate insulating film 15b, and the logic gate insulating film 25a can be collectively formed in the same manufacturing process, and the metal memory gate electrode MG, the metal first selection gate electrode DG, and the metal The same applies to the second select gate electrode SG and the metal logic gate electrode LG1 on the corresponding upper memory gate insulating film 11, first select gate insulating film 15a, second select gate insulating film 15b, and logic gate insulating film 25a, respectively. It can be formed at a time in the manufacturing process.
- the metal logic gate electrode LG1 made of, for example, a metal material for N-type MOS is formed in a series of manufacturing steps on the semiconductor substrate W.
- the metal memory gate electrode MG, the metal first selection gate electrode DG, and the metal second selection gate electrode SG made of the same metal material as the gate electrode LG1 can be formed simultaneously with the metal logic gate electrode LG1.
- the present invention is not limited to the first to fourth embodiments described above, and various modifications can be made within the scope of the gist of the present invention.
- various voltage values may be applied to the voltage value of each part in the above-mentioned “(1-2) Data writing method” and “(1-3) Other operations”.
- a semiconductor integrated circuit device in which the configurations according to the embodiments are combined may be used.
- the peripheral circuit L1 (L3) having the N-type MOS transistor structure is formed in one NMOS peripheral circuit region ER4, and the peripheral circuit L2 (L4 having the P-type MOS transistor structure) is formed.
- the present invention is not limited to this, and both of these peripheral circuits L1, L2 (L3, L4) are P-type or N-type MOS transistors.
- a peripheral circuit region ER3 having a structure may be used.
- the metal memory gate electrode MG and the metal first select gate in the memory cells 1, 51 are made of the metal material for the N-type MOS that forms the metal logic gate electrode LG1 in the NMOS peripheral circuit region ER4.
- the present invention is not limited to this, depending on the metal material for the P-type MOS that forms the metal logic gate electrode LG2 in the PMOS peripheral circuit region ER5,
- the metal memory gate electrode MG, the metal first selection gate electrode DG, and the metal second selection gate electrode SG in the memory cells 1 and 51 may be formed.
- the memory cell can be formed on the semiconductor substrate W into which the N-type impurity is implanted, if necessary.
- the present invention is not limited to this.
- a plurality of types of metal metal layers made of different types of metal materials are sequentially stacked to form a metal memory gate electrode MG having a stacked structure.
- the metal first selection gate electrode DG, the metal second selection gate electrode SG, and the metal logic gate electrode LG1 may be formed.
- the tips of the dummy memory gate electrode DMG, the dummy first selection gate electrode DDG, the dummy second selection gate electrode DSG, and the dummy logic gate electrodes DLG1 and DLG2 are separated from the interlayer insulating layer ILD.
- the present invention is not limited to this, and the dummy memory gate electrode DMG, the dummy first selection gate electrode DDG, the dummy first As long as the tips of the two selection gate electrodes DSG and the dummy logic gate electrodes DLG1 and DLG2 can be exposed to the outside from the interlayer insulating layer ILD, various other processes such as etching to the interlayer insulating layer ILD may be applied.
- a voltage of 1.5 [V] defined by the above-mentioned “(1-2) Data writing method” and “(1-3) Other operations” for example, the first selection gate voltage, the second selection gate voltage, For the off voltage, the read voltage, and the like, a power supply voltage VDD of 1.5 [V] or lower such as 1.2 [V] or 1.0 [V] may be used. Even when such a power supply voltage VDD is used, the same operation as described above can be performed.
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Abstract
Description
<1.第1の実施の形態>
1-1.第1の実施の形態によるメモリセルの構成
1-2.データの書き込み手法
1-2-1.第1の書き込み手法
1-2-2.第2の書き込み手法
1-3.その他の動作
1-4.第1の実施の形態による半導体集積回路装置の構成
1-5.第1の実施の形態による半導体集積回路装置の製造方法
1-6.作用および効果
<2.第2の実施の形態>
2-1.第2の実施の形態による半導体集積回路装置の構成
2-2.第2の実施の形態による半導体集積回路装置の製造方法
2-3.作用および効果
<3.第3の実施の形態>
3-1.第3の実施の形態によるメモリセルの構成
3-2.第3の実施の形態による半導体集積回路装置の構成
3-3.第3の実施の形態による半導体集積回路装置の製造方法
3-4.作用および効果
<4.第4の実施の形態>
4-1.第4の実施の形態による半導体集積回路装置の構成
4-2.第4の実施の形態による半導体集積回路装置の製造方法
4-3.作用および効果
<5.他の実施の形態>
(1-1)第1の実施の形態によるメモリセルの構成
図1において、1は本発明によるメモリセルを示す。メモリセル1は、例えばP型不純物が注入された半導体基板Wに、N型のトランジスタ構造を形成するメモリゲート構造体2と、N型のMOSトランジスタ構造を形成する第1選択ゲート構造体3と、同じくN型のMOSトランジスタ構造を形成する第2選択ゲート構造体4とが形成されている。半導体基板Wの表面には、第1選択ゲート構造体3の一端にあるドレイン領域6aと、第2選択ゲート構造体4の一端にあるソース領域6bとが所定距離を空けて形成されており、ドレイン領域6aにビット線BLが接続されているとともに、ソース領域6bにソース線SLが接続されている。
因みに、このような構成を有するメモリセル1は、(i)データの書き込み動作を実行するのに先立って、メタルメモリゲート電極MGと対向する半導体基板Wにおいて、チャネル層を形成するキャリアが存在している領域(以下、チャネル層形成キャリア領域と呼ぶ)から当該キャリアを排除し(以下、この動作をキャリア排除動作と呼ぶ)、その後、データの書き込み動作を実行する第1の書き込み手法と、これとは別に、(ii)キャリア排除動作を行わずにデータの書き込み動作を実行する第2の書き込み手法とのいずれかにより、データの書き込み動作が行われる。
ここで、第1の書き込み手法では、キャリア排除動作を実行する際、第1選択ゲート構造体3に、例えば、第1選択ゲート線DGLからメタル第1選択ゲート電極DGに1.5[V]の第1選択ゲート電圧が印加され、ビット線BLからドレイン領域6aに0[V]のビット電圧が印加され得る。これにより第1選択ゲート構造体3は、メタル第1選択ゲート電極DGと対向した半導体基板W表面で導通状態となり、ビット線BLが接続されたドレイン領域6aと、メモリゲート構造体2と対向した半導体基板Wのチャネル層形成キャリア領域とが電気的に接続し得る。
第2の書き込み手法では、メモリセル1にデータを書き込む際、キャリア排除動作を行わない以外は上述した「(1-2-1)第1の書き込み手法」と同じであるため、その説明は省略する。一方、高電圧の電荷蓄積ゲート電圧がメタルメモリゲート電極MGに印加されたときに、メモリセル1の電荷蓄積層ECに電荷を注入させない場合には、メモリゲート線MGLからメタルメモリゲート電極MGに12[V]の電荷蓄積ゲート電圧が印加されることから、電荷蓄積ゲート電圧が半導体基板Wまで伝わり、当該メタルメモリゲート電極MGと対向する半導体基板Wの表面に沿ってチャネル層が形成され得る。
なお、読み出し動作では、読み出しの対象となるメモリセル1に接続されたビット線BLを例えば1.5[V]にプリチャージし、ソース線SLを0[V]にしてメモリセル1に電流が流れるか否かによって変化するビット線BLの電位を検知することにより、電荷蓄積層ECに電荷が蓄積されているか否かを判断し得る。具体的には、データを読み出す際、メモリゲート構造体2の電荷蓄積層ECに電荷が蓄積されている場合(データが書き込まれている場合)、メモリゲート構造体2直下の半導体基板Wで非導通状態となり、ドレイン領域6aとソース領域6bとの電気的な接続が遮断され得る。これにより、データを読み出すメモリセル1では、第1選択ゲート構造体3と隣接するドレイン領域6aに接続されたビット線BLでの1.5[V]の読み出し電圧がそのまま維持され得る。
本発明のメモリセル1を有する半導体集積回路装置は、複数のメモリセル1が行列状に配置された構成を有しており、これら複数のメモリセル1の他に、周辺回路が設けられた構成を有する。図2は、半導体集積回路装置20において、例えば、1つのメモリセル1と、2つの周辺回路L1,L2とが設けられた領域での断面構成を示す概略図である。この場合、半導体集積回路装置20は、メモリセル1が設けられたメモリ回路領域ER1と、周辺回路L1,L2が設けられた周辺回路領域ER3とを有しており、メモリ回路領域ER1および周辺回路領域ER3が境界領域ER2によって分離されている。また、周辺回路領域ER3には、例えばN型のMOSトランジスタ構造の周辺回路L1が形成されたNMOS周辺回路領域ER4と、P型のMOSトランジスタ構造の周辺回路L2が形成されたPMOS周辺回路領域ER5とが設けられており、これらNMOS周辺回路領域ER4およびPMOS周辺回路領域ER5間の半導体基板W表面に素子分離層IL2が形成されている。
以上のような構成を有する半導体集積回路装置20は、下記の製造工程に従って製造することにより、周辺回路領域ER3にN型MOS用の金属材料でなるメタルロジックゲート電極LG1を有した周辺回路L1を形成する一連の製造工程において、メモリ回路領域ER1にメモリセル1を形成することができる。この場合、先ず始めに、図3Aに示すように、例えばSiでなる半導体基板W表面の所定位置に、STI(Shallow Trench Isolation)法等によりSiO2等の絶縁材料でなる複数の素子分離層IL1,IL2,IL3を所定間隔で形成する。なお、周辺回路領域ER3には、半導体基板Wの閾値電圧を調整するために、例えばイオン注入法によって、素子分離層層IL1,IL2間のNMOS周辺回路領域ER4の半導体基板WにP型不純物が注入され、一方、素子分離層層IL2,IL3間のPMOS周辺回路領域ER5の半導体基板WにN型不純物が注入され得る。
以上の構成において、メモリセル1では、ドレイン領域6aおよびソース領域6b間の半導体基板W上に、下部メモリゲート絶縁膜10、電荷蓄積層EC、上部メモリゲート絶縁膜11、およびメタルメモリゲート電極MGの順で積層形成されたメモリゲート構造体2を備え、メモリゲート構造体2の一の側壁に設けた側壁スペーサ8aの側壁に沿って第1選択ゲート構造体3が形成され、当該メモリゲート構造体2の他の側壁に設けた側壁スペーサ8bの側壁に沿って第2選択ゲート構造体4が形成されている。
(2-1)第2の実施の形態による半導体集積回路装置の構成
図2との対応部分に同一符号を付して示す図7の46は、第2の実施の形態による半導体集積回路装置を示し、上述した第1の実施の形態による半導体集積回路装置20とは境界領域ER2の構成のみが相違している。実際上、この半導体集積回路装置46は、上述した第1の実施の形態による半導体集積回路装置20が有する残存部29(図2)が境界領域ER2に形成されておらず、素子分離層IL1上に層間絶縁層ILDが形成された構成を有する。このような半導体集積回路装置46は、境界領域ER2に残存部29(図2)が形成されていない分、全体の構成を簡素化し得る。
以上のような構成を有する半導体集積回路装置46は、下記のような製造工程に従って製造されることにより、金属材料でなるメタルロジックゲート電極LG1,LG2のうち、例えばN型MOS用の金属材料で形成されたメタルロジックゲート電極LG1を半導体基板Wに形成する一連の製造工程において、境界領域ER2に残存部29(図2)を形成することなく、当該メタルロジックゲート電極LG1と同じ金属材料によりメタルメモリゲート電極MG、メタル第1選択ゲート電極DG、およびメタル第2選択ゲート電極SGを、メタルロジックゲート電極LG1と同時に形成し得る。
以上の構成において、このような製造方法によって製造されたメモリセル1や、第2の実施の形態による半導体集積回路装置46でも、上述した第1の実施の形態と同様の効果を得ることができる。
(3-1)第3の実施の形態によるメモリセルの構成
図1との対応部分に同一符号を付して示す図9において、51は第3の実施の形態によるメモリセルを示し、このメモリセル51は、メモリゲート構造体52のメタルメモリゲート電極MG内にメモリゲート側壁絶縁膜57a,57bが設けられ、第1選択ゲート構造体53のメタル第1選択ゲート電極DG内に対向側壁絶縁膜56aが形成され、さらに第2選択ゲート構造体54のメタル第2選択ゲート電極SG内に対向側壁絶縁膜56bが形成されている点で、上述した第1の実施の形態によるメモリセル1と相違している。なお、ここでは、上述した第1の実施の形態によるメモリセル1との重複部分についての説明は省略し、以下、メモリゲート側壁絶縁膜57a,57bおよび対向側壁絶縁膜56a,56bの構成に着目して説明する。
次に、上述したメモリセル51を有した半導体集積回路装置の構成について説明する。図2との対応部分に同一符号を付して示す図10の60は、第3の実施の形態による半導体集積回路装置を示し、上述した第1の実施の形態による半導体集積回路装置20とは、メモリ回路領域ER1にメモリゲート側壁絶縁膜57a,57bおよび対向側壁絶縁膜56a,56bが形成され、境界領域ER2に断面凹状の絶縁膜63,64が形成され、さらに周辺回路領域ER3に側壁絶縁膜73a,73b,74a,74bが形成されている点で相違している。なお、メモリ回路領域ER1に形成されているメモリセル51については、図9により説明していることから、ここでは、メモリ回路領域ER1の説明については省略し、境界領域ER2と周辺回路領域ER3とについて以下説明する。
以上のような構成を有する半導体集積回路装置60は、下記のような製造工程に従って製造されることにより、金属材料でなるメタルロジックゲート電極LG1,LG2のうち、例えばN型MOS用の金属材料により形成されたメタルロジックゲート電極LG1を半導体基板Wに形成する一連の製造工程において、当該メタルロジックゲート電極LG1と同じ金属材料によりメタルメモリゲート電極MG、メタル第1選択ゲート電極DG、およびメタル第2選択ゲート電極SGを、メタルロジックゲート電極LG1と同時に形成し得る。
以上の構成において、このような製造方法によって製造されたメモリセル51や、第3の実施の形態による半導体集積回路装置60でも、上述した第1の実施の形態と同様の効果を得ることができる。
(4-1)第4の実施の形態による半導体集積回路装置の構成
図10との対応部分に同一符号を付して示す図14の80は、第4の実施の形態による半導体集積回路装置を示し、上述した第3の実施の形態による半導体集積回路装置60とは境界領域ER2の構成のみが相違している。実際上、この半導体集積回路装置80は、上述した第3の実施の形態による半導体集積回路装置60が有する残存部61(図10)が境界領域ER2に形成されておらず、素子分離層IL1上に層間絶縁層ILDが形成された構成を有する。このような半導体集積回路装置80は、境界領域ER2に残存部61(図9)が形成されていない分、全体の構成を簡素化し得る。
以上のような構成を有する半導体集積回路装置80は、下記のような製造工程に従って製造されることにより、金属材料でなるメタルロジックゲート電極LG1,LG2のうち、例えばN型MOS用の金属材料で形成されたメタルロジックゲート電極LG1を半導体基板Wに形成する一連の製造工程において、境界領域ER2に残存部61(図10)を形成することなく、当該メタルロジックゲート電極LG1と同じ金属材料によりメタルメモリゲート電極MG、メタル第1選択ゲート電極DG、およびメタル第2選択ゲート電極SGを、メタルロジックゲート電極LG1と同時に形成し得る。
以上の構成において、このような製造方法によって製造されたメモリセル51や、第4の実施の形態による半導体集積回路装置80でも、上述した第1の実施の形態と同様の効果を得ることができる。
なお、本発明は、上述した第1~第4の各実施の形態に限定されるものではなく、本発明の要旨の範囲内で種々の変形実施が可能であり、例えば、上述した「(1-2)データの書き込み手法」や「(1-3)その他の動作」時における各部位の電圧値について種々の電圧値を適用してもよい。また、各実施の形態による構成を組み合わせた半導体集積回路装置としてもよい。
20,46,60,80 半導体集積回路装置
2 メモリゲート構造体
3 第1選択ゲート構造体
4 第2選択ゲート構造体
6a ドレイン領域
6b ソース領域
8a 側壁スペーサ
8b 側壁スペーサ
10 下部メモリゲート絶縁膜
11 上部メモリゲート絶縁膜
15a 第1選択ゲート絶縁膜
15b 第2選択ゲート絶縁膜
D2,D22 ダミーメモリゲート構造体
D3 ダミー第1選択ゲート構造体
D4 ダミー第2選択ゲート構造体
DG メタル第1選択ゲート電極
EC 電荷蓄積層
MG メタルメモリゲート電極
SG メタル第2選択ゲート電極
W 半導体基板
Claims (12)
- 金属材料を含むメタルロジックゲート電極を有した周辺回路と同じ半導体基板に形成されるメモリセルであって、
前記半導体基板表面に形成され、ビット線が接続されたドレイン領域と、
前記半導体基板表面に形成され、ソース線が接続されたソース領域と、
前記ドレイン領域および前記ソース領域間に形成され、下部メモリゲート絶縁膜、電荷蓄積層、上部メモリゲート絶縁膜、および前記金属材料を含むメタルメモリゲート電極の順で前記半導体基板上に積層形成されたメモリゲート構造体と、
前記ドレイン領域および前記メモリゲート構造体間の前記半導体基板上に第1選択ゲート絶縁膜を介して、前記金属材料を含むメタル第1選択ゲート電極が形成され、かつ前記メモリゲート構造体の一の側壁に一の側壁スペーサを介して隣接した第1選択ゲート構造体と、
前記ソース領域および前記メモリゲート構造体間の前記半導体基板上に第2選択ゲート絶縁膜を介して、前記金属材料を含むメタル第2選択ゲート電極が形成され、かつ前記メモリゲート構造体の他の側壁に他の側壁スペーサを介して隣接した第2選択ゲート構造体と
を備え、
前記一の側壁スペーサは、前記メモリゲート構造体の一の側壁に沿って形成された一の側壁絶縁膜と、前記第1選択ゲート構造体の側壁に沿って形成され、かつ前記第1選択ゲート絶縁膜と一体形成された第1選択ゲート側壁絶縁膜とで構成され、
前記他の側壁スペーサは、前記メモリゲート構造体の他の側壁に沿って形成された他の側壁絶縁膜と、前記第2選択ゲート構造体の側壁に沿って形成され、かつ前記第2選択ゲート絶縁膜と一体形成された第2選択ゲート側壁絶縁膜とで構成されており、
前記第1選択ゲート側壁絶縁膜および前記第2選択ゲート側壁絶縁膜は、前記側壁絶縁膜の絶縁材料とは異なる絶縁材料により形成されており、
前記側壁絶縁膜は、前記第1選択ゲート側壁絶縁膜および前記第2選択ゲート側壁絶縁膜よりも比誘電率が小さい絶縁材料で形成されている
ことを特徴とするメモリセル。 - 前記第1選択ゲート側壁絶縁膜および前記第2選択ゲート側壁絶縁膜は、High-k材料から形成されている
ことを特徴とする請求項1に記載のメモリセル。 - 金属材料を含むメタルロジックゲート電極を有した周辺回路と同じ半導体基板に形成されるメモリセルであって、
前記半導体基板表面に形成され、ビット線が接続されたドレイン領域と、
前記半導体基板表面に形成され、ソース線が接続されたソース領域と、
前記ドレイン領域および前記ソース領域間に形成され、下部メモリゲート絶縁膜、電荷蓄積層、上部メモリゲート絶縁膜、および前記金属材料を含むメタルメモリゲート電極の順で前記半導体基板上に積層形成されたメモリゲート構造体と、
前記ドレイン領域および前記メモリゲート構造体間の前記半導体基板上に第1選択ゲート絶縁膜を介して、前記金属材料を含むメタル第1選択ゲート電極が形成され、かつ前記メモリゲート構造体の一の側壁に一の側壁スペーサを介して隣接した第1選択ゲート構造体と、
前記ソース領域および前記メモリゲート構造体間の前記半導体基板上に第2選択ゲート絶縁膜を介して、前記金属材料を含むメタル第2選択ゲート電極が形成され、かつ前記メモリゲート構造体の他の側壁に他の側壁スペーサを介して隣接した第2選択ゲート構造体と
を備え、
前記メタルメモリゲート電極と、前記一の側壁スペーサとの間には、該側壁スペーサに沿って形成され、かつ前記上部メモリゲート絶縁膜と一体形成された一のメモリゲート側壁絶縁膜が設けられており、
前記メタルメモリゲート電極と、前記他の側壁スペーサとの間には、該側壁スペーサに沿って形成され、かつ前記上部メモリゲート絶縁膜と一体形成された他のメモリゲート側壁絶縁膜が設けられている
ことを特徴とするメモリセル。 - 前記メタルメモリゲート電極、前記メタル第1選択ゲート電極、および前記メタル第2選択ゲート電極は、各先端が平坦化され、前記メタルメモリゲート電極の先端平坦面と、前記メタル第1選択ゲート電極の先端平坦面と、前記メタル第2選択ゲート電極の先端平坦面とが揃っている
ことを特徴とする請求項1~3のいずれか1項に記載のメモリセル。 - ビット線およびソース線が接続されたメモリセルが行列状に配置された半導体集積回路装置であって、
前記メモリセルが請求項1~4のいずれか1項に記載のメモリセルであり、
前記メモリセルが配置されたメモリ回路領域の周辺には、前記周辺回路が設けられた周辺回路領域を有する
ことを特徴とする半導体集積回路装置。 - 前記周辺回路は、
前記半導体基板表面にロジックゲート絶縁膜を介して、前記金属材料を含んだ前記メタルロジックゲート電極が形成された構成を有し、
前記メタルメモリゲート電極と、前記メタル第1選択ゲート電極と、前記メタル第2選択ゲート電極と、前記メタルロジックゲート電極とが同じ前記金属材料により形成されている
ことを特徴とする請求項5に記載の半導体集積回路装置。 - 第1選択ゲート構造体および第2選択ゲート構造体間にメモリゲート構造体が配置されたメモリセルが形成されるメモリ回路領域と、
ロジックゲート構造体を有した周辺回路が形成される周辺回路領域と
を備えた半導体集積回路装置の製造方法であって、
前記メモリ回路領域の半導体基板上に層状の下部メモリゲート絶縁膜および電荷蓄積層を順に形成した後、前記メモリ回路領域の前記電荷蓄積層上と、前記周辺回路領域の半導体基板上とに、層状の第1絶縁膜およびロジック用ダミー電極層を順に積層形成する第1ダミー電極層形成工程と、
パターニングされたレジストを利用して、前記メモリ回路領域の前記ロジック用ダミー電極層、前記第1絶縁膜、前記電荷蓄積層、および前記下部メモリゲート絶縁膜をパターニングすることにより、パターニングされた前記下部メモリゲート絶縁膜、前記電荷蓄積層、上部メモリゲート絶縁膜、およびダミーメモリゲート電極が順に積層形成されたダミーメモリゲート構造体を前記メモリ回路領域に形成しつつ、該レジストを利用して、前記周辺回路領域に前記第1絶縁膜および前記ロジック用ダミー電極層をそのまま残存させるダミーメモリゲート構造体形成工程と、
前記メモリ回路領域の前記ダミーメモリゲート構造体の対向する側壁に沿って側壁絶縁膜を形成する側壁絶縁膜形成工程と、
前記メモリ回路領域および前記周辺回路領域に亘って層状の第2絶縁膜を形成して、前記ダミーメモリゲート構造体の対向する側壁にそれぞれ前記側壁絶縁膜および前記第2絶縁膜でなる側壁スペーサを形成した後、前記第2絶縁膜上に層状のメモリ用ダミー電極層を積層形成し、パターニングされたレジストを利用して、前記周辺回路領域の前記メモリ用ダミー電極層および前記第2絶縁膜を順に除去して、前記メモリ回路領域に前記第2絶縁膜および前記メモリ用ダミー電極層を残存させる第2ダミー電極層形成工程と、
パターニングされたレジストを利用して、前記周辺回路領域の前記ロジック用ダミー電極層および前記第1絶縁膜をパターニングすることにより、前記半導体基板上にロジックゲート絶縁膜を介してダミーロジックゲート電極が順に積層されたダミーロジックゲート構造体を形成しつつ、前記メモリ回路領域の前記メモリ用ダミー電極層および前記第2絶縁膜をエッチバックすることにより、前記ダミーメモリゲート構造体の一の前記側壁スペーサに沿ってサイドウォール状のダミー第1選択ゲート電極を形成して、前記ダミー第1選択ゲート電極の下部に前記第2絶縁膜を残存させて第1選択ゲート絶縁膜を形成するとともに、前記ダミーメモリゲート構造体の他の前記側壁スペーサに沿ってサイドウォール状のダミー第2選択ゲート電極を形成して、前記ダミー第2選択ゲート電極の下部に前記第2絶縁膜を残存させて第2選択ゲート絶縁膜を形成するダミーゲート電極形成工程と、
前記メモリ回路領域および前記周辺回路領域に層間絶縁層を形成した後、前記層間絶縁層を加工して、前記ダミーメモリゲート電極、前記ダミー第1選択ゲート電極、前記ダミー第2選択ゲート電極、および前記ダミーロジックゲート電極の各先端を前記層間絶縁層から外部に露出させる電極露出工程と、
前記ダミーメモリゲート電極、前記ダミー第1選択ゲート電極、前記ダミー第2選択ゲート電極、および前記ダミーロジックゲート電極を除去した後、前記ダミーメモリゲート電極、前記ダミー第1選択ゲート電極、前記ダミー第2選択ゲート電極、および前記ダミーロジックゲート電極が形成されていた電極形成空間に、金属材料を含んだメタルメモリゲート電極、メタル第1選択ゲート電極、メタル第2選択ゲート電極、およびメタルロジックゲート電極を形成するメタルゲート電極形成工程と
を備えることを特徴とする半導体集積回路装置の製造方法。 - 第1選択ゲート構造体および第2選択ゲート構造体間にメモリゲート構造体が配置されたメモリセルが形成されるメモリ回路領域と、
ロジックゲート構造体を有した周辺回路が形成される周辺回路領域と
を備えた半導体集積回路装置の製造方法であって、
パターニングされた下部メモリゲート絶縁膜、電荷蓄積層、上部メモリゲート絶縁膜、およびダミーメモリゲート電極が半導体基板上に順に積層形成されたダミーメモリゲート構造体が前記メモリ回路領域に設けられた後、前記ダミーメモリゲート構造体の対向する側壁に沿って側壁絶縁膜を形成する側壁絶縁膜形成工程と、
前記メモリ回路領域および前記周辺回路領域に層状の絶縁膜を形成して、前記ダミーメモリゲート構造体の対向する側壁にそれぞれ前記側壁絶縁膜および前記絶縁膜でなる側壁スペーサを形成した後、前記絶縁膜上に層状のロジック用ダミー電極層を積層形成するダミー電極層形成工程と、
パターニングされたレジストを利用して、前記周辺回路領域の前記ロジック用ダミー電極層および前記絶縁膜をパターニングすることにより、前記半導体基板上にロジックゲート絶縁膜を介してダミーロジックゲート電極が順に積層されたダミーロジックゲート構造体を形成しつつ、前記メモリ回路領域の前記ロジック用ダミー電極層および前記絶縁膜をエッチバックすることにより、前記ダミーメモリゲート構造体の一の前記側壁スペーサに沿ってサイドウォール状のダミー第1選択ゲート電極を形成して、前記ダミー第1選択ゲート電極の下部に前記絶縁膜を残存させて第1選択ゲート絶縁膜を形成するとともに、前記ダミーメモリゲート構造体の他の前記側壁スペーサに沿ってサイドウォール状のダミー第2選択ゲート電極を形成して、前記ダミー第2選択ゲート電極の下部に前記絶縁膜を残存させて第2選択ゲート絶縁膜を形成するダミーゲート電極形成工程と、
前記メモリ回路領域および前記周辺回路領域に層間絶縁層を形成した後、前記層間絶縁層を加工して、前記ダミーメモリゲート電極、前記ダミー第1選択ゲート電極、前記ダミー第2選択ゲート電極、および前記ダミーロジックゲート電極の各先端を前記層間絶縁層から外部に露出させる電極露出工程と、
前記ダミーメモリゲート電極、前記ダミー第1選択ゲート電極、前記ダミー第2選択ゲート電極、および前記ダミーロジックゲート電極を除去した後、前記ダミーメモリゲート電極、前記ダミー第1選択ゲート電極、前記ダミー第2選択ゲート電極、および前記ダミーロジックゲート電極が形成されていた電極形成空間に、金属材料を含んだメタルメモリゲート電極、メタル第1選択ゲート電極、メタル第2選択ゲート電極、およびメタルロジックゲート電極を形成するメタルゲート電極形成工程と
を備えることを特徴とする半導体集積回路装置の製造方法。 - 第1選択ゲート構造体および第2選択ゲート構造体間にメモリゲート構造体が配置されたメモリセルが形成されるメモリ回路領域と、
ロジックゲート構造体を有した周辺回路が形成される周辺回路領域と
を備えた半導体集積回路装置の製造方法であって、
前記メモリ回路領域の半導体基板上に層状の下部メモリゲート絶縁膜および電荷蓄積層を順に形成した後、前記メモリ回路領域の前記電荷蓄積層上と、前記周辺回路領域の半導体基板上とに、層状のロジック用ダミー電極層を形成する第1ダミー電極層形成工程と、
パターニングされたレジストを利用して、前記メモリ回路領域の前記ロジック用ダミー電極層、前記電荷蓄積層および前記下部メモリゲート絶縁膜をパターニングすることにより、パターニングされた前記下部メモリゲート絶縁膜、前記電荷蓄積層、およびダミーメモリゲート電極が順に積層形成されたダミーメモリゲート構造体を前記メモリ回路領域に形成しつつ、該レジストによって、前記周辺回路領域に前記ロジック用ダミー電極層をそのまま残存させるダミーメモリゲート構造体形成工程と、
前記メモリ回路領域の前記ダミーメモリゲート構造体の対向する側壁に沿って側壁絶縁膜を形成する側壁絶縁膜形成工程と、
前記メモリ回路領域および前記周辺回路領域に亘って層状のメモリ用ダミー電極層を形成した後、パターニングされたレジストを利用して、前記周辺回路領域の前記メモリ用ダミー電極層を除去し、前記メモリ回路領域に前記メモリ用ダミー電極層を残存させる第2ダミー電極層形成工程と、
パターニングされたレジストを利用して、前記周辺回路領域の前記ロジック用ダミー電極層をパターニングすることにより、前記半導体基板上にダミーロジックゲート電極を形成しつつ、前記メモリ回路領域の前記メモリ用ダミー電極層をエッチバックすることにより、前記ダミーメモリゲート構造体の一の前記側壁絶縁膜に沿ってサイドウォール状のダミー第1選択ゲート電極を形成するとともに、前記ダミーメモリゲート構造体の他の前記側壁絶縁膜に沿ってサイドウォール状のダミー第2選択ゲート電極を形成するダミーゲート電極形成工程と、
前記メモリ回路領域および前記周辺回路領域に層間絶縁層を形成した後、前記層間絶縁層を加工して、前記ダミーメモリゲート電極、前記ダミー第1選択ゲート電極、前記ダミー第2選択ゲート電極、および前記ダミーロジックゲート電極の各先端を前記層間絶縁層から外部に露出させる電極露出工程と、
前記ダミーメモリゲート電極、前記ダミー第1選択ゲート電極、前記ダミー第2選択ゲート電極、および前記ダミーロジックゲート電極を除去した後、前記ダミーメモリゲート電極、前記ダミー第1選択ゲート電極、前記ダミー第2選択ゲート電極、および前記ダミーロジックゲート電極が形成されていた各空間に、層状の絶縁膜を形成した後、各前記空間の前記絶縁膜に囲まれた電極形成空間に、金属材料を含んだメタルメモリゲート電極、メタル第1選択ゲート電極、メタル第2選択ゲート電極、およびメタルロジックゲート電極を形成するメタルゲート電極形成工程と
を備えることを特徴とする半導体集積回路装置の製造方法。 - 前記ダミーゲート電極形成工程で形成される前記ダミー第1選択ゲート電極および前記ダミー第2選択ゲート電極は、前記第2ダミー電極層形成工程で形成される前記メモリ用ダミー電極層の膜厚を調整することにより所望の幅に形成される
ことを特徴とする請求項7または9に記載の半導体集積回路装置の製造方法。 - 第1選択ゲート構造体および第2選択ゲート構造体間にメモリゲート構造体が配置されたメモリセルが形成されるメモリ回路領域と、
ロジックゲート構造体を有した周辺回路が形成される周辺回路領域と
を備えた半導体集積回路装置の製造方法であって、
パターニングされた下部メモリゲート絶縁膜、電荷蓄積層、およびダミーメモリゲート電極が半導体基板上に順に積層形成されたダミーメモリゲート構造体が前記メモリ回路領域に設けられた後、前記ダミーメモリゲート構造体の対向する側壁に沿って側壁絶縁膜を形成する側壁絶縁膜形成工程と、
前記メモリ回路領域および前記周辺回路領域に層状のロジック用ダミー電極層を形成するダミー電極層形成工程と、
パターニングされたレジストを利用して、前記周辺回路領域の前記ロジック用ダミー電極層をパターニングすることにより、前記半導体基板上にダミーロジックゲート電極を形成しつつ、前記メモリ回路領域の前記ロジック用ダミー電極層をエッチバックすることにより、前記ダミーメモリゲート構造体の一の前記側壁絶縁膜に沿ってサイドウォール状のダミー第1選択ゲート電極を形成するとともに、前記ダミーメモリゲート構造体の他の前記側壁絶縁膜に沿ってサイドウォール状のダミー第2選択ゲート電極を形成するダミーゲート電極形成工程と、
前記メモリ回路領域および前記周辺回路領域に層間絶縁層を形成した後、前記層間絶縁層を加工して、前記ダミーメモリゲート電極、前記ダミー第1選択ゲート電極、前記ダミー第2選択ゲート電極、および前記ダミーロジックゲート電極の各先端を前記層間絶縁層から外部に露出させる電極露出工程と、
前記ダミーメモリゲート電極、前記ダミー第1選択ゲート電極、前記ダミー第2選択ゲート電極、および前記ダミーロジックゲート電極を除去した後、前記ダミーメモリゲート電極、前記ダミー第1選択ゲート電極、前記ダミー第2選択ゲート電極、および前記ダミーロジックゲート電極が形成されていた各空間に、層状の絶縁膜を形成した後、各前記空間の前記絶縁膜に囲まれた電極形成空間に、金属材料を含んだメタルメモリゲート電極、メタル第1選択ゲート電極、メタル第2選択ゲート電極、およびメタルロジックゲート電極を形成するメタルゲート電極形成工程と
を備えることを特徴とする半導体集積回路装置の製造方法。 - 前記ダミーゲート電極形成工程の後には、
前記周辺回路領域をレジストで覆い、前記メモリ回路領域の前記ダミー第1選択ゲート電極および前記ダミー第2選択ゲート電極を所定量除去して、前記ダミー第1選択ゲート電極および前記ダミー第2選択ゲート電極の幅を調整するダミー電極調整工程を備える
ことを特徴とする請求項8または11に記載の半導体集積回路装置の製造方法。
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US10615168B2 (en) | 2020-04-07 |
JP5956033B1 (ja) | 2016-07-20 |
EP3300111A1 (en) | 2018-03-28 |
US10431589B2 (en) | 2019-10-01 |
TW201804570A (zh) | 2018-02-01 |
SG11201710135RA (en) | 2018-01-30 |
US20190371799A1 (en) | 2019-12-05 |
KR20180027413A (ko) | 2018-03-14 |
TWI711124B (zh) | 2020-11-21 |
IL256588A (en) | 2018-02-28 |
EP3300111B1 (en) | 2021-02-17 |
CN107851581B (zh) | 2021-08-06 |
TW201709425A (zh) | 2017-03-01 |
EP3300111A4 (en) | 2019-06-26 |
KR102424022B1 (ko) | 2022-07-22 |
US20180211965A1 (en) | 2018-07-26 |
JP2017028133A (ja) | 2017-02-02 |
CN107851581A (zh) | 2018-03-27 |
TWI610401B (zh) | 2018-01-01 |
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