WO2017012320A1 - Tft阵列基板及其制造方法及维修方法、显示面板 - Google Patents

Tft阵列基板及其制造方法及维修方法、显示面板 Download PDF

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Publication number
WO2017012320A1
WO2017012320A1 PCT/CN2016/071613 CN2016071613W WO2017012320A1 WO 2017012320 A1 WO2017012320 A1 WO 2017012320A1 CN 2016071613 W CN2016071613 W CN 2016071613W WO 2017012320 A1 WO2017012320 A1 WO 2017012320A1
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Prior art keywords
array substrate
tft array
pixel electrode
substrate
projection area
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PCT/CN2016/071613
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English (en)
French (fr)
Inventor
任兴凤
方冲
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/120,347 priority Critical patent/US10185192B2/en
Publication of WO2017012320A1 publication Critical patent/WO2017012320A1/zh
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a TFT (Thin Film Transistor) array substrate, a method of manufacturing the same, a method of repairing the same, and a display panel.
  • TFT Thin Film Transistor
  • Pixel darkening can be used to repair pixel highlights and improve product yield. First, by cutting the drain, the electrical connection between the drain and the pixel electrode is broken; then, the pixel electrode is electrically connected to the gate line or the common electrode line by soldering the pixel electrode to the gate line or the common electrode line. In order to achieve the purpose of pixel darkening.
  • the inventors have found that at least the following problems exist in the related art: since the pixel electrode is usually made of ITO (Indium-Tin Oxide) material, the ITO material is brittle, and the pixel electrode is When soldering with a gate line or a common electrode line, ITO cracking easily occurs, resulting in a low soldering success rate and a high probability of repair failure.
  • ITO Indium-Tin Oxide
  • Embodiments provide a TFT array substrate, a display panel, a manufacturing method, and a maintenance method.
  • the technical solution is as follows:
  • a TFT array substrate including:
  • a substrate a gate line, a common electrode line, and a data line formed over the substrate; and a pixel electrode formed in a pixel unit region formed by the intersection of the gate line and the data line;
  • the TFT array substrate further includes: a solder metal electrically connected to the pixel electrode;
  • An intersection region is formed between a projection area of the solder metal on the substrate and a projection area of the target trace on the substrate, and the target trace refers to the gate line or the common electrode line.
  • the pixel electrode is electrically connected to the solder metal through a via.
  • the via hole is a circular hole, and the diameter of the circular hole is 6-15 ⁇ m;
  • the via hole is a square hole, and the square hole has a side length of 6 to 15 um.
  • the pixel electrode directly overlaps the solder metal.
  • the weld metal is in the same layer as the data line.
  • the target routing includes: a strip-shaped routing body and a soldering portion electrically connected to the routing body;
  • the overlap region is formed between a projection area of the solder metal on the substrate and a projection area of the solder portion on the substrate.
  • the welded portion has a length of 6-18 um and a width of 3-5 um.
  • the overlapping area is all or part of the connection projection area
  • connection projection area refers to a projection area of the connection area where the pixel electrode and the solder metal form the electrical connection on the substrate.
  • the overlap region is wholly or partially located outside the projected area of the pixel electrode on the substrate.
  • the weld metal has a length of 6 to 18 um, a width of 3 to 5 um, and a thickness of 1 to 3 um.
  • the overlapping area has a width of 2-8 um and a length of 3-18 um.
  • a display panel comprising the TFT array substrate of the first aspect.
  • a method of fabricating a TFT array substrate comprising:
  • the pixel electrode is located in a pixel unit region formed by the intersection of the gate line and the data line, and a projection area of the solder metal on the substrate and a projection area of the target trace on the substrate An overlap region is formed, and the target trace refers to the gate line or the common electrode line.
  • a fourth aspect provides a method for repairing a TFT array substrate according to the first aspect, the method comprising:
  • the welding the overlapping area comprises:
  • connection projection area refers to a projection area of the connection area where the pixel electrode and the solder metal form the electrical connection on the substrate.
  • the welding the overlapping area comprises:
  • Welding is performed on a region of the overlap region that is outside the projection area of the pixel electrode on the substrate.
  • the gate line and the common electrode line are formed in the same layer.
  • the soldering point of the overlapping area is located in an area of the overlapping area outside the connected projection area.
  • a soldering point of the overlap region is located in an area of the overlap region outside a projection area of the pixel electrode on the substrate.
  • a bonding metal is formed by forming a solder metal electrically connected to the pixel electrode, and a projection area of the solder metal on the substrate and a projection area of the target trace on the substrate are formed. In this way, when the pixel bright spot is repaired by means of pixel dark dot, the overlapping area is soldered to form an electrical connection between the solder metal and the target trace.
  • the prior art directly solves the problem that the ITO is cracked when the pixel electrode is directly soldered to the gate line or the common electrode line, resulting in a low welding success rate and a high probability of failure in maintenance.
  • the welding between the metal and the ITO is converted into the welding between the metal and the metal, the ITO cracking is effectively reduced, the welding success rate is improved, and the repair success rate of the TFT array substrate is improved.
  • 1 is a schematic structural view of a conventional TFT array substrate
  • FIG. 2 is a schematic structural diagram of a TFT array substrate according to some embodiments of the present disclosure.
  • Figure 3 is a cross-sectional view of the TFT array substrate shown in Figure 2 taken along the line AA;
  • FIG. 4 is a schematic structural diagram of another TFT array substrate according to some embodiments of the present disclosure.
  • Figure 5 is a cross-sectional view of the TFT array substrate shown in Figure 4 taken along the line BB;
  • FIG. 6 is a schematic structural diagram of still another TFT array substrate according to some embodiments of the present disclosure.
  • Figure 7 is a cross-sectional view of the TFT array substrate shown in Figure 6 taken along the CC direction;
  • FIG. 8 is a flow chart of a method of fabricating a TFT array substrate according to some embodiments of the present disclosure
  • FIG. 9 is a flow chart of a method of repairing a TFT array substrate provided by some embodiments of the present disclosure.
  • FIG. 1 shows a schematic structural diagram of a conventional TFT array substrate.
  • FIG. 1 is only a part of the TFT array substrate.
  • the TFT array substrate includes a plurality of parts shown in FIG. 1 , and only this part will be described here as an example.
  • the TFT array substrate includes: a substrate (not shown); a gate line 1, a common electrode line 2, and a data line 3 formed on the substrate; and is formed on the gate line 1 and the data line 3 intersects the pixel electrode 4 in the pixel unit region formed.
  • the gate line 1 includes a gate electrode 11, and the data line 3 includes a source electrode 31 and a drain electrode 32.
  • the gate 11, source 31 and drain 32 constitute a thin film transistor.
  • the display panel including the TFT array substrate is divided into two types: a normally white mode and a normally black mode.
  • a normally white mode For the problem of TFT switch damage, when the pixel bright spot is repaired by the pixel dark dot method, the pixel electrode and the gate line need to be soldered for the normally white mode display panel, and for the normally black mode display panel, The pixel electrode is soldered to the common electrode line. As shown in FIG. 1 , for example, the pixel electrode and the gate line are soldered, and the soldering is performed at the soldering point 5, and the metal component of the gate line 1 is melted and connected to the pixel electrode 4, so that the pixel electrode is formed. 4 is electrically connected to the gate line 1. Since the pixel electrode is made of an ITO material, the ITO material is brittle, and ITO cracking easily occurs when the metal is soldered to the ITO.
  • FIG. 2 is a schematic structural diagram of a TFT array substrate provided by some embodiments of the present disclosure. 2 is only a part of the TFT array substrate, and those skilled in the art can understand that the TFT array substrate includes a plurality of parts shown in FIG. 2, and only this part will be described here as an example.
  • the TFT array substrate includes: a substrate (not shown); a gate line 11 formed on the substrate, a common electrode line 12 and a data line 13; and, formed on the gate line 11 and the data line 13 intersects the pixel electrode 14 in the pixel unit region formed.
  • the gate line 11 includes a gate 111 and a data line 13 includes a source 131 and a drain 132.
  • the gate electrode 111, the source electrode 131, and the drain electrode 132 constitute a thin film transistor.
  • the TFT array substrate may be a bottom gate structure or a top gate structure.
  • a plurality of lateral gate lines 11 are formed on the substrate.
  • a first insulating layer is formed over the gate line 11, and the first insulating layer includes a gate insulating layer and an active layer.
  • a plurality of longitudinal data lines 13 are formed on the first insulating layer.
  • a second insulating layer is formed over the data line 13.
  • a transparent electrode layer is formed on the second insulating layer, and a pixel electrode 14 is formed in the transparent electrode layer, and the pixel electrode 14 is located in a pixel unit region formed by the intersection of the gate line 11 and the data line 13.
  • the common electrode line 12 may be located in the same layer as the gate line 11.
  • the common electrode line 12 may also be located between the gate line 11 and the transparent electrode layer.
  • the common electrode line 12 may be located between the gate line 11 and the data line 13, or may be located in the same layer as the data line 13, or may be located between the data line 13 and the transparent electrode layer.
  • a transparent electrode layer is formed on the substrate, and the pixel electrode 14 is formed in the transparent electrode layer.
  • a second insulating layer is formed over the transparent electrode layer.
  • a plurality of longitudinal data lines 13 are formed on the second insulating layer.
  • a first insulating layer is formed over the data line 13, the first insulating layer including a gate insulating layer and an active layer.
  • a plurality of lateral gate lines 11 are formed on the first insulating layer.
  • the pixel electrode 14 is located in a pixel unit region formed by the intersection of the gate line 11 and the data line 13.
  • the common electrode line 12 is located on the upper layer of the data line 13.
  • the common electrode line 12 may be located between the data line 13 and the gate line 11, or may be located in the same layer as the gate line 11, or may be located on the upper layer of the gate line 11.
  • the TFT array substrate further includes a solder metal 15 electrically connected to the pixel electrode 14 .
  • An overlap region is formed between the projected area of the solder metal 15 on the substrate and the projected area of the target trace on the substrate, and the target trace refers to the gate line 11 or the common electrode line 12.
  • an overlapping region is formed between the projection region of the bonding metal 15 on the first metal layer and the gate line 11.
  • the solder metal 15 and the gate need to be ensured.
  • the wire 11 may be welded, and for the display panel of the normally black mode, it is only necessary to ensure that the weld metal 15 and the common electrode wire 12 are welded.
  • laser welding may be used to weld at the welding spot 10 of the overlapping region, and the metal components of the welding metal 15 and the gate wire 11 may be melted.
  • the connection is such that the solder metal 15 is electrically connected to the gate line 11.
  • the TFT provided in this embodiment is soldered to the ITO compared to the prior art.
  • the array substrate is welded to the metal during maintenance, which can effectively reduce the occurrence of ITO cracking.
  • the soldering metal 15 may be located in the upper layer of the pixel electrode 14 or in the same layer as the pixel electrode 14 , and may also be located in the lower layer of the pixel electrode 14 , which is not limited in some embodiments of the present disclosure.
  • the gate line 11 and the common electrode line 12 are located in the same layer, and the solder metal 15 and the data line 13 are located in the same layer, which can be beneficial to reduce the thickness of the TFT array substrate and facilitate the soldering of the metal 15 Formation.
  • the welding metal 15 should not be too small or too large, and the welding metal 15 is too small to affect the welding, and the excessively large welding metal 15 may affect the light transmittance of the TFT array substrate. Therefore, in one possible embodiment, the weld metal 15 has a length of 6 to 18 um, a width of 3 to 5 um, and a thickness of 1 to 3 um. Alternatively, the length of the weld metal 15 is 10 um. In addition, in order to ensure a sufficient welding position, the overlapping area formed between the projection area of the bonding metal 15 on the substrate and the projection area of the target wiring on the substrate has a width of 2 to 8 ⁇ m and a length of 3 to 18 ⁇ m.
  • FIG. 3 is a cross-sectional view of the TFT array substrate shown in FIG. 2 along the AA direction.
  • a first metal layer is formed on the substrate 17, and a gate line 11 is formed in the first metal layer.
  • a first insulating layer 18 is formed over the first metal layer.
  • a second metal layer is formed over the first insulating layer 18, and the data line 12 and the bonding metal 15 are formed in the second metal layer.
  • a second insulating layer 19 is formed over the second metal layer, and a via hole 16 is formed at a position where the second insulating layer 19 corresponds to the solder metal 15.
  • a transparent electrode layer is formed on the second insulating layer 19, and the pixel electrode 14 is formed in the transparent electrode layer. The pixel electrode 14 is electrically connected to the solder metal 15 through the via 16 .
  • the vias 16 may be circular, square, or other shapes.
  • the via 16 should not be too small or too large.
  • the diameter of the circular hole is 6-15 um, and optionally, the diameter of the circular hole is 8 um; for example, when the via hole 16 is a square hole, the side of the square hole The length is 6-15 um, and optionally, the side length of the square hole is 8 um.
  • the pixel electrode 14 is directly overlapped with the solder metal 15.
  • the solder metal 15 may be directly overlapped on the edge of the edge of the pixel electrode 14, or may be directly overlapped on the edge of the pixel electrode 14, or may be in the same layer as the pixel electrode 14 and overlap the edge of the pixel electrode 14.
  • FIG. 4 is a schematic structural view of another TFT array substrate according to some embodiments of the present disclosure
  • FIG. 5 is a cross-sectional view of the TFT array substrate shown in FIG. 4 along the BB direction.
  • an overlapping region is formed between a projection area of the bonding metal 15 on the substrate and a projection area of the gate line 11 on the substrate, and the gate line 11 includes a strip-shaped gate line body 11a and is electrically connected to the gate line body 11a.
  • the connected welded portion 11b has an overlapping region formed between the projected region of the bonding metal 15 on the substrate and the projected portion of the welded portion 11b on the substrate.
  • the size of the welded portion may be similar to the size of the weld metal 15, and the length of the welded portion is 6-18 um and the width is 3-5 um.
  • connection projection area is a projection area of the connection area where the pixel electrode 14 is electrically connected to the solder metal 15 on the substrate.
  • the welding spot 10 is set in an area in the overlapping area outside the connection projection area. As shown in FIGS. 2 through 5, the solder joint 10 is adjacent to the via 16 without overlapping the via 16 to avoid damaging the electrical connections that have been formed between the pixel electrode 14 and the solder metal 15 during soldering.
  • FIG. 6 is a schematic structural view of still another TFT array substrate according to some embodiments of the present disclosure
  • FIG. 7 is a cross-sectional view of the TFT array substrate shown in FIG.
  • An overlap region is formed between the projected area of the solder metal 15 on the substrate and the projected area of the target trace on the substrate, the overlap region being located wholly or partially outside the projected area of the pixel electrode 14 on the substrate.
  • an overlapping region is formed between a projection area of the bonding metal 15 on the substrate and a projection area of the gate line 11 on the substrate, and the overlapping region is entirely located at the pixel electrode 14 on the substrate. Outside the projection area.
  • the soldering spot 10 is set in a region outside the projected area of the pixel electrode 14 on the substrate in the overlapping region. As shown in FIGS. 6 and 7, the soldering point 10 is next to the pixel electrode 14 without overlapping the pixel electrode 14. Compared with the TFT array substrate shown in FIGS. 2 and 4, since the TFT array substrate shown in FIG. 6 does not touch the pixel electrode 14 during maintenance soldering, ITO cracking during soldering can be completely avoided.
  • some embodiments of the present disclosure provide a TFT array substrate by forming a solder metal electrically connected to a pixel electrode, and a projection area of the solder metal on the substrate and a target trace on the substrate An overlapping area is formed between the upper projection areas.
  • the overlapping area is soldered to form an electrical connection between the solder metal and the target trace.
  • the prior art directly solves the problem that the ITO is cracked when the pixel electrode is directly soldered to the gate line or the common electrode line, resulting in a low welding success rate and a high probability of failure in maintenance.
  • the welding between the metal and the ITO is converted into the welding between the metal and the metal, the ITO cracking is effectively reduced, the welding success rate is improved, and the repair success rate of the TFT array substrate is improved.
  • the solder metal and the data line are formed in the same layer, which is advantageous for reducing the thickness of the TFT array substrate, and at the same time facilitating the formation of the solder metal and ensuring the TFT array substrate. Production efficiency.
  • the soldering point is positioned in the overlapping area outside the connecting projection area during maintenance to avoid destroying the pixel electrode and soldering during soldering.
  • the electrical connection has been formed between the metals to ensure the success rate of repair.
  • the solder joint is positioned in an area of the overlap region outside the projection area of the pixel electrode on the substrate, Ensure that the pixel electrode is not touched during repair welding, thus completely avoiding ITO cracking during soldering, further reducing the risk of repair failure.
  • the display panel includes: a color film substrate, a TFT array substrate, and a liquid crystal layer between the color filter substrate and the TFT array substrate.
  • the TFT array substrate may be the TFT array substrate shown in any of FIG. 2, FIG. 4 or FIG. 6 provided in the above embodiment.
  • the display panel may be a product in a normally white mode, or may also be a product in a normally black mode.
  • the normally white mode display panel an overlapping region is formed between a projection area of the bonding metal on the substrate and a projection area of the gate line on the substrate.
  • the display panel of the normally black mode an overlapping region is formed between a projection area of the bonding metal on the substrate and a projection area of the common electrode line on the substrate.
  • Some embodiments of the present disclosure also provide a method of fabricating a TFT array substrate, which may include the following steps:
  • a gate line, a common electrode line, a data line, a pixel electrode, and a solder metal electrically connected to the pixel electrode are formed on the substrate.
  • the pixel electrode is located in a pixel unit region formed by the intersection of the gate line and the data line.
  • An overlap region is formed between a projected area of the solder metal on the substrate and a projected area of the target trace on the substrate.
  • the target trace refers to a gate line or a common electrode line.
  • some embodiments of the present disclosure provide a method for fabricating a TFT array substrate by forming a solder metal electrically connected to a pixel electrode, and a projection area of the solder metal on the substrate and a target trace on the substrate. An overlapping area is formed between the projection areas. In this way, when the pixel bright spot is repaired by means of pixel dark dot, the overlapping area is soldered to form an electrical connection between the solder metal and the target trace.
  • the prior art directly solves the problem that the ITO is cracked when the pixel electrode is directly soldered to the gate line or the common electrode line, resulting in a low welding success rate and a high probability of failure in maintenance.
  • the welding between the metal and the ITO is converted into the welding between the metal and the metal, the ITO cracking is effectively reduced, the welding success rate is improved, and the repair success rate of the TFT array substrate is improved.
  • FIG. 8 shows a flowchart of a method of fabricating a TFT array substrate provided by some embodiments of the present disclosure.
  • a TFT array substrate in which a bottom gate structure is fabricated is taken as an example.
  • the manufacturing method can include the following steps:
  • Step 801 forming a first metal layer on the substrate, and performing a patterning process to obtain a gate line and a common electrode line.
  • a first metal layer can be formed on the substrate using a magnetron sputtering method.
  • the first metal layer may generally be a metal such as molybdenum, aluminum, an aluminum-nickel alloy, a molybdenum-tungsten alloy, chromium or copper, or a film composite structure formed of the above various metals.
  • a photoresist is coated on the first metal layer, and a patterning process such as exposure, development, etching, and stripping is performed by using a mask to form a plurality of lateral gate lines and a plurality of common electrode lines on the substrate.
  • the gate line includes a gate.
  • Step 802 forming a first insulating layer over the first metal layer.
  • the first insulating layer includes a gate insulating layer formed over the first metal layer, and an active layer formed over the gate insulating layer.
  • the material of the gate insulating layer is usually silicon nitride, and silicon oxide, silicon oxynitride or the like can also be used.
  • the material of the active layer is usually amorphous silicon.
  • a gate insulating layer and an active layer may be formed by continuous deposition on the first metal layer by chemical vapor deposition.
  • Step 803 forming a second metal layer on the first insulating layer, and processing the data line and the solder metal by a patterning process.
  • a weld metal is formed in the second metal layer. That is, the weld metal is in the same layer as the data line.
  • an overlap region is formed between a projection area of the solder metal on the substrate and a projection area of the target trace on the substrate, and the target trace refers to a gate line or a common electrode line.
  • the method of manufacturing the data line and the solder metal is similar to the method of manufacturing the gate line and the common electrode line in step 801, and details are not described herein again.
  • the data line includes a source and a drain.
  • the length of the weld metal is 6-18 um, the width is 3-5 um, and the thickness is 1-3 um.
  • Step 804 forming a second insulating layer over the second metal layer.
  • a second insulating layer may be formed on the second metal layer by chemical vapor deposition, and the material of the second insulating layer is usually silicon nitride or silicon dioxide.
  • Step 805 forming a via hole at a position where the second insulating layer corresponds to the solder metal.
  • the vias may be round holes, square holes, or other shapes.
  • the via hole is a circular hole
  • the diameter of the circular hole is 6-15 ⁇ m
  • the side length of the square hole is 6-15 ⁇ m.
  • a second via hole is further formed at a position where the second insulating layer corresponds to the drain.
  • Step 806 forming a transparent electrode layer on the second insulating layer, and performing a patterning process to obtain a pixel electrode electrically connected to the solder metal through the via.
  • a transparent electrode layer may be formed on the second insulating layer by chemical vapor deposition, and a mask is used to process the pixel in the pixel unit region formed by the intersection of the gate line and the data line. electrode.
  • the pixel electrode is usually made of an ITO material.
  • ITO Indium Tin Oxide
  • the pixel electrode is electrically connected to the solder metal through the via hole.
  • the pixel electrode is also electrically connected to the drain through the second via.
  • the common electrode line may also be located on the gate line layer and located under the transparent electrode layer.
  • the common electrode line may be located between the gate line and the data line, or may be located in the same layer as the data line, or may be located between the data line and the transparent electrode layer.
  • the solder metal may be located on the upper layer of the pixel electrode, or in the same layer as the pixel electrode, and may also be located on the lower layer of the pixel electrode.
  • only the pixel electrode is electrically connected to the solder metal through the via hole.
  • the pixel electrode and the solder metal may also directly overlap.
  • the manufacturing method of the TFT array substrate of the bottom gate structure is taken as an example, and the TFT array substrate of the top gate structure can be manufactured. Similar to the process flow, this part is content that is easy to be considered by those skilled in the art based on the content disclosed in this embodiment, and the disclosure does not introduce and explain this.
  • FIG. 9 shows a flowchart of a method of repairing a TFT array substrate provided by some embodiments of the present disclosure.
  • the maintenance method can be used to repair the TFT array substrate shown in any of FIG. 2, FIG. 4 or FIG. 6 provided in the above embodiment.
  • the repair method can include the following steps:
  • Step 901 cutting a drain formed in the data line, and disconnecting an electrical connection between the drain and the pixel electrode.
  • Step 902 soldering the overlap region to form an electrical connection between the solder metal and the target trace.
  • the laser can be used to cut the drain and disconnect the electrical connection between the drain and the pixel electrode. Then, since the TFT array substrate provided by some embodiments of the present disclosure has formed an electrical connection between the pixel electrode and the solder metal at the time of manufacture, it is only necessary to use a laser welding technique to solder the solder joints in the overlap region. Therefore, an electrical connection can be made between the solder metal and the target trace.
  • connection projection area refers to a projection area formed on the substrate by a connection region in which the pixel electrode and the solder metal are electrically connected. In this way, it is possible to avoid the electrical connection that has been formed between the pixel electrode and the solder metal during soldering, and to ensure the success rate of repair.
  • the projection area of the overlapping electrode located on the substrate is on the substrate.
  • the outer region is soldered, that is, the solder joint is positioned in an area of the overlap region outside the projected area of the pixel electrode on the substrate. In this way, it is ensured that the pixel electrode is not touched during maintenance welding, thereby completely avoiding ITO cracking during soldering, further reducing the risk of maintenance failure.
  • some embodiments of the present disclosure provide a method for repairing a TFT array substrate by soldering an overlap region formed between a solder metal and a target trace to form an electrical property between the solder metal and the target trace. connection.
  • the prior art directly solves the problem that the ITO is cracked when the pixel electrode is directly soldered to the gate line or the common electrode line, resulting in a low welding success rate and a high probability of failure in maintenance.
  • the welding between the metal and the ITO is converted into the welding between the metal and the metal, the ITO cracking is effectively reduced, the welding success rate is improved, and the repair success rate of the TFT array substrate is improved.
  • a person skilled in the art may understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium.
  • the storage medium mentioned may be a read only memory, a magnetic disk or an optical disk or the like.

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Abstract

一种TFT阵列基板、显示面板、制造方法及维修方法，属于显示技术领域。TFT阵列基板包括：基板；形成在基板之上的栅线（11）、公共电极线（12）和数据线（13）；以及，形成于栅线（11）和数据线（13）交叉形成的像素单元区域中的像素电极（14）；TFT阵列基板还包括：与像素电极（14）电性连接的焊接金属（15）；焊接金属（15）在基板上的投影区域与目标走线在基板上的投影区域之间形成有交叠区域，目标走线是指栅线（11）或者公共电极线（12）。

Description

TFT阵列基板及其制造方法及维修方法、显示面板
相关申请的交叉引用
本申请主张在2015年7月22日在中国提交的中国专利申请号No.201510437816.5的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，特别涉及一种TFT(Thin Film Transistor，薄膜晶体管)阵列基板及其制造方法及维修方法、显示面板。
背景技术
TFT阵列基板在生产过程中，会发生TFT开关损坏的问题，导致产生像素亮点。
采用像素暗点化的方式可以对像素亮点进行维修，提高产品良率。首先，通过切割漏极，断开漏极与像素电极之间的电性连接；然后，通过将像素电极与栅线或者公共电极线进行焊接，使得像素电极与栅线或者公共电极线电性连接，从而达到像素暗点化的目的。
在实现本公开的过程中，发明人发现相关技术中至少存在以下问题：由于像素电极通常是由ITO(Indium-Tin Oxide，氧化铟锡)材料制成的，ITO材料质脆，在将像素电极与栅线或者公共电极线进行焊接时容易产生ITO崩裂，导致焊接成功率低，维修失败的概率大。
发明内容
为了解决现有技术在采用像素暗点化的方式对像素亮点进行维修时，将像素电极与栅线或者公共电极线进行焊接时的成功率低，维修失败的概率大的问题，本公开的一些实施例提供了一种TFT阵列基板、显示面板、制造方法及维修方法。所述技术方案如下：
第一方面，提供了一种TFT阵列基板，包括：
基板；形成在所述基板之上的栅线、公共电极线和数据线；以及，形成于所述栅线和所述数据线交叉形成的像素单元区域中的像素电极；
其中，所述TFT阵列基板，还包括：与所述像素电极电性连接的焊接金属；
所述焊接金属在所述基板上的投影区域与目标走线在所述基板上的投影区域之间形成有交叠区域，所述目标走线是指所述栅线或者所述公共电极线。
可选地，所述像素电极通过过孔与所述焊接金属电性连接。
可选地，所述过孔为圆孔，且所述圆孔的直径为6～15um；
或者，所述过孔为方孔，且所述方孔的边长为6～15um。
可选地，所述像素电极与所述焊接金属直接搭接。
可选地，所述焊接金属与所述数据线位于同一层中。
可选地，所述目标走线包括：呈条状的走线本体以及与所述走线本体电性连接的焊接部；
所述焊接金属在所述基板上的投影区域与所述焊接部在所述基板上的投影区域之间形成有所述交叠区域。
可选地，所述焊接部的长度为6～18um，宽度为3～5um。
可选地，所述交叠区域全部或部分位于连接投影区域之外；
其中，所述连接投影区域是指所述像素电极与所述焊接金属形成所述电性连接的连接区域在所述基板上的投影区域。
可选地，所述交叠区域全部或部分位于所述像素电极在所述基板上的投影区域之外。
可选地，所述焊接金属的长度为6～18um，宽度为3～5um，厚度为1～3um。
可选地，所述交叠区域的宽度为2～8um，长度为3～18um。
第二方面，提供了一种显示面板，所述显示面板包括如第一方面所述的TFT阵列基板。
第三方面，提供了一种TFT阵列基板的制造方法，所述方法包括：
在基板上形成栅线、公共电极线、数据线、像素电极以及与所述像素电极电性连接的焊接金属；
其中，所述像素电极位于所述栅线和所述数据线交叉形成的像素单元区域中，所述焊接金属在所述基板上的投影区域与目标走线在所述基板上的投影区域之间形成有交叠区域，所述目标走线是指所述栅线或者所述公共电极线。
第四方面，提供了一种如第一方面所述的TFT阵列基板的维修方法，所述方法包括：
对所述数据线中形成的漏极进行切割，断开所述漏极与所述像素电极之间的电性连接；
对所述交叠区域进行焊接，使得所述焊接金属与所述目标走线之间形成电 性连接。
可选地，所述对所述交叠区域进行焊接，包括：
对所述交叠区域中位于连接投影区域之外的区域进行焊接；
其中，所述连接投影区域是指所述像素电极与所述焊接金属形成所述电性连接的连接区域在所述基板上的投影区域。
可选地，所述对所述交叠区域进行焊接，包括：
对所述交叠区域中位于所述像素电极在所述基板上的投影区域之外的区域进行焊接。
可选的，所述栅线和所述公共电极线形成于同一层。
可选的，所述交叠区域的焊接点位位于所述交叠区域中位于所述连接投影区域之外的区域。
可选的，所述交叠区域的焊接点位位于所述交叠区域中位于所述像素电极在所述基板上的投影区域之外的区域。
本公开的一些实施例提供的技术方案带来的有益效果包括：
通过形成与像素电极电性连接的焊接金属，且该焊接金属在基板上的投影区域与目标走线在基板上的投影区域之间形成有交叠区域。这样，在采用像素暗点化的方式对像素亮点进行维修时，通过对上述交叠区域进行焊接，使得焊接金属与目标走线之间形成电性连接。解决了现有技术直接将像素电极与栅线或者公共电极线进行焊接时容易产生ITO崩裂，导致焊接成功率低，维修失败的概率大的问题。实现了将金属与ITO之间的焊接转化为金属与金属之间的焊接，有效减少ITO崩裂发生，提高了焊接成功率，进而提高了TFT阵列基板的维修成功率。
附图说明
为了更清楚地说明本公开的一些实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是一种现有的TFT阵列基板的结构示意图；
图2是本公开的一些实施例提供的一种TFT阵列基板的结构示意图；
图3是图2所示的TFT阵列基板沿AA方向的剖面图；
图4是本公开的一些实施例提供的另一TFT阵列基板的结构示意图；
图5是图4所示的TFT阵列基板沿BB方向的剖面图；
图6是本公开的一些实施例提供的再一TFT阵列基板的结构示意图；
图7是图6所示的TFT阵列基板沿CC方向的剖面图；
图8是本公开的一些实施例提供的TFT阵列基板的制造方法的流程图；
图9是本公开的一些实施例提供的TFT阵列基板的维修方法的流程图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
在对本公开的一些实施例进行介绍和说明之前，首先对现有的TFT阵列基板及其维修方法做简单介绍。请参考图1，其示出了一种现有的TFT阵列基板的结构示意图。图1仅是TFT阵列基板的一部分，本领域技术人员可以理解TFT阵列基板包括多个图1所示的部分，此处仅以此部分为例进行说明。
如图1所示，该TFT阵列基板包括：基板(图中未示出)；形成在基板之上的栅线1、公共电极线2和数据线3；以及，形成于栅线1和数据线3交叉形成的像素单元区域中的像素电极4。栅线1包括有栅极11，数据线3包括有源极31和漏极32。栅极11、源极31和漏极32构成薄膜晶体管。
包含有TFT阵列基板的显示面板分为常白模式和常黑模式两种不同类型。针对TFT开关损坏的问题，在采用像素暗点化的方式对像素亮点进行维修时，对于常白模式的显示面板，需要将像素电极与栅线进行焊接，而对于常黑模式的显示面板，需要将像素电极与公共电极线进行焊接。如图1所示，以将像素电极与栅线进行焊接为例，可采用激光焊接方式在焊接点位5处进行焊接，栅线1的金属成分会熔化连接到像素电极4上，使得像素电极4与栅线1电性连接。由于像素电极是由ITO材料制成的，ITO材料质脆，在将金属与ITO焊接时容易产生ITO崩裂。
请参考图2，其示出了本公开的一些实施例提供的一种TFT阵列基板的结构示意图。图2仅是TFT阵列基板的一部分，本领域技术人员可以理解TFT阵列基板包括多个图2所示的部分，此处仅以此部分为例进行说明。
如图2所示，该TFT阵列基板包括：基板(图中未示出)；形成在基板之上的栅线11、公共电极线12和数据线13；以及，形成于栅线11和数据线13交叉形成的像素单元区域中的像素电极14。栅线11包括有栅极111，数据线 13包括有源极131和漏极132。栅极111、源极131和漏极132构成薄膜晶体管。
该TFT阵列基板可以是底栅结构，也可以是顶栅结构。
对于底栅结构的TFT阵列基板，基板之上形成有多条横向的栅线11。栅线11之上形成有第一绝缘层，该第一绝缘层包括栅绝缘层和有源层。第一绝缘层之上形成有多条纵向的数据线13。数据线13之上形成有第二绝缘层。第二绝缘层之上形成有透明电极层，该透明电极层中形成有像素电极14，像素电极14位于栅线11和数据线13交叉形成的像素单元区域中。另外，公共电极线12可以与栅线11位于同一层中。或者，公共电极线12也可以位于栅线11与透明电极层之间。比如，公共电极线12可位于栅线11和数据线13之间，也可与数据线13位于同一层，还可位于数据线13和透明电极层之间。
对于顶栅结构的TFT阵列基板，基板之上形成有透明电极层，该透明电极层中形成有像素电极14。透明电极层之上形成有第二绝缘层。第二绝缘层之上形成有多条纵向的数据线13。数据线13之上形成有第一绝缘层，该第一绝缘层包括栅绝缘层和有源层。第一绝缘层之上形成有多条横向的栅线11。像素电极14位于栅线11和数据线13交叉形成的像素单元区域中。另外，公共电极线12位于数据线13的上层。比如，公共电极线12可以位于数据线13和栅线11之间，也可与栅线11位于同一层，还可位于栅线11的上层。
需要说明的一点是，在图2中，仅以底栅结构的TFT阵列基板为例进行举例说明，并不用于限定本公开。
如图2所示，该TFT阵列基板还包括：与像素电极14电性连接的焊接金属15。焊接金属15在基板上的投影区域与目标走线在基板上的投影区域之间形成有交叠区域，该目标走线是指栅线11或者公共电极线12。在图2所示的TFT阵列基板中，以焊接金属15在第一金属层上的投影区域与栅线11之间形成有交叠区域为例。
由于像素电极14与焊接金属15之间已经形成有电性连接，因此在采用像素暗点化的方式对像素亮点进行维修时，对于常白模式的显示面板，仅需保证将焊接金属15与栅线11进行焊接即可，而对于常黑模式的显示面板，仅需保证将焊接金属15与公共电极线12进行焊接即可。如图2所示，以将焊接金属15与栅线11进行焊接为例，可采用激光焊接方式在交叠区域的焊接点位10处进行焊接，焊接金属15和栅线11的金属成分会熔化连接，使得焊接金属15与栅线11电性连接。相比于现有技术将金属与ITO焊接，本实施例提供的TFT 阵列基板在进行维修时将金属与金属焊接，可有效减少ITO崩裂发生。
不论是底栅结构的TFT阵列基板还是顶栅结构的TFT阵列基板。焊接金属15可位于像素电极14的上层，也可与像素电极14位于同一层，还可位于像素电极14的下层，本公开的一些实施例对此不作限定。在一种可能的实施方式中，栅线11和公共电极线12位于同一层中，焊接金属15与数据线13位于同一层中，可有利于减小TFT阵列基板的厚度，同时便于焊接金属15的形成。
另外，焊接金属15不宜过小也不宜过大，焊接金属15过小会影响焊接，而焊接金属15过大又会影响TFT阵列基板的透光性。因此，在一种可能的实施方式中，焊接金属15的长度为6～18um，宽度为3～5um，厚度为1～3um。可选地，焊接金属15的长度为10um。另外，为了保证有足够的焊接位置，焊接金属15在基板上的投影区域与目标走线在基板上的投影区域之间形成的交叠区域的宽度为2～8um，长度为3～18um。
另外，像素电极14与焊接金属15之间形成电性连接的方式存在如下两种可能的情况。
在第一种可能的连接方式中，像素电极14通过过孔16与焊接金属15电性连接。可选地，结合参考图2和图3，图3是图2所示的TFT阵列基板沿AA方向的剖面图。基板17上形成有第一金属层，该第一金属层中形成有栅线11。第一金属层之上形成有第一绝缘层18。第一绝缘层18之上形成有第二金属层，该第二金属层中形成有数据线12和焊接金属15。第二金属层之上形成有第二绝缘层19，在该第二绝缘层19对应焊接金属15的位置处形成有过孔16。第二绝缘层19之上形成有透明电极层，该透明电极层中形成有像素电极14。像素电极14通过过孔16与焊接金属15电性连接。
可选地，过孔16可以是圆孔，也可以是方孔，或者是其它形状。为了确保像素电极14与焊接金属15之间的电性连接的稳定性，同时又不影响到像素电极14的性能，过孔16不宜过小也不宜过大。例如，当过孔16为圆孔时，该圆孔的直径为6～15um，可选地，该圆孔的直径为8um；再例如，当过孔16为方孔时，该方孔的边长为6～15um，可选地，该方孔的边长为8um。
在第二种可能的连接方式中，像素电极14与焊接金属15直接搭接。例如，焊接金属15可直接搭接在像素电极14的边缘上层，也可直接搭接在像素电极14的边缘下层，还可与像素电极14位于同一层且与像素电极14的边缘形成搭接。
另外，由于焊接金属15在基板上的投影区域与目标走线在基板上的投影 区域之间需要形成交叠区域，以便于在维修时对该交叠区域进行焊接。因此，当目标走线的宽度较小，不便于形成上述交叠区域时，目标走线包括呈条状的走线本体以及与走线本体电性连接的焊接部。焊接金属15在基板上的投影区域与焊接部在基板上的投影区域之间形成有交叠区域。结合参考图4和图5，图4是本公开的一些实施例提供的另一TFT阵列基板的结构示意图，图5是图4所示的TFT阵列基板沿BB方向的剖面图。以焊接金属15在基板上的投影区域与栅线11在基板上的投影区域之间形成有交叠区域为例，栅线11包括呈条状的栅线本体11a以及与栅线本体11a电性连接的焊接部11b，焊接金属15在基板上的投影区域与焊接部11b在基板上的投影区域之间形成有交叠区域。
在一种可能的实施方式中，焊接部的大小可以与焊接金属15的大小类似，焊接部的长度为6～18um，宽度为3～5um。
可选地，为了保证在维修时，对交叠区域的焊接不会影响到像素电极14与焊接金属15之间已经形成的电性连接。交叠区域全部或部分位于连接投影区域之外，该连接投影区域是指像素电极14与焊接金属15形成电性连接的连接区域在基板上的投影区域。例如，当像素电极14通过过孔16与焊接金属15电性连接时，交叠区域全部或部分位于过孔16在基板上的投影区域之外。在维修时，将焊接点位10定在交叠区域中位于连接投影区域之外的区域。如图2至图5所示，焊接点位10在过孔16旁边，而不与过孔16交叠，避免在焊接时破坏掉像素电极14与焊接金属15之间已经形成的电性连接。
进一步地，结合参考图6和图7，图6是本公开的一些实施例提供的再一TFT阵列基板的结构示意图，图7是图6所示的TFT阵列基板沿CC方向的剖面图。焊接金属15在基板上的投影区域与目标走线在基板上的投影区域之间形成有交叠区域，该交叠区域全部或部分位于像素电极14在基板上的投影区域之外。如图6和图7所示，以焊接金属15在基板上的投影区域与栅线11在基板上的投影区域之间形成有交叠区域为例，该交叠区域全部位于像素电极14在基板上的投影区域之外。在维修时，将焊接点位10定在交叠区域中位于像素电极14在基板上的投影区域之外的区域。如图6和图7所示，焊接点位10在像素电极14旁边，而不与像素电极14交叠。相比于图2和图4所示的TFT阵列基板，图6所示的TFT阵列基板由于在维修焊接时不会触及到像素电极14，故可完全避免在焊接时发生ITO崩裂。
综上所述，本公开的一些实施例提供的TFT阵列基板，通过形成与像素电极电性连接的焊接金属，且该焊接金属在基板上的投影区域与目标走线在基板 上的投影区域之间形成有交叠区域。这样，在采用像素暗点化的方式对像素亮点进行维修时，通过对上述交叠区域进行焊接，使得焊接金属与目标走线之间形成电性连接。解决了现有技术直接将像素电极与栅线或者公共电极线进行焊接时容易产生ITO崩裂，导致焊接成功率低，维修失败的概率大的问题。实现了将金属与ITO之间的焊接转化为金属与金属之间的焊接，有效减少ITO崩裂发生，提高了焊接成功率，进而提高了TFT阵列基板的维修成功率。
另外，还通过将栅线和公共电极线形成于同一层中，将焊接金属与数据线形成于同一层中，有利于减小TFT阵列基板的厚度，同时便于焊接金属的形成，确保TFT阵列基板的生产效率。
另外，当交叠区域全部或部分位于连接投影区域之外时，在维修时，将焊接点位定在交叠区域中位于连接投影区域之外的区域，避免在焊接时破坏掉像素电极与焊接金属之间已经形成的电性连接，保证维修成功率。
另外，当交叠区域全部或部分位于像素电极在基板上的投影区域之外时，在维修时，将焊接点位定在交叠区域中位于像素电极在基板上的投影区域之外的区域，确保在维修焊接时不会触及到像素电极，从而完全避免在焊接时发生ITO崩裂，进一步减小维修失败风险。
本公开的一些实施例还提供了一种显示面板，该显示面板包括上述实施例提供的TFT阵列基板。在一种可能的实施方式中，显示面板包括：彩膜基板、TFT阵列基板以及位于彩膜基板和TFT阵列基板之间的液晶层。其中，TFT阵列基板可以是上述实施例提供的图2、图4或图6任一所示的TFT阵列基板。
可选地，显示面板可以是常白模式的产品，或者也可以是常黑模式的产品。对于常白模式的显示面板，焊接金属在基板上的投影区域与栅线在基板上的投影区域之间形成有交叠区域。对于常黑模式的显示面板，焊接金属在基板上的投影区域与公共电极线在基板上的投影区域之间形成有交叠区域。
下述为本公开的方法实施例，在方法实施例中未进行详细描述的细节具体参见上述TFT阵列基板的实施例。
本公开的一些实施例还提供了一种TFT阵列基板的制造方法，该制造方法可以包括如下步骤：
在基板上形成栅线、公共电极线、数据线、像素电极以及与像素电极电性连接的焊接金属。
其中，像素电极位于栅线和数据线交叉形成的像素单元区域中。焊接金属在基板上的投影区域与目标走线在基板上的投影区域之间形成有交叠区域。该 目标走线是指栅线或者公共电极线。
综上所述，本公开的一些实施例提供的TFT阵列基板的制造方法，通过形成与像素电极电性连接的焊接金属，且该焊接金属在基板上的投影区域与目标走线在基板上的投影区域之间形成有交叠区域。这样，在采用像素暗点化的方式对像素亮点进行维修时，通过对上述交叠区域进行焊接，使得焊接金属与目标走线之间形成电性连接。解决了现有技术直接将像素电极与栅线或者公共电极线进行焊接时容易产生ITO崩裂，导致焊接成功率低，维修失败的概率大的问题。实现了将金属与ITO之间的焊接转化为金属与金属之间的焊接，有效减少ITO崩裂发生，提高了焊接成功率，进而提高了TFT阵列基板的维修成功率。
请参考图8，其示出了本公开的一些实施例提供的TFT阵列基板的制造方法的流程图。在本实施例中，以制造底栅结构的TFT阵列基板为例。该制造方法可以包括如下几个步骤：
步骤801，在基板上形成第一金属层，通过构图工艺处理得到栅线和公共电极线。
具体来讲，可使用磁控溅射方法，在基板上形成第一金属层。该第一金属层通常可采用钼、铝、铝镍合金、钼钨合金、铬或铜等金属，也可采用上述多种金属形成的薄膜组合结构。之后，在第一金属层上涂覆光刻胶，用掩膜版通过曝光、显影、刻蚀、剥离等构图工艺处理，在基板上形成多条横向的栅线以及多条公共电极线。栅线包括有栅极。
步骤802，在第一金属层之上形成第一绝缘层。
具体来讲，第一绝缘层包括形成于第一金属层之上的栅绝缘层，以及形成于栅绝缘层之上的有源层。栅绝缘层的材料通常是氮化硅，也可以使用氧化硅和氮氧化硅等。有源层的材料通常是非晶硅。可采用化学汽相沉积法在第一金属层上连续沉积形成栅绝缘层和有源层。
步骤803，在第一绝缘层之上形成第二金属层，通过构图工艺处理得到数据线和焊接金属。
在本公开的一些实施例中，焊接金属形成于第二金属层中。也即，焊接金属与数据线位于同一层中。另外，焊接金属在基板上的投影区域与目标走线在基板上的投影区域之间形成有交叠区域，该目标走线是指栅线或者公共电极线。制造数据线和焊接金属的方法与步骤801中制造栅线和公共电极线的方法相类似，此处不再赘述。数据线包括有源极和漏极。
可选地，焊接金属的长度为6～18um，宽度为3～5um，厚度为1～3um。
步骤804，在第二金属层之上形成第二绝缘层。
具体来讲，可采用化学汽相沉积法在第二金属层上沉积形成第二绝缘层，该第二绝缘层的材料通常是氮化硅或二氧化硅。
步骤805，在第二绝缘层对应焊接金属的位置处形成过孔。
可选地，过孔可以是圆孔，也可以是方孔，或者是其它形状。可选地，当过孔为圆孔时，该圆孔的直径为6～15um；当过孔为方孔时，该方孔的边长为6～15um。
另外，在第二绝缘层对应漏极的位置处还形成有第二过孔。
步骤806，在第二绝缘层之上形成透明电极层，通过构图工艺处理得到与焊接金属通过过孔电性连接的像素电极。
具体来讲，可采用化学汽相沉积法在第二绝缘层上沉积形成透明电极层，使用掩膜版，通过构图工艺处理，最终形成位于栅线和数据线交叉形成的像素单元区域中的像素电极。像素电极通常采用ITO材料制成。当然，本公开的一些实施例对其它材料并不限定，如IZO(Indium Zinc Oxide，氧化铟锌)。
像素电极通过过孔与焊接金属电性连接。另外，像素电极还通过第二过孔与漏极电性连接。
需要说明的一点是，在本实施例中，仅以栅线和公共电极线位于同一层中，且焊接金属与数据线位于同一层中进行举例说明，这样有利于减小TFT阵列基板的厚度，同时便于焊接金属的形成，确保TFT阵列基板的生产效率。在其它可能的实施例中，公共电极线也可以位于栅线上层，且位于透明电极层下层。比如，公共电极线可位于栅线和数据线之间，也可与数据线位于同一层，还可位于数据线和透明电极层之间。焊接金属可位于像素电极的上层，也可与像素电极位于同一层，还可位于像素电极的下层。另外，在本公开的一些实施例中，仅以像素电极通过过孔与焊接金属电性连接进行举例说明，在其它可能的实施例中，像素电极与焊接金属也可直接搭接。
还需要说明的一点是，在本公开的一些实施例中，仅对各个不同层的制造顺序进行介绍和说明。对于在制造过程中所形成的焊接金属的位置，焊接金属在基板上的投影区域与目标走线在基板上的投影区域之间形成的交叠区域的位置，以及像素电极与焊接金属形成电性连接的连接区域的位置等，参见上述TFT阵列基板的实施例中的介绍和说明。
还需要说明的一点是，在本公开的一些实施例中，仅以底栅结构的TFT阵列基板的制造方法为例进行举例说明，顶栅结构的TFT阵列基板的制造可采用 类似相反的工艺流程，此部分内容是本领域技术人员在本实施例公开的内容的基础上易于思及的内容，本公开对此不做介绍和说明。
请参考图9，其示出了本公开的一些实施例提供的TFT阵列基板的维修方法的流程图。该维修方法可用于维修如上述实施例提供的图2、图4或图6任一所示的TFT阵列基板。该维修方法可以包括如下几个步骤：
步骤901，对数据线中形成的漏极进行切割，断开漏极与像素电极之间的电性连接。
步骤902，对交叠区域进行焊接，使得焊接金属与目标走线之间形成电性连接。
针对TFT开关损坏的问题，采用像素暗点化的方式对像素亮点进行维修，以提高产品良率。首先，可采用激光切割技术对漏极进行切割，断开漏极与像素电极之间的电性连接。然后，由于本公开的一些实施例提供的TFT阵列基板在制造时已使得像素电极与焊接金属之间形成有电性连接，因此仅需采用激光焊接技术对交叠区域中的焊接点位进行焊接，使得焊接金属与目标走线之间形成电性连接即可。
可选地，结合参考图2和图4所示的TFT阵列基板，当交叠区域全部或部分位于连接投影区域之外时，对交叠区域中位于连接投影区域之外的区域进行焊接，也即将焊接点位定在交叠区域中位于连接投影区域之外的区域。其中，连接投影区域是指像素电极与焊接金属形成电性连接的连接区域在基板上形成的投影区域。这样，可以避免在焊接时破坏掉像素电极与焊接金属之间已经形成的电性连接，保证维修成功率。
可选地，结合参考图6所示的TFT阵列基板，当交叠区域全部或部分位于像素电极在基板上的投影区域之外时，对交叠区域中位于像素电极在基板上的投影区域之外的区域进行焊接，也即将焊接点位定在交叠区域中位于像素电极在基板上的投影区域之外的区域。这样，可以确保在维修焊接时不会触及到像素电极，从而完全避免在焊接时发生ITO崩裂，进一步减小维修失败风险。
综上所述，本公开的一些实施例提供的TFT阵列基板的维修方法，通过对焊接金属与目标走线之间形成的交叠区域进行焊接，使得焊接金属与目标走线之间形成电性连接。解决了现有技术直接将像素电极与栅线或者公共电极线进行焊接时容易产生ITO崩裂，导致焊接成功率低，维修失败的概率大的问题。实现了将金属与ITO之间的焊接转化为金属与金属之间的焊接，有效减少ITO崩裂发生，提高了焊接成功率，进而提高了TFT阵列基板的维修成功率。
上述本公开的一些实施例序号仅仅为了描述，不代表实施例的优劣。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本公开的较佳实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (19)

  1. 一种薄膜晶体管(TFT)阵列基板，包括：
    基板；形成在所述基板之上的栅线、公共电极线和数据线；以及，形成于所述栅线和所述数据线交叉形成的像素单元区域中的像素电极；
    其中，所述TFT阵列基板还包括：与所述像素电极电性连接的焊接金属；
    所述焊接金属在所述基板上的投影区域与目标走线在所述基板上的投影区域之间形成有交叠区域，所述目标走线是指所述栅线或者所述公共电极线。
  2. 根据权利要求1所述的TFT阵列基板，其中，所述像素电极通过过孔与所述焊接金属电性连接。
  3. 根据权利要求2所述的TFT阵列基板，其中，
    所述过孔为圆孔，且所述圆孔的直径为6～15um；
    或者，
    所述过孔为方孔，且所述方孔的边长为6～15um。
  4. 根据权利要求1所述的TFT阵列基板，其中，所述像素电极与所述焊接金属直接搭接。
  5. 根据权利要求1所述的TFT阵列基板，其中，所述焊接金属与所述数据线位于同一层中。
  6. 根据权利要求1所述的TFT阵列基板，其中，所述目标走线包括：呈条状的走线本体以及与所述走线本体电性连接的焊接部；
    所述焊接金属在所述基板上的投影区域与所述焊接部在所述基板上的投影区域之间形成有所述交叠区域。
  7. 根据权利要求6所述的TFT阵列基板，其中，所述焊接部的长度为6～18um，宽度为3～5um。
  8. 根据权利要求1至7任一所述的TFT阵列基板，其中，
    所述交叠区域全部或部分位于连接投影区域之外；
    其中，所述连接投影区域是指所述像素电极与所述焊接金属形成所述电性连接的连接区域在所述基板上的投影区域。
  9. 根据权利要求1至7任一所述的TFT阵列基板，其中，所述交叠区域全部或部分位于所述像素电极在所述基板上的投影区域之外。
  10. 根据权利要求1至7任一所述的TFT阵列基板，其中，所述焊接金属的长度为6～18um，宽度为3～5um，厚度为1～3um。
  11. 根据权利要求1至7任一所述的TFT阵列基板，其中，所述交叠区域的宽度为2～8um，长度为3～18um。
  12. 一种显示面板，包括如权利要求1至11任一所述的TFT阵列基板。
  13. 一种薄膜晶体管(TFT)阵列基板的制造方法，包括：
    在基板上形成栅线、公共电极线、数据线、像素电极以及与所述像素电极电性连接的焊接金属；
    其中，所述像素电极位于所述栅线和所述数据线交叉形成的像素单元区域中，所述焊接金属在所述基板上的投影区域与目标走线在所述基板上的投影区域之间形成有交叠区域，所述目标走线是指所述栅线或者所述公共电极线。
  14. 一种如权利要求1至11任一项所述的TFT阵列基板的维修方法，包括：
    对所述数据线中形成的漏极进行切割，断开所述漏极与所述像素电极之间的电性连接；
    对所述交叠区域进行焊接，使得所述焊接金属与所述目标走线之间形成电性连接。
  15. 根据权利要求14所述的方法，其中，所述对所述交叠区域进行焊接，包括：
    对所述交叠区域中位于连接投影区域之外的区域进行焊接；
    其中，所述连接投影区域是指所述像素电极与所述焊接金属形成所述电性连接的连接区域在所述基板上的投影区域。
  16. 根据权利要求14所述的方法，其中，所述对所述交叠区域进行焊接，包括：
    对所述交叠区域中位于所述像素电极在所述基板上的投影区域之外的区域进行焊接。
  17. 根据权利要求1所述的TFT阵列基板，其中，所述栅线和所述公共电极线形成于同一层。
  18. 根据权利要求8所述的TFT阵列基板，其中，所述交叠区域的焊接点位位于所述交叠区域中位于所述连接投影区域之外的区域。
  19. 根据权利要求9所述的TFT阵列基板，其中，所述交叠区域的焊接点位位于所述交叠区域中位于所述像素电极在所述基板上的投影区域之外的区域。
PCT/CN2016/071613 2015-07-22 2016-01-21 Tft阵列基板及其制造方法及维修方法、显示面板 Ceased WO2017012320A1 (zh)

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