WO2017012174A1 - 一种平板显示器中的面板结构及制作方法 - Google Patents

一种平板显示器中的面板结构及制作方法 Download PDF

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Publication number
WO2017012174A1
WO2017012174A1 PCT/CN2015/088365 CN2015088365W WO2017012174A1 WO 2017012174 A1 WO2017012174 A1 WO 2017012174A1 CN 2015088365 W CN2015088365 W CN 2015088365W WO 2017012174 A1 WO2017012174 A1 WO 2017012174A1
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signal line
panel structure
nanometers
angle
layer
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PCT/CN2015/088365
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English (en)
French (fr)
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徐洪远
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深圳市华星光电技术有限公司
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Priority to US14/905,862 priority Critical patent/US9799681B2/en
Publication of WO2017012174A1 publication Critical patent/WO2017012174A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a panel structure and a manufacturing method thereof in a flat panel display.
  • LCDs Liquid Crystal displays
  • LCDs are mainly composed of an array plate, a color filter (CF) plate, and a liquid crystal layer sandwiched therebetween.
  • the RGB color resistance on the CF board in the LCDs is directly applied to the position between the pixel electrode of the transparent conductive film of the array board and the second metal layer to increase the pixel. The distance between the electrode and the signal line, thereby reducing the parasitic capacitance between the pixel electrode and the signal line, thereby reducing the signal delay of the entire panel to improve the display quality of the panel.
  • the above method can reduce the parasitic capacitance between the pixel electrode and the signal line, the signal line overlaps the scan line due to the small distance, so there is still a large parasitic capacitance, resulting in signals on the signal line and the scan line.
  • the delay causes the signal at the end of the trace to be distorted, which affects the display quality of the panel.
  • Embodiments of the present invention provide a panel structure and a manufacturing method in a flat panel display, which can further improve a panel structure in a flat panel display.
  • the embodiment of the invention discloses a panel structure and a manufacturing method thereof in a flat panel display, comprising: a first signal line, a second signal line, a transparent conductive film and a scanning line, wherein the transparent conductive film is composed of a first edge and a first edge a second side and a third side, wherein the first end of the first side is connected to the first end of the second side at a predetermined first angle, and the second end of the second side is The first end of the third side is connected at a predetermined second angle, and the first side, the second side and the third side form an arch frame, the first signal line and the first a second end of the first leg is connected, the second signal line is connected to a second end of the third leg, the scan line passes through the first direction of the arch frame, and is not associated with the arch The fractal frames intersect.
  • the panel structure further includes: a gate insulating layer, wherein the gate insulating layer is deposited on a predetermined substrate including the scan line.
  • the panel structure further includes a passivation layer, wherein the passivation layer is deposited on the gate insulating layer.
  • the panel structure further includes: a color resist layer, wherein the color resist layer is deposited on the passivation layer.
  • the color resist layer has a thickness ranging from 1 micron to 1.5 microns.
  • the passivation layer has a thickness of 300+n nanometers or 300-n nanometers, wherein the n is a real number greater than 0 and less than 50.
  • the gate insulating layer has a thickness of 500+n nanometers or 500-n nanometers, wherein the n is a real number greater than 0 and less than 50.
  • the preset first angle ranges from 30 degrees to 60 degrees and the predetermined second angle ranges from 30 degrees to 60 degrees.
  • the panel structure includes: a first signal line, a second signal line, a transparent conductive film, and a scan line, wherein the transparent conductive film is composed of a first side, a second side, and a third side, wherein a first end of the first leg and a first end of the second leg are connected at a predetermined first angle, and a second end of the second leg and a first end of the third leg are a preset second angle is connected, and the first side, the second side and the third side form an arch frame, and the first signal line is connected to the second end of the first side,
  • the second signal line is coupled to the second end of the third leg, the scan line passing through the first direction of the arched frame and not intersecting the arcuate frame.
  • the first signal line is connected to the second signal line through an arch frame formed of a transparent conductive film to increase the relationship between the signal line and the scan line.
  • the distance reduces the parasitic capacitance between the signal line and the scan line to improve the display quality of the panel.
  • FIG. 1 is a schematic cross-sectional view showing a panel structure in a flat panel display according to an embodiment of the present invention
  • FIG. 1a is a schematic structural view of an arch frame disclosed in an embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view showing a structure of a panel in another flat panel display according to an embodiment of the present invention
  • Figure 3 is a plan view of the panel structure shown in Figure 2;
  • FIG. 4 is a diagram of a method for fabricating a panel structure in a flat panel display according to an embodiment of the present invention.
  • the embodiment of the invention discloses a panel structure and a manufacturing method in a flat panel display.
  • the first signal line is formed by an arch frame formed of a transparent conductive film at an overlap of the signal line and the scan line.
  • the second signal line is connected to increase the distance between the signal line and the scan line, thereby reducing the parasitic capacitance of the signal line and the scan line at the overlap, thereby improving the display quality of the panel.
  • FIG. 1 is a schematic cross-sectional view showing a panel structure in a flat panel display according to an embodiment of the present invention.
  • the panel structure in the flat panel display includes: a first signal line 11 , a second signal line 12 , a transparent conductive film 2 , and a scan line 3 , wherein the transparent conductive film has a first side 21 and a second side.
  • first leg 22 and a third leg 23 wherein the first end of the first leg 21 and the first end of the second leg 22 are connected at a predetermined first angle, and the second end of the second leg 22 and the third leg 23 The first ends are connected at a predetermined second angle, and the first side 21, the second side 22 and the third side 23 constitute an arched frame, and the first signal line 11 is connected to the second end of the first side 21, The second signal line 12 is connected to the second end of the third leg 23, and the scan line 3 passes through the first direction of the arched frame and does not intersect the arched frame.
  • FIG. 1a is a schematic structural view of an arch frame disclosed in an embodiment of the present invention.
  • the arch frame is composed of a first side 21, a second side 22 and a third side 23 of the transparent conductive film 2.
  • the first leg 21 and the second leg 22 are connected at a predetermined first angle
  • the second leg 22 and the third leg 23 are connected at a predetermined second angle.
  • the arch frame formed by the first side edge 21, the second side edge 22 and the third side edge 23 is a complete whole, that is, as shown in FIG. 1a, the connection between the first side edge 21 and the second side edge 22 is There is no crack, and there is no crack at the junction of the second side 22 and the third side 23.
  • the relationship between the first side 21, the second side 22 and the third side 23 can also be expressed as follows: the second side 22 is regarded as a body, wherein the first side 21 and the third side 23 are the second side
  • the ends of the ends extend at an angle.
  • the preset first angle and the preset second angle have a value ranging from 30 degrees to 60 degrees, and the preset first angle is not necessarily the same as the preset second angle. . Since Fig.
  • FIG. 1a is a cross-sectional view, the angles are not apparent in Fig. 1a, but are matched at a predetermined angle during the actual fabrication process.
  • the first signal line 11 is connected to the second signal line 12 through the arch frame formed of the transparent conductive film 2, thereby increasing the distance between the signal line and the scan line, thereby The parasitic capacitance between the signal line and the scan line is reduced to improve the display quality of the panel.
  • the transparent conductive film 2 is a film which is electrically conductive and has a high transparency in the visible light range, and mainly has a metal film system, an oxide film system, another compound film system, and a polymer film system. , composite film system, etc. Among them, the metal film has good electrical conductivity, but the transparency is poor.
  • the semiconductor film series is just the opposite, with poor conductivity and high transparency. At present, the most widely studied and applied are metal film systems and oxide film systems.
  • Transparent conductive films are mainly used for window materials of photovoltaic devices such as thin film solar cells.
  • a common transparent conductive film is ITO.
  • the main component of ITO is indium tin oxide.
  • the indium oxide has a high transmittance
  • the tin oxide has a high conductivity.
  • the ITO glass used in the flat panel display is positive. It is a conductive glass with high transmittance. Because ITO has a strong water absorption, it absorbs moisture and carbon dioxide in the air and chemically reacts and deteriorates. It is commonly called “mildew", so it should be protected from moisture during storage.
  • the ITO has a suitable shielding performance in the range of 150 kHz to 1 GHz, and the light transmittance is much better than that of the common grid material shielding glass, and the light transmittance can reach more than 85%.
  • the scan line 3 passes primarily through the first direction of the arched frame and does not intersect the arched frame.
  • the first direction may be below the arch frame.
  • the first direction may be different. Therefore, the determination of the first direction is determined by the actual image. .
  • the first signal line 11 is connected to the second signal line 12 through the arch frame formed of the transparent conductive film 2 at the overlap of the signal line and the scanning line, it can be increased in a certain range. The distance between the signal line and the scan line, thereby reducing the parasitic capacitance of the signal line and the scan line at the overlap, so as to improve the display quality of the panel.
  • the arch frame may be a U-shaped frame having a sharp edge or a U-shaped frame having a circular arc.
  • the panel structure mainly includes: a first signal line 11 , a second signal line 12 , a transparent conductive film 2 , and a scan line 3 , wherein the transparent conductive film has a first side 21 , a second side 22 , and a third side 23, wherein the first end of the first leg 21 and the first end of the second leg 22 are connected at a predetermined first angle, and the second end of the second leg 22 and the first end of the third leg 23 are The preset second angles are connected, and the first side 21, the second side 22 and the third side 23 constitute an arch frame, and the first signal line 11 is connected to the second end of the first leg 21, and the second signal line 12 is connected.
  • the scan line 3 passes through the first direction of the arched frame and does not intersect the arched frame.
  • the first signal line 11 and the second signal line 12 are connected by an arch frame formed of a transparent conductive film to increase the signal line and the scan line. The distance between them reduces the parasitic capacitance of the signal line and the scan line at the overlap to improve the display quality of the panel.
  • FIG. 2 is a schematic cross-sectional view showing a panel structure in another flat panel display according to an embodiment of the present invention. 2 is further refined on the basis of FIG. 1 , and may include gate insulation in addition to the first signal line 11 , the second signal line 12 , the transparent conductive film 2 , and the scan line 3 illustrated in FIG. 1 . a layer 4, a passivation layer 5, and a color resist layer 6, wherein
  • the gate insulating layer 4 is deposited on a predetermined substrate including the scan lines 3, the passivation layer 5 is deposited on the gate insulating layer 4, and the color resist layer 6 is deposited on the passivation layer 5; and the thickness of the color resist layer 6 is taken
  • the range is from 1 micrometer to 1.5 micrometers, and the thickness of the passivation layer 5 is 300+n nanometers or 300-n nanometers, wherein n is a real number greater than 0 and less than 50, and the thickness of the gate insulating layer 4 is 500+n nanometers or 500-n nanometers, where n is a real number greater than zero and less than 50.
  • the color resist layer 6 mainly includes three primary colors (Red Green Blue, RGB) color resistance.
  • the passivation layer 5 refers to depositing or growing a specific dielectric film on the surface of the silicon wafer or the semiconductor device chip to prevent the surface from being contaminated by the environment and possible damage to the surface of the silicon wafer by subsequent operations.
  • the passivation layer 5 has a thickness of 300+n nanometers or 300-n nanometers, wherein n is a real number greater than 0 and less than 50.
  • the properties of the semiconductor surface layer are sensitive to the nature of the environment or the medium in contact with the semiconductor surface.
  • the passivation film which is in direct contact with the silicon wafer is generally referred to as a primary passivation film.
  • a passivation film is sometimes applied once before the chip package, which is called a secondary passivation film.
  • Polyimide can also be used for secondary passivation.
  • the gate insulating layer 4 is mainly an insulating layer, and the thickness thereof ranges from 500+n nanometers to 500-n nanometers. Where n is a real number greater than 0 and less than 50.
  • the transparent conductive film 2 is an arched frame composed of the first leg 21, the second leg 22 and the third leg 23, and the first end and the second side of the first leg 21
  • the first end of the second side 22 is connected to the first end of the third side edge 23 at a predetermined second angle value.
  • the preset first angle value ranges from 30 degrees to 60 degrees; and the preset second angle ranges from 30 degrees to 60 degrees.
  • the gate insulating layer 4 is deposited on a predetermined substrate including the scanning lines 3, the passivation layer 5 is deposited on the gate insulating layer 4, and the color resist layer 6 is deposited in passivation. On layer 5.
  • the thickness of the color resist layer 6 ranges from 1 micrometer to 1.5 micrometers, and the thickness of the passivation layer 5 is 300+n nanometers or 300-n nanometers, wherein n is a real number greater than 0 and less than 50, and a gate insulating layer
  • the thickness of 4 is 500+n nanometers or 500-n nanometers, where n is a real number greater than 0 and less than 50.
  • the thickness of the color resist layer 6, the passivation layer 5, and the gate insulating layer 4 are all selected to an optimum range, thereby forming a good isolation layer to improve the display quality of the panel. .
  • FIG. 3 is a top view of the panel structure shown in FIG. 2 , therefore, the first signal line 11 , the second signal line 12 , the transparent conductive film 2 , the scan line 3 , and the gate insulation included in FIG. 2 .
  • Layer 4, passivation layer 5, and color resist 6 are also included in FIG. Since FIG. 3 is a plan view of the panel structure shown in FIG. 2, the partial color resist layer 6, the passivation layer 5, and the gate insulating layer 4 are not shown in the drawings.
  • the signal line does not directly cross the scan line, but the first signal line is connected to the second signal line through an arch frame composed of a transparent conductive film.
  • the transparent conductive film 2 is an arched frame composed of a first side, a second side and a third side, the distance between the signal line and the scanning line can be increased by such a bridge method, thereby reducing the signal line and scanning.
  • the parasitic capacitance of the lines at the overlap improves the display quality of the panel.
  • FIG. 4 is a diagram of a method for fabricating a panel structure in a flat panel display according to an embodiment of the present invention. As shown in FIG. 4, the method for fabricating the panel structure in the flat panel display may include the following steps:
  • step S102 depositing a gate insulating layer on the substrate completing step S101, and photolithing the first signal line and the second signal line on the substrate;
  • step S103 depositing a passivation layer on the substrate completing step S102;
  • step S104 depositing a color resist layer on the substrate on which step S103 is completed;
  • step S105 passing through the hole on the substrate of step S104 to obtain a first hole and a second hole;
  • step S106 depositing a transparent conductive film on the substrate on which step S105 is completed.
  • the transparent conductive film is a film which is electrically conductive and has a high transparency in the visible light range, and mainly has a metal film system, an oxide film system, another compound film system, a polymer film system, Composite film system, etc.
  • the metal film has good electrical conductivity, but the transparency is poor.
  • the semiconductor film series is just the opposite, with poor conductivity and high transparency.
  • Transparent conductive films are mainly used for window materials of photovoltaic devices such as thin film solar cells.
  • a common transparent conductive film is ITO.
  • the main component of ITO is indium tin oxide.
  • the indium oxide has a high transmittance
  • the tin oxide has a high conductivity.
  • the ITO glass used in the flat panel display is positive. It is a conductive glass with high transmittance. Because ITO has a strong water absorption, it absorbs moisture and carbon dioxide in the air and chemically reacts and deteriorates. It is commonly called “mildew", so it should be protected from moisture during storage. And ITO has suitable shielding effectiveness in the range of 150KHz ⁇ 1GHz, The light transmittance is much better than that of ordinary grid material shielding glass, and the light transmittance can reach more than 85%.
  • the thickness of the gate insulating layer should be larger than the thickness of the scan line, that is, the gate insulating layer should completely cover the scan line; the thickness of the passivation layer should be larger than the thickness of the signal line, that is, The passivation layer should cover the signal line; the thickness of the color resist layer should match the length of the first side and the second side of the transparent conductive film.
  • a gate insulating layer is deposited on the predetermined substrate including the scan lines, a passivation layer is deposited on the gate insulating layer, and a color resist layer is deposited on the passivation layer; and the thickness of the color resist layer ranges from 1 micrometer to 1.5 micrometers.
  • the thickness of the passivation layer is 300+n nanometers or 300-n nanometers, wherein n is a real number greater than 0 and less than 50, and the thickness of the gate insulating layer is 500+n nanometers or 500-n nanometers, wherein n is Real numbers greater than 0 and less than 50.
  • the color resist layer mainly comprises three primary colors (Red Green Blue, RGB) color resistance.
  • the passivation layer refers to depositing or growing a specific dielectric film on the surface of the silicon wafer or the semiconductor device chip to prevent the surface from being contaminated by the environment and possible damage to the surface of the silicon wafer by subsequent operations.
  • the passivation layer has a thickness of 300+n nanometers or 300-n nanometers, wherein n is a real number greater than 0 and less than 50.
  • the properties of the semiconductor surface layer are sensitive to the nature of the environment or the medium in contact with the semiconductor surface. Surface contamination ions, interface state charges, movable charges in the dielectric layer, and fixed charges all affect the surface potential of the semiconductor, causing the carrier to accumulate, deplete, or invert the surface layer and cause the metal.
  • the passivation film used earlier is thermally grown silicon dioxide, but the silicon dioxide film cannot block the diffusion of alkali metal ions such as sodium. More commonly used in production are silica-phosphorus silica composite membranes, silica-silicon nitride composite membranes, silica-alumina composite membranes or polyimide membranes.
  • the passivation film which is in direct contact with the silicon wafer is generally referred to as a primary passivation film.
  • a passivation film is sometimes applied once before the chip package, which is called a secondary passivation film. Polyimide can also be used for secondary passivation.
  • the gate insulating layer is mainly a layer of isolation layer, and the thickness thereof ranges from 500+n nanometers or 500-n nanometers. Where n is a real number greater than 0 and less than 50.
  • the first signal line is connected to the second signal line through an arch frame formed of a transparent conductive film, thereby increasing the signal line and the scan line in a certain range. Distance, thereby reducing the parasitic capacitance of the signal line and the scan line at the overlap, thereby improving the panel display Show quality.

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Abstract

提供一种平板显示器中的面板结构及制作方法，该面板结构包括：第一信号线（11）、第二信号线（12）、透明导电薄膜（2）以及扫描线（3），其中，透明导电薄膜（2）由第一支边（21）、第二支边（22）以及第三支边（23）组成，第一支边（21）的第一端与第二支边（22）的第一端以预先设定的第一角度相连，第二支边（22）的第二端与第三支边（23）的第一端以预先设定的第二角度相连，且第一支边（21）、第二支边（22）以及第三支边（23）构成拱形框架，第一信号线（11）与第一支边（21）的第二端相连，第二信号线（12）与第三支边（23）的第二端相连，扫描线（3）从拱形框架的第一方向穿过，且不与拱形框架相交。本发明可以降低信号线与扫描线在重叠处的寄生电容，以提高面板显示品质。

Description

一种平板显示器中的面板结构及制作方法
本申请要求于2015年7月21日提交中国专利局、申请号为201510432536.5、发明名称为“一种平板显示器中的面板结构及制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种平板显示器中的面板结构及制作方法。
背景技术
LCDs(Liquid crystal displays)是一种被广泛应用的平板显示器，主要是通过液晶开关调制背光源光场强度来实现画面显示。通常LCDs主要由阵列板、色阻(Color Filter，CF)板以及夹在二者之间的液晶层三部分组成。在实际应用中，为了提高LCDs的显示品质，主要是将LCDs中CF板上的RGB色阻直接涂布在阵列板透明导电薄膜的像素电极和第二层金属层之间的位置，以增加像素电极和信号线之间的距离，从而达到减小像素电极与信号线之间的寄生电容，进而减小整个面板的信号延迟，以提高面板显示品质。然而，上述方法虽然可以减小像素电极与信号线之间的寄生电容，但信号线与扫描线重叠处由于距离较小，所以仍存在较大的寄生电容，导致信号线和扫描线上的信号延迟，造成走线尾端信号变形，从而影响了面板显示品质。
发明内容
本发明实施例提供了一种平板显示器中的面板结构及制作方法，能够进一步完善平板显示器中的面板结构。
本发明实施例公开了一种平板显示器中的面板结构及制作方法，包括：第一信号线、第二信号线、透明导电薄膜以及扫描线，其中，所述透明导电薄膜由第一支边、第二支边以及第三支边组成，其中，所述第一支边的第一端与所述第二支边的第一端以预先设定的第一角度相连，所述第二支边的第二端与所 述第三支边的第一端以预先设定的第二角度相连，且所述第一支边、所述第二支边以及所述第三支边构成拱形框架，所述第一信号线与所述第一支边的第二端相连，所述第二信号线与所述第三支边的第二端相连，所述扫描线从所述拱形框架的第一方向穿过，且不与所述拱形框架相交。
在一个实施例中，所述面板结构还包括：栅绝缘层，其中，所述栅绝缘层沉积在包含所述扫描线的预设基板上。
在一个实施例中，所述面板结构还包括：钝化层，其中，所述钝化层沉积在所述栅绝缘层上。
在一个实施例中，所述面板结构还包括：色阻层，其中，所述色阻层沉积在所述钝化层上。
在一个实施例中，所述色阻层的厚度取值范围为1微米至1.5微米。
在一个实施例中，所述钝化层的厚度为300+n纳米或者300-n纳米，其中，所述n为大于0且小于50的实数。
在一个实施例中，所述栅绝缘层的厚度为500+n纳米或者500-n纳米，其中，所述n为大于0且小于50的实数。
在一个实施例中，所述预先设定的第一角度的取值范围为30度至60度以及所述预先设定的第二角度的取值范围为30度至60度。
本发明实施例中，该面板结构包括：第一信号线、第二信号线、透明导电薄膜以及扫描线，其中，所述透明导电薄膜由第一支边、第二支边以及第三支边组成，其中，所述第一支边的第一端与所述第二支边的第一端以预先设定的第一角度相连，所述第二支边的第二端与所述第三支边的第一端以预先设定的第二角度相连，且所述第一支边、所述第二支边以及所述第三支边构成拱形框架，所述第一信号线与所述第一支边的第二端相连，所述第二信号线与所述第三支边的第二端相连，所述扫描线从所述拱形框架的第一方向穿过，且不与所述拱形框架相交。在本发明实施例中，在信号线与扫描线的重叠处，通过由透明导电薄膜构成的拱形框架将第一信号线与第二信号线相连，以增加了信号线与扫描线之间的距离，从而降低了信号线与扫描线在重叠处的寄生电容，以提高了面板显示品质。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例公开的一种平板显示器中的面板结构截面示意图；
图1a是本发明实施例公开的一种拱形框架的结构示意图；
图2是本发明实施例公开的另一种平板显示器中的面板结构截面示意图；
图3是图2所示的面板结构的俯视图；
图4是本发明实施例提供的一种平板显示器中面板结构的制作方法。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例公开了一种平板显示器中的面板结构及制作方法，在本发明实施例中，在信号线与扫描线的重叠处，通过由透明导电薄膜构成的拱形框架将第一信号线与第二信号线相连，以增加了信号线与扫描线之间的距离，从而降低了信号线与扫描线在重叠处的寄生电容，以提高了面板显示品质。
请参阅图1，图1是本发明实施例公开的一种平板显示器中的面板结构截面示意图。如图1所示，该平板显示器中的面板结构包括：第一信号线11、第二信号线12、透明导电薄膜2以及扫描线3，其中，透明导电薄膜由第一支边21、第二支边22以及第三支边23组成，其中，第一支边21的第一端与第二支边22的第一端以预先设定的第一角度相连，第二支边22的第二端与第三支边23的第一端以预先设定的第二角度相连，且第一支边21、第二支边22以及第三支边23构成拱形框架，第一信号线11与第一支边21的第二端相连，第二信号线12与第三支边23的第二端相连，扫描线3从拱形框架的第一方向穿过，且不与拱形框架相交。
本发明实施例中，主要选取了在信号线与扫描线重叠处的面板结构。其中，如图1所示，在信号线与扫描线的重叠处，将第一信号线11与第二信号线12通过由材质为透明导电薄膜的拱形框架作为中间介质相连。其中，如图1a所示，图1a是本发明实施例公开的一种拱形框架的结构示意图。其中，该拱形框架是由透明导电薄膜2的第一支边21、第二支边22以及第三支边23构成。在本发明实施例中，第一支边21与第二支边22以预先设定的第一角度相连，第二支边22与第三支边23以预先设定的第二角度相连。其中，第一支边21、第二支边22以及第三支边23构成的拱形框架是一个完整的整体，也即如图1a所示的图，第一支边21与第二支边22的连接处并无裂缝，第二支边22与第三支边23的连接处并无裂缝。其中，第一支边21、第二支边22与第三支边23之间的关系也可以表述成如下：将第二支边22视为本体，其中，第一支边21与第三支边23是第二支边的两端的以一定角度的延伸。预先设定的第一角度与预先设定的第二角度的取值范围均为30度至60度，且预先设定的第一角度与预先设定的第二角度的取值不一定严格相同。由于图1a是截面图，因此角度在图1a中显示不明显，但在实际制作过程则以预先设定的角度相匹配。当在信号线与扫描线的重叠处，通过由透明导电薄膜2构成的拱形框架将第一信号线11与第二信号线12相连，以增加了信号线与扫描线之间的距离，从而降低了信号线与扫描线在重叠处的寄生电容，以提高了面板显示品质。
本发明实施例中，透明导电薄膜2是一种既能导电又在可见光范围内具有高透明率的一种薄膜，主要有金属膜系、氧化物膜系、其他化合物膜系、高分子膜系、复合膜系等。其中，金属膜系导电性能好，但是透明率差。半导体薄膜系列刚好相反，导电性差，透明率高。目前，研究和应用最为广泛的是金属膜系和氧化物膜系。透明导电薄膜主要用于光电器件(如薄膜太阳能电池等)的窗口材料。常见的透明导电薄膜为ITO，其中，ITO的主要成份是氧化铟锡，在厚度只有几千埃的情况下，氧化铟透过率高，氧化锡导电能力强，平板显示器中所用的ITO玻璃正是一种具有高透过率的导电玻璃。由于ITO具有很强的吸水性，所以会吸收空气中的水份和二氧化碳并产生化学反应而变质，俗称“霉变”，因此在存放时要防潮。且ITO在150KHz～1GHz范围内有适宜的屏蔽效能，透光性较普通网栅材料屏蔽玻璃好很多，透光率可达到85％以上。
本发明实施例中，扫描线3主要从拱形框架的第一方向穿过，且不与拱形框架相交。如图1所示，该第一方向可以是拱形框架的下方，当将该图以不同的角度看时，第一方向可能不一样，因此，第一方向的确定均以实际图作为确定依据。在本发明实施例中，由于在信号线与扫描线的重叠处，通过由透明导电薄膜2构成的拱形框架将第一信号线11与第二信号线12相连，由此可以在一定范围增加信号线与扫描线的距离，从而降低了信号线与扫描线在重叠处的寄生电容，以提高了面板显示品质。
本发明实施例中，拱形框架可以是具有明显棱角的U型框架，也可以是具有圆弧的U型框架。
在图1中，面板结构主要包括：第一信号线11、第二信号线12、透明导电薄膜2以及扫描线3，其中，透明导电薄膜由第一支边21、第二支边22以及第三支边23组成，其中，第一支边21的第一端与第二支边22的第一端以预先设定的第一角度相连，第二支边22的第二端与第三支边23的第一端以预先设定的第二角度相连，且第一支边21、第二支边22以及第三支边23构成拱形框架，第一信号线11与第一支边21的第二端相连，第二信号线12与第三支边23的第二端相连，扫描线3从拱形框架的第一方向穿过，且不与拱形框架相交。在本发明实施例中，在信号线与扫描线的重叠处，通过由透明导电薄膜构成的拱形框架将第一信号线11与第二信号线12相连，以增加了信号线与扫描线之间的距离，从而降低了信号线与扫描线在重叠处的寄生电容，以提高了面板显示品质。
请参阅图2，图2是本发明实施例公开的另一种平板显示器中的面板结构截面示意图。其中，图2是在图1的基础上进一步细化得到，除包括图1所示的第一信号线11、第二信号线12、透明导电薄膜2以及扫描线3以外，还可以包括栅绝缘层4、钝化层5以及色阻层6，其中，
栅绝缘层4沉积在包含扫描线3的预设基板上，钝化层5沉积在栅绝缘层4上，以及色阻层6沉积在钝化层5上；且色阻层6的厚度取值范围为1微米至1.5微米，钝化层5的厚度为300+n纳米或者300-n纳米，其中，n为大于0且小于50的实数，以及栅绝缘层4的厚度为500+n纳米或者500-n纳米，其中，n为大于0且小于50的实数。
本发明实施例中，色阻层6主要包括三原色(Red Green Blue，RGB)色阻。
本发明实施例中，钝化层5是指在硅片或半导体器件芯片的表面淀积或生长特定的介质膜，以防止表面受环境沾污和以后的操作对硅片表面可能造成的损伤。且在本发明实施例中，钝化层5的厚度为300+n纳米或者300-n纳米，其中，n为大于0且小于50的实数。半导体表面层的性质对于环境或与半导体表面接触的介质的性质是很敏感的。表面沾污离子、界面态电荷、介质层内的可动电荷和固定电荷都会影响半导体的表面电势，从而引起表面层中载流子的积累，耗尽，或者使表面层反型，并引起金属-绝缘体-半导体结构电容-电压特性和半导体器件特性的变化。为了保证半导体器件工作的稳定性和可靠性，必须在半导体器件芯片表面覆盖某些经过选择的介质膜，使表面钝化。较早采用的钝化膜是热生长的二氧化硅，但是二氧化硅膜不能阻挡钠等碱金属离子的扩散。现在生产上更常用的是二氧化硅-磷硅玻璃复合膜、二氧化硅-氮化硅复合膜、二氧化硅-三氧化二铝复合膜或聚酰亚胺膜。上述与硅片直接接触的钝化膜通常称为一次钝化膜，为了改善钝化效果，有时芯片封装前还要再涂敷一次钝化膜，称为二次钝化膜。聚酰亚胺也可用于二次钝化。
本发明实施例中，栅绝缘层4主要是一层隔绝层，且其的厚度的取值范围为500+n纳米或者500-n纳米。其中，n为大于0且小于50的实数。
作为另一种可选的实施方式，由于透明导电薄膜2是由第一支边21、第二支边22以及第三支边23构成的拱形框架，且第一支边21的第一端与第二支边22第一端是以预先设定的第一角度相连，第二支边22的第二端与第三支边23的第一端以预先设定的第二角度值相连。其中预先设定的第一角度值的取值范围为30度至60度；且预先设定的第二角度的取值范围为30度至60度。
在图2中，平板显示器中的面板结构中，栅绝缘层4沉积在包含扫描线3的预设基板上，钝化层5沉积在栅绝缘层4上，以及色阻层6沉积在钝化层5上。且色阻层6的厚度取值范围为1微米至1.5微米，钝化层5的厚度为300+n纳米或者300-n纳米，其中，n为大于0且小于50的实数，以及栅绝缘层4的厚度为500+n纳米或者500-n纳米，其中，n为大于0且小于50的实数。在本发明实施例中，色阻层6、钝化层5以及栅绝缘层4的厚度都是选取了一个最佳的范围，从而构成了隔绝效果较好的隔绝层，以提高了面板显示品质。
请参阅图3，其中，图3是图2所示的面板结构的俯视图，因此，图2中包括的第一信号线11、第二信号线12、透明导电薄膜2、扫描线3、栅绝缘层4、钝化层5以及色阻6在图3中也都包括。由于图3是图2所示的面板结构的俯视图，因此部分色阻层6、钝化层5以及栅绝缘层4不在图中体现。如图3所示，在信号线与扫描线的重叠处，信号线并不直接跨过扫描线，而是通过由透明导电薄膜构成的拱形框架将第一信号线与第二信号线相连。由于透明导电薄膜2是由第一支边、第二支边以及第三支边构成的拱形框架，因此通过这样的搭桥方式可以增加了信号线与扫描线之间的距离，从而降低了信号线与扫描线在重叠处的寄生电容，以提高了面板显示品质。
请参阅图4，图4是本发明实施例提供的一种平板显示器中面板结构的制作方法。如图4所示，该平板显示器中面板结构的制作方法可以包括以下步骤：
S101、在预设基板上光刻扫描线；
S102、在完成步骤S101的基板上沉积栅绝缘层，并在该基板上光刻第一信号线与第二信号线；
S103、在完成步骤S102的基板上沉积钝化层；
S104、在完成步骤S103的基板上沉积色阻层；
S105、在完成步骤S104的基板上过孔，以得第一孔与第二孔；
S106、在完成步骤S105的基板上沉积透明导电薄膜。
本发明实施例中，透明导电薄膜是一种既能导电又在可见光范围内具有高透明率的一种薄膜，主要有金属膜系、氧化物膜系、其他化合物膜系、高分子膜系、复合膜系等。其中，金属膜系导电性能好，但是透明率差。半导体薄膜系列刚好相反，导电性差，透明率高。目前，研究和应用最为广泛的是金属膜系和氧化物膜系。透明导电薄膜主要用于光电器件(如薄膜太阳能电池等)的窗口材料。常见的透明导电薄膜为ITO，其中，ITO的主要成份是氧化铟锡，在厚度只有几千埃的情况下，氧化铟透过率高，氧化锡导电能力强，平板显示器中所用的ITO玻璃正是一种具有高透过率的导电玻璃。由于ITO具有很强的吸水性，所以会吸收空气中的水份和二氧化碳并产生化学反应而变质，俗称“霉变”，因此在存放时要防潮。且ITO在150KHz～1GHz范围内有适宜的屏蔽效能， 透光性较普通网栅材料屏蔽玻璃好很多，透光率可达到85％以上。
作为一种可选的实施方式，栅绝缘层的厚度应比扫描线的厚度大，也即，栅绝缘层应将扫描线完全覆盖；钝化层的厚度应比信号线的厚度大，也即钝化层应将信号线完成覆盖；色阻层的厚度应该与透明导电薄膜的第一支边、第二支边的长度相匹配。
栅绝缘层沉积在包含扫描线的预设基板上，钝化层沉积在栅绝缘层上，以及色阻层沉积在钝化层上；且色阻层的厚度取值范围为1微米至1.5微米，钝化层的厚度为300+n纳米或者300-n纳米，其中，n为大于0且小于50的实数，以及栅绝缘层的厚度为500+n纳米或者500-n纳米，其中，n为大于0且小于50的实数。
本发明实施例中，色阻层主要包括三原色(Red Green Blue，RGB)色阻。
本发明实施例中，钝化层是指在硅片或半导体器件芯片的表面淀积或生长特定的介质膜，以防止表面受环境沾污和以后的操作对硅片表面可能造成的损伤。且在本发明实施例中，钝化层的厚度为300+n纳米或者300-n纳米，其中，n为大于0且小于50的实数。半导体表面层的性质对于环境或与半导体表面接触的介质的性质是很敏感的。表面沾污离子、界面态电荷、介质层内的可动电荷和固定电荷都会影响半导体的表面电势，从而引起表面层中载流子的积累，耗尽，或者使表面层反型，并引起金属-绝缘体-半导体结构电容-电压特性和半导体器件特性的变化。为了保证半导体器件工作的稳定性和可靠性，必须在半导体器件芯片表面覆盖某些经过选择的介质膜，使表面钝化。较早采用的钝化膜是热生长的二氧化硅，但是二氧化硅膜不能阻挡钠等碱金属离子的扩散。现在生产上更常用的是二氧化硅-磷硅玻璃复合膜、二氧化硅-氮化硅复合膜、二氧化硅-三氧化二铝复合膜或聚酰亚胺膜。上述与硅片直接接触的钝化膜通常称为一次钝化膜，为了改善钝化效果，有时芯片封装前还要再涂敷一次钝化膜，称为二次钝化膜。聚酰亚胺也可用于二次钝化。
本发明实施例中，栅绝缘层主要是一层隔绝层，且其的厚度的取值范围为500+n纳米或者500-n纳米。其中，n为大于0且小于50的实数。
在图4中，在信号线与扫描线的重叠处，通过由透明导电薄膜构成的拱形框架将第一信号线与第二信号线相连，由此可以在一定范围增加信号线与扫描线的距离，从而降低了信号线与扫描线在重叠处的寄生电容，以提高了面板显 示品质。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (14)

  1. 一种平板显示器中的面板结构，包括：第一信号线、第二信号线、透明导电薄膜以及扫描线，其中，所述透明导电薄膜由第一支边、第二支边以及第三支边组成，其中，所述第一支边的第一端与所述第二支边的第一端以预先设定的第一角度相连，所述第二支边的第二端与所述第三支边的第一端以预先设定的第二角度相连，且所述第一支边、所述第二支边以及所述第三支边构成拱形框架，所述第一信号线与所述第一支边的第二端相连，所述第二信号线与所述第三支边的第二端相连，所述扫描线从所述拱形框架的第一方向穿过，且不与所述拱形框架相交。
  2. 根据权利要求1所述的面板结构，其中，所述面板结构还包括：栅绝缘层，其中，所述栅绝缘层沉积在包含所述扫描线的预设基板上。
  3. 根据权利要求2所述的面板结构，其中，所述面板结构还包括：钝化层，其中，所述钝化层沉积在所述栅绝缘层上。
  4. 根据权利要求3所述的面板结构，其中，所述面板结构还包括：色阻层，其中，所述色阻层沉积在所述钝化层上。
  5. 根据权利要求4所述的面板结构，其中，所述色阻层的厚度取值范围为1微米至1.5微米。
  6. 根据权利要求3所述的面板结构，其中，所述钝化层的厚度为300+n纳米或者300-n纳米，其中，所述n为大于0且小于50的实数。
  7. 根据权利要求2所述的面板结构，其中，所述栅绝缘层的厚度为500+n纳米或者500-n纳米，其中，所述n为大于0且小于50的实数。
  8. 根据权利要求1～7中任意一项所述的面板结构，其中，所述预先设定 的第一角度的取值范围为30度至60度，以及所述预先设定的第二角度的取值范围为30度至60度。
  9. 一种平板显示器中的面板结构的制作方法，其中，包括：
    步骤一，在预设基板上光刻扫描线；
    步骤二，在完成所述步骤一的基板上沉积栅绝缘层，并在该基板上光刻第一信号线与第二信号线；
    步骤三，在完成所述步骤二的基板上沉积钝化层；
    步骤四，在完成所述步骤三的基板上沉积色阻层；
    步骤五，在完成所述步骤四的基板上过孔，以得第一孔与第二孔；
    步骤六、在完成所述步骤五的基板上沉积透明导电薄膜。
  10. 根据权利要求9所述的方法，其中，所述栅绝缘层的厚度为500+n纳米或者500-n纳米，其中，所述n为大于0且小于50的实数。
  11. 根据权利要求9所述的方法，其中，所述钝化层的厚度为300+n纳米或者300-n纳米，其中，所述n为大于0且小于50的实数。
  12. 根据权利要求9所述的方法，其中，所述色阻层的厚度取值范围为1微米至1.5微米。
  13. 根据权利要求9～12中任意一项所述的方法，其中，所述透明导电薄膜由第一支边、第二支边以及第三支边组成，所述第一支边的第一端与所述第二支边的第一端以预先设定的第一角度相连，所述第二支边的第二端与所述第三支边的第一端以预先设定的第二角度相连，且所述第一支边、所述第二支边以及所述第三支边构成拱形框架。
  14. 根据权利要求13所述的方法，其中，所述预先设定的第一角度的取值范围为30度至60度，以及所述预先设定的第二角度的取值范围为30度至 60度。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1693973A (zh) * 2004-04-30 2005-11-09 Lg.菲利浦Lcd株式会社 薄膜晶体管上滤色片型液晶显示器件及其制造方法
KR20060077473A (ko) * 2004-12-30 2006-07-05 엘지.필립스 엘시디 주식회사 액정표시장치 및 그 제조방법
US20090167733A1 (en) * 2007-12-28 2009-07-02 Bong-Jun Lee Display substrate, method of manufacturing the display substrate and display apparatus having the display substrate
CN102866552A (zh) * 2012-09-26 2013-01-09 南京中电熊猫液晶显示科技有限公司 一种金属氧化物平面开关型液晶显示面板及其制造方法
CN103985714A (zh) * 2013-12-31 2014-08-13 上海天马微电子有限公司 阵列基板及其制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2397889A4 (en) * 2009-02-10 2013-01-23 Sharp Kk LIQUID CRYSTAL DISPLAY DEVICE
CN103069334A (zh) * 2010-08-18 2013-04-24 夏普株式会社 显示装置用基板及其制造方法、显示装置
JP2013045971A (ja) * 2011-08-25 2013-03-04 Sony Corp 薄膜トランジスタおよびその製造方法、ならびに電子機器
JP6320782B2 (ja) * 2014-02-06 2018-05-09 株式会社ジャパンディスプレイ アレイ基板
CN104571720B (zh) * 2015-02-06 2017-07-07 京东方科技集团股份有限公司 一种阵列基板、内嵌式触摸面板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1693973A (zh) * 2004-04-30 2005-11-09 Lg.菲利浦Lcd株式会社 薄膜晶体管上滤色片型液晶显示器件及其制造方法
KR20060077473A (ko) * 2004-12-30 2006-07-05 엘지.필립스 엘시디 주식회사 액정표시장치 및 그 제조방법
US20090167733A1 (en) * 2007-12-28 2009-07-02 Bong-Jun Lee Display substrate, method of manufacturing the display substrate and display apparatus having the display substrate
CN102866552A (zh) * 2012-09-26 2013-01-09 南京中电熊猫液晶显示科技有限公司 一种金属氧化物平面开关型液晶显示面板及其制造方法
CN103985714A (zh) * 2013-12-31 2014-08-13 上海天马微电子有限公司 阵列基板及其制造方法

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