WO2017008337A1 - 薄膜晶体管阵列基板及其制作方法 - Google Patents

薄膜晶体管阵列基板及其制作方法 Download PDF

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Publication number
WO2017008337A1
WO2017008337A1 PCT/CN2015/085379 CN2015085379W WO2017008337A1 WO 2017008337 A1 WO2017008337 A1 WO 2017008337A1 CN 2015085379 W CN2015085379 W CN 2015085379W WO 2017008337 A1 WO2017008337 A1 WO 2017008337A1
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Prior art keywords
layer
region
film transistor
thin film
array substrate
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Ceased
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PCT/CN2015/085379
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English (en)
French (fr)
Inventor
甘启明
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/773,342 priority Critical patent/US20170170212A1/en
Publication of WO2017008337A1 publication Critical patent/WO2017008337A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor array substrate and a method of fabricating the same.
  • the fabrication process of a conventional thin film transistor array substrate generally requires providing a via hole on the passivation layer, and providing a recess on the passivation layer, and setting a surface on the passivation layer and the recess Pixel electrode layer.
  • the pixel electrode layer is connected to the data line layer in the thin film transistor array substrate through the through hole.
  • disposing the through hole on the passivation layer and disposing the groove on the passivation layer are separately performed, that is, setting on the passivation layer
  • the vias and the placement of the recesses on the passivation layer are two separate steps.
  • An object of the present invention is to provide a thin film transistor array substrate and a manufacturing method thereof, which can save the manufacturing cost of the thin film transistor array substrate and improve the fabrication efficiency of the thin film transistor array substrate.
  • a thin film transistor array substrate comprising: a device combination board comprising: a substrate; a first signal line layer; a semiconductor layer; and a second signal line layer; a passivation layer, the passivation layer is disposed on the device combination board, the passivation layer is provided with an array of holes and a groove, the groove array includes at least one groove; a pixel electrode layer, a pixel electrode layer disposed on the passivation layer and the groove array, the pixel electrode layer being connected to the second signal line layer through the hole; the hole having a first depth, the groove Having a second depth; the groove array and the holes are both formed by the same mask process and etching process; the device combination board further includes a first insulating layer, a second insulating layer, and a drain line layer
  • the first signal line layer is a scan line layer
  • the semiconductor layer is an amorphous silicon layer or a polysilicon layer
  • the second signal line layer is a data line layer
  • the semiconductor layer is the amorph
  • the mask corresponding to the mask process includes: a first region, the first region has a first light transmittance, and the first region corresponds to the hole, The first light transmittance corresponds to the first depth; at least one second region, the second region has a second light transmittance, the second region corresponds to the groove, and the second light transmittance Corresponding to the second depth.
  • the mask is a halftone mask.
  • the first light transmittance is 100%
  • the second light transmittance is in a range of 0% to 100%.
  • the second light transmittance is in the range of 13% to 91%.
  • the groove array and the hole are formed by performing the mask process on the photoresist material layer on the passivation layer to form a third layer on the photoresist material layer Forming a first recess and a second recess on the region and the fourth region, respectively, and etching the passivation layer and the photoresist layer at the first recess and the second recess; wherein
  • the third region corresponds to the first region
  • the fourth region corresponds to the second region
  • the first recess has a third depth
  • the second recess has a fourth depth.
  • a thin film transistor array substrate comprising: a device combination board comprising: a substrate; a first signal line layer; a semiconductor layer; and a second signal line layer; a passivation layer, the passivation layer is disposed on the device combination board, the passivation layer is provided with an array of holes and a groove, the groove array includes at least one groove; a pixel electrode layer, A pixel electrode layer is disposed on the passivation layer and in the groove array, and the pixel electrode layer is connected to the second signal line layer through the hole.
  • the hole has a first depth, and the groove has a second depth; the groove array and the hole are both formed by the same mask process and etching process.
  • the mask corresponding to the mask process includes: a first region, the first region has a first light transmittance, and the first region corresponds to the hole, The first light transmittance corresponds to the first depth; at least one second region, the second region has a second light transmittance, the second region corresponds to the groove, and the second light transmittance Corresponding to the second depth.
  • the mask is a halftone mask.
  • the first light transmittance is 100%
  • the second light transmittance is in a range of 0% to 100%.
  • the second light transmittance is in the range of 13% to 91%.
  • the groove array and the hole are formed by performing the mask process on the photoresist material layer on the passivation layer to form a third layer on the photoresist material layer Forming a first recess and a second recess on the region and the fourth region, respectively, and etching the passivation layer and the photoresist layer at the first recess and the second recess; wherein
  • the third region corresponds to the first region
  • the fourth region corresponds to the second region
  • the first recess has a third depth
  • the second recess has a fourth depth.
  • a method of fabricating a thin film transistor array substrate comprising the steps of: forming a device composite board, wherein the device combination board comprises a substrate, a first signal line layer, a semiconductor layer, and a second signal line a layer B is disposed on the device combination board; C, performing a mask process and an etching process on the passivation layer, so that a hole and a recess are formed on the surface of the passivation layer; a groove array, wherein the groove array includes at least one groove; D, a pixel electrode layer is disposed in the surface of the passivation layer and the groove array, wherein the pixel electrode layer passes through A hole is connected to the second signal line layer.
  • the hole has a first depth, and the groove has a second depth;
  • the step C includes the following steps: c1, passing the same on the passivation layer A mask process and the etching process to form the array of grooves and the holes.
  • the mask corresponding to the mask process includes: a first region, the first region has a first light transmittance, and the first region corresponds to the hole, The first light transmittance corresponds to the first depth; at least one second region, the second region has a second light transmittance, the second region corresponds to the groove, and the second region The light rate corresponds to the second depth.
  • the mask is a halftone mask.
  • the first light transmittance is 100%
  • the second light transmittance is in a range of 0% to 100%.
  • the second light transmittance is in a range of 13% to 91%.
  • the step c1 includes the following steps: c11, providing a photoresist material layer on the passivation layer; c12, performing the photomask process on the photoresist material layer, Forming a first recess and a second recess respectively on the third region and the fourth region on the photoresist material layer, wherein the third region corresponds to the first region, and the fourth region Corresponding to the second region, the first recess has a third depth, the second recess has a fourth depth; c13, the passivation layer and the at the first recess and the second recess A layer of photoresist material is etched to form the array of grooves and the holes on the passivation layer.
  • the present invention can save a mask process, save the manufacturing cost of the thin film transistor array substrate, and improve the fabrication efficiency of the thin film transistor array substrate.
  • FIG. 6 are schematic views showing a first embodiment of a method of fabricating a thin film transistor array substrate according to the present invention
  • FIG. 6 is a schematic view of a thin film transistor array substrate of the present invention.
  • FIGS. 1 to 6 are schematic views of a mask used in the fabrication process of the thin film transistor array substrate shown in FIGS. 1 to 6;
  • FIG. 8 is a flow chart of a first embodiment of a method of fabricating a thin film transistor array substrate of the present invention.
  • FIG. 9 is a flow chart showing a second embodiment of a method of fabricating a thin film transistor array substrate of the present invention.
  • Figure 10 is a flow chart showing a third embodiment of a method of fabricating a thin film transistor array substrate of the present invention.
  • the display panel of the present invention may be a TFT-LCD (Thin Film Transistor Liquid) Crystal Display, thin film transistor liquid crystal display panel).
  • TFT-LCD Thin Film Transistor Liquid
  • LCD Thin Film Transistor Liquid
  • FIG. 6 is a schematic diagram of a thin film transistor array substrate of the present invention.
  • the thin film transistor array substrate of the present invention includes a device combination board 101, a passivation layer 201, and a pixel electrode layer 601.
  • the device assembly board 101 includes a substrate 1011, a first signal line layer 1012, a semiconductor layer 1014, and a second signal line layer 1017.
  • the device assembly board 101 further includes a first insulating layer 1013, a second insulating layer 1015, and a drain line layer 1016.
  • the first signal line layer 1012 may be a scan line layer
  • the semiconductor layer 1014 may be an amorphous silicon layer or a polysilicon layer
  • the second signal line layer 1017 may be a data line layer.
  • the scan line layer is disposed under the semiconductor layer 1014 (the semiconductor layer 1014 is the amorphous silicon layer), and the first insulation is disposed between the scan line layer and the amorphous silicon layer a layer 1013
  • the second insulating layer 1015 is disposed above the amorphous silicon layer
  • the data line layer is disposed above the second insulating layer 1015, and the data line layer passes through the second layer
  • the insulating layer 1015 is connected to the amorphous silicon layer; or the scan line layer is disposed over the semiconductor layer 1014 (the semiconductor layer 1014 is the polysilicon layer), the polysilicon layer and the scan line
  • the first insulating layer 1013 is disposed between the layers
  • the second insulating layer 1015 is disposed above the scan line layer
  • the passivation layer 201 is disposed on the device composite board 101.
  • the passivation layer 201 is provided with a hole 2011 and a groove array 2012, and the groove array 2012 includes at least one groove 20121.
  • the pixel electrode layer 601 is disposed on the passivation layer 201 and in the groove array 2012, and the pixel electrode layer 601 is connected to the second signal line layer 1017 through the hole 2011.
  • the hole 2011 has a first depth H3, and the groove 20121 has a second depth H4.
  • the groove array 2012 and the holes 2011 are both formed by the same mask process and etching process. That is to say, the groove array 2012 and the holes 2011 are both formed in the same mask process.
  • the above technical solution can save a mask process (Normal)
  • the mask is used to save the manufacturing cost of the thin film transistor array substrate and improve the fabrication efficiency of the thin film transistor array substrate.
  • FIG. 7 is a schematic view of a mask used in the fabrication process of the thin film transistor array substrate shown in FIGS. 1 to 6.
  • the mask 701 corresponding to the mask process includes a first region 7011 and a second region 7012.
  • the first region 7011 has a first light transmittance
  • the first region 7011 corresponds to the hole 2011, and the first light transmittance corresponds to the first depth H3.
  • the second region 7012 has a second light transmittance
  • the second region 7012 corresponds to the groove 20121, and the second light transmittance corresponds to the second depth H4.
  • the mask 701 is a Half Tone Mask (HTM).
  • HTM Half Tone Mask
  • the depth of the hole 2011 (the first depth H3) and the depth of the groove 20121 (the second depth H4) may be set according to the light transmittance of the HTM (open interval of 0-100%) .
  • the first depth H3 and the second depth H4 in the passivation layer 201 are formed in such a manner as to:
  • the mask process is performed on the passivation layer 201 by using the mask 701 having the first region 7011 and the second region 7012 to simultaneously form the first depth H3 and the second a depth H4, wherein the first region 7011 has the first light transmittance and the second region 7012 has the second light transmittance.
  • the first light transmittance is 100%
  • the second light transmittance (a%) is in a range of 0% to 100% (open interval), for example, the a% is 0.5%, 1%.
  • the groove array 2012 and the hole 2011 are performed on the photoresist layer 301 on the passivation layer 201 by the photomask process on the photoresist material layer 301.
  • a first recess 3011 and a second recess 3012 are formed on the third region and the fourth region, respectively, and the passivation layer 201 and the photoresist material are disposed at the first recess 3011 and the second recess 3012
  • Layer 301 is formed by etching.
  • the third area corresponds to the first area 7011
  • the fourth area corresponds to the second area 7012
  • the first recess 3011 has a third depth H1
  • the second recess 3012 has a Four depths H2.
  • FIG. 1 to FIG. 6 are schematic diagrams showing a first embodiment of a method for fabricating a thin film transistor array substrate according to the present invention
  • FIG. 8 is a first embodiment of a method for fabricating a thin film transistor array substrate of the present invention. A flow chart of an embodiment.
  • the manufacturing method of the thin film transistor array substrate of the present invention comprises the following steps:
  • the device assembly board 101 is formed, wherein the device combination board 101 includes a substrate 1011, a first signal line layer 1012, a semiconductor layer 1014, and a second signal line layer 1017.
  • the passivation layer 201 is disposed on the device combination board 101.
  • step 803 performing a mask process and an etching process on the passivation layer 201 such that a hole 2011 and a groove array 2012 are formed on the surface of the passivation layer 201, wherein the groove array 2012 includes at least one groove 20121.
  • step 804 providing a pixel electrode layer 601 in the surface of the passivation layer 201 and the groove array 2012, wherein the pixel electrode layer 601 passes through the hole 2011 and the second signal
  • the line layer 1017 is connected.
  • FIG. 9 is a flow chart showing a second embodiment of a method of fabricating a thin film transistor array substrate of the present invention. This embodiment is similar to the first embodiment described above, except that:
  • the hole 2011 has a first depth H3, and the groove 20121 has a second depth H4, that is, the hole 2011 is different from the depth of the groove 20121, and has different depths.
  • the hole 2011 and the groove 20121 are formed in the same mask process and the same etching process. That is, the step C (ie, the step 803) includes the following steps:
  • step 901 the groove array 2012 and the hole 2011 are formed on the passivation layer 201 by the same mask process and the etching process.
  • the above technical solution can save a mask process (Normal)
  • the mask is used to save the manufacturing cost of the thin film transistor array substrate and improve the fabrication efficiency of the thin film transistor array substrate.
  • the mask 701 corresponding to the mask process includes a first region 7011 and a second region 7012.
  • the first region 7011 has a first light transmittance
  • the first region 7011 corresponds to the hole 2011, and the first light transmittance corresponds to the first depth H3.
  • the second region 7012 has a second light transmittance
  • the second region 7012 corresponds to the groove 20121, and the second light transmittance corresponds to the second depth H4.
  • the mask 701 is a halftone mask.
  • the depth of the hole 2011 (the first depth H3) and the depth of the groove 20121 (the second depth H4) may be set according to the light transmittance of the HTM (open interval of 0-100%) .
  • the first depth H3 and the second depth H4 in the passivation layer 201 are formed in such a manner as to:
  • the mask process is performed on the passivation layer 201 by using the mask 701 having the first region 7011 and the second region 7012 to simultaneously form the first depth H3 and the second a depth H4, wherein the first region 7011 has the first light transmittance and the second region 7012 has the second light transmittance.
  • the first light transmittance is 100%
  • the second light transmittance (a%) is in a range of 0% to 100% (open interval), for example, the a% is 0.5%, 1%.
  • FIG. 10 is a flow chart showing a third embodiment of a method of fabricating a thin film transistor array substrate of the present invention. This embodiment is similar to the second embodiment described above, except that:
  • step c1 (ie, the step 901) includes the following steps:
  • step 1001 providing a photoresist material layer 301 on the passivation layer 201;
  • step 1002 performing the mask process on the photoresist layer 301 to form a first recess 3011 and a second recess on the third region and the fourth region on the photoresist layer 301, respectively 3012, wherein the third area corresponds to the first area 7011, the fourth area corresponds to the second area 7012, the first recess 3011 has a third depth H1, and the second recess 3012 Has a fourth depth H2.
  • step 1003 etching the passivation layer 201 and the photoresist layer 301 at the first recess 3011 and the second recess 3012 to form a layer on the passivation layer 201
  • the groove array 2012 and the hole 2011 are described.

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Abstract

一种薄膜晶体管阵列基板及其制作方法。薄膜晶体管阵列基板包括器件组合板（101）、钝化层（201）和像素电极层（601）；器件组合板（101）包括：基板（1011）、第一信号线层（1012）、半导体层（1014）和第二信号线层（1017）；钝化层（201）上设置有孔洞（2011）和凹槽（20121）；像素电极层（601）设置在钝化层（201）上以及凹槽（20121）内，像素电极层（601）通过孔洞（2011）与第二信号线层（1017）连接。该方法可以节省薄膜晶体管阵列基板的制作成本以及提高制作效率。

Description

薄膜晶体管阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，特别涉及一种薄膜晶体管阵列基板及其制作方法。
背景技术
传统的薄膜晶体管阵列基板的制作过程一般都需要在钝化层上设置通孔，以及在所述钝化层上设置凹槽，并在所述钝化层上的表面和所述凹槽内设置像素电极层。其中，该像素电极层通过所述通孔与所述薄膜晶体管阵列基板中的数据线层连接。
在上述传统的技术方案中，在所述钝化层上设置所述通孔和在所述钝化层上设置所述凹槽是分开实施的，也就是说，在所述钝化层上设置所述通孔和在所述钝化层上设置所述凹槽是两个独立的步骤。
针对上述两个独立的步骤，需要两次不同的Normal Mask（普通掩模）光罩制程，这导致上述技术方案具有较高的成本，并且使得所述薄膜晶体管阵列基板的制作效率不高。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种薄膜晶体管阵列基板及其制作方法，其能节省薄膜晶体管阵列基板的制作成本以及提高薄膜晶体管阵列基板的制作效率。
 技术解决方案
一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：一器件组合板，所述器件组合板包括：一基板；一第一信号线层；一半导体层；以及一第二信号线层；一钝化层，所述钝化层设置在所述器件组合板上，所述钝化层上设置有孔洞和凹槽阵列，所述凹槽阵列包括至少一凹槽；一像素电极层，所述像素电极层设置在所述钝化层上以及所述凹槽阵列内，所述像素电极层通过所述孔洞与所述第二信号线层连接；所述孔洞具有第一深度，所述凹槽具有第二深度；所述凹槽阵列和所述孔洞均是通过相同的光罩制程和蚀刻制程来形成的；所述器件组合板还包括第一绝缘层、第二绝缘层和漏极线层；所述第一信号线层是扫描线层，所述半导体层是非晶硅层或多晶硅层，所述第二信号线层是数据线层；在所述半导体层是所述非晶硅层的情况下，所述扫描线层设置在所述非晶硅层的下方，所述扫描线层与所述非晶硅层之间设置有所述第一绝缘层，所述第二绝缘层设置在所述非晶硅层的上方，所述数据线层设置在所述第二绝缘层的上方，并且所述数据线层穿过所述第二绝缘层与所述非晶硅层相连；在所述半导体层是所述多晶硅层的情况下，所述扫描线层设置在所述多晶硅层的上方，所述多晶硅层与所述扫描线层之间设置有所述第一绝缘层，所述第二绝缘层设置在所述扫描线层的上方，所述数据线层设置在所述第二绝缘层的上方，并且所述数据线层穿过所述第一绝缘层和所述第二绝缘层与所述多晶硅层相连。
在上述薄膜晶体管阵列基板中，所述光罩制程所对应的掩模包括：一第一区域，所述第一区域具有第一透光率，所述第一区域与所述孔洞对应，所述第一透光率与所述第一深度对应；至少一第二区域，所述第二区域具有第二透光率，所述第二区域与所述凹槽对应，所述第二透光率与所述第二深度对应。
在上述薄膜晶体管阵列基板中，所述掩模为半色调掩模。
在上述薄膜晶体管阵列基板中，所述第一透光率为100%，所述第二透光率处于0%至100%的范围内。
在上述薄膜晶体管阵列基板中，所述第二透光率处于13%至91%的范围内。
在上述薄膜晶体管阵列基板中，所述凹槽阵列和所述孔洞是通过对所述钝化层上的光阻材料层进行所述光罩制程，以在所述光阻材料层上的第三区域和第四区域上分别形成第一凹陷和第二凹陷，并在所述第一凹陷和所述第二凹陷处对所述钝化层和所述光阻材料层进行蚀刻来形成的；其中，所述第三区域与所述第一区域对应，所述第四区域与所述第二区域对应，所述第一凹陷具有第三深度，所述第二凹陷具有第四深度。
一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：一器件组合板，所述器件组合板包括：一基板；一第一信号线层；一半导体层；以及一第二信号线层；一钝化层，所述钝化层设置在所述器件组合板上，所述钝化层上设置有孔洞和凹槽阵列，所述凹槽阵列包括至少一凹槽；一像素电极层，所述像素电极层设置在所述钝化层上以及所述凹槽阵列内，所述像素电极层通过所述孔洞与所述第二信号线层连接。
在上述薄膜晶体管阵列基板中，所述孔洞具有第一深度，所述凹槽具有第二深度；所述凹槽阵列和所述孔洞均是通过相同的光罩制程和蚀刻制程来形成的。
在上述薄膜晶体管阵列基板中，所述光罩制程所对应的掩模包括：一第一区域，所述第一区域具有第一透光率，所述第一区域与所述孔洞对应，所述第一透光率与所述第一深度对应；至少一第二区域，所述第二区域具有第二透光率，所述第二区域与所述凹槽对应，所述第二透光率与所述第二深度对应。
在上述薄膜晶体管阵列基板中，所述掩模为半色调掩模。
在上述薄膜晶体管阵列基板中，所述第一透光率为100%，所述第二透光率处于0%至100%的范围内。
在上述薄膜晶体管阵列基板中，所述第二透光率处于13%至91%的范围内。
在上述薄膜晶体管阵列基板中，所述凹槽阵列和所述孔洞是通过对所述钝化层上的光阻材料层进行所述光罩制程，以在所述光阻材料层上的第三区域和第四区域上分别形成第一凹陷和第二凹陷，并在所述第一凹陷和所述第二凹陷处对所述钝化层和所述光阻材料层进行蚀刻来形成的；其中，所述第三区域与所述第一区域对应，所述第四区域与所述第二区域对应，所述第一凹陷具有第三深度，所述第二凹陷具有第四深度。
一种上述薄膜晶体管阵列基板的制作方法，所述方法包括以下步骤：A、形成所述器件组合板，其中，所述器件组合板包括基板、第一信号线层、半导体层以及第二信号线层；B、在所述器件组合板上设置所述钝化层；C、对所述钝化层实施光罩制程和蚀刻制程，以使所述钝化层的表面上形成有一孔洞和一凹槽阵列，其中，所述凹槽阵列包括至少一凹槽；D、在所述钝化层的所述表面和所述凹槽阵列内设置像素电极层，其中，所述像素电极层通过所述孔洞与所述第二信号线层连接。
在上述薄膜晶体管阵列基板的制作方法中，所述孔洞具有第一深度，所述凹槽具有第二深度；所述步骤C包括以下步骤：c1、在所述钝化层上通过相同的所述光罩制程和所述蚀刻制程来形成所述凹槽阵列和所述孔洞。
在上述薄膜晶体管阵列基板的制作方法中，所述光罩制程所对应掩模包括：一第一区域，所述第一区域具有第一透光率，所述第一区域与所述孔洞对应，所述第一透光率与所述第一深度对应；至少一第二区域，所述第二区域具有第二透光率，所述第二区域与所述凹槽对应，所述第二透光率与所述第二深度对应。
在上述薄膜晶体管阵列基板的制作方法中，所述掩模为半色调掩模。
在上述薄膜晶体管阵列基板的制作方法，其中，所述第一透光率为100%，所述第二透光率处于0%至100%的范围内。
在上述薄膜晶体管阵列基板的制作方法，其中，所述第二透光率处于13%至91%的范围内。
在上述薄膜晶体管阵列基板的制作方法中，所述步骤c1包括以下步骤：c11、在所述钝化层上设置光阻材料层；c12、对所述光阻材料层进行所述光罩制程，以在所述光阻材料层上的第三区域和第四区域上分别形成第一凹陷和第二凹陷，其中，所述第三区域与所述第一区域对应，所述第四区域与所述第二区域对应，所述第一凹陷具有第三深度，所述第二凹陷具有第四深度；c13、在所述第一凹陷和所述第二凹陷处对所述钝化层和所述光阻材料层进行蚀刻，以在所述钝化层上形成所述凹槽阵列和所述孔洞。
 有益效果
相对现有技术，本发明可以节约一道光罩制程，有利于节省所述薄膜晶体管阵列基板的制作成本，以及提高所述薄膜晶体管阵列基板的制作效率。
附图说明
图1至图6为本发明的薄膜晶体管阵列基板的制作方法的第一实施例的示意图；
图6为本发明的薄膜晶体管阵列基板的示意图；
图7为图1至图6所示的薄膜晶体管阵列基板的制作过程中所使用的掩模的示意图；
图8为本发明的薄膜晶体管阵列基板的制作方法的第一实施例的流程图；
图9为本发明的薄膜晶体管阵列基板的制作方法的第二实施例的流程图；
图10为本发明的薄膜晶体管阵列基板的制作方法的第三实施例的流程图。
 本发明的最佳实施方式
本说明书所使用的词语“实施例”意指实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为“一个或多个”，除非另外指定或从上下文可以清楚确定单数形式。
本发明的显示面板可以是TFT-LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示面板）。
参考图6，图6为本发明的薄膜晶体管阵列基板的示意图。
本发明的薄膜晶体管阵列基板包括器件组合板101、钝化层201及像素电极层601。
所述器件组合板101包括基板1011、第一信号线层1012、半导体层1014及第二信号线层1017。所述器件组合板101还包括第一绝缘层1013、第二绝缘层1015和漏极线层1016。
所述第一信号线层1012可以是扫描线层，所述半导体层1014可以是非晶硅层或多晶硅层，所述第二信号线层1017可以是数据线层。所述扫描线层设置在所述半导体层1014（所述半导体层1014为所述非晶硅层）的下方，所述扫描线层与所述非晶硅层之间设置有所述第一绝缘层1013，所述第二绝缘层1015设置在所述非晶硅层的上方，所述数据线层设置在所述第二绝缘层1015的上方，并且所述数据线层穿过所述第二绝缘层1015与所述非晶硅层相连；或者，所述扫描线层设置在所述半导体层1014（所述半导体层1014为所述多晶硅层）的上方，所述多晶硅层与所述扫描线层之间设置有所述第一绝缘层1013，所述第二绝缘层1015设置在所述扫描线层的上方，所述数据线层设置在所述第二绝缘层1015的上方，并且所述数据线层穿过所述第一绝缘层1013和所述第二绝缘层1015与所述多晶硅层相连。
所述钝化层201设置在所述器件组合板101上，所述钝化层201上设置有孔洞2011和凹槽阵列2012，所述凹槽阵列2012包括至少一凹槽20121。所述像素电极层601设置在所述钝化层201上以及所述凹槽阵列2012内，所述像素电极层601通过所述孔洞2011与所述第二信号线层1017连接。
在本实施例中，所述孔洞2011具有第一深度H3，所述凹槽20121具有第二深度H4。所述凹槽阵列2012和所述孔洞2011均是通过相同的光罩制程和蚀刻制程来形成的。也就是说，所述凹槽阵列2012与所述孔洞2011均是在同一道光罩制程中形成的。
相比传统的技术方案，上述技术方案可以节约一道光罩制程（Normal Mask，普通掩模），有利于节省所述薄膜晶体管阵列基板的制作成本，以及提高所述薄膜晶体管阵列基板的制作效率。
参考图7，图7为图1至图6所示的薄膜晶体管阵列基板的制作过程中所使用的掩模的示意图。
在本实施例中，所述光罩制程所对应的掩模701包括第一区域7011及第二区域7012。所述第一区域7011具有第一透光率，所述第一区域7011与所述孔洞2011对应，所述第一透光率与所述第一深度H3对应。所述第二区域7012具有第二透光率，所述第二区域7012与所述凹槽20121对应，所述第二透光率与所述第二深度H4对应。
优选地，在本实施例中，所述掩模701为半色调掩模（HTM，Half Tone Mask）。
所述孔洞2011的深度（所述第一深度H3）和所述凹槽20121的深度（所述第二深度H4）可根据所述HTM的透光率（0-100%的开区间）来设置。
也就是说，所述钝化层201中的所述第一深度H3和所述第二深度H4是通过这样的方式来形成的：
利用具有所述第一区域7011和所述第二区域7012的所述掩模701，对所述钝化层201实施所述光罩制程，以同时形成所述第一深度H3和所述第二深度H4，其中，所述第一区域7011具有所述第一透光率，所述第二区域7012具有所述第二透光率。例如，所述第一透光率为100%，所述第二透光率（a%）处于0%至100%的范围（开区间）内，例如，所述a%为0.5%、1%、3%、5%、7%、9%、11%、13%、15%、17%、19%、21%、23%、25%、27%、29%、31%、33%、35%、37%、39%、41%、43%、45%、47%、49%、51%、53%、55%、57%、59%、61%、63%、65%、67%、69%、71%、73%、75%、77%、79%、81%、83%、85%、87%、89%、91%、93%、95%、97%、99%。
如图1至图6所示。在本实施例中，所述凹槽阵列2012和所述孔洞2011是通过对所述钝化层201上的光阻材料层301进行所述光罩制程，以在所述光阻材料层301上的第三区域和第四区域上分别形成第一凹陷3011和第二凹陷3012，并在所述第一凹陷3011和所述第二凹陷3012处对所述钝化层201和所述光阻材料层301进行蚀刻来形成的。
其中，所述第三区域与所述第一区域7011对应，所述第四区域与所述第二区域7012对应，所述第一凹陷3011具有第三深度H1，所述第二凹陷3012具有第四深度H2。
参考图1至图6以及图8，图1至图6为本发明的薄膜晶体管阵列基板的制作方法的第一实施例的示意图，图8为本发明的薄膜晶体管阵列基板的制作方法的第一实施例的流程图。
本发明的薄膜晶体管阵列基板的制作方法包括以下步骤：
A（步骤801）、形成所述器件组合板101，其中，所述器件组合板101包括基板1011、第一信号线层1012、半导体层1014以及第二信号线层1017。
B（步骤802）、在所述器件组合板101上设置所述钝化层201。
C（步骤803）、对所述钝化层201实施光罩制程和蚀刻制程，以使所述钝化层201的表面上形成有一孔洞2011和一凹槽阵列2012，其中，所述凹槽阵列2012包括至少一凹槽20121。
D（步骤804）、在所述钝化层201的所述表面和所述凹槽阵列2012内设置像素电极层601，其中，所述像素电极层601通过所述孔洞2011与所述第二信号线层1017连接。
参考图9，图9为本发明的薄膜晶体管阵列基板的制作方法的第二实施例的流程图。本实施例与上述第一实施例相似，不同之处在于：
在本实施例中，所述孔洞2011具有第一深度H3，所述凹槽20121具有第二深度H4，也就是说，所述孔洞2011与所述凹槽20121的深度不同，具有不同深度的所述孔洞2011与所述凹槽20121是在同一道光罩制程以及同一道蚀刻制程中形成的。即，所述步骤C（即，所述步骤803）包括以下步骤：
c1（步骤901）、在所述钝化层201上通过相同的所述光罩制程和所述蚀刻制程来形成所述凹槽阵列2012和所述孔洞2011。
相比传统的技术方案，上述技术方案可以节约一道光罩制程（Normal Mask，普通掩模），有利于节省所述薄膜晶体管阵列基板的制作成本，以及提高所述薄膜晶体管阵列基板的制作效率。
在本实施例中，所述光罩制程所对应掩模701包括第一区域7011和第二区域7012。所述第一区域7011具有第一透光率，所述第一区域7011与所述孔洞2011对应，所述第一透光率与所述第一深度H3对应。所述第二区域7012具有第二透光率，所述第二区域7012与所述凹槽20121对应，所述第二透光率与所述第二深度H4对应。
优选地，在本实施例中，所述掩模701为半色调掩模。
所述孔洞2011的深度（所述第一深度H3）和所述凹槽20121的深度（所述第二深度H4）可根据所述HTM的透光率（0-100%的开区间）来设置。
也就是说，所述钝化层201中的所述第一深度H3和所述第二深度H4是通过这样的方式来形成的：
利用具有所述第一区域7011和所述第二区域7012的所述掩模701，对所述钝化层201实施所述光罩制程，以同时形成所述第一深度H3和所述第二深度H4，其中，所述第一区域7011具有所述第一透光率，所述第二区域7012具有所述第二透光率。例如，所述第一透光率为100%，所述第二透光率（a%）处于0%至100%的范围（开区间）内，例如，所述a%为0.5%、1%、3%、5%、7%、9%、11%、13%、15%、17%、19%、21%、23%、25%、27%、29%、31%、33%、35%、37%、39%、41%、43%、45%、47%、49%、51%、53%、55%、57%、59%、61%、63%、65%、67%、69%、71%、73%、75%、77%、79%、81%、83%、85%、87%、89%、91%、93%、95%、97%、99%。
参考图10，图10为本发明的薄膜晶体管阵列基板的制作方法的第三实施例的流程图。本实施例与上述第二实施例相似，不同之处在于：
在本实施例中，所述步骤c1（即，所述步骤901）包括以下步骤：
c11（步骤1001）、在所述钝化层201上设置光阻材料层301；
c12（步骤1002）、对所述光阻材料层301进行所述光罩制程，以在所述光阻材料层301上的第三区域和第四区域上分别形成第一凹陷3011和第二凹陷3012，其中，所述第三区域与所述第一区域7011对应，所述第四区域与所述第二区域7012对应，所述第一凹陷3011具有第三深度H1，所述第二凹陷3012具有第四深度H2。
c13（步骤1003）、在所述第一凹陷3011和所述第二凹陷3012处对所述钝化层201和所述光阻材料层301进行蚀刻，以在所述钝化层201上形成所述凹槽阵列2012和所述孔洞2011。
尽管已经相对于一个或多个实现方式示出并描述了本发明，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本发明包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括：
    一器件组合板，所述器件组合板包括：
    一基板；
    一第一信号线层；
    一半导体层；以及
    一第二信号线层；
    一钝化层，所述钝化层设置在所述器件组合板上，所述钝化层上设置有孔洞和凹槽阵列，所述凹槽阵列包括至少一凹槽；
    一像素电极层，所述像素电极层设置在所述钝化层上以及所述凹槽阵列内，所述像素电极层通过所述孔洞与所述第二信号线层连接；
    所述孔洞具有第一深度，所述凹槽具有第二深度；
    所述凹槽阵列和所述孔洞均是通过相同的光罩制程和蚀刻制程来形成的；
    所述器件组合板还包括第一绝缘层、第二绝缘层和漏极线层；
    所述第一信号线层是扫描线层，所述半导体层是非晶硅层或多晶硅层，所述第二信号线层是数据线层；
    在所述半导体层是所述非晶硅层的情况下，所述扫描线层设置在所述非晶硅层的下方，所述扫描线层与所述非晶硅层之间设置有所述第一绝缘层，所述第二绝缘层设置在所述非晶硅层的上方，所述数据线层设置在所述第二绝缘层的上方，并且所述数据线层穿过所述第二绝缘层与所述非晶硅层相连；
    在所述半导体层是所述多晶硅层的情况下，所述扫描线层设置在所述多晶硅层的上方，所述多晶硅层与所述扫描线层之间设置有所述第一绝缘层，所述第二绝缘层设置在所述扫描线层的上方，所述数据线层设置在所述第二绝缘层的上方，并且所述数据线层穿过所述第一绝缘层和所述第二绝缘层与所述多晶硅层相连。
  2. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述光罩制程所对应的掩模包括：
    一第一区域，所述第一区域具有第一透光率，所述第一区域与所述孔洞对应，所述第一透光率与所述第一深度对应；
    至少一第二区域，所述第二区域具有第二透光率，所述第二区域与所述凹槽对应，所述第二透光率与所述第二深度对应。
  3. 根据权利要求2所述的薄膜晶体管阵列基板，其中，所述掩模为半色调掩模。
  4. 根据权利要求3所述的薄膜晶体管阵列基板，其中，所述第一透光率为100%，所述第二透光率处于0%至100%的范围内。
  5. 根据权利要求4所述的薄膜晶体管阵列基板，其中，所述第二透光率处于13%至91%的范围内。
  6. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述凹槽阵列和所述孔洞是通过对所述钝化层上的光阻材料层进行所述光罩制程，以在所述光阻材料层上的第三区域和第四区域上分别形成第一凹陷和第二凹陷，并在所述第一凹陷和所述第二凹陷处对所述钝化层和所述光阻材料层进行蚀刻来形成的；
    其中，所述第三区域与所述第一区域对应，所述第四区域与所述第二区域对应，所述第一凹陷具有第三深度，所述第二凹陷具有第四深度。
  7. 一种薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括：
    一器件组合板，所述器件组合板包括：
    一基板；
    一第一信号线层；
    一半导体层；以及
    一第二信号线层；
    一钝化层，所述钝化层设置在所述器件组合板上，所述钝化层上设置有孔洞和凹槽阵列，所述凹槽阵列包括至少一凹槽；
    一像素电极层，所述像素电极层设置在所述钝化层上以及所述凹槽阵列内，所述像素电极层通过所述孔洞与所述第二信号线层连接。
  8. 根据权利要求7所述的薄膜晶体管阵列基板，其中，所述孔洞具有第一深度，所述凹槽具有第二深度；
    所述凹槽阵列和所述孔洞均是通过相同的光罩制程和蚀刻制程来形成的。
  9. 根据权利要求8所述的薄膜晶体管阵列基板，其中，所述光罩制程所对应的掩模包括：
    一第一区域，所述第一区域具有第一透光率，所述第一区域与所述孔洞对应，所述第一透光率与所述第一深度对应；
    至少一第二区域，所述第二区域具有第二透光率，所述第二区域与所述凹槽对应，所述第二透光率与所述第二深度对应。
  10. 根据权利要求9所述的薄膜晶体管阵列基板，其中，所述掩模为半色调掩模。
  11. 根据权利要求10所述的薄膜晶体管阵列基板，其中，所述第一透光率为100%，所述第二透光率处于0%至100%的范围内。
  12. 根据权利要求11所述的薄膜晶体管阵列基板，其中，所述第二透光率处于13%至91%的范围内。
  13. 根据权利要求8所述的薄膜晶体管阵列基板，其中，所述凹槽阵列和所述孔洞是通过对所述钝化层上的光阻材料层进行所述光罩制程，以在所述光阻材料层上的第三区域和第四区域上分别形成第一凹陷和第二凹陷，并在所述第一凹陷和所述第二凹陷处对所述钝化层和所述光阻材料层进行蚀刻来形成的；
    其中，所述第三区域与所述第一区域对应，所述第四区域与所述第二区域对应，所述第一凹陷具有第三深度，所述第二凹陷具有第四深度。
  14. 一种如权利要求7所述的薄膜晶体管阵列基板的制作方法，其中，所述方法包括以下步骤：
    A、形成所述器件组合板，其中，所述器件组合板包括基板、第一信号线层、半导体层以及第二信号线层；
    B、在所述器件组合板上设置所述钝化层；
    C、对所述钝化层实施光罩制程和蚀刻制程，以使所述钝化层的表面上形成有一孔洞和一凹槽阵列，其中，所述凹槽阵列包括至少一凹槽；
    D、在所述钝化层的所述表面和所述凹槽阵列内设置像素电极层，其中，所述像素电极层通过所述孔洞与所述第二信号线层连接。
  15. 根据权利要求14所述的薄膜晶体管阵列基板的制作方法，其中，所述孔洞具有第一深度，所述凹槽具有第二深度；
    所述步骤C包括以下步骤：
    c1、在所述钝化层上通过相同的所述光罩制程和所述蚀刻制程来形成所述凹槽阵列和所述孔洞。
  16. 根据权利要求15所述的薄膜晶体管阵列基板的制作方法，其中，所述光罩制程所对应掩模包括：
    一第一区域，所述第一区域具有第一透光率，所述第一区域与所述孔洞对应，所述第一透光率与所述第一深度对应；
    至少一第二区域，所述第二区域具有第二透光率，所述第二区域与所述凹槽对应，所述第二透光率与所述第二深度对应。
  17. 根据权利要求16所述的薄膜晶体管阵列基板的制作方法，其中，所述掩模为半色调掩模。
  18. 根据权利要求17所述的薄膜晶体管阵列基板的制作方法，其中，所述第一透光率为100%，所述第二透光率处于0%至100%的范围内。
  19. 根据权利要求18所述的薄膜晶体管阵列基板的制作方法，其中，所述第二透光率处于13%至91%的范围内。
  20. 根据权利要求15所述的薄膜晶体管阵列基板的制作方法，其中，所述步骤c1包括以下步骤：
    c11、在所述钝化层上设置光阻材料层；
    c12、对所述光阻材料层进行所述光罩制程，以在所述光阻材料层上的第三区域和第四区域上分别形成第一凹陷和第二凹陷，其中，所述第三区域与所述第一区域对应，所述第四区域与所述第二区域对应，所述第一凹陷具有第三深度，所述第二凹陷具有第四深度；
    c13、在所述第一凹陷和所述第二凹陷处对所述钝化层和所述光阻材料层进行蚀刻，以在所述钝化层上形成所述凹槽阵列和所述孔洞。
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