WO2017008334A1 - Tft基板结构及其制作方法 - Google Patents

Tft基板结构及其制作方法 Download PDF

Info

Publication number
WO2017008334A1
WO2017008334A1 PCT/CN2015/085164 CN2015085164W WO2017008334A1 WO 2017008334 A1 WO2017008334 A1 WO 2017008334A1 CN 2015085164 W CN2015085164 W CN 2015085164W WO 2017008334 A1 WO2017008334 A1 WO 2017008334A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
metal oxide
oxide semiconductor
amorphous silicon
strip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/085164
Other languages
English (en)
French (fr)
Inventor
吕晓文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/778,079 priority Critical patent/US9525070B1/en
Publication of WO2017008334A1 publication Critical patent/WO2017008334A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT substrate structure and a method of fabricating the same.
  • Amorphous silicon is the most widely used semiconductor layer material in the semiconductor industry.
  • A-Si materials are in contact with metals, it is difficult to form ohmic contacts because of the large potential difference.
  • the ohmic contact between them generally super-does the P element on the semiconductor surface, reduces the contact resistance between the metal and the semiconductor, and improves the current efficiency.
  • FIG. 1 is a schematic cross-sectional view showing a structure of a conventional TFT substrate.
  • the TFT substrate structure includes a substrate 100, a gate electrode 200 disposed on the substrate 100, a gate insulating layer 300 disposed on the substrate 100 and covering the gate electrode 200, and corresponding to the gate electrode 200.
  • the amorphous silicon layer 400 on the gate insulating layer 300 and the source 500 and the drain 600 provided on the amorphous silicon layer 400 and the gate insulating layer 300 are described.
  • the central portion of the amorphous silicon layer 400 is recessed downward, and a channel region 450 is formed above the gate electrode 200; the surface of the amorphous silicon layer 400 is ion-doped corresponding to both sides of the channel region 450.
  • the first and second N-type heavily doped regions 410, 420 are formed.
  • the source 500 and the drain 600 are in contact with the surfaces of the first and second N-type heavily doped regions 410, 420, respectively.
  • FIG. 2 is a graph showing leakage current of an A-Si device having the TFT substrate structure of FIG. 1.
  • the TFT substrate structure of FIG. 1 has a certain operating current (Ion), and there is also a certain
  • Ion operating current
  • the problem is that when a negative voltage is applied to a certain level, a positive charge is formed to form a hole conducting channel, and a leakage current (Ioff) is also increased, and the curve warpage is severe, causing a problem of reliability.
  • An object of the present invention is to provide a TFT substrate structure in which a metal oxide semiconductor layer is used instead of the N-type heavily doped layer, and a barrier between the metal oxide semiconductor layer and the metal layer is small, an ohmic contact can be formed, and current efficiency is improved. And reduce leakage current.
  • Another object of the present invention is to provide a method for fabricating a TFT substrate structure by forming a metal oxide semiconductor layer on an amorphous silicon layer instead of an N-type heavily doped layer, and a barrier between the metal oxide semiconductor layer and the metal layer. Smaller, can form ohmic contacts, no need to dope other ions to form N The type of heavily doped layer reduces the leakage current of the hole conducting region and slows the curve warping, thereby improving the reliability of the TFT substrate structure.
  • the present invention provides a TFT substrate structure including a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the substrate and covering the gate electrode, and the gate insulating layer disposed on the gate electrode.
  • the second metal layer includes a first strip-shaped channel corresponding to the top of the gate, and a source and a drain respectively disposed on opposite sides of the first strip-shaped channel;
  • the active layer includes an amorphous silicon layer and a metal oxide semiconductor layer disposed on the amorphous silicon layer;
  • the metal oxide semiconductor layer includes a second strip corresponding to the first strip-shaped channel a channel, and first and second metal oxide semiconductor segments disposed on opposite sides of the second strip-shaped channel and respectively corresponding to the source and the drain;
  • the amorphous silicon layer corresponding to the second strip a channel region is formed under the channel, and a thickness of the channel region on the amorphous silicon layer is less than or equal to a thickness of other regions;
  • the source and the drain are respectively in contact with the surfaces of the first metal oxide semiconductor segment and the second metal oxide semiconductor segment, and the source and the first metal oxide semiconductor segment are distributed on the substrate
  • the area is the same, and the drain and the second metal oxide semiconductor segment have the same area distributed on the substrate.
  • the material of the metal oxide semiconductor layer is IGZO.
  • the invention also provides a method for fabricating a TFT substrate structure, comprising the following steps:
  • Step 1 providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer to form a gate;
  • Step 2 sequentially depositing a gate insulating layer, an amorphous silicon layer, a metal oxide semiconductor layer, and a second metal layer on the substrate and the gate; the amorphous silicon layer and the metal oxide semiconductor layer are active Floor;
  • Step 3 patterning the second metal layer and the metal oxide semiconductor layer by using a photolithography process; forming a first strip-shaped channel corresponding to the gate on the second metal layer, And a source and a drain respectively disposed on two sides of the first strip-shaped channel; forming a second strip-shaped channel corresponding to the first strip-shaped channel on the metal oxide semiconductor layer, and separately providing a first metal oxide semiconductor segment and a second metal oxide semiconductor segment on both sides of the second strip-shaped channel; a channel formed on the amorphous silicon layer corresponding to a position below the second strip-shaped channel a region, and the thickness of the amorphous silicon layer on the channel region is equal to the thickness of the other regions;
  • the source and the drain are respectively in contact with the surfaces of the first metal oxide semiconductor segment and the second metal oxide semiconductor segment, and the source and the first metal oxide semiconductor segment are distributed on the substrate The same area, the drain and the second metal oxide semiconductor segment are distributed on the substrate The area is the same.
  • the method further includes the step of: surface-treating the amorphous silicon layer located in the channel region, removing the residual metal oxide semiconductor layer located above the channel region, and the thickness of the amorphous silicon layer on the channel region after the treatment remains Equal to the thickness of other areas.
  • the method further includes a step 4' of partially etching the amorphous silicon layer located in the channel region by using the source, the drain, and the first and second metal oxide semiconductor segments as an etch barrier layer, thereby causing the non- The thickness of the crystalline silicon layer on the channel region is smaller than the thickness of other regions.
  • the step 2 deposits the gate insulating layer and the amorphous silicon layer by chemical vapor deposition, and deposits the metal oxide semiconductor layer by physical vapor deposition.
  • the step 3 performs a patterning process on the second metal layer and the metal oxide semiconductor layer by a wet etching process.
  • the step 4 etches the amorphous silicon layer located in the channel region by a dry etching process.
  • the substrate is a glass substrate
  • the material of the gate is a stack combination of one or more of molybdenum, titanium, aluminum and copper.
  • the material of the metal oxide semiconductor layer is IGZO.
  • the invention also provides a method for fabricating a TFT substrate structure, comprising the following steps:
  • Step 1 providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer to form a gate;
  • Step 2 sequentially depositing a gate insulating layer, an amorphous silicon layer, a metal oxide semiconductor layer, and a second metal layer on the substrate and the gate; the amorphous silicon layer and the metal oxide semiconductor layer are active Floor;
  • Step 3 patterning the second metal layer and the metal oxide semiconductor layer by using a photolithography process; forming a first strip-shaped channel corresponding to the gate on the second metal layer, And a source and a drain respectively disposed on two sides of the first strip-shaped channel; forming a second strip-shaped channel corresponding to the first strip-shaped channel on the metal oxide semiconductor layer, and separately providing a first metal oxide semiconductor segment and a second metal oxide semiconductor segment on both sides of the second strip-shaped channel; a channel formed on the amorphous silicon layer corresponding to a position below the second strip-shaped channel a region, and the thickness of the amorphous silicon layer on the channel region is equal to the thickness of the other regions;
  • the source and the drain are respectively in contact with the surfaces of the first metal oxide semiconductor segment and the second metal oxide semiconductor segment, and the source and the first metal oxide semiconductor segment are distributed on the substrate The same area, the drain and the second metal oxide semiconductor segment are distributed on the substrate in the same area;
  • step 2 deposits the gate insulating layer and the amorphous silicon layer by chemical vapor deposition, and deposits the metal oxide semiconductor layer by physical vapor deposition;
  • step 3 the second metal layer and the metal oxide semiconductor layer are patterned by a wet etching process
  • the substrate is a glass substrate
  • the material of the gate is a stack combination of one or more of molybdenum, titanium, aluminum and copper;
  • the material of the metal oxide semiconductor layer is IGZO.
  • a metal oxide semiconductor layer is disposed on the amorphous silicon layer instead of the N-type heavily doped layer, and a barrier between the amorphous silicon layer and the metal layer is small, and an ohmic layer can be formed. Contact to improve current efficiency.
  • the barrier between the amorphous silicon layer and the metal layer is small, and an ohmic contact can be formed.
  • FIG. 1 is a schematic cross-sectional view showing a structure of a conventional TFT substrate
  • FIG. 2 is a graph showing leakage current of an A-Si device having the TFT substrate structure of FIG. 1;
  • FIG. 3 is a cross-sectional view showing a first embodiment of a TFT substrate structure of the present invention.
  • FIG. 4 is a cross-sectional view showing a second embodiment of a TFT substrate structure of the present invention.
  • FIG. 5 is a graph comparing curves of leakage current of an A-Si device having the TFT substrate structure of FIG. 4 and leakage current of an A-Si device having the TFT substrate structure of FIG. 1;
  • FIG. 6 is a flow chart showing a method of fabricating a TFT substrate structure of the present invention.
  • step 7 is a schematic diagram of step 1 of a method for fabricating a TFT substrate structure according to the present invention.
  • FIG. 8 is a schematic view showing the second step of the method for fabricating the TFT substrate structure of the present invention.
  • the present invention firstly provides a TFT substrate structure, including a substrate 1, a gate 2 disposed on the substrate 1, and a gate insulation disposed on the substrate 1 to cover the gate 2.
  • the layer 3 includes an active layer 4 disposed on the gate insulating layer 3 and a second metal layer 5 disposed on the active layer 4.
  • the second metal layer 5 includes a first strip-shaped channel 51 corresponding to the gate 2 and a source 52 and a drain 53 respectively disposed on opposite sides of the first strip-shaped channel 51.
  • the active layer 4 includes an amorphous silicon layer 41 and a metal oxide semiconductor layer 42 disposed on the amorphous silicon layer 41;
  • the metal oxide semiconductor layer 42 includes a first strip channel corresponding to the first a second strip-shaped channel 421 of 51, and first and second metal-oxide-semiconductor segments 422, 423 disposed on opposite sides of the second strip-shaped channel 421 and corresponding to the source and drain electrodes 52, 53, respectively;
  • a channel region 415 is formed on the amorphous silicon layer 41 corresponding to a position below the second strip-shaped channel 421, and the thickness of the amorphous silicon layer 41 on the channel region 415 is less than or equal to the thickness of other regions.
  • the source 52 and the drain 52 are in contact with the surfaces of the first metal oxide semiconductor segment 422 and the second metal oxide semiconductor segment 423, respectively, and the source 52 and the first metal oxide semiconductor segment
  • the area of 422 distributed on the substrate 1 is the same, and the area where the drain electrode 53 and the second metal oxide semiconductor segment 423 are distributed on the substrate 1 is the same.
  • first strip-shaped channel 51 and the second strip-shaped channel 421 have the same width and are smaller than the width of the gate 2 .
  • FIG 3 is a schematic cross-sectional view showing a first embodiment of a TFT substrate structure according to the present invention, wherein the amorphous silicon layer 41 has a thickness in the channel region 415 equal to the thickness of other regions.
  • FIG. 4 is a schematic cross-sectional view showing a second embodiment of the TFT substrate structure of the present invention, wherein the thickness of the amorphous silicon layer 41 on the channel region 415 is smaller than the thickness of other regions.
  • the substrate 1 is a glass substrate.
  • the material of the gate 2, the source 52 and the drain 53 may be a stacked combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the material of the gate insulating layer 3 may be silicon oxide, silicon nitride, or a combination of both.
  • the material of the metal oxide semiconductor layer 5 is IGZO (Indium Gallium Zinc Oxide).
  • FIG. 5 is a graph comparing curves of leakage current of an A-Si device having the TFT substrate structure of FIG. 4 and leakage current of an A-Si device having the TFT substrate structure of FIG. 1, wherein "N+” represents the TFT having FIG.
  • the leakage current Ioff of the A-Si device of the substrate structure changes with the gate voltage Vg
  • "IGZO" represents the curve of the leakage current Ioff of the A-Si device having the TFT substrate structure of FIG. 4 as a function of the gate voltage Vg, from FIG.
  • an IGZO layer is provided on the amorphous silicon layer instead of the N-type heavily doped layer, and a barrier between the IGZO layer and the source/drain is small, an ohmic contact can be formed, and current efficiency is improved.
  • the present invention also provides a method of fabricating a TFT substrate structure.
  • a method for fabricating a TFT substrate structure of the present invention includes the following steps:
  • Step 1 As shown in FIG. 7, a substrate 1 is provided, a first metal layer is deposited on the substrate 1, and the first metal layer is patterned to form a gate 2.
  • the substrate 1 is a glass substrate.
  • the material of the gate 2 may be a stacked combination of one or more of molybdenum, titanium, aluminum, and copper.
  • Step 2 sequentially depositing a gate insulating layer 3, an amorphous silicon layer 41, a metal oxide semiconductor layer 42, and a second metal layer 5 on the substrate 1 and the gate 2;
  • the crystalline silicon layer 41 and the metal oxide semiconductor layer 42 constitute the active layer 4.
  • the gate insulating layer 3 and the amorphous silicon layer 41 are deposited by a chemical vapor deposition (CVD) method, and the metal oxide semiconductor layer 42 and the second metal layer are deposited by a physical vapor deposition (PVD) method. 5.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • the material of the gate insulating layer 3 may be silicon oxide, silicon nitride, or a combination of the two.
  • the material of the metal oxide semiconductor layer 42 is IGZO.
  • the material of the second metal layer 5 may be a stacked combination of one or more of molybdenum, titanium, aluminum, and copper.
  • Step 3 referring to FIG. 3, patterning the second metal layer 5 and the metal oxide semiconductor layer 42 by a photolithography process; forming a gate corresponding to the gate on the second metal layer 5 a first strip-shaped channel 51 on the upper side, and a source 52 and a drain 53 respectively disposed on opposite sides of the first strip-shaped channel 51; forming a corresponding to the first on the metal oxide semiconductor layer 42 a second strip-shaped channel 421 of the strip-shaped channel 51, and first and second metal-oxide-semiconductor segments 422, 423 respectively disposed on opposite sides of the second strip-shaped channel 421; the amorphous silicon layer 41 A channel region 415 is formed corresponding to a position below the second strip-shaped channel 421, and a thickness of the amorphous silicon layer 41 on the channel region 415 is equal to a thickness of other regions;
  • the source 52 and the drain 52 are in contact with the surfaces of the first metal oxide semiconductor segment 422 and the second metal oxide semiconductor segment 423, respectively, and the source 52 and the first metal oxide semiconductor segment
  • the area of 422 distributed on the substrate 1 is the same, and the area where the drain electrode 53 and the second metal oxide semiconductor segment 423 are distributed on the substrate 1 is the same.
  • first strip-shaped channel 51 and the second strip-shaped channel 421 have the same width and small The width of the gate 2 is.
  • the second metal layer 5 and the metal oxide semiconductor layer 42 are patterned by a wet etching process; the etching conditions need to be debugged during the wet etching process to avoid an Undercut phenomenon.
  • step 3 If the step 3 is completed, no metal oxide semiconductor layer 42 remains above the amorphous silicon layer 41 of the channel region 415, that is, the step 3 can place the metal oxide semiconductor layer 42 over the channel region 415. If the etching is clean, no further steps are required, and the TFT substrate structure as shown in FIG. 3 is obtained;
  • step 3 does not etch the metal oxide semiconductor layer 42 over the channel region 415, proceed to step 4 or step 4':
  • Step 4 surface treatment is performed on the amorphous silicon layer 41 located in the channel region 415 to remove the residual metal oxide semiconductor layer 42 located above the channel region 415. After the processing, the amorphous silicon layer 41 is located in the channel region. The thickness of 415 is still equal to the thickness of other regions, resulting in a TFT substrate structure as shown in FIG.
  • Step 4 ′ partially etching the amorphous silicon layer 41 located in the channel region 415 by using the source, the drains 52 and 53 , and the first and second metal oxide semiconductor segments 52 and 53 as an etch barrier layer. Therefore, the thickness of the amorphous silicon layer 41 on the channel region 415 is smaller than that of the other regions, and finally the TFT substrate structure as shown in FIG. 4 is obtained.
  • the amorphous silicon layer 41 located in the channel region 415 is etched by a dry etching process.
  • the barrier between the IGZO layer and the source/drain is small, and ohmic contact can be formed.
  • no need to dope other ions to form an N-type heavily doped layer and because there are many defects in the IGZO layer that trap holes, even if a large negative pressure is applied to the gate during TFT operation, hole conduction is formed.
  • Channels and holes are also difficult to pass from the source/drain through the IGZO layer and the amorphous silicon layer to the conductive path, which improves the leakage problem of the hole conduction region of the conventional TFT substrate structure, and improves the hole current warpage and the reliability. Poor sex.
  • a metal oxide semiconductor layer is disposed on the amorphous silicon layer instead of the N-type heavily doped layer, and a barrier between the amorphous silicon layer and the metal layer is small, and an ohmic contact can be formed.
  • Improve current efficiency in the method for fabricating the TFT substrate structure of the present invention, by forming a metal oxide semiconductor layer on the amorphous silicon layer instead of the N-type heavily doped layer, the barrier between the amorphous silicon layer and the metal layer is small, and an ohmic contact can be formed.

Landscapes

  • Thin Film Transistor (AREA)

Abstract

提供一种TFT基板结构及其制作方法，通过在非晶硅层（41）上形成金属氧化物半导体层（42）代替N型重掺杂层，非晶硅层（41）与金属层（5）间的势垒较小，可形成欧姆接触，提高电流效率，无需再掺杂其它离子形成N型重掺杂层，并且由于金属氧化物半导体层（42）中有很多俘获空穴的缺陷，在TFT工作过程中即使栅极（2）施加很大负压，形成空穴导电通道，空穴也很难由源/漏极（52，53）通过金属氧化物半导体层（42）及半导体层到达导电通道，改善了传统TFT基板结构的空穴导电区的漏电问题，同时改善了空穴电流翘曲严重、信赖性差的问题。

Description

TFT基板结构及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板结构及其制作方法。
背景技术
非晶硅(A-Si)是目前半导体行业应用最广泛的半导体层材料，A-Si材料与金属接触时因为有较大的势能差，难以形成欧姆接触，实际应用中，为了获得金属和半导体之间的欧姆接触，一般对半导体表面进行重掺杂P元素，降低金属和半导体的接触阻抗，提高电流效率。
图1所示为一种现有TFT基板结构的剖面示意图。该TFT基板结构包括基板100、设于所述基板100上的栅极200、设于所述基板100上覆盖所述栅极200的栅极绝缘层300、对应所述栅极200上方设于所述栅极绝缘层300上的非晶硅层400、及设于非晶硅层400与所述栅极绝缘层300上的源极500与漏极600。所述非晶硅层400的中部向下凹陷，对应所述栅极200的上方形成有沟道区450；所述非晶硅层400表面对应所述沟道区450的两侧分别经过离子掺杂，形成有第一、第二N型重掺杂区410、420。所述源极500与漏极600分别与所述第一、第二N型重掺杂区410、420的表面相接触。
图2为具有图1的TFT基板结构的A-Si器件的漏电流的曲线图，从图2中可以看出，图1的TFT基板结构在增大工作电流(Ion)的同时，也存在一定的问题，当加负电压到一定程度时，会引出正电荷形成空穴导电通道，漏电流(Ioff)也随之增大，曲线翘曲严重，造成信赖性的问题。
因此，有必要提供一种TFT基板结构及其制作方法，以解决上述问题。
发明内容
本发明的目的在于提供一种TFT基板结构，采用金属氧化物半导体层代替N型重掺杂层，金属氧化物半导体层与金属层间的势垒较小，可形成欧姆接触，提高电流效率，并降低漏电流。
本发明的目的还在于提供一种TFT基板结构的制作方法，通过在非晶硅层上形成金属氧化物半导体层以代替N型重掺杂层，金属氧化物半导体层与金属层间的势垒较小，可形成欧姆接触，无需再掺杂其它离子形成N 型重掺杂层，同时使得空穴导电区的漏电流降低，曲线翘曲变缓，提升了TFT基板结构的信赖性。
为实现上述目的，本发明提供一种TFT基板结构，包括基板、设于所述基板上的栅极、设于所述基板上覆盖所述栅极的栅极绝缘层、设于所述栅极绝缘层上的有源层、及设于所述有源层上的第二金属层；
所述第二金属层包括一对应于所述栅极上方的第一条形通道、及分别设于所述第一条形通道两侧的源极与漏极；
所述有源层包括非晶硅层及设于所述非晶硅层上的金属氧化物半导体层；所述金属氧化物半导体层包括一对应于所述第一条形通道的第二条形通道、及设于所述第二条形通道两侧且分别对应所述源、漏极的第一、第二金属氧化物半导体段；所述非晶硅层上对应于所述第二条形通道下方的位置形成沟道区，所述非晶硅层上位于沟道区的厚度小于或等于其它区域的厚度；
所述源极与漏极分别与所述第一金属氧化物半导体段、及第二金属氧化物半导体段的表面相接触，且所述源极与第一金属氧化物半导体段在基板上分布的面积相同，所述漏极与第二金属氧化物半导体段在基板上分布的面积相同。
所述金属氧化物半导体层的材料为IGZO。
本发明还提供一种TFT基板结构的制作方法，包括如下步骤：
步骤1、提供基板，在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极；
步骤2、依次在所述基板与栅极上沉积栅极绝缘层、非晶硅层、金属氧化物半导体层、及第二金属层；所述非晶硅层与金属氧化物半导体层构成有源层；
步骤3、采用一道光刻制程对所述第二金属层及金属氧化物半导体层进行图案化处理；在所述第二金属层上形成一对应于所述栅极上方的第一条形通道、及分别设于所述第一条形通道两侧的源极与漏极；在所述金属氧化物半导体层上形成一对应于所述第一条形通道的第二条形通道、及分别设于所述第二条形通道两侧的第一金属氧化物半导体段、及第二金属氧化物半导体段；所述非晶硅层上对应于所述第二条形通道下方的位置形成沟道区，且所述非晶硅层上位于沟道区的厚度等于其它区域的厚度；
所述源极与漏极分别与所述第一金属氧化物半导体段、及第二金属氧化物半导体段的表面相接触，且所述源极与第一金属氧化物半导体段在基板上分布的面积相同，所述漏极与第二金属氧化物半导体段在基板上分布 的面积相同。
还包括步骤4、对位于沟道区的非晶硅层进行表面处理，去除位于沟道区上方的残留的金属氧化物半导体层，处理后所述非晶硅层上位于沟道区的厚度依然等于其它区域的厚度。
还包括步骤4’、以所述源、漏极、及第一、第二金属氧化物半导体段为刻蚀阻挡层，对位于沟道区的非晶硅层进行部分蚀刻，从而使得所述非晶硅层上位于沟道区的厚度小于其它区域的厚度。
所述步骤2采用化学气相沉积法沉积所述栅极绝缘层、及非晶硅层，采用物理气相沉积法沉积所述金属氧化物半导体层。
所述步骤3采用湿法蚀刻制程对所述第二金属层及金属氧化物半导体层进行图案化处理。
所述步骤4采用干法蚀刻制程对位于沟道区的非晶硅层进行蚀刻。
所述步骤1中，所述基板为玻璃基板，所述栅极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
所述步骤2中，所述金属氧化物半导体层的材料为IGZO。
本发明还提供一种TFT基板结构的制作方法，包括如下步骤：
步骤1、提供基板，在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极；
步骤2、依次在所述基板与栅极上沉积栅极绝缘层、非晶硅层、金属氧化物半导体层、及第二金属层；所述非晶硅层与金属氧化物半导体层构成有源层；
步骤3、采用一道光刻制程对所述第二金属层及金属氧化物半导体层进行图案化处理；在所述第二金属层上形成一对应于所述栅极上方的第一条形通道、及分别设于所述第一条形通道两侧的源极与漏极；在所述金属氧化物半导体层上形成一对应于所述第一条形通道的第二条形通道、及分别设于所述第二条形通道两侧的第一金属氧化物半导体段、及第二金属氧化物半导体段；所述非晶硅层上对应于所述第二条形通道下方的位置形成沟道区，且所述非晶硅层上位于沟道区的厚度等于其它区域的厚度；
所述源极与漏极分别与所述第一金属氧化物半导体段、及第二金属氧化物半导体段的表面相接触，且所述源极与第一金属氧化物半导体段在基板上分布的面积相同，所述漏极与第二金属氧化物半导体段在基板上分布的面积相同；
其中，所述步骤2采用化学气相沉积法沉积所述栅极绝缘层、及非晶硅层，采用物理气相沉积法沉积所述金属氧化物半导体层；
其中，所述步骤3采用湿法蚀刻制程对所述第二金属层及金属氧化物半导体层进行图案化处理；
其中，所述步骤1中，所述基板为玻璃基板，所述栅极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合；
其中，所述步骤2中，所述金属氧化物半导体层的材料为IGZO。
本发明的有益效果：本发明的TFT基板结构，非晶硅层上设有金属氧化物半导体层代替N型重掺杂层，非晶硅层与金属层间的势垒较小，可形成欧姆接触，提高电流效率。本发明的TFT基板结构的制作方法，通过在非晶硅层上形成金属氧化物半导体层代替N型重掺杂层，非晶硅层与金属层间的势垒较小，可形成欧姆接触，提高电流效率，无需再掺杂其它离子形成N型重掺杂层，并且由于金属氧化物半导体层中有很多抓空穴的缺陷，在TFT工作过程中即使栅极施加很大负压，形成空穴导电通道，空穴也很难由源/漏极通过金属氧化物半导体层及半导体层到达导电通道，改善了传统TFT基板结构的空穴导电区的漏电问题，同时改善了空穴电流翘曲严重，信赖性差的问题。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为一种现有TFT基板结构的剖面示意图；
图2为具有图1的TFT基板结构的A-Si器件的漏电流的曲线图；
图3为本发明的TFT基板结构第一实施例的剖面示意图；
图4为本发明的TFT基板结构第二实施例的剖面示意图；
图5为具有图4的TFT基板结构的A-Si器件的漏电流与具有图1的TFT基板结构的A-Si器件的漏电流的曲线对比图；
图6为本发明的TFT基板结构的制作方法的流程图；
图7为本发明的TFT基板结构的制作方法的步骤1的示意图；
图8为本发明的TFT基板结构的制作方法的步骤2的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3-4，本发明首先提供一种TFT基板结构，包括基板1、设于所述基板1上的栅极2、设于所述基板1上覆盖所述栅极2的栅极绝缘层3、设于所述栅极绝缘层3上的有源层4、及设于所述有源层4上的第二金属层5。
所述第二金属层5包括一对应于所述栅极2上方的第一条形通道51、及分别设于所述第一条形通道51两侧的源极52与漏极53。
所述有源层4包括非晶硅层41及设于所述非晶硅层41上的金属氧化物半导体层42；所述金属氧化物半导体层42包括一对应于所述第一条形通道51的第二条形通道421、及设于所述第二条形通道421两侧且分别对应所述源、漏极52、53的第一、第二金属氧化物半导体段422、423；所述非晶硅层41上对应于所述第二条形通道421下方的位置形成沟道区415，所述非晶硅层41上位于沟道区415的厚度小于或等于其它区域的厚度。
所述源极52与漏极52分别与所述第一金属氧化物半导体段422、及第二金属氧化物半导体段423的表面相接触，且所述源极52与第一金属氧化物半导体段422在基板1上分布的面积相同，所述漏极53与第二金属氧化物半导体段423在基板1上分布的面积相同。
具体的，所述第一条形通道51与第二条形通道421的宽度相同，且小于所述栅极2的宽度。
如图3所示，为本发明的TFT基板结构第一实施例的剖面示意图，其中，所述非晶硅层41上位于沟道区415的厚度等于其它区域的厚度。
如图4所示，为本发明的TFT基板结构第二实施例的剖面示意图，其中，所述非晶硅层41上位于沟道区415的厚度小于其它区域的厚度。
具体的，所述基板1为玻璃基板。
所述栅极2、源极52与漏极53的材料可以是钼、钛、铝和铜中的一种或多种的堆栈组合。
所述栅极绝缘层3的材料可以是氧化硅、氮化硅、或二者的组合。
具体的，所述金属氧化物半导体层5的材料为IGZO(Indium Gallium Zinc Oxide，氧化铟镓锌)。
图5为具有图4的TFT基板结构的A-Si器件的漏电流与具有图1的TFT基板结构的A-Si器件的漏电流的曲线对比图，其中，“N+”代表具有图1的TFT基板结构的A-Si器件的漏电流Ioff随栅电压Vg变化的曲线，“IGZO”代表具有图4的TFT基板结构的A-Si器件的漏电流Ioff随栅电压Vg变化的曲线，从图5中可以看出，与具有图1(现有技术)的TFT基板结构的A-Si器件相比，具有图4(本发明)的TFT基板结构的A-Si器件 的漏电流Ioff降低，曲线的翘曲变缓(虚线框内所示)，提高了A-Si器件的信赖性。
上述TFT基板结构中，非晶硅层上设有IGZO层以代替N型重掺杂层，IGZO层与源/漏极间的势垒较小，可形成欧姆接触，提高电流效率。
基于同一发明构思，本发明还提供一种TFT基板结构的制作方法。
请参阅图6，本发明的TFT基板结构的制作方法包括如下步骤：
步骤1、如图7所示，提供基板1，在所述基板1上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极2。
具体的，所述基板1为玻璃基板。所述栅极2的材料可以是钼、钛、铝和铜中的一种或多种的堆栈组合。
步骤2、如图8所示，依次在所述基板1与栅极2上沉积栅极绝缘层3、非晶硅层41、金属氧化物半导体层42、及第二金属层5；所述非晶硅层41与金属氧化物半导体层42构成有源层4。
具体的，采用化学气相沉积(CVD)法沉积所述栅极绝缘层3、及非晶硅层41，采用物理气相沉积(PVD)法沉积所述金属氧化物半导体层42、及第二金属层5。
具体的，所述栅极绝缘层3的材料可以是氧化硅、氮化硅、或二者的组合。
所述金属氧化物半导体层42的材料为IGZO。
所述第二金属层5的材料可以是钼、钛、铝和铜中的一种或多种的堆栈组合。
步骤3、请参阅图3，采用一道光刻制程对所述第二金属层5及金属氧化物半导体层42进行图案化处理；在所述第二金属层5上形成一对应于所述栅极2上方的第一条形通道51、及分别设于所述第一条形通道51两侧的源极52与漏极53；在所述金属氧化物半导体层42上形成一对应于所述第一条形通道51的第二条形通道421、及分别设于所述第二条形通道421两侧的第一、第二金属氧化物半导体段422、423；所述非晶硅层41上对应于所述第二条形通道421下方的位置形成沟道区415，且所述非晶硅层41上位于沟道区415的厚度等于其它区域的厚度；
所述源极52与漏极52分别与所述第一金属氧化物半导体段422、及第二金属氧化物半导体段423的表面相接触，且所述源极52与第一金属氧化物半导体段422在基板1上分布的面积相同，所述漏极53与第二金属氧化物半导体段423在基板1上分布的面积相同。
具体的，所述第一条形通道51与第二条形通道421的宽度相同，且小 于所述栅极2的宽度。
具体的，采用湿法蚀刻制程对所述第二金属层5及金属氧化物半导体层42进行图案化处理；在湿蚀刻过程中需要对蚀刻条件进行调试以避免产生Undercut(底切)现象。
如果所述步骤3进行完之后，位于沟道区415的非晶硅层41上方没有金属氧化物半导体层42残留，即所述步骤3能够将位于沟道区415上方的金属氧化物半导体层42蚀刻干净的话，就无需再进行其它步骤，得到如图3所示的TFT基板结构；
如果所述步骤3没有将位于沟道区415上方的金属氧化物半导体层42蚀刻干净的话，则继续进行步骤4或步骤4’：
步骤4、对位于沟道区415的非晶硅层41进行表面处理，去除位于沟道区415上方的残留的金属氧化物半导体层42，处理后所述非晶硅层41上位于沟道区415的厚度依然等于其它区域的厚度，得到如图3所示的TFT基板结构。
步骤4’、以所述源、漏极52、53、及第一、第二金属氧化物半导体段52、53为刻蚀阻挡层，对位于沟道区415的非晶硅层41进行部分蚀刻，从而使得所述非晶硅层41上位于沟道区415的厚度小于其它区域的厚度，最终制得如图4所示的TFT基板结构。
具体的，采用干法蚀刻制程对位于沟道区415的非晶硅层41进行蚀刻。
上述TFT基板结构的制作方法，通过在非晶硅层上形成IGZO层，以代替传统结构中的N型重掺杂层，IGZO层与源/漏极间的势垒较小，可形成欧姆接触，提高电流效率，无需再掺杂其它离子形成N型重掺杂层，并且由于IGZO层中有很多抓空穴的缺陷，在TFT工作过程中即使栅极施加很大负压，形成空穴导电通道，空穴也很难由源/漏极通过IGZO层及非晶硅层到达导电通道，改善了传统TFT基板结构的空穴导电区的漏电问题，同时改善了空穴电流翘曲严重，信赖性差的问题。
综上所述，本发明的TFT基板结构，非晶硅层上设有金属氧化物半导体层代替N型重掺杂层，非晶硅层与金属层间的势垒较小，可形成欧姆接触，提高电流效率。本发明的TFT基板结构的制作方法，通过在非晶硅层上形成金属氧化物半导体层代替N型重掺杂层，非晶硅层与金属层间的势垒较小，可形成欧姆接触，提高电流效率，无需再掺杂其它离子形成N型重掺杂层，并且由于金属氧化物半导体层中有很多抓空穴的缺陷，在TFT工作过程中即使栅极施加很大负压，形成空穴导电通道，空穴也很难由源/漏极通过金属氧化物半导体层及半导体层到达导电通道，改善了传统TFT 基板结构的空穴导电区的漏电问题，同时改善了空穴电流翘曲严重，信赖性差的问题。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (14)

  1. 一种TFT基板结构，包括基板、设于所述基板上的栅极、设于所述基板上覆盖所述栅极的栅极绝缘层、设于所述栅极绝缘层上的有源层、及设于所述有源层上的第二金属层；
    所述第二金属层包括一对应于所述栅极上方的第一条形通道、及分别设于所述第一条形通道两侧的源极与漏极；
    所述有源层包括非晶硅层及设于所述非晶硅层上的金属氧化物半导体层；所述金属氧化物半导体层包括一对应于所述第一条形通道的第二条形通道、及设于所述第二条形通道两侧且分别对应所述源、漏极的第一、第二金属氧化物半导体段；所述非晶硅层上对应于所述第二条形通道下方的位置形成沟道区，所述非晶硅层上位于沟道区的厚度小于或等于其它区域的厚度；
    所述源极与漏极分别与所述第一金属氧化物半导体段、及第二金属氧化物半导体段的表面相接触，且所述源极与第一金属氧化物半导体段在基板上分布的面积相同，所述漏极与第二金属氧化物半导体段在基板上分布的面积相同。
  2. 如权利要求1所述的TFT基板结构，其中，所述金属氧化物半导体层的材料为IGZO。
  3. 一种TFT基板结构的制作方法，包括如下步骤：
    步骤1、提供基板，在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极；
    步骤2、依次在所述基板与栅极上沉积栅极绝缘层、非晶硅层、金属氧化物半导体层、及第二金属层；所述非晶硅层与金属氧化物半导体层构成有源层；
    步骤3、采用一道光刻制程对所述第二金属层及金属氧化物半导体层进行图案化处理；在所述第二金属层上形成一对应于所述栅极上方的第一条形通道、及分别设于所述第一条形通道两侧的源极与漏极；在所述金属氧化物半导体层上形成一对应于所述第一条形通道的第二条形通道、及分别设于所述第二条形通道两侧的第一金属氧化物半导体段、及第二金属氧化物半导体段；所述非晶硅层上对应于所述第二条形通道下方的位置形成沟道区，且所述非晶硅层上位于沟道区的厚度等于其它区域的厚度；
    所述源极与漏极分别与所述第一金属氧化物半导体段、及第二金属氧 化物半导体段的表面相接触，且所述源极与第一金属氧化物半导体段在基板上分布的面积相同，所述漏极与第二金属氧化物半导体段在基板上分布的面积相同。
  4. 如权利要求3所述的TFT基板结构的制作方法，其中，还包括步骤4、对位于沟道区的非晶硅层进行表面处理，去除位于沟道区上方的残留的金属氧化物半导体层，处理后所述非晶硅层上位于沟道区的厚度依然等于其它区域的厚度。
  5. 如权利要求3所述的TFT基板结构的制作方法，其中，还包括步骤4’、以所述源、漏极、及第一、第二金属氧化物半导体段为刻蚀阻挡层，对位于沟道区的非晶硅层进行部分蚀刻，从而使得所述非晶硅层上位于沟道区的厚度小于其它区域的厚度。
  6. 如权利要求3所述的TFT基板结构的制作方法，其中，所述步骤2采用化学气相沉积法沉积所述栅极绝缘层、及非晶硅层，采用物理气相沉积法沉积所述金属氧化物半导体层。
  7. 如权利要求3所述的TFT基板结构的制作方法，其中，所述步骤3采用湿法蚀刻制程对所述第二金属层及金属氧化物半导体层进行图案化处理。
  8. 如权利要求5所述的TFT基板结构的制作方法，其中，所述步骤4’采用干法蚀刻制程对位于沟道区的非晶硅层进行蚀刻。
  9. 如权利要求3所述的TFT基板结构的制作方法，其中，所述步骤1中，所述基板为玻璃基板，所述栅极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
  10. 如权利要求3所述的TFT基板结构的制作方法，其中，所述步骤2中，所述金属氧化物半导体层的材料为IGZO。
  11. 一种TFT基板结构的制作方法，包括如下步骤：
    步骤1、提供基板，在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极；
    步骤2、依次在所述基板与栅极上沉积栅极绝缘层、非晶硅层、金属氧化物半导体层、及第二金属层；所述非晶硅层与金属氧化物半导体层构成有源层；
    步骤3、采用一道光刻制程对所述第二金属层及金属氧化物半导体层进行图案化处理；在所述第二金属层上形成一对应于所述栅极上方的第一条形通道、及分别设于所述第一条形通道两侧的源极与漏极；在所述金属氧化物半导体层上形成一对应于所述第一条形通道的第二条形通道、及分别 设于所述第二条形通道两侧的第一金属氧化物半导体段、及第二金属氧化物半导体段；所述非晶硅层上对应于所述第二条形通道下方的位置形成沟道区，且所述非晶硅层上位于沟道区的厚度等于其它区域的厚度；
    所述源极与漏极分别与所述第一金属氧化物半导体段、及第二金属氧化物半导体段的表面相接触，且所述源极与第一金属氧化物半导体段在基板上分布的面积相同，所述漏极与第二金属氧化物半导体段在基板上分布的面积相同；
    其中，所述步骤2采用化学气相沉积法沉积所述栅极绝缘层、及非晶硅层，采用物理气相沉积法沉积所述金属氧化物半导体层；
    其中，所述步骤3采用湿法蚀刻制程对所述第二金属层及金属氧化物半导体层进行图案化处理；
    其中，所述步骤1中，所述基板为玻璃基板，所述栅极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合；
    其中，所述步骤2中，所述金属氧化物半导体层的材料为IGZO。
  12. 如权利要求11所述的TFT基板结构的制作方法，其中，还包括步骤4、对位于沟道区的非晶硅层进行表面处理，去除位于沟道区上方的残留的金属氧化物半导体层，处理后所述非晶硅层上位于沟道区的厚度依然等于其它区域的厚度。
  13. 如权利要求11所述的TFT基板结构的制作方法，其中，还包括步骤4’、以所述源、漏极、及第一、第二金属氧化物半导体段为刻蚀阻挡层，对位于沟道区的非晶硅层进行部分蚀刻，从而使得所述非晶硅层上位于沟道区的厚度小于其它区域的厚度。
  14. 如权利要求13所述的TFT基板结构的制作方法，其中，所述步骤4’采用干法蚀刻制程对位于沟道区的非晶硅层进行蚀刻。
PCT/CN2015/085164 2015-07-14 2015-07-27 Tft基板结构及其制作方法 Ceased WO2017008334A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/778,079 US9525070B1 (en) 2015-07-27 2015-07-27 TFT substrate structure and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510411724.XA CN104966697B (zh) 2015-07-14 2015-07-14 Tft基板结构及其制作方法
CN201510411724.X 2015-07-14

Publications (1)

Publication Number Publication Date
WO2017008334A1 true WO2017008334A1 (zh) 2017-01-19

Family

ID=54220715

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/085164 Ceased WO2017008334A1 (zh) 2015-07-14 2015-07-27 Tft基板结构及其制作方法

Country Status (2)

Country Link
CN (1) CN104966697B (zh)
WO (1) WO2017008334A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105390510B (zh) * 2015-12-14 2018-06-01 武汉华星光电技术有限公司 低温多晶硅tft基板及其制作方法
CN106328587A (zh) * 2016-08-26 2017-01-11 深圳市华星光电技术有限公司 一种阵列基板及其制作方法、液晶显示面板
CN106784016B (zh) * 2017-01-25 2020-03-31 京东方科技集团股份有限公司 一种薄膜晶体管、制作方法、显示基板及显示装置
CN109935627A (zh) * 2019-01-21 2019-06-25 上海易密值半导体技术有限公司 薄膜晶体管
US12211854B2 (en) 2020-12-10 2025-01-28 Infovision Optoelectronics (Kunshan) Co., Ltd. Array substrate and manufacturing method therefor, and display panel

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080258143A1 (en) * 2007-04-18 2008-10-23 Samsung Electronics Co., Ltd. Thin film transitor substrate and method of manufacturing the same
CN101814455A (zh) * 2009-02-19 2010-08-25 乐金显示有限公司 制造阵列基板的方法
KR20110077264A (ko) * 2009-12-30 2011-07-07 엘지디스플레이 주식회사 박막 트랜지스터 및 그 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080258143A1 (en) * 2007-04-18 2008-10-23 Samsung Electronics Co., Ltd. Thin film transitor substrate and method of manufacturing the same
CN101814455A (zh) * 2009-02-19 2010-08-25 乐金显示有限公司 制造阵列基板的方法
KR20110077264A (ko) * 2009-12-30 2011-07-07 엘지디스플레이 주식회사 박막 트랜지스터 및 그 제조 방법

Also Published As

Publication number Publication date
CN104966697B (zh) 2017-06-27
CN104966697A (zh) 2015-10-07

Similar Documents

Publication Publication Date Title
US9882055B2 (en) TFT substrate structure and manufacturing method thereof
US10229978B2 (en) Semiconductor device and manufacturing method thereof
CN104966720B (zh) Tft基板结构及其制作方法
TWI725433B (zh) 半導體裝置的製作方法
WO2017008334A1 (zh) Tft基板结构及其制作方法
WO2014148255A1 (ja) 窒化物半導体装置および窒化物半導体装置の製造方法
WO2017008332A1 (zh) Tft基板结构及其制作方法
CN108878515B (zh) 薄膜晶体管及其制备方法、阵列基板
JP2018157100A (ja) 窒化物半導体装置
WO2015155828A1 (ja) 半導体装置及びその製造方法
US9741826B1 (en) Transistor structure
CN112805837B (zh) 栅控二极管及芯片
CN112786699A (zh) 高电子迁移率晶体管及其制作方法
US9525070B1 (en) TFT substrate structure and manufacturing method thereof
CN106409917B (zh) 半导体装置以及半导体装置的制造方法
EP4020588A1 (en) Method for processing a fet device
KR102280449B1 (ko) 산화물 박막트랜지스터의 제조방법
CN105308721B (zh) 在氮化镓器件和集成电路中制备自对准隔离的方法
JP5564790B2 (ja) 半導体装置及びその製造方法
KR20160084923A (ko) 박막 트랜지스터 기판 및 그 제조 방법
JP6517535B2 (ja) シリコン系薄膜半導体装置、およびシリコン系薄膜半導体装置の製造方法
CN109148299B (zh) 半导体装置及其制造方法
US10186430B2 (en) Transistor and method of manufacturing the same
US20130237010A1 (en) Method for manufacturing a gate-control diode semiconductor memory device
CN105390509B (zh) 一种阵列基板的制作方法、阵列基板及液晶面板

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14778079

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15898061

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15898061

Country of ref document: EP

Kind code of ref document: A1