WO2017004869A1 - 模数转换器误差估计校正的装置及其方法 - Google Patents

模数转换器误差估计校正的装置及其方法 Download PDF

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WO2017004869A1
WO2017004869A1 PCT/CN2015/087676 CN2015087676W WO2017004869A1 WO 2017004869 A1 WO2017004869 A1 WO 2017004869A1 CN 2015087676 W CN2015087676 W CN 2015087676W WO 2017004869 A1 WO2017004869 A1 WO 2017004869A1
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correction
error
signal
clock
unit
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PCT/CN2015/087676
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English (en)
French (fr)
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蒲杰
胡刚毅
沈晓峰
徐学良
付东兵
张瑞涛
王友华
王育新
陈光炳
李儒章
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中国电子科技集团公司第二十四研究所
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Priority to US15/742,835 priority Critical patent/US10291245B2/en
Publication of WO2017004869A1 publication Critical patent/WO2017004869A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
    • H03M1/0609—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1028—Calibration at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing

Definitions

  • the present invention belongs to the technical field of Analog-to-Digital Converter (ADC), and more particularly, to an apparatus and method for gain and clock phase error estimation correction of a dual-channel time division multiplex converter.
  • ADC Analog-to-Digital Converter
  • TI ADCs time-interleaved analog-to-digital converters
  • M channel sub-ADCs each channel sub-ADC operates at Fs/M, where Fs is the sampling rate of the TI ADC.
  • the output from each channel sub-ADC is combined in Fs using a multiplexer (MUX) to produce a sample rate converter operating in Fs.
  • MUX multiplexer
  • the existing error estimation correction method is a conventional statistical method based on M.Seo et al., which mainly uses the ADC's own input sampling signal to estimate and correct the error parameter, and the calibration does not affect the ADC itself, as long as the input
  • the sampled signal is a band-limited generalized stationary random signal, and the signal is larger than a certain range, and the gain and clock phase error estimation can be eliminated.
  • the accuracy of the estimation is proportional to the number of sample points of the effective input sampling signal used for each estimation.
  • the estimation effect is not good. Will cause estimation errors, which will affect the correction effect;
  • a single estimate increases the time used for a single estimate when the number of sample points of the valid input sample signal used is large, reducing the convergence rate of the real-time estimation correction.
  • an object of the present invention is to provide an apparatus for error estimation correction of an analog-to-digital converter and a method thereof for solving the prior art, when using a sample with higher conversion accuracy requirements When there are more points, the time required for a single estimation is increased, resulting in a problem that the estimation convergence is slower.
  • an apparatus for error correction of an analog to digital converter At least include:
  • the dual-channel time division multiplexing analog-to-digital converter is adapted to sample the reference channel signal and the correction clock signal respectively in the reference channel and the correction channel to generate corresponding first digital signals and second digital signals;
  • the adaptive digital signal processor is adapted to calculate a clock phase error estimation result and a gain error estimation result of the second digital signal according to the preset initial value of the calibration parameter update unit and the first digital signal and the second digital signal,
  • the correction parameter update unit initial value includes a gain correction parameter initial value and a time correction parameter initial value; and is further adapted to adopt a gradient descent method, update a time correction parameter according to the clock phase error estimation result, and according to the gain error
  • the estimation result updates the gain correction parameters.
  • an adaptive digital signal processor for use in an analog to digital converter error estimation correction apparatus, the adaptive digital signal processor comprising at least:
  • a gain correcting unit configured to perform gain correction on the second digital signal according to the initial value of the gain correction parameter to generate a second path correction signal
  • a buffer unit configured to buffer the first digital channel signal and the second path correction signal
  • the segmentation error estimating unit is adapted to invoke the first digital channel signal and the second path correction signal, and is processed by a cyclic correlation method to generate a preliminary estimation result, wherein the preliminary estimation result includes a preliminary estimation of the gain error
  • the result is initially estimated with the clock phase error
  • a low-pass filter accumulating unit configured to process the preliminary estimation result when the corresponding set signal is received, to generate an error estimation result
  • a counting unit configured to send a set signal to the low pass filter accumulating unit and the correction parameter updating unit according to a sampling period of the clock signal, and send a reset signal to each unit;
  • the correction parameter updating unit is adapted to update the clock correction parameter and the gain correction parameter according to a gradient descent method when receiving the corresponding set signal, and latch the updated clock correction parameter and the gain correction parameter.
  • the method further includes:
  • a delay unit comprising: a fixed delay unit and a numerical control analog delay unit, wherein the fixed delay unit is adapted to set a time delay in the reference channel, generate a reference clock delay amount, and control the first digital signal a clock phase; the numerical control analog delay unit is adapted to generate a control signal according to the time correction parameter, and fine-tune a clock phase of the second digital signal.
  • Another object of the present invention is to provide a method for error correction of an analog to digital converter, the method comprising:
  • Step 1 preset a correction parameter update unit initial value, where the correction parameter update unit initial value includes a clock correction parameter initial value and a gain correction parameter initial value;
  • Step 2 calling the clock correction parameter initial value decoding to generate a control signal, and fine-tuning the numerical control according to the control signal Simulating the delay amount of the delay unit, correcting the phase error of the sampling clock of the second digital signal with respect to the sampling clock of the first digital signal;
  • Step 3 performing gain correction on the second digital signal according to the initial value of the gain correction parameter, generating a second correction signal, buffering and coupling the first digital signal and the second correction signal to generate an overall correction Signal and trigger the counting unit to start counting;
  • Step 4 calling the buffered first digital signal and the second correction signal, and processing by using a cyclic correlation method to generate a preliminary estimation result;
  • Step 5 when the counting unit counts to a preset value, and the clock signal edge time comes, setting an enable end of the low-pass filter accumulating unit and the correction parameter updating unit to generate the preliminary estimation result An error estimation result, and updating and latching the clock correction parameter and the gain correction parameter according to the error estimation result.
  • the apparatus and method for correcting the error of the analog-to-digital converter of the present invention have the following beneficial effects:
  • auxiliary analog signals, and the estimation correction process does not depend on the specific circuit implementation structure of the sub-ADC; and the number of valid sample points required for each estimation is small, and the requirement for effective signal duration is reduced in real-time correction, and the estimation is accelerated. Correcting the speed of convergence; and in the case of the same error estimation accuracy, when using the single estimation method to correct the error estimation, the sample points of the sample can be greatly reduced, and the correction convergence speed of the error estimation is also greatly reduced. .
  • FIG. 1 is a flow chart showing a method for correcting error estimation of an analog-to-digital converter according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of an analog-to-digital converter error estimation and correction apparatus according to an embodiment of the present invention
  • FIG. 3 is a clock signal diagram of an analog-to-digital converter error estimation correction apparatus according to an embodiment of the present invention.
  • FIG. 4 is a block diagram showing the structure of a gain correcting unit in an adaptive signal processor according to an embodiment of the present invention
  • FIG. 5 is a block diagram showing the structure of a cache unit in an adaptive signal processor according to an embodiment of the present invention.
  • FIG. 6 is a block diagram showing the structure of a segmentation error estimation unit and a low-pass filter accumulation unit in an adaptive signal processor according to an embodiment of the present invention
  • FIG. 8 is a graph showing convergence curves of an analog-to-digital converter error estimation corrected clock phase error correction parameter according to an embodiment of the present invention.
  • FIG. 9 is a simulation diagram showing dynamic performance comparison of an analog-to-digital converter error estimation correction according to an embodiment of the present invention.
  • FIG. 10 is a simulation diagram showing dynamic performance comparison of an analog-to-digital converter error estimation correction according to an embodiment of the present invention
  • FIG. 11 is a simulation diagram showing dynamic performance before correction using a conventional statistical method based correction method in an embodiment of the present invention
  • FIG. 12 is a diagram showing a dynamic performance simulation after correction using a conventional statistical method based correction method in an embodiment of the present invention.
  • FIG. 1 a flow chart of a method for error correction of an analog-to-digital converter in an embodiment of the present invention is shown.
  • Step 1 the initial value of the correction parameter updating unit 6 is preset, wherein the initial value of the correction parameter updating unit 6 includes a clock correction parameter initial value, a gain correction parameter initial value, and a parameter update step initial value;
  • the parameter update step size may be a fixed value or a set of parameters, and the clock correction parameter and the gain correction parameter may both be fixed values.
  • Step 2 calling the clock correction parameter initial value decoding to generate a control signal, fine-tuning the delay amount of the numerical control analog delay unit 10 according to the control signal, and correcting the sampling clock of the second digital signal relative to the first digital signal Sampling time Phase error of the clock;
  • the analog-to-digital converter in the present invention is a dual-channel time division multiplexing analog-to-digital converter, wherein the first channel sub-ADC is used as a reference channel, and a fixed delay unit 9 is disposed in the reference channel to obtain the reference channel. Outputting a reference clock delay amount; using the second channel sub-ADC as a correction channel, setting the numerical control analog delay unit 10 in the correction channel, and acquiring a corrected clock delay amount output by the correction channel;
  • Step 3 Decoding the clock correction parameter into a binary code, wherein the binary code is a control signal, and when the actual delay amount corresponding to the control signal is less than the reference clock delay amount, shifting the second digital number forward a clock phase of the signal; when the actual delay amount corresponding to the control signal is greater than the reference clock delay amount, shifting the clock phase of the second digital signal backward.
  • Step 3 performing gain correction on the second digital signal according to the initial value of the gain correction parameter, generating a second correction signal, buffering and coupling the first digital signal and the second correction signal to generate an overall correction Signal, and trigger counting unit 7 to start counting;
  • a multiplier is used to obtain a product of the second digital signal and the gain correction parameter, and an adder is used to obtain a sum of an output of the multiplier and the second digital signal;
  • the sum of the gain correction parameter and the original multiple is obtained by an adder, and a product of the second digital signal and the output of the adder is obtained by a multiplier.
  • the gain error correction is performed according to the second digital signal, and the second correction signal is output, and the timings of the first digital signal and the second correction signal are aligned, and the multiplexer 8 is coupled.
  • a digital signal and a second correction signal generate an overall correction signal.
  • the counting unit 7 is triggered to start counting.
  • Step 4 calling the first digital signal and the second correction signal in the buffer, and processing by using a cyclic correlation method to generate a preliminary estimation result;
  • the preliminary estimation result includes a preliminary estimation result of the gain error and a preliminary estimation result of the clock phase error.
  • Step 5 when the counting unit 7 counts to a preset value, and the clock signal edge time comes, the enable ends of the low-pass filter accumulating unit 5 and the correction parameter updating unit 6 are set, and the preliminary The estimation result generates an error estimation result, and updates and latches the clock correction parameter and the gain correction parameter according to the error estimation result;
  • the preliminary estimation result is processed to generate an error
  • the error estimation result includes a gain error estimation result and a clock phase error estimation result.
  • the enable end of the correction parameter updating unit 6 is set, the error estimation result is latched, and the error estimation result is called. Updating the clock correction parameter and the gain correction parameter according to a gradient descent method, and latching the updated clock correction parameter and the gain correction parameter;
  • the counting unit 7 sets the two time nodes according to the period of the clock signal, respectively sets the low-pass filter accumulating unit 5 and the correction parameter updating unit 6; when the counting unit 7 counts When the set value is reached, when the period of the clock signal is cycled to the set signal, the low-pass filter accumulating unit 5 and the correction parameter updating unit 6 are set.
  • step 5 when the counting unit 7 outputs a reset signal, resetting the buffer unit 3, the low-pass filter accumulating unit 5, the correction parameter updating unit 6, the The segmentation error estimating unit 4, the low-pass filtering accumulating unit 5 and the enabling end of the counting unit 7, and repeating steps 2 to 5.
  • the operating clocks of the gain correcting unit 2, the buffer unit 3, the counting unit 7, the segmentation error estimating unit 4, and the low-pass filter accumulating unit 5 are the clock signals
  • the period of the clock signal completes setting the enable terminals of the low pass filter accumulating unit and the correction parameter updating unit 6, and resetting the respective units in the adaptive digital signal processor.
  • the analog-to-digital converter can also be a multi-channel time division multiplexing analog-to-digital converter, wherein one of the channels is used as a reference channel, and the reference channel is used as a reference signal, and the remaining channels in the multiple channels need to be corrected channels, and the same reason.
  • the sampling signals in the multi-channel correction channel are calculated.
  • the multi-channel time division multiplexing analog-to-digital converter is a three-channel time division multiplexing analog-to-digital converter
  • the first channel is a reference channel
  • the digital signals are all reference signals
  • the second clock signal and the third channel clock signal corresponding to the second channel and the third channel, and the second digital signal and the third digital signal are both required for error estimation correction.
  • the delay amount corresponding to the first clock signal is used as the reference delay
  • the second clock signal is based on the second clock correction parameter (the first correction is the clock correction parameter initial value)
  • the numerical control analog delay unit 10 acquires a binary-based control signal according to the second clock correction parameter, and fine-tunes the clock phase of the second clock signal according to the control signal, thereby achieving the purpose of correcting the clock phase error.
  • the third clock signal needs to be corrected
  • the second clock signal corrected by the current time is used as a reference standard, and a binary-based control signal is obtained according to the third clock correction parameter, and the third road is fine-tuned according to the control signal. Clock phase of the clock signal, thus reaching the correction The purpose of the clock phase error.
  • the second digital signal is corrected by using the first digital signal as a standard, and the gain correcting unit 2 generates the second corrected signal according to the second digital gain correction parameter (Note: The first gain error correction is based on the initial value of the second gain correction parameter.
  • the third-channel digital signal gain error is corrected, the second-channel correction signal corresponding to the output of the second digital signal is used as a standard, and the gain of the third-channel digital signal is corrected according to the third-channel gain correction parameter, and a third is generated. Road correction signal.
  • the clock correction parameter and the gain correction parameter are continuously updated according to the gain error estimation result and the clock phase error estimation result, and multiple cyclic error estimation and correction are completed, so that the final correction is performed. Accuracy is more accurate.
  • N M ⁇ (N 1 -N 2 )+N 1 (2)
  • the clock signal generator of the TI ADC In a two-channel time division multiplexing analog-to-digital converter (TI ADC) correction, the clock signal generator of the TI ADC generates a first clock signal and a second clock signal according to a clock signal; the first clock signal and The second clock signal is a clock signal having the same period and 180 degrees out of phase, and the first channel sub-ADC samples and holds the input signal during the period of the first clock signal to provide a first path.
  • the digital signal is a reference signal; the second channel sub-ADC samples and holds the input signal over a period of the two-way clock signal to provide a second digital signal as a signal to be corrected.
  • DCDC digital control delay cell
  • the adaptive signal processor Outputting the error estimation result, and using the gradient descent method to implement the update and convergence of the correction parameter according to the error estimation result; in the feedback processing, the adaptive signal processor outputs the control signal according to the clock phase error correction parameter, and controls the numerical control analog delay unit 10 The amount of delay reaches the purpose of correcting the clock phase error; the adaptive signal processor outputs the first digital signal and the second corrected signal, and is synthesized into a TI ADC output signal through the multiplexer 8 (MUX). (ie the overall correction signal).
  • MUX multiplexer 8
  • FIG. 2 is a schematic structural diagram of an apparatus for estimating an error of an analog-to-digital converter according to an embodiment of the present invention, including:
  • the dual-channel time division multiplexing analog-to-digital converter is adapted to sample the reference channel signal and the correction clock signal respectively in the reference channel and the correction channel to generate corresponding first digital signals and second digital signals;
  • the clock generation circuit 1 generates two clock signals, wherein the two clock signals are the reference clock signal and the corrected clock signal, and the period is the same, and the phase difference is approximately 180 degrees, when the first digital signal in the reference channel is used as a standard. , performing gain correction of the second digital signal, and correcting the clock phase of the correction channel by using a fixed delay in the analog clock signal collected in the analog-to-digital converter reference channel, so that the corrected clock phase is closest to 180 degree.
  • a delay unit comprising a fixed delay unit 9 and a digitally controlled analog delay unit 10, wherein the fixed delay unit 9 is adapted to set a time delay in the reference channel, generate a reference clock delay amount, and control the first path The clock phase of the digital signal; the numerical control analog delay unit 10 is adapted to generate a control signal according to the time correction parameter, and fine-tune the clock phase of the second digital signal;
  • a multiplexer 8 adapted to couple the second corrected digital signal and the first digital signal to output an overall correction signal
  • An adaptive digital signal processor configured to calculate a clock phase error estimation result and a gain error estimate of the second digital signal according to the preset initial value of the calibration parameter updating unit 6 and the second digital signal and the first digital signal a result, wherein the correction parameter updating unit 6 initial value includes a gain correction parameter initial value and a time correction parameter initial value; and is further adapted to adopt a gradient descent method, update a time correction parameter according to the clock phase error estimation result, and The gain error estimation result updates the gain correction parameter.
  • the adaptive digital signal processor comprises:
  • the gain correcting unit 2 is adapted to perform gain correction on the second digital signal according to the initial value of the gain correction parameter to generate a second path correction signal;
  • the buffer unit 3 is adapted to buffer the first digital channel signal and the second path correction signal
  • the segmentation error estimation unit 4 is adapted to invoke the first digital signal and the second correction signal, and is processed by a cyclic correlation method to generate a preliminary estimation result, wherein the preliminary estimation result includes a preliminary estimation of the gain error
  • the result is initially estimated with the clock phase error
  • the segmentation error estimation unit 4 includes a gain error estimation subunit and a clock phase error estimation subunit, and the gain error estimation subunit calculates a gain error loss function according to the cyclic correlation method, and generates a corresponding preliminary estimation of the gain error.
  • the clock phase error estimation sub-unit calculates a clock phase error loss function according to the cyclic correlation method, and generates a corresponding preliminary estimation result of the clock phase error.
  • the low-pass filter accumulating unit 5 is adapted to process the preliminary estimation result when the corresponding set signal is received, to generate an error estimation result;
  • the low-pass filter accumulating unit 5 includes at least one accumulating unit, or includes at least one low-pass filter and one accumulating unit.
  • the counting unit 7 is adapted to respectively send a set signal to the low pass filter accumulating unit and the correction parameter updating unit 6 according to the sampling period of the clock signal and the preset value, and send a reset signal to each unit when the sampling ends;
  • the correction parameter updating unit 6 is adapted to update the clock correction parameter and the gain correction parameter according to a gradient descent method when receiving the corresponding set signal, and latch the updated clock correction parameter and the gain correction parameter .
  • the clock correction parameter is updated, and the sampling period of the second clock signal relative to the first clock signal can be changed, so that the clock displacement of the analog signals sampled by the two is closer to 180 degrees, and the gain correction is updated.
  • the parameter can change the gain error of the second digital signal relative to the first digital signal, and improve the error correction precision.
  • FIG. 3 it is a clock signal pulse diagram of an analog-to-digital converter error estimation correction device according to an embodiment of the present invention.
  • the clock signal clock includes a first clock signal clock1 and a second clock signal clock2.
  • the first clock signal clock1 and the second clock signal clock2 are the same period and have a 180° difference clock signal.
  • the fixed channel delay unit 9 is inserted into the reference channel ADC, and the digitally controlled analog delay unit 10 (DCDC) is inserted into the correction channel ADC clock path, and the clock correction parameter is obtained according to the clock correction parameter output by the correction parameter updating unit 6.
  • DCDC digitally controlled analog delay unit 10
  • An output signal of the two channel sub-ADCs (including the first digital signal and the second digital signal), and the gain correcting unit 2 performs gain correction on the output signal according to the gain correction parameter to generate a second path correction a signal
  • the multiplexer 8MUX coupling the first digital signal and the second correction signal to generate an overall ADC output signal (ie, an overall correction signal)
  • the first digital signal and the second correction signal are input to the buffer unit 3
  • the buffering is performed, and the trigger counting unit 7 starts counting.
  • the counting unit 7 counts the set value
  • the low-pass filtering accumulating unit 5 enable signal (when the counting unit 7 count value is equal to N 1 ) and the set correction parameter are respectively set.
  • the update unit 6 enables the signal (when the count value of the counting unit 7 is equal to N); the buffer signal of the buffer unit 3 is called, and the segmentation error estimating unit 4 generates the initial digital signal and the second corrected signal according to the cyclic correlation method. Estimation result; when the low-pass filter accumulating unit enable terminal is set, the preliminary estimation result is input to the low-pass filter accumulating unit for estimation of the error value, and the error estimation knot is output. ; When the correction parameter updating unit 6 so that the end can be set, a result to the error correction estimation parameter updating unit 6, update the clock correction parameters and the gain correction parameters, and the latch clock correction parameters and the updating of the gain correction parameter.
  • the reset buffer unit 3, the segmentation error estimating unit 4, the register values in the low-pass filter accumulating unit 5 and the counting unit 7, and the reset correction parameter updating unit 6 enable signal and the low-pass filter accumulating unit 5 enable signal;
  • the correction of the error amount is achieved by continuous feedback, and the purpose of real-time tracking and accurate error estimation correction is achieved.
  • a single channel 250 MHz, dual channel time interleaved 500 MHz sampling rate 14-bit A/D converter is taken as an example for specific description.
  • the two channel sub-ADCs sample the input signal in parallel, the first clock signal and the second clock signal are 180 degrees out of phase with each other, and the sampling period is 4 ns.
  • the DCDC is a digitally controlled analog delay unit 10, which is controlled by 8-bit binary code (0-255), which has a total of 256 codes, and the unit code corresponding adjustment has a delay step of 60 fs.
  • the reference channel ADC clock path is inserted into the same DCDC as the correction channel ADC clock path; wherein the control code of the DCDC in the reference channel ADC clock path is fixed at 128, achieving a fixed delay of 7.68 ps; correcting the channel within the ADC clock path
  • the DCDC control code is determined by the binary code corresponding to the clock correction parameter.
  • the gain correction parameters and the clock correction parameters are set to ⁇ g (k) and ⁇ code (k) , respectively, and the update steps of the gain correction parameters and the clock correction parameters are respectively with
  • the superscript k represents the updated result of the kth correction parameter
  • the binary code of ⁇ code (k) that is, the DCDC control signal in the correction channel ADC
  • the value range of ⁇ code (k) is (0-255) ).
  • Set the initial value of the gain correction parameter to ⁇ g (0) 0 and the initial gain correction amount to 0.
  • Set the initial value of the clock phase correction parameter to ⁇ code (0) 128.
  • the clock delay of the correction channel ADC is consistent with the clock delay of the reference channel ADC, and the initial clock phase correction is 0; when ⁇ code (k)
  • the advance adjustment of the correction channel clock phase is realized, and when ⁇ code (k) is increased, the lag adjustment of the correction channel clock phase is realized.
  • the accuracy of setting the gain correction parameter is 0.0121%, and the initial value of the gain correction parameter update step is Set the accuracy of the clock correction parameter to 1, and the initial value of the clock correction parameter update step.
  • the gain correcting unit 2 corrects the sub-ADC output data of the two channels according to the estimated gain correction parameter ⁇ g (k) , and the operation is as shown in equations (5) and (6):
  • the gradient descent algorithm is used to update the correction parameters.
  • e(u) is the monotonic function of the mismatch error. It can be seen that the gradient of the error loss function is proportional to the error loss function e(u), and the gradient information of the error loss function can be obtained by calculating the error loss function for updating the correction parameters.
  • n is a variable
  • the value range is a natural number.
  • the error loss function is calculated by using the segmentation calculation and the filter accumulation method, and the number of sample points used for a single estimation is reduced under the same estimation precision.
  • the segmentation error estimation unit 4 uses the principles of equations (9) and (10), the segmentation error estimation unit 4 performs operations on the gain error and the clock phase error using the input and output data in the buffer unit 3, and realizes the operation as equation (11). ) and (12):
  • the low-pass filter accumulating unit 5 processes the output result of the segmentation error unit to obtain an error estimation result, and the operation is as shown in equations (13) and (14):
  • the correction parameter updating unit 6 enable signal is set, the outputs g o , ⁇ o of the low-pass filter accumulating unit 5 are latched, and the latched g o , ⁇ o are input to the correction parameter updating unit 6, and the update of the correction parameters is completed by the gradient descent method.
  • the gain correction parameter update expression is:
  • the clock correction parameter update expression is:
  • the correction parameter update is implemented using equations (17) and (19).
  • the binary tree search mode is used to complete the update of the correction parameter update step, that is, after each update of the correction parameter is completed, the update step of the correction parameter is halved until the update step reaches the accuracy of the set correction parameter.
  • the update step size update can also be implemented in other ways.
  • the clock correction parameter is updated once, and the parameter update step corresponding to the clock correction parameter is halved; each time the gain correction parameter is updated, the parameter update step corresponding to the gain correction parameter is halved, and the correction is performed.
  • the implementation expression of the parameter update step size is as shown in equations (21) and (22).
  • the gain error between the two channels is calculated to be 1%
  • the clock phase error is 5.05 ps
  • the ADC inputs a 95.1 MHz sinusoidal signal.
  • the gain error estimation result and the clock phase error estimation result, and the correction of the gain error and the clock phase error are realized by adopting the above method or device for error estimation correction.
  • the convergence curves of the gain error parameter and the clock phase error parameter in the calibration process are respectively shown in FIG. 7 to FIG. 8.
  • the correction parameter is continuously updated, the gain correction parameter and the time correction parameter are updated with the number of times. Increasing, gradually approaching the corresponding ideal correction value, each forming a convergence curve time is shorter.
  • FIG. 9 to FIG. 10 are respectively a simulation diagram of dynamic performance comparison before and after the error estimation of the analog-to-digital converter in the embodiment of the present invention.
  • the device and method for error estimation correction in the invention can effectively suppress the spurious frequency caused by the gain and the clock phase error, and achieve the purpose of accurately estimating the correction.
  • the simulated correction result formed and the number of points adopted by the present invention are N.
  • the sampled clock signal and the second digital signal between the channels are corrected, and the corresponding clock phase error estimates are respectively obtained by the first digital signal and the second corrected signal.
  • the result and the gain error estimation result, the clock phase error estimation result and the gain error estimation result are latched, and the corresponding clock correction parameters and gain correction parameters are obtained, which are respectively fed back to the numerical control analog delay unit 10 and the gain correction unit 2 to implement feedback.
  • the error is precisely adjusted.
  • the estimation correction process only needs to use the output signal normally sampled by the two channel sub-ADCs, without additional extra addition at the sub-ADC input or sub-ADC circuit.
  • auxiliary analog signals, and the estimation correction process does not depend on the specific circuit implementation structure of the sub-ADC; and the number of valid sample points required for each estimation is small, and the requirement for effective signal duration is reduced in real-time correction, Quickly estimate the speed at which the correction converges; and in the case of the same error estimation accuracy, the correction of the error estimate using the single estimation method can greatly reduce the number of sample points sampled, and at the same time greatly reduce the correction of the error estimate. convergence speed. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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Abstract

一种模数转换器误差估计校正的装置及其方法，该方法包括：根据预先设定的校正参数初始值，生成控制信号微调数控模拟延时单元，调节时延量，校正通道间的时钟相位误差；以及根据校正参数初始值校正通道间的增益误差，生成总体校正信号，将总体校正信号缓存并触发计数单元开始计数，同时，调用缓存中的总体校正信号采用循环相关法生成初步估计结果，当计数到预先设定值时，置位低通滤波器累加单元和校正参数更新单元的使能端，将初步估计结果生成误差估计结果并锁存，根据梯度下降法更新时钟校正参数与增益校正参数，并将其锁存，复位进行循环估计校正。该方法在使用有效样本点数较少情况下，提高了估计精度，加快了估计校正收敛速度。

Description

模数转换器误差估计校正的装置及其方法 技术领域
本发明属于模数转换器(Analog-to-Digital Converter、ADC)技术领域，更具体地，特别是涉及一种双通道时分复用转换器的增益和时钟相位误差估计校正的装置及其方法。
背景技术
近年来，在需要极高采样率和采样精度(即，现今单一的ADC无法达到如此之高的采样率和精度)的应用中，时间交错模拟至数字转换器(TI ADC)已越来越备受关注。在使用M个通道子ADC的TI ADC中，每一个通道子ADC以Fs/M操作，其中Fs为TI ADC的采样率。使用多路复用器(MUX)以Fs组合来自每一个通道子ADC的输出以产生一以Fs操作的采样率转换器。但是由于工艺误差、温度、电压以及环境扰动等因素影响下，通道间存在增益以及时钟相位误差并且会随着时间变化，该误差导致在k·fs/L±fin(fs为A/D转换器采样频率，fin为输入信号频率，L为通道数，k＝1，2，…，L-1)处出现误差杂散分量，极大地降低了时间交错ADC的性能。
现有的误差估计校正方法为M.Seo等提出的常规的基于统计方式的方法，其主要是利用ADC自身的输入采样信号对误差参数进行估计校正，并且校正中不影响ADC自身工作，只要输入采样信号是频带受限的广义平稳随机信号，且该信号大于一定范围，就可消除增益和时钟相位误差估计。
然而，该误差估计校正方法存在以下缺点：
第一，在误差校正过程中，估计精度的高低与每次估计使用的有效输入采样信号的样本点数量多少成正比，当使用的有效输入采样信号的样本点较少时，估计效果不佳，会造成估计错误，从而影响校正效果；
第二，单次估计在使用的有效输入采样信号的样本点较多时，增加了单次估计所使用的时间，降低了实时估计校正的收敛速度。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种模数转换器误差估计校正的装置及其方法，用于解决现有技术中，当在较高转换精度要求下，使用样本点较多时，增加了单次估计所需的时间，导致估计校正收敛速度较慢的问题。
为实现上述目的及其他相关目的，提供一种模数转换器误差估计校正的装置，所述装置 至少包括：
双通道时分复用模数转换器，适用于在参考通道与校正通道分别采用参考时钟信号和校正时钟信号进行采样，生成对应的第一路数字信号与第二路数字信号；以及
自适应数字信号处理器，适用于根据预先设定校正参数更新单元初始值以及第一路数字信号和第二路数字信号，计算第二路数字信号的时钟相位误差估计结果与增益误差估计结果，其中所述校正参数更新单元初始值包括增益校正参数初始值与时间校正参数初始值；以及还适用于采用梯度下降法，根据所述时钟相位误差估计结果更新时间校正参数，以及根据所述增益误差估计结果更新增益校正参数。
本发明的目的还在于提供一种应用在模数转换器误差估计校正装置中的自适应数字信号处理器，所述自适应数字信号处理器至少包括：
增益校正单元，适用于根据所述增益校正参数初始值对所述第二路数字信号进行增益校正，生成第二路校正信号；
缓存单元，适用于缓存所述第一路数字路信号与所述第二路校正信号；
分段误差估计单元，适用于调用所述第一路数字路信号与所述第二路校正信号，采用循环相关法进行处理，生成初步估计结果，其中，所述初步估计结果包括增益误差初步估计结果与时钟相位误差初步估计结果；
低通滤波累加单元，适用于接收到对应的置位信号时，对所述初步估计结果进行处理，生成误差估计结果；
计数单元，适用于根据时钟信号的采样周期向低通滤波器累加单元和校正参数更新单元发送置位信号，以及向各个单元发送复位信号；
校正参数更新单元，适用于接收到对应的置位信号时，根据梯度下降法更新所述时钟校正参数与所述增益校正参数，并锁存更新的所述时钟校正参数与所述增益校正参数。
作为上述一种模数转换器误差估计校正的装置的优选方案，还包括：
延时单元，其包括固定时延单元与数控模拟延时单元，所述固定时延单元，适用于在参考通道设定时延，生成参考时钟时延量，控制所述第一路数字信号的时钟相位；所述数控模拟延时单元，适用于根据时间校正参数生成控制信号，微调所述第二路数字信号的时钟相位。
本发明的另一目的在于提供一种模数转换器误差估计校正的方法，所述方法包括：
步骤1，预先设定校正参数更新单元初始值，其中，所述校正参数更新单元初始值包括时钟校正参数初始值与增益校正参数初始值；
步骤2，调用所述时钟校正参数初始值译码生成控制信号，根据所述控制信号微调数控 模拟延时单元的时延量，校正第二路数字信号的采样时钟相对于第一路数字信号的采样时钟的相位误差；
步骤3，根据所述增益校正参数初始值对第二路数字信号进行增益校正，生成第二路校正信号，缓存并耦合所述第一路数字信号与所述第二路校正信号，生成总体校正信号，并触发计数单元开始计数；
步骤4，调用缓存的所述第一路数字信号与所述第二路校正信号，采用循环相关法进行处理，生成初步估计结果；
步骤5，当所述计数单元计数到预先设定值，且所述时钟信号边沿时刻到来时，置位低通滤波器累加单元和校正参数更新单元的使能端，将所述初步估计结果生成误差估计结果，以及根据所述误差估计结果更新并锁存所述时钟校正参数与所述增益校正参数。
如上所述，本发明的模数转换器误差估计校正的装置及其方法，具有以下有益效果：
通过设置自适应信号处理器，校正通道间采样的时钟信号和第二路数字信号，通过所述第一路数字信号和第二路校正信号获取相应的时钟相位误差估计结果与增益误差估计结果，锁存时钟相位误差估计结果、增益误差估计结果，并获取其相应的时钟校正参数与增益校正参数，分别反馈至数控模拟延时单元与增益校正单元，实现反馈的误差精确调整。当TI ADC的模拟输入信号位于奈奎斯特采样带宽内时，估计校正过程仅需要利用两个通道子ADC正常采样的输出信号，不需要额外的在子ADC输入端或者子ADC电路中额外添加其他辅助模拟信号，且估计校正过程不依赖于子ADC具体电路实现结构；以及每次估计所需要使用的有效样本点数较少，在实时校正时，降低了对有效信号持续时间的要求，加快估计校正收敛的速度；并且在相同的误差估计精度情况下，使用单次估计方式进行误差估计的校正时，可大大地减少采样的样本点数，同时，也极大的缩减了误差估计的校正收敛速度。
附图说明
图1显示为本发明实施例中的一种模数转换器误差估计校正的方法流程图；
图2显示为本发明实施例中的一种模数转换器误差估计校正装置的结构示意图；
图3显示为本发明实施例中的一种模数转换器误差估计校正装置时钟信号脉冲图；
图4显示为本发明实施例中的自适应信号处理器中增益校正单元结构框图；
图5显示为本发明实施例中的自适应信号处理器中缓存单元结构框图；
图6显示为本发明实施例中的自适应信号处理器中分段误差估计单元与低通滤波累加单元结构框图；
图7显示为本发明实施例中的模数转换器误差估计校正增益误差校正参数的收敛曲线；
图8显示为本发明实施例中的模数转换器误差估计校正时钟相位误差校正参数的收敛曲线；
图9显示为本发明实施例中的模数转换器误差估计校正前的动态性能对比仿真图；
图10显示为本发明实施例中的模数转换器误差估计校正后的动态性能对比仿真图；
图11显示为本发明实施例中使用常规的基于统计方式的校正方法校正前的动态性能仿真图；
图12显示为本发明实施例中使用常规的基于统计方式的校正方法校正后的动态性能仿真图。
元件标号说明：
1、时钟生成电路，2、增益校正单元，3、缓存单元，4、分段误差估计单元，5、低通滤波累加单元，6、校正参数更新单元，7、计数单元，8、多路复用器，9、固定时延单元，10、数控模拟延时单元。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图12。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
如图1所示，显示为本发明实施例中的一种模数转换器误差估计校正的方法流程图。
步骤1，预先设定校正参数更新单元6初始值，其中，所述校正参数更新单元6初始值包括时钟校正参数初始值、增益校正参数初始值与参数更新步长初始值；
具体地，所述参数更新步长可以为定值或者一组参数，所述时钟校正参数与所述增益校正参数均可以为定值。
步骤2，调用所述时钟校正参数初始值译码生成控制信号，根据所述控制信号微调数控模拟延时单元10的时延量，校正第二路数字信号的采样时钟相对于第一路数字信号的采样时 钟的相位误差；
其中，本文中的模数转换器为双通道时分复用模数转换器，以所述第一通道子ADC为参考通道，在所述参考通道内设置固定时延单元9，获取所述参考通道输出的参考时钟时延量；以所述第二通道子ADC为校正通道，在所述校正通道内设置所述数控模拟延时单元10，获取所述校正通道输出的校正时钟时延量；
所述时钟校正参数译码为二进制编码，以所述二进制编码为控制信号，当所述控制信号对应的实际时延量小于所述参考时钟时延量时，向前平移所述第二路数字信号的时钟相位；当所述控制信号对应的实际时延量大于所述参考时钟时延量时，向后平移所述第二路数字信号的时钟相位。步骤3，根据所述增益校正参数初始值对第二路数字信号进行增益校正，生成第二路校正信号，缓存并耦合所述第一路数字信号与所述第二路校正信号，生成总体校正信号，并触发计数单元7开始计数；
其中，用乘法器获取所述第二路数字信号与所述增益校正参数的乘积，用加法器获取所述乘法器的输出与所述第二路数字信号之和；或者
用加法器获取所述增益校正参数与原始倍数之和，用乘法器获所述第二路数字信号与所述加法器输出之积。
具体的，根据所述第二路数字信号进行增益误差校正，输出第二路校正信号，对齐所述第一路数字信号与所述第二校正信号的时序，采用多路复用器8耦合第一路数字信号与第二路校正信号生成总体校正信号。
具体地，当接收到所述第一路数字信号与所述第二路校正信号时，缓存所述第一路数字信号与所述第二路校正信号，并触发计数单元7开始计数。
步骤4，调用缓存中的所述第一路数字信号与所述第二路校正信号，采用循环相关法进行处理，生成初步估计结果；
其中，所述初步估计结果包括增益误差初步估计结果与时钟相位误差初步估计结果。
具体地，调用所述第一路数字信号与所述第二路校正信号，根据所述循环相关法计算增益误差损失函数，生成相应的增益误差初步估计结果；根据所述循环相关法计算时钟相位误差损失函数，生成相应的时钟相位误差初步估计结果。
步骤5，当所述计数单元7计数到预先设定值，且所述时钟信号边沿时刻到来时，置位低通滤波器累加单元5和校正参数更新单元6的使能端，将所述初步估计结果生成误差估计结果，以及根据所述误差估计结果更新并锁存所述时钟校正参数与所述增益校正参数；
当置位所述低通滤波累加单元5的使能端时，对所述初步估计结果进行处理，生成误差 估计结果，所述误差估计结果包括增益误差估计结果与时钟相位误差估计结果，当置位所述校正参数更新单元6的使能端时，锁存所述误差估计结果，调用所述误差估计结果，根据梯度下降法更新所述时钟校正参数与所述增益校正参数，并锁存更新的所述时钟校正参数与所述增益校正参数；
其中，所述计数单元7通过根据所述时钟信号的周期，设置两个时间节点，分别置位所述低通滤波器累加单元5和所述校正参数更新单元6；当所述计数单元7计数到设定的数值时，根据时钟信号的周期循环到置位信号时，则置位低通滤波累加单元5与校正参数更新单元6。
在最优实施例当中，执行步骤1-5之后，只能粗略的进行误差的估计和校正，并不能精确的计算，达到精确的误差估计校正的目的。因此，执行步骤5之后，还包括：步骤6：当所述计数单元7输出复位信号时，复位所述缓存单元3、所述低通滤波累加单元5、所述校正参数更新单元6、所述分段误差估计单元4、所述低通滤波累加单元5与所述计数单元7的使能端，并重复步骤2至步骤5。
具体地，所述增益校正单元2、所述缓存单元3、所述计数单元7、所述分段误差估计单元4和所述低通滤波累加单元5的工作时钟为所述时钟信号，通过所述时钟信号的周期完成置位低通滤波器累加单元和校正参数更新单元6的使能端，以及复位所述自适应数字信号处理器内各个单元。
另外，所述模数转换器还可以为多通道时分复用模数转换器，以其中的一条通道为参考通道，并以此为参考信号，多通道中的其余通道为需要校正通道，同理，按照模数转换器误差估计校正的方法步骤2至步骤6，依次执行，计算出多通道内校正通道内采样信号。
在本实施例中，当多通道时分复用模数转换器为三通道时分复用模数转换器时，其第一通道为参考通道，第一通道对应的第一路时钟信号与第一路数字信号均为参考信号；第二通道与第三通道对应的第二路时钟信号与第三路时钟信号以及第二路数字信号与第三路数字信号，均为需要误差估计校正。
其中，在时钟相位误差校正时，以第一路时钟信号对应的时延量为参考时延，第二路时钟信号以第二路时钟校正参数为标准(第一次校正以时钟校正参数初始值为标准)，数控模拟延时单元10根据第二路时钟校正参数获取二进制为基础的控制信号，根据控制信号微调第二路时钟信号的时钟相位，从而到达校正时钟相位误差的目的。其次，当第三路时钟信号需要校正时，以当前次校正的第二路时钟信号为参考标准，根据第三路时钟校正参数获取二进制为基础的控制信号，根据所述控制信号微调第三路时钟信号的时钟相位，从而到达校正时 钟相位误差的目的。
在增益误差校正时，以第一路数字信号为标准，校正第二路数字信号，增益校正单元2根据第二路增益校正参数将所述第二路数字信号生成第二路校正信号(注：第一次增益误差校正以第二路增益校正参数初始值为标准)。同理，第三路数字信号增益误差校正时，以第二路数字信号对应输出的第二路校正信号为标准，根据第三路增益校正参数校正第三路数字信号的增益，并生成第三路校正信号。
缓存第一路数字信号，第二路校正信号和第三路校正信号，根据所述循环相关法，计算通道间的增益误差损失函数和时钟相位误差损失函数，生成相应增益误差初步估计结果和时钟相位误差初步估计结果。
在时钟相位误差与增益相位误差的校正过程，将会根据增益误差估计结果与时钟相位误差估计结果，不断地更新时钟校正参数与增益校正参数，完成多次循环误差估计和校正，使最终校正的精度更准确。
在模数转换器校正之前，需要确定单次估计使用的总样本点数N、分段估计处理样点数N1、段间重合样点数N2。
分段数目M满足如下关系式：
Figure PCTCN2015087676-appb-000001
确定分段数目M后，对N进行调整如下：
N＝M·(N1-N2)+N1     (2)
其中符号
Figure PCTCN2015087676-appb-000002
表示取整数下限，必须满足N2＜N1。
实施例1
在双通道时分复用模数转换器(TI ADC)校正中，所述TI ADC的时钟信号发生器根据时钟信号产生第一路时钟信号与第二路时钟信号；所述第一路时钟信号与所述第二路时钟信号为周期相同且相位相差180度的时钟信号，所述第一通道子ADC在所述第一路时钟信号的周期上对输入信号进行采样和保持，以提供第一路数字信号为参考信号；所述第二通道子ADC在所述二路时钟信号的周期上对输入信号进行采样和保持，以提供第二路数字信号为待校正信号。
且在所述第二路数字信号的采样时钟路径中设置数控模拟延时单元10(digital control delay cell，DCDC)，可对时钟相位进行微调从而校正第二路时钟信号相对于第一路时钟信号的相位误差，输出的所述第一路数字信号与所述第二路数字信号进入自适应信号处理器中， 完成增益误差的估计和校正以及时钟相位误差的估计，每次误差估计使用一定数量的样本点，对样本点采用循环相关的方法进行分段处理，输出初步估计结果，初步估计结果进行滤波累加处理输出误差估计结果，根据误差估计结果利用梯度下降法实现校正参数的更新和收敛；在反馈处理中，自适应信号处理器根据时钟相位误差校正参数输出控制信号，控制所述数控模拟延时单元10的时延量，达到校正时钟相位误差的目的；所述自适应信号处理器输出第一路数字信号与第二路校正信号，经过多路复用器8(MUX)后合成为TI ADC输出信号(即总体校正信号)。
如图2所示，为本发明实施例中的一种模数转换器误差估计校正装置的结构示意图，包括：
双通道时分复用模数转换器，适用于在参考通道与校正通道分别采用参考时钟信号和校正时钟信号进行采样，生成对应的第一路数字信号与第二路数字信号；以及
其中，时钟生成电路1生成两路时钟信号，两路时钟信号为参考时钟信号与校正时钟信号，且其周期相同，相位差近似为180度，当按照参考通道内的第一路数字信号为标准，进行第二路数字信号的增益校正，以及以模数转换器参考通道内采集的模拟时钟信号中的固定时延为标准，修正校正通道的时钟相位，以至于校正后时钟相位为最接近180度。
延时单元，其包括固定时延单元9与数控模拟延时单元10，所述固定时延单元9，适用于在参考通道设定时延，生成参考时钟时延量，控制所述第一路数字信号的时钟相位；所述数控模拟延时单元10，适用于根据时间校正参数生成控制信号，微调所述第二路数字信号的时钟相位；
多路复用器8，适用于耦合所述第二路校正数字信号与所述第一路数字信号，输出总体校正信号；
自适应数字信号处理器，适用于根据预先设定校正参数更新单元6初始值以及第二路数字信号与所述第一路数字信号，计算第二数字信号的时钟相位误差估计结果与增益误差估计结果，其中所述校正参数更新单元6初始值包括增益校正参数初始值与时间校正参数初始值；以及还适用于采用梯度下降法，根据所述时钟相位误差估计结果更新时间校正参数，以及根据所述增益误差估计结果更新增益校正参数。
其中，所述自适应数字信号处理器包括：
增益校正单元2，适用于根据所述增益校正参数初始值对第二路数字信号进行增益校正，生成第二路校正信号；
缓存单元3，适用于缓存所述第一路数字路信号与所述第二路校正信号；
分段误差估计单元4，适用于调用所述第一路数字信号与所述第二路校正信号，采用循环相关法进行处理，生成初步估计结果，其中，所述初步估计结果包括增益误差初步估计结果与时钟相位误差初步估计结果；
其中，所述分段误差估计单元4包括增益误差估计子单元与时钟相位误差估计子单元，所述增益误差估计子单元根据所述循环相关法计算增益误差损失函数，生成相应的增益误差初步估计结果；所述时钟相位误差估计子单元据所述循环相关法计算时钟相位误差损失函数，生成相应的时钟相位误差初步估计结果。
低通滤波累加单元5，适用于接收到对应的置位信号时，对所述初步估计结果进行处理，生成误差估计结果；
其中，所述低通滤波累加单元5包括至少一个累加单元，或者包括至少一个低通滤波器与一个累加单元。
计数单元7，适用于根据时钟信号的采样周期以及预先设定值分别向低通滤波器累加单元和校正参数更新单元6发送置位信号，以及采样结束时，向各个单元发送复位信号；
校正参数更新单元6，适用于接收到对应的置位信号时，根据梯度下降法更新所述时钟校正参数与所述增益校正参数，并锁存更新的所述时钟校正参数与所述增益校正参数。
在本实施例中，更新时钟校正参数，可改变第二路时钟信号相对于第一路时钟信号的采样周期，使得两者采样的模拟信号的时钟位移更接近于180度，同时，更新增益校正参数，可改变第二路数字信号相对于第一路数字信号增益误差，提高误差校正精度。
如图3所示，为本发明实施例中的一种模数转换器误差估计校正装置时钟信号脉冲图。
时钟信号clock，其包括第一路时钟信号clock1与第二路时钟信号clock2，所述第一路时钟信号clock1与第二路时钟信号clock2为周期相同且位移相差180度时钟信号。
在本实施例中，参考通道ADC内插入固定时延单元9，校正通道ADC时钟通路中插入数控模拟延时单元10(DCDC)，根据校正参数更新单元6输出的时钟校正参数，将时钟校正参数译成二进制的控制信号，对时钟相位进行微调，达到校正时钟相位误差的目的。两个通道子ADC的输出信号(包括为第一路数字信号与所述第二路数字信号)，根据增益校正参数所述增益校正单元2对所述输出信号进行增益校正，生成第二路校正信号，多路复用器8MUX耦合第一路数字信号与第二路校正信号生成总体ADC输出信号(即总体校正信号)，第一路数字信号与第二路校正信号被输入到缓存单元3，进行缓存，且触发计数单元7开始计数，当计数单元7计数到设定值时，分别置位低通滤波累加单元5使能信号(计数单元7计数值等于N1时)及置位校正参数更新单元6使能信号(计数单元7计数值等于N时)；调用缓存单元3 的缓存信号，分段误差估计单元4根据循环相关法，将第一路数字信号与第二路校正信号生成初步估计结果；当低通滤波器累加单元使能端被置位时，初步估计结果输入到低通滤波器累加单元中进行误差值的估计，并输出误差估计结果；当校正参数更新单元6的使能端被置位时，误差估计结果输入到校正参数更新单元6中，更新时钟校正参数以及增益校正参数，并锁存更新的钟校正参数以及增益校正参数。复位缓存单元3、分段误差估计单元4，低通滤波累加单元5与计数单元7中的寄存器值，以及复位校正参数更新单元6使能信号和低通滤波累加单元5使能信号；重复上述步骤，通过连续的反馈实现误差量的校正收敛，达到实时跟踪与精确误差估计校正的目的。
实施例2
以单通道250MHz，双通道时间交织500MHz采样率14比特A/D转换器为例进行具体说明。当两个通道子ADC并行的对输入信号进行采样，采样时钟之间，第一时钟信号与第二时钟信号相位相差180度，采样周期为4ns。设定参考通道ADC输出数据为y1(n)；校正通道ADC输出数据为y2(n)。DCDC为数控模拟延时单元10，由8比特的二进制编码(0-255)控制，共有256个编码，单位编码对应调节的时延步长为60fs。参考通道ADC时钟通路，插入与校正通道ADC时钟通路内相同的DCDC；其中，参考通道ADC时钟通路内的DCDC的控制编码固定为128，实现固定时延为7.68ps；校正通道ADC时钟通路内的DCDC控制编码由时钟校正参数对应的二进制编码决定。
选取满足公式(1)与公式(2)的总样本点数，确定单次估计使用总样本点数为N＝1000，分段估计处理样本点数为N1＝50，段间重复样本点数为N2＝48，则分段数目M＝475，令N3＝N1-N2＝2。
设定增益校正参数与时钟校正参数分别为Δg(k)和τcode (k)，增益校正参数和时钟校正参数的更新步长分别为
Figure PCTCN2015087676-appb-000003
和
Figure PCTCN2015087676-appb-000004
其中，上标k代表第k次校正参数更新后结果，τcode (k)的二进制编码(即为校正通道ADC中的DCDC控制信号)，那么τcode (k)的数值范围为(0-255)。设定增益校正参数初始值为Δg(0)＝0，初始增益校正量为0。设定时钟相位校正参数初始值为τcode (0)＝128，此时，校正通道ADC的时钟时延量与参考通道ADC的时钟时延量一致，初始时钟相位校正量为0；当τcode (k)减小时，实现对校正通道时钟相位的超前调整，当τcode (k)增大时，实现对校正通道时钟相位的滞后调整。设定增益校正参数的精度为0.0121％，增益校正参数更新步长的初始值为
Figure PCTCN2015087676-appb-000005
设定时钟校正参数的精度为1，时钟校正参数更新步长的初始值为
Figure PCTCN2015087676-appb-000006
自适应处理器中，增益校正单元2依据估计出的增益校正参数Δg(k)对两个通道的子ADC输出数据进行校正，实现操作如式(5)和(6)所示：
x1(n)＝y1(n)      (5)
x2(n)＝y2(n)·(1+Δg(k))    (6)
增益校正单元2的两路输出结果如图4至图6所示，经多路复用器8MUX后合成为总体ADC输出x(n)，其中x(2n)＝x1(n)，x(2n+1)＝x2(n)；同时，所述第一路数字信号与所述第二路校正信号保存至缓存单元3中，用于误差估计。
采用循环相关函数R(n，n′)＝E{x(n)x(n′)}，根据双通道时分复用ADC有R(n，n′)＝R(n+2，n′+2)；定义误差函数为e(u)＝R(u，0)-R(u+1，1)，误差损失函数为P＝argmin(e(u)2)，如果两个通道间不存在失配误差，则P＝0。
如果两个通道间存在失配误差，利用梯度下降算法实现校正参数的更新，e(u)为失配误差的单调函数，由
Figure PCTCN2015087676-appb-000007
可知，误差损失函数的梯度与误差损失函数e(u)成比例，可通过计算误差损失函数获取误差损失函数的梯度信息，用于更新校正参数。
令u＝0，获得增益误差损失函数为：
Figure PCTCN2015087676-appb-000008
令u＝1，获得时钟相位误差损失函数为：
et＝E{x1(n)x2(n)}-E{x1(n+1)x2(n)}     (8)
在实际实现时，取一定长度样本点，计算误差损失函数，数学表达式如下所示：
Figure PCTCN2015087676-appb-000009
Figure PCTCN2015087676-appb-000010
在上述公式中，n为变量，取值范围为自然数，其中通过采用分段计算和滤波累加方式，计算误差损失函数，在相同估计精度下，减少了单次估计使用的样本点数量。
利用式(9)和(10)的原理，分段误差估计单元4，使用缓存单元3中的输入和输出数据进行运算，实现对增益误差以及时钟相位误差的初步估计，实现操作如式(11)和(12)所示：
增益误差初步估计结果
Figure PCTCN2015087676-appb-000011
时钟相位误差初步估计结果
Figure PCTCN2015087676-appb-000012
其中，m＝0，…，M-1。
在分段误差估计单元4使能信号置位后，低通滤波累加单元5对分段误差单元的输出结果进行处理，得到误差估计结果，实现操作如式(13)和(14)所示：
增益误差估计结果
Figure PCTCN2015087676-appb-000013
时钟相位误差估计结果
Figure PCTCN2015087676-appb-000014
其中h(m)为低通滤波器，
Figure PCTCN2015087676-appb-000015
为卷积符号，由于累加本身可视为低通滤波器，本实施例实现中令h(m)＝1，则式(13)和(14)分别简化为：
Figure PCTCN2015087676-appb-000016
Figure PCTCN2015087676-appb-000017
go，τo则为计算出的误差损失函数，在校正参数更新单元6使能信号被置位时，低通滤波累加单元5的输出go、τo被锁存，将锁存的go、τo输入到校正参数更新单元6中，利用梯度下降法，完成校正参数的更新。
增益校正参数更新表达式为：
Figure PCTCN2015087676-appb-000018
或者
Figure PCTCN2015087676-appb-000019
时钟校正参数更新表达式为：
Figure PCTCN2015087676-appb-000020
或者
Figure PCTCN2015087676-appb-000021
其中，sign为符号函数，当go或τo大于等于0时，sign(go/τo)＝1；即0时刻开始，信号的幅度均为1；当go或τo小于0时，sign(go/τo)＝-1；在0时刻之前，信号幅度均为-1。
本实施例中，当所述增益校正参数为公式时，采用公式(17)和(19)实现校正参数更新。
本实施例中采用二叉树搜索方式，完成校正参数更新步长的更新，即每完成一次校正参数的更新后，校正参数的更新步长减半，直至更新步长达到设定的校正参数的精度为止，也可采用其他方式实现更新步长的更新。本实施例中时钟校正参数每更新一次，所述时钟校正参数对应的参数更新步长减半；所述增益校正参数每更新一次，所述增益校正参数对应的参数更新步长减半，且校正参数更新步长的实现表达式如式(21)和(22)所示。
Figure PCTCN2015087676-appb-000022
Figure PCTCN2015087676-appb-000023
可根据假设值，计算出两个通道之间的增益误差为1％，时钟相位误差为5.05ps，ADC输入95.1MHz正弦信号。
在双通道时分复用模数转换器的转换过程中，通过采用上述误差估计校正的方法或装置，实现增益误差估计结果与时钟相位误差估计结果，以及增益误差与时钟相位误差的校正。并且校正过程中增益误差参数与时钟相位误差参数的收敛曲线分别如图7至图8所示，在几次之内随着校正参数的不断更新，增益校正参数与时间校正参数随着更新次数的增加，逐渐趋向对应的理想校正值，各自形成的收敛曲线时间更短。
如图9至图10，分别为本发明实施例中的模数转换器误差估计校正前、后的动态性能对比仿真图。采用本发明中误差估计校正的装置及其方法，能够有效的抑制增益、时钟相位误差导致的杂散频率，达到准确估计校正的目的。如图11为本发明实施例中使用常规的基于统计方式的校正方法校正后的动态性能仿真图，对比图9、图10、图11可知，使用相同样本点数N＝1000，在单次估计的情况下，本发明提出方法比常规方法估计精度更高，校正效果更好；常规方法需使用更多的样本点数才能达到与本发明方法相同的校正精度。
如图12所示，为基于统计方式的校正方法校正后的动态性能仿真图，其采用的样本点数为N＝10000，在单次估计的情况下，形成的仿真校正结果与本发明采用点数N＝1000的校正结果相似，因此，本发明的误差估计校正的装置及其方法相达到同样的校正精度，可大量减少校正采样的样本点数。
综上所述，通过设置自适应信号处理器，校正通道间的采样的时钟信号和第二路数字信号，通过所述第一路数字信号和第二路校正信号分别获取相应的时钟相位误差估计结果与增益误差估计结果，锁存时钟相位误差估计结果、增益误差估计结果，并获取其相应的时钟校正参数与增益校正参数，分别反馈至数控模拟延时单元10与增益校正单元2，实现反馈的误差精确调整。当TI ADC的模拟输入信号位于奈奎斯特采样带宽内时，估计校正过程仅需要利用两个通道子ADC正常采样的输出信号，不需要额外的在子ADC输入端或者子ADC电路中额外添加其他辅助模拟信号，且估计校正过程不依赖于子ADC具体电路实现结构；以及每次估计所需要使用的有效样本点数较少，在实时校正时，降低了对有效信号持续时间的要求，加 快估计校正收敛的速度；并且在相同的误差估计精度情况下，使用单次估计方式进行误差估计的校正时，可大大地减少采样的样本点数，同时，也极大的缩减了误差估计的校正收敛速度。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (15)

  1. 一种模数转换器误差估计校正的装置，其特征在于，至少包括：
    双通道时分复用模数转换器，适用于在参考通道与校正通道分别采用参考时钟信号和校正时钟信号进行采样，生成对应的第一路数字信号与第二路数字信号；以及
    自适应数字信号处理器，适用于根据预先设定校正参数更新单元初始值以及第一路数字信号和第二路数字信号，计算第二路数字信号的时钟相位误差估计结果与增益误差估计结果，其中所述校正参数更新单元初始值包括增益校正参数初始值与时间校正参数初始值；以及还适用于采用梯度下降法，根据所述时钟相位误差估计结果更新时间校正参数，以及根据所述增益误差估计结果更新增益校正参数。
  2. 根据权利要求1所述的模数转换器误差估计校正的装置，其特征在于，所述自适应数字信号处理器至少包括：
    增益校正单元，适用于根据所述增益校正参数初始值对所述第二路数字信号进行增益校正，生成第二路校正信号；
    缓存单元，适用于缓存所述第一路数字信号与所述第二路校正信号；
    分段误差估计单元，适用于调用所述第一路数字信号与所述第二路校正信号，采用循环相关法进行处理，生成初步估计结果，其中，所述初步估计结果包括增益误差初步估计结果与时钟相位误差初步估计结果；
    低通滤波累加单元，适用于接收到对应的置位信号时，对所述初步估计结果进行处理，生成误差估计结果；
    计数单元，适用于根据时钟信号的采样周期以及预先设定值分别向低通滤波器累加单元和校正参数更新单元发送置位信号，以及向各个单元发送复位信号；
    校正参数更新单元，适用于接收到对应的置位信号时，根据梯度下降法更新所述时钟校正参数与所述增益校正参数，并锁存更新的所述时钟校正参数与所述增益校正参数。
  3. 根据权利要求2所述的模数转换器误差估计校正的装置，其特征在于，所述分段误差估计单元包括增益误差估计子单元与时钟相位误差估计子单元，所述增益误差估计子单元，适用于根据所述循环相关法计算增益误差损失函数，生成相应的增益误差初步估计结果；所述时钟相位误差估计子单元，适用于根据所述循环相关法计算时钟相位误差损失函数，生成相应的时钟相位误差初步估计结果。
  4. 根据权利要求2所述的模数转换器误差估计校正的装置，其特征在于，所述低通滤波累加单元包括至少一个累加单元，或者包括至少一个低通滤波器与一个累加单元。
  5. 根据权利要求2所述的模数转换器误差估计校正的装置，其特征在于，所述增益校正单元、所述缓存单元、所述计数单元、所述分段误差估计单元和所述低通滤波累加单元的工作时钟为所述时钟信号。
  6. 根据权利要求1所述的模数转换器误差估计校正的装置，其特征在于，还包括：
    延时单元，其包括固定时延单元与数控模拟延时单元，所述固定时延单元，适用于在参考通道设定时延，生成参考时钟时延量，控制所述第一路数字信号的时钟相位；所述数控模拟延时单元，适用于根据时间校正参数生成控制信号，生成校正时钟时延量，微调所述第二路数字信号的时钟相位，使之与所述第一路数字信号的时钟相位相匹配。
  7. 根据权利要求1所述的模数转换器误差估计校正的装置，其特征在于，所述模数转换器还包括多通道时分复用模数转换器。
  8. 一种模数转换器误差估计校正的方法，其特征在于，包括：
    步骤1，预先设定校正参数更新单元初始值，其中，所述校正参数更新单元初始值包括时钟校正参数初始值与增益校正参数初始值；
    步骤2，调用所述时钟校正参数初始值译码生成控制信号，根据所述控制信号微调数控模拟延时单元的时延量，校正第二路数字信号的采样时钟相对于第一路数字信号的采样时钟的相位误差；
    步骤3，根据所述增益校正参数初始值对第二路数字信号进行增益校正，生成第二路校正信号，缓存并耦合所述第一路数字信号与所述第二路校正信号，生成总体校正信号，并触发计数单元开始计数；
    步骤4，调用缓存的所述第一路数字信号与所述第二路校正信号，采用循环相关法进行处理，生成初步估计结果；
    步骤5，当所述计数单元计数到预先设定值，且所述时钟信号边沿到来时，置位低通滤波器累加单元和校正参数更新单元的使能端，将所述初步估计结果生成误差估计结果，以及根据所述误差估计结果更新并锁存所述时钟校正参数与所述增益校正参数。
  9. 根据权利要求8所述的模数转换器误差估计校正的方法，其特征在于，在所述步骤5之后，还包括：当所述计数单元计数到预先设定值，且所述时钟信号边沿到来时，复位缓存单元、低通滤波累加单元、分段误差估计单元、所述校正参数更新单元、所述低通滤波累加单元与所述计数单元的使能端，并重复步骤2至步骤5。
  10. 根据权利要求8所述的模数转换器误差估计校正的方法，其特征在于，所述步骤2具体包括：
    在参考通道内设置固定时延单元，获取所述参考通道输出的参考时钟时延量，在校正通道内设置所述数控模拟延时单元，获取所述校正通道输出的校正时钟时延量；
    所述时钟校正参数译码为二进制编码，以所述二进制编码为控制信号，当所述控制信号对应的实际时延量小于所述参考时钟时延量时，向前平移所述第二路数字信号的时钟相位；当所述控制信号对应的实际时延量大于所述参考时钟时延量时，向后平移所述第二路数字信号的时钟相位。
  11. 根据权利要求8所述的模数转换器误差估计校正的方法，其特征在于，所述步骤3具体包括：
    用乘法器获取所述第二路数字信号与所述增益校正参数的乘积，用加法器获取所述乘法器的输出与所述第二路数字信号之和；或者
    用加法器获取所述增益校正参数与原始倍数之和，用乘法器获取所述第二路数字信号与所述加法器输出之积。
  12. 根据权利要求11所述的模数转换器误差估计校正的方法，其特征在于根据所述第二路数字信号进行增益误差校正，输出第二路校正信号，对齐所述第一路数字信号与所述第二增益校正信号的时序，耦合生成总体校正信号。
  13. 根据权利要求8所述的模数转换器误差估计校正的方法，其特征在于，所述步骤4，调用缓存的所述第一路数字信号与所述第二路校正信号，采用循环相关法进行处理，生成初步估计结果，具体包括：
    其中，所述初步估计结果包括增益误差初步估计结果与时钟相位误差初步估计结果，调用所述第一路数字信号与所述第二路校正信号，根据所述循环相关法计算增益误差损 失函数，生成相应的增益误差初步估计结果；根据所述循环相关法计算时钟相位误差损失函数，生成相应的时钟相位误差初步估计结果。
  14. 根据权利要求8所述的模数转换器误差估计校正的方法，其特征在于，所述步骤5中所述将所述初步估计结果生成误差估计结果，以及根据所述误差估计结果更新并锁存所述时钟校正参数与所述增益校正参数，具体包括：
    当置位所述低通滤波累加单元的使能端时，对所述初步估计结果进行处理，生成误差估计结果，所述误差估计结果包括增益误差估计结果与时钟相位误差估计结果，当置位所述校正参数更新单元的使能端时，锁存所述误差估计结果，调用所述误差估计结果，根据梯度下降法更新所述时钟校正参数与所述增益校正参数，并锁存更新的所述时钟校正参数与所述增益校正参数。
  15. 根据权利要求14所述的模数转换器误差估计校正的方法，其特征在于，所述步骤5中所述时钟校正参数每更新一次，所述时钟校正参数对应的参数更新步长减半；所述增益校正参数每更新一次，所述增益校正参数对应的参数更新步长减半。
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CN115955240A (zh) * 2023-03-13 2023-04-11 江苏润石科技有限公司 时间交织adc的采样误差的校准方法、装置及时间交织adc
CN115955240B (zh) * 2023-03-13 2023-06-02 江苏润石科技有限公司 时间交织adc的采样误差的校准方法、装置及时间交织adc

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