WO2016202011A1 - 一种fpga系统的jtag调试方法及系统 - Google Patents

一种fpga系统的jtag调试方法及系统 Download PDF

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WO2016202011A1
WO2016202011A1 PCT/CN2016/075534 CN2016075534W WO2016202011A1 WO 2016202011 A1 WO2016202011 A1 WO 2016202011A1 CN 2016075534 W CN2016075534 W CN 2016075534W WO 2016202011 A1 WO2016202011 A1 WO 2016202011A1
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jtag
debugging
fpga
chip
socket
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PCT/CN2016/075534
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French (fr)
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陈华
刘如民
程海林
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中兴通讯股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing

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  • JTAG Joint Test Action Group loading is a common logic download method for FPGA chips.
  • JTAG can also be connected to the FPGA debug software installed on the debugger to implement functions such as grabbing and interacting with the internal signals of the FPGA chip. Therefore, in the initial stage of debugging of the FPGA chip and the joint debugging JTAG load debugging is a very effective debugging method when the fault is located in detail.
  • the JTAG interface of the FPGA chip requires a daisy-chain serial connection to support system JTAG mode debugging using system-level JTAG devices or devices.
  • a serial JTAG socket is also typically connected to the daisy chain for common multi-chip joint debugging. It can be seen that the related method cannot meet the requirement of multiple people to simultaneously perform JTAG debugging of a single FPGA chip on multiple FPGA chips on the same board.
  • the technical problem to be solved by the present invention is to provide a JTAG debugging method and system for an FPGA system, which can implement JTAG debugging of a single-chip or multi-chip FPGA chip in a multi-FPGA system.
  • a joint test action group JTAG debugging method for a field programmable gate array FPGA system include:
  • the step of connecting the FPGA chip and the JTAG debugging socket required for the debugging requirement according to the debugging requirement includes:
  • the JTAG serial debugging socket and the multi-chip FPGA chip are connected, or the system-level JTAG debugging socket and the multi-chip FPGA chip are connected.
  • the method further includes:
  • the method further comprises: connecting the JTAG serial debugging socket to the serial debugging Commissioning machine
  • the method further comprises: connecting the system level JTAG debug socket to the system level JTAG debug device.
  • the step of connecting the JTAG serial debugging socket and the plurality of serially connected FPGA chips comprises: turning on and off the control chip between the JTAG serial debugging socket and the plurality of serially connected FPGA chips;
  • the step of connecting the system level JTAG debug socket and the plurality of serially connected FPGA chips comprises: turning on the on/off control chip between the system level JTAG debug socket and the plurality of serially connected FPGA chips.
  • a JTAG debug system for an FPGA system including:
  • Multiple FPGA chips are directly connected to the JTAG debug socket or connected through the on/off control chip.
  • the FPGA chip When the on/off control chip is turned off or turned on according to the debugging requirements, the FPGA chip is connected to the JTAG debug socket required for the debugging requirement.
  • the JTAG debugging socket required for the different debugging requirements includes: a JTAG single chip debugging socket, and the JTAG single chip debugging socket has a one-to-one correspondence with the FPGA chip;
  • the JTAG debug socket required for the different debugging requirements further includes a JTAG serial debug socket or a system level JTAG debug socket, and the plurality of on/off control chips are connected to the JTAG serial debug socket or the system level JTAG debug socket and different Between FPGA chips;
  • the JTAG serial debug socket or the system level JTAG debug socket is connected to the plurality of serial FPGA chips for performing JTAG debugging of the plurality of FPGA chips.
  • system further includes: a plurality of single-chip debugging and debugging machines, and the single-chip debugging and debugging machine has a one-to-one correspondence with the JTAG single-chip debugging socket.
  • system further includes: a serial debugging debugger, and the serial debugging debugger is connected to the JTAG serial debugging socket.
  • system further includes: a system level JTAG debugging device, wherein the system level JTAG debugging device is correspondingly connected to the system level JTAG debugging socket.
  • a computer program comprising program instructions that, when executed by a computer, cause the computer to perform the JTAG debugging method of any of the above FPGA systems.
  • multiple FPGA chips are directly or indirectly connected to JTAG debugging sockets required by different debugging requirements through JTAG signals; according to debugging requirements, the FPGA chip is connected The JTAG debug socket required for this debug requirement.
  • JTAG debugging which can support different debugging requirements at the same time, such as serial JTAG debugging and single-chip JTAG debugging, improves the development efficiency of the board development process.
  • the implementation of the present invention is convenient and reliable, and the development cost is greatly saved.
  • FIG. 1 is a schematic diagram of a JTAG debugging system of an FPGA system according to an embodiment of the present invention
  • FIG. 2 is a flowchart of a JTAG debugging method of an FPGA system according to an embodiment of the present invention.
  • the embodiment of the invention provides a JTAG debugging method for an FPGA system, which comprises: directly or indirectly connecting a plurality of FPGA chips through a JTAG signal to a JTAG debugging socket required for different debugging requirements; connecting the FPGA chip and the debugging according to debugging requirements The JTAG debug socket required for the request.
  • the FPGA chip and the corresponding JTAG single chip debugging socket are connected; when performing JTAG debugging of multiple FPGA chips, the JTAG serial debugging socket and the plurality of chips are connected in series.
  • the FPGA chip or, is connected to a system-level JTAG debug socket and a multi-chip FPGA chip.
  • the method further includes: connecting each JTAG single-chip debugging socket to the corresponding single piece. Debug the debugger.
  • the method further comprises: connecting the JTAG serial debugging socket to the serial debugging debugger ;
  • the method further includes: connecting the system level JTAG debug socket to the system level JTAG debug device.
  • the JTAG serial debugging socket and the plurality of serially connected FPGA chips comprise: an on/off control chip between the JTAG serial debugging socket and the plurality of serially connected FPGA chips;
  • the system-level JTAG debug socket and the multi-chip serialized FPGA chip include: an on-off control chip between the system-level JTAG debug socket and the multi-chip FPGA chip.
  • the on/off control chip includes, for example, a switching circuit or a jumper circuit.
  • the embodiment of the present invention further provides a JTAG debugging system for an FPGA system, including: a plurality of on-off control chips and a JTAG debugging socket required for different debugging requirements, and multiple FPGA chips are directly connected to the JTAG debugging socket, or pass through The control chip is disconnected.
  • the on/off control chip is disconnected or turned on according to the debugging requirements, the FPGA chip is connected to the JTAG debug socket required for the debugging requirement.
  • the JTAG debugging socket required for the different debugging requirements includes: a JTAG single chip debugging socket, and each JTAG single chip debugging socket has a one-to-one correspondence with each FPGA chip, and also includes a JTAG serial debugging socket or a system level JTAG. Debugging the socket, the plurality of on/off control chips are connected between the JTAG serial debugging socket or the system level JTAG debugging socket and the different FPGA chips;
  • the JTAG serial debug socket or system level JTAG debug socket is connected to multiple serial FPGA chips for JTAG debugging of multiple FPGA chips.
  • system further includes: a plurality of single-chip debugging and debugging machines, and each of the single-chip debugging and debugging machines has a one-to-one correspondence with each of the JTAG single-chip debugging sockets.
  • system further includes: a serial debugging debugger, and is connected to the JTAG serial debugging socket.
  • system further includes: a system level JTAG debugging device, and is correspondingly connected to the system level JTAG debugging socket.
  • the on/off control chip includes, for example, a switching circuit or a jumper circuit.
  • FIG. 1 is a schematic diagram of a JTAG debugging system of an FPGA system according to an embodiment of the present invention.
  • the JTAG debugging system of the FPGA system provided by the embodiment of the present invention is applied to multiple FPGA system of chip FPGA chip (such as FPGA chip FPGA_1, FPGA_2, FPGA_n), including serial debugging debugger or system level JTAG debugging device, JTAG serial debugging socket or system level JTAG debugging socket, multiple single chip debugging and debugging machine ( For example, single-chip debug debugger L1, L2, Ln), multiple JTAG single-chip debug sockets (eg, JTAG single-chip debug sockets S1, S2, Sn) and multiple on-off control chips (eg, on/off control chip T1) , T2, Tn).
  • n is an integer greater than one.
  • the serial debugging debugger and the single-chip debugging debugger are, for example, a computer (PC, Personal Computer) that installs and runs the corresponding FPGA debugging software.
  • System level JTAG debug devices are, for example, devices or devices that support system level JTAG debug. Since the JTAG interface protocol is a common interface protocol standard, the system level JTAG debug device can use the corresponding debug device or device developed by itself.
  • the JTAG serial debug socket and the JTAG single-chip debug socket are the corresponding sockets defined by the mating cable connectors as needed.
  • the on-off control chip is a chip with on-off function, which can use a common digital signal switch chip, for example, a 244 series chip with enable control, using the level of the enable pin to achieve signal disconnection and transmission.
  • the FPGA chip refers to the FPGA logic chip of each chip manufacturer. Among them, because JTAG is a general-purpose protocol, multiple FPGAs in the system can refer to multiple FPGA chips of the same manufacturer, and can also refer to multiple FPGA chips of different manufacturers, as long as the supported interface level standards are consistent.
  • the serial debug debugger can be connected to the JTAG serial debug socket, or the system-level JTAG debug device can be connected to the system-level JTAG debug socket.
  • the single-chip debugging and debugging machine can be connected to the corresponding JTAG single-chip debugging socket.
  • the single-chip debugging and debugging machine L1 is connected with the JTAG single-chip debugging socket S1
  • the single-chip debugging and debugging machine L2 is connected with the JTAG single-chip debugging socket S2.
  • the single-chip debugging and debugging machine Ln is connected to the JTAG single-chip debugging socket Sn.
  • the on/off control chip is connected between the JTAG serial debug socket and the JTAG single chip debug socket and between different FPGA chips.
  • the on/off control chip T1 is connected between the JTAG serial debug socket and the FPGA chip FPGA_1
  • the on/off control chip T2 is connected between the FPGA chip FPGA_1 and the FPGA chip FPGA_2.
  • the communication signal between each device and the device is a JTAG signal
  • the complete JTAG signal includes a JTAG input signal TDI, a JTAG output signal TDO, a JTAG clock signal TCK, a JTAG control signal TMS, and a JTAG reset signal TRST.
  • Common debug sockets include TRST, which are not used in Xilinx and Altera's FPGA debug sockets.
  • some FPGA chips themselves have TRST signal pins, which can be connected in the periphery of the chip according to the manual requirements.
  • the other JTAG signals in Figure 1 are understood in common FPGA debug sockets, including TCK and TMS signals. It should be understood that FIG. 1 is only used to illustrate and explain the present invention and is not intended to limit the invention.
  • FIG. 2 is a flowchart of a JTAG debugging method of an FPGA system according to an embodiment of the present invention. As shown in Figure 2, the following steps are included:
  • Step 201 Determine whether the board needs to support serial JTAG debugging or single-chip JTAG debugging, that is, determine whether single-chip JTAG debugging is required;
  • Step 202 In the case of using single-chip JTAG debugging, the enable and disable of the on-off control chip is turned off, that is, set to be off, where the on-off control of the enable pin of the on-off control chip includes, for example, using a switch or Jumper, however, the invention is not limited thereto;
  • Step 203 Each FPGA uses a separate JTAG single-chip debugging socket to connect the corresponding single-chip debugging debugger for debugging, corresponding to FIG. 1, that is, the FPGA chip FPGA_1 is connected to the single-chip debugging and debugging machine L1 through the JTAG single-chip debugging socket S1 for debugging.
  • the FPGA chip FPGA_2 is connected to the single-chip debugging and debugging machine L2 through the JTAG single-chip debugging socket S2 for debugging, and so on;
  • Step 204 When the serial JTAG mode is used for debugging, the enable and disable of the on/off control chip is turned on, that is, set to be connected.
  • the on/off control of the enable pin of the on/off control chip includes, for example, using a switch or a jumper.
  • the invention is not limited thereto;
  • Step 205 When debugging by using the serial JTAG mode, each JTAG single chip debugging socket is disconnected and a cable connection corresponding to the single chip debugging debugger is performed;
  • Step 206 When using the serial JTAG mode debugging, connect the serial debugging debugger through the JTAG serial debugging socket for debugging, or connect to the system level JTAG debugging device through the system level JTAG debugging socket for debugging, corresponding to FIG. FPGA chip FPGA_1, FPGA_2, FPGA_n are connected in series, connected to the serial debugging debugger through JTAG serial debugging socket for debugging, or connected to system level JTAG debugging device through system level JTAG debugging socket for debugging;
  • Step 207 The process ends, and the debugging mode can be reselected according to the debugging requirements.
  • the JTAG signal is directly or indirectly connected to the socket required for JTAG debugging of a single chip or a plurality of FPGA chips on the outside of each FPGA chip. Therefore, under different debugging requirements, the on/off control of the connection between the debug socket and the FPGA chip is realized by the on/off control chip to realize different JTAG debugging.
  • the embodiment of the invention also discloses a computer program, comprising program instructions, which when executed by a computer, enable the computer to execute the JTAG debugging method of any of the above FPGA systems.
  • the embodiment of the invention also discloses a carrier carrying the computer program.
  • all or part of the steps of the above embodiments may also be implemented by using an integrated circuit. These steps may be separately fabricated into individual integrated circuit modules, or multiple modules or steps may be fabricated into a single integrated circuit module. achieve. Thus, the invention is not limited to any specific combination of hardware and software.
  • the devices/function modules/functional units in the above embodiments may be implemented by a general-purpose computing device, which may be centralized on a single computing device or distributed over a network of multiple computing devices.
  • each device/function module/functional unit in the above embodiment When each device/function module/functional unit in the above embodiment is implemented in the form of a software function module and sold or used as a stand-alone product, it can be stored in a computer readable storage medium.
  • the above mentioned computer readable storage medium may be a read only memory, a magnetic disk or an optical disk or the like.
  • multiple FPGA chips are directly or indirectly connected to the JTAG debugging socket required by different debugging requirements through the JTAG signal; according to the debugging requirements, the FPGA chip and the JTAG debugging socket required for the debugging requirement are connected.
  • JTAG debugging which can support different debugging requirements at the same time, such as serial JTAG debugging and single-chip JTAG debugging, improves the development efficiency of the board development process.
  • the implementation of the present invention is convenient and reliable, and the development cost is greatly saved. Therefore, the present invention has strong industrial applicability.

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Abstract

一种FPGA系统的JTAG调试方法及系统，该方法包括：将多片FPGA芯片通过JTAG信号直接或间接地连接至不同调试需求所需的JTAG调试插座；根据调试需求，连通FPGA芯片与该调试需求所需的JTAG调试插座。该JTAG调试方法及系统，能够实现在多FPGA系统支持单片或多片FPGA芯片的JTAG调试。

Description

一种FPGA系统的JTAG调试方法及系统 技术领域
本文涉及现场可编程门阵列(FPGA，Field Programmable Gate Array)的配置及调试技术，尤其涉及一种FPGA系统的联合测试行动组(JTAG，Joint Test Action Group)调试方法及系统。
背景技术
联合测试行动组(JTAG，Joint Test Action Group)加载是FPGA芯片常用的一种逻辑下载方法。JTAG加载除了可以直接通过电缆从调试机下载逻辑文件之外，还可以连接调试机上安装的FPGA调试软件实现对FPGA芯片内部信号的抓取交互等功能，因此，在FPGA芯片的调试初期以及对联调故障详细定位的时候，JTAG加载调试都是一种十分有效的调试方法。
由于FPGA芯片内部集成的逻辑资源越多，价格就越昂贵，为了节省成本，在单板硬件版本还未稳定的时候会尽量减少调试初期单板的焊接数量。在这种前提下，存在多人对同一块单板上的多片FPGA芯片同时进行单片FPGA芯片的JTAG调试的需求。
在正常应用中，FPGA芯片的JTAG接口需要用菊花链串行连接，从而支持使用系统级JTAG设备或装置进行系统JTAG方式的调试。一般也在菊花链上连接一个串行的JTAG插座用于常见的多片联合调试。可见，相关方式并无法满足多人对同一块单板上的多片FPGA芯片同时进行单片FPGA芯片的JTAG调试的需求。
发明内容
本发明要解决的技术问题是提供一种FPGA系统的JTAG调试方法及系统，能够实现在多FPGA系统支持单片或多片FPGA芯片的JTAG调试。
为了达到上述技术目的，采用如下技术方案：
一种现场可编程门阵列FPGA系统的联合测试行动组JTAG调试方法， 包括：
将多片FPGA芯片通过JTAG信号直接或间接地连接至不同调试需求所需的JTAG调试插座；
根据调试需求，连通FPGA芯片与该调试需求所需的JTAG调试插座。
可选地，所述根据调试需求，连通FPGA芯片与该调试需求所需的JTAG调试插座的步骤包括：
当进行单片FPGA芯片的JTAG调试时，连通多片FPGA芯片与对应的JTAG单片调试插座；
当进行多片FPGA芯片的JTAG调试时，连通JTAG串行调试插座与多片串联的FPGA芯片，或者，连通系统级JTAG调试插座与多片串联的FPGA芯片。
可选地，所述当进行单片FPGA芯片的JTAG调试时，连通多片FPGA芯片与对应的JTAG单片调试插座的步骤之后，该方法还包括：
将多个JTAG单片调试插座分别连接至对应的单片调试调试机。
可选地，所述当进行多片FPGA芯片的JTAG调试时，连通JTAG串行调试插座与多片串联的FPGA芯片的步骤之后，该方法还包括：将JTAG串行调试插座连接至串行调试调试机；
所述连通系统级JTAG调试插座与多片串联的FPGA芯片的步骤之后，该方法还包括：将系统级JTAG调试插座连接至系统级JTAG调试装置。
可选地，所述连通JTAG串行调试插座与多片串联的FPGA芯片的步骤包括：导通JTAG串行调试插座与多片串联的FPGA芯片之间的通断控制芯片；
所述连通系统级JTAG调试插座与多片串联的FPGA芯片的步骤包括：导通系统级JTAG调试插座与多片串联的FPGA芯片之间的通断控制芯片。
一种FPGA系统的JTAG调试系统，包括：
多个通断控制芯片以及不同调试需求所需的JTAG调试插座，
多片FPGA芯片与JTAG调试插座直接连接，或通过通断控制芯片连接，
当根据调试需求控制通断控制芯片断开或导通时，FPGA芯片与该调试需求所需的JTAG调试插座连通。
可选地，所述不同调试需求所需的JTAG调试插座包括：JTAG单片调试插座，JTAG单片调试插座与FPGA芯片一一对应；
所述不同调试需求所需的JTAG调试插座还包括JTAG串行调试插座或系统级JTAG调试插座，所述多个通断控制芯片连接在所述JTAG串行调试插座或系统级JTAG调试插座以及不同的FPGA芯片之间；
当多个通断控制芯片均断开时，所述JTAG串行调试插座或系统级JTAG调试插座与多个FPGA芯片之间的连接断开，每个FPGA芯片与对应的JTAG单片调试插座连通，用于进行单片FPGA芯片的JTAG调试；
当多个通断控制芯片均导通时，所述JTAG串行调试插座或系统级JTAG调试插座与多片串联FPGA芯片连通，用于进行多片FPGA芯片的JTAG调试。
可选地，该系统还包括：多个单片调试调试机，单片调试调试机与JTAG单片调试插座一一对应。
可选地，该系统还包括：串行调试调试机，该串行调试调试机与所述JTAG串行调试插座对应连接。
可选地，该系统还包括：系统级JTAG调试装置，该系统级JTAG调试装置与所述系统级JTAG调试插座对应连接。
一种计算机程序，包括程序指令，当该程序指令被计算机执行时，使得该计算机可执行上述任意的FPGA系统的JTAG调试方法。
一种载有所述的计算机程序的载体。
本发明技术方案中，将多片FPGA芯片通过JTAG信号直接或间接地连接至不同调试需求所需的JTAG调试插座；根据调试需求，连通FPGA芯片 与该调试需求所需的JTAG调试插座。如此，能够同时支持不同调试需求的JTAG调试，如串行JTAG调试及单片JTAG调试，从而提高了单板开发过程中的研发效率。而且，本发明的实现方便可靠，大大节省了研发成本。
附图概述
图1为本发明一实施例提供的FPGA系统的JTAG调试系统的示意图；
图2为本发明一实施例提供的FPGA系统的JTAG调试方法的流程图。
本发明的较佳实施方式
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
以下结合附图对本发明的实施例进行详细说明，应当理解，以下所说明的实施例仅用于说明和解释本发明，并不用于限定本发明。
本发明实施例提供一种FPGA系统的JTAG调试方法，包括：将多片FPGA芯片通过JTAG信号直接或间接地连接至不同调试需求所需的JTAG调试插座；根据调试需求，连通FPGA芯片与该调试需求所需的JTAG调试插座。
具体而言，当进行单片FPGA芯片的JTAG调试时，连通各FPGA芯片与对应的JTAG单片调试插座；当进行多片FPGA芯片的JTAG调试时，连通JTAG串行调试插座与多片串联的FPGA芯片，或者，连通系统级JTAG调试插座与多片串联的FPGA芯片。
在一实施例中，当进行单片FPGA芯片的JTAG调试时，连通各FPGA芯片与对应的JTAG单片调试插座之后，该方法还包括：将各JTAG单片调试插座分别连接至对应的单片调试调试机。
在一实施例中，当进行多片FPGA芯片的JTAG调试时，连通JTAG串行调试插座与多片串联的FPGA芯片之后，该方法还包括：将JTAG串行调试插座连接至串行调试调试机；
连通系统级JTAG调试插座与多片串联的FPGA芯片之后，该方法还包括：将系统级JTAG调试插座连接至系统级JTAG调试装置。
在一实施例中，连通JTAG串行调试插座与多片串联的FPGA芯片包括：导通JTAG串行调试插座与多片串联的FPGA芯片之间的通断控制芯片；
连通系统级JTAG调试插座与多片串联的FPGA芯片包括：导通系统级JTAG调试插座与多片串联的FPGA芯片之间的通断控制芯片。
其中，通断控制芯片例如包括开关电路或跳线电路。
此外，本发明实施例还提供一种FPGA系统的JTAG调试系统，包括：多个通断控制芯片以及不同调试需求所需的JTAG调试插座，多片FPGA芯片与JTAG调试插座直接连接，或通过通断控制芯片连接，当根据调试需求控制通断控制芯片断开或导通时，FPGA芯片与该调试需求所需的JTAG调试插座连通。
在一实施例中，所述不同调试需求所需的JTAG调试插座包括：JTAG单片调试插座，各JTAG单片调试插座与各FPGA芯片一一对应，还包括JTAG串行调试插座或系统级JTAG调试插座，所述多个通断控制芯片连接在JTAG串行调试插座或系统级JTAG调试插座以及不同的FPGA芯片之间；
当多个通断控制芯片均断开时，JTAG串行调试插座或系统级JTAG调试插座与多个FPGA芯片之间的连接断开，各FPGA芯片与对应的JTAG单片调试插座连通，用于进行单片FPGA芯片的JTAG调试；
当多个通断控制芯片均导通时，JTAG串行调试插座或系统级JTAG调试插座与多片串联FPGA芯片连通，用于进行多片FPGA芯片的JTAG调试。
在一实施例中，上述系统还包括：多个单片调试调试机，各单片调试调试机与各JTAG单片调试插座一一对应。
在一实施例中，上述系统还包括：串行调试调试机，与JTAG串行调试插座对应连接。
在一实施例中，上述系统还包括：系统级JTAG调试装置，与系统级JTAG调试插座对应连接。
其中，通断控制芯片例如包括开关电路或跳线电路。
图1为本发明一实施例提供的FPGA系统的JTAG调试系统的示意图。如图1所示，本发明实施例提供的FPGA系统的JTAG调试系统，应用于多 片FPGA芯片(如FPGA芯片FPGA_1、FPGA_2、FPGA_n)的FPGA系统，包括串行调试调试机或系统级JTAG调试装置、JTAG串行调试插座或系统级JTAG调试插座、多个单片调试调试机(如，单片调试调试机L1、L2、Ln)、多个JTAG单片调试插座(如，JTAG单片调试插座S1、S2、Sn)以及多个通断控制芯片(如，通断控制芯片T1、T2、Tn)。其中，n为大于1的整数。
其中，串行调试调试机和单片调试调试机例如为安装并运行了相应FPGA调试软件的电脑(PC，Personal Computer)。系统级JTAG调试装置例如为支持系统级JTAG调试的设备或装置。由于JTAG接口协议为通用的接口协议标准，因此，系统级JTAG调试装置可使用自行开发的相应调试设备或装置。JTAG串行调试插座和JTAG单片调试插座为按照需要对接的线缆接头配合定义的相应的插座。通断控制芯片为具有通断功能的芯片，可使用常见的数字信号的开关芯片，例如，带使能控制的244系列芯片，利用给使能管脚的电平高低来实现信号的断开和传输。FPGA芯片指各芯片厂家的FPGA逻辑芯片。其中，由于JTAG是一个通用协议，系统中的多片FPGA可以指多片相同厂家的FPGA芯片，也可以指多片不同厂家的FPGA芯片，只要支持的接口电平标准一致。
如图1所示，串行调试调试机可与JTAG串行调试插座对应相连，或系统级JTAG调试装置可与系统级JTAG调试插座对应相连。单片调试调试机可与对应的JTAG单片调试插座相连，例如，单片调试调试机L1与JTAG单片调试插座S1对应相连，单片调试调试机L2与JTAG单片调试插座S2对应相连，单片调试调试机Ln与JTAG单片调试插座Sn对应相连。通断控制芯片分别连接在JTAG串行调试插座与JTAG单片调试插座之间以及不同的FPGA芯片之间。例如，通断控制芯片T1连接在JTAG串行调试插座与FPGA芯片FPGA_1之间，通断控制芯片T2连接在FPGA芯片FPGA_1与FPGA芯片FPGA_2之间。
具体而言，各设备和器件之间的通信信号为JTAG信号，完整的JTAG信号包括JTAG输入信号TDI、JTAG输出信号TDO、JTAG时钟信号TCK、JTAG控制信号TMS以及JTAG复位信号TRST。常见的调试插座包括赛灵思(Xilinx)公司和阿尔特拉(Altera)公司的FPGA调试插座中都不使用TRST， 另外，有部分FPGA芯片本身会有TRST信号管脚，在芯片外围按手册要求相应连接即可。在此，图1中的其它JTAG信号按常见的FPGA调试插座进行理解，包括有TCK和TMS信号。应当理解，图1仅用于说明和解释本发明，并不用于限定本发明。
图2是本发明的一实施例提供的FPGA系统的JTAG调试方法的流程图。如图2所示，包括以下步骤：
步骤201：判断单板需要支持串行JTAG调试还是单片JTAG调试，即判断是否需要单片JTAG调试；
步骤202：在使用单片JTAG调试的情况下，将通断控制芯片的使能关闭，即设置为断开，在此，通断控制芯片的使能管脚的通断控制例如包括使用开关或跳线，然而，本发明并不限定于此；
步骤203：各FPGA使用单独的JTAG单片调试插座连接对应的单片调试调试机进行调试，对应于图1，即FPGA芯片FPGA_1通过JTAG单片调试插座S1连接单片调试调试机L1进行调试，FPGA芯片FPGA_2通过JTAG单片调试插座S2连接单片调试调试机L2进行调试，依此类推；
步骤204：在使用串行JTAG方式调试时，将通断控制芯片的使能打开，即设置为连通，在此，通断控制芯片的使能管脚的通断控制例如包括使用开关或跳线，然而，本发明并不限定于此；
步骤205：在使用串行JTAG方式调试时，各JTAG单片调试插座断开和对应单片调试调试机的线缆连接；
步骤206：在使用串行JTAG方式调试时，通过JTAG串行调试插座连接串行调试调试机进行调试，或者通过系统级JTAG调试插座接入系统级JTAG调试装置进行调试，对应于图1，即FPGA芯片FPGA_1、FPGA_2、FPGA_n串联连接，通过JTAG串行调试插座连接串行调试调试机进行调试，或者通过系统级JTAG调试插座连接系统级JTAG调试装置进行调试；
步骤207：流程结束，按调试需要可以重新选择调试方式。
综上所述，在本发明较佳实施例中，在各FPGA芯片的外部通过JTAG信号直接或间接地连接到单片或多片FPGA芯片的JTAG调试所需要的插座， 从而在不同调试需求下，通过通断控制芯片对调试插座与FPGA芯片连接的通断控制实现不同的JTAG调试。
本发明实施例还公开了一种计算机程序，包括程序指令，当该程序指令被计算机执行时，使得该计算机可执行上述任意的FPGA系统的JTAG调试方法。
本发明实施例还公开了一种载有所述的计算机程序的载体。
在阅读并理解了附图和详细描述后，可以明白其他方面。
本领域普通技术人员可以理解上述实施例的全部或部分步骤可以使用计算机程序流程来实现，所述计算机程序可以存储于一计算机可读存储介质中，所述计算机程序在相应的硬件平台上(如系统、设备、装置、器件等)执行，在执行时，包括方法实施例的步骤之一或其组合。
可选地，上述实施例的全部或部分步骤也可以使用集成电路来实现，这些步骤可以被分别制作成一个个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件结合。
上述实施例中的各装置/功能模块/功能单元可以采用通用的计算装置来实现，它们可以集中在单个的计算装置上，也可以分布在多个计算装置所组成的网络上。
上述实施例中的各装置/功能模块/功能单元以软件功能模块的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。上述提到的计算机可读取存储介质可以是只读存储器，磁盘或光盘等。
任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以权利要求所述的保护范围为准。
工业实用性
本发明技术方案中，将多片FPGA芯片通过JTAG信号直接或间接地连接至不同调试需求所需的JTAG调试插座；根据调试需求，连通FPGA芯片与该调试需求所需的JTAG调试插座。如此，能够同时支持不同调试需求的JTAG调试，如串行JTAG调试及单片JTAG调试，从而提高了单板开发过程中的研发效率。而且，本发明的实现方便可靠，大大节省了研发成本。因此本发明具有很强的工业实用性。

Claims (12)

  1. 一种现场可编程门阵列FPGA系统的联合测试行动组JTAG调试方法，包括：
    将多片FPGA芯片通过JTAG信号直接或间接地连接至不同调试需求所需的JTAG调试插座；
    根据调试需求，连通FPGA芯片与该调试需求所需的JTAG调试插座。
  2. 如权利要求1所述的FPGA系统的JTAG调试方法，其中，所述根据调试需求，连通FPGA芯片与该调试需求所需的JTAG调试插座的步骤包括：
    当进行单片FPGA芯片的JTAG调试时，连通多片FPGA芯片与对应的JTAG单片调试插座；
    当进行多片FPGA芯片的JTAG调试时，连通JTAG串行调试插座与多片串联的FPGA芯片，或者，连通系统级JTAG调试插座与多片串联的FPGA芯片。
  3. 如权利要求2所述的FPGA系统的JTAG调试方法，其中，所述当进行单片FPGA芯片的JTAG调试时，连通多片FPGA芯片与对应的JTAG单片调试插座的步骤之后，该方法还包括：
    将多个JTAG单片调试插座分别连接至对应的单片调试调试机。
  4. 如权利要求2所述的FPGA系统的JTAG调试方法，其中
    所述当进行多片FPGA芯片的JTAG调试时，连通JTAG串行调试插座与多片串联的FPGA芯片的步骤之后，该方法还包括：将JTAG串行调试插座连接至串行调试调试机；
    所述连通系统级JTAG调试插座与多片串联的FPGA芯片的步骤之后，该方法还包括：将系统级JTAG调试插座连接至系统级JTAG调试装置。
  5. 如权利要求2所述的FPGA系统的JTAG调试方法，其中
    所述连通JTAG串行调试插座与多片串联的FPGA芯片的步骤包括：导通JTAG串行调试插座与多片串联的FPGA芯片之间的通断控制芯片；
    所述连通系统级JTAG调试插座与多片串联的FPGA芯片的步骤包括： 导通系统级JTAG调试插座与多片串联的FPGA芯片之间的通断控制芯片。
  6. 一种FPGA系统的JTAG调试系统，包括：
    多个通断控制芯片以及不同调试需求所需的JTAG调试插座，
    多片FPGA芯片与JTAG调试插座直接连接，或通过通断控制芯片连接，
    当根据调试需求控制通断控制芯片断开或导通时，FPGA芯片与该调试需求所需的JTAG调试插座连通。
  7. 如权利要求6所述的FPGA系统的JTAG调试系统，其中
    所述不同调试需求所需的JTAG调试插座包括：JTAG单片调试插座，JTAG单片调试插座与FPGA芯片一一对应；
    所述不同调试需求所需的JTAG调试插座还包括JTAG串行调试插座或系统级JTAG调试插座，所述多个通断控制芯片连接在所述JTAG串行调试插座或系统级JTAG调试插座以及不同的FPGA芯片之间；
    当多个通断控制芯片均断开时，所述JTAG串行调试插座或系统级JTAG调试插座与多个FPGA芯片之间的连接断开，每个FPGA芯片与对应的JTAG单片调试插座连通，用于进行单片FPGA芯片的JTAG调试；
    当多个通断控制芯片均导通时，所述JTAG串行调试插座或系统级JTAG调试插座与多片串联FPGA芯片连通，用于进行多片FPGA芯片的JTAG调试。
  8. 如权利要求7所述的FPGA系统的JTAG调试系统，该系统还包括：多个单片调试调试机，单片调试调试机与JTAG单片调试插座一一对应。
  9. 如权利要求7所述的FPGA系统的JTAG调试系统，该系统还包括：串行调试调试机，该串行调试调试机与所述JTAG串行调试插座对应连接。
  10. 如权利要求7所述的FPGA系统的JTAG调试系统，该系统还包括：系统级JTAG调试装置，该系统级JTAG调试装置与所述系统级JTAG调试插座对应连接。
  11. 一种计算机程序，包括程序指令，当该程序指令被计算机执行时，使得该计算机可执行如权利要求1-5中任一项所述的FPGA系统的JTAG调 试方法。
  12. 一种载有如权利要求11所述的计算机程序的载体。
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Publication number Priority date Publication date Assignee Title
US20220317178A1 (en) * 2019-09-25 2022-10-06 Inspur Suzhou Intelligent Technology Co., Ltd JTAG-Based Burning Device
US11874323B2 (en) * 2019-09-25 2024-01-16 Inspur Suzhou Intelligent Technology Co., Ltd. JTAG-based burning device

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