WO2016201752A1 - 一种阵列基板及其制成方法、显示面板 - Google Patents

一种阵列基板及其制成方法、显示面板 Download PDF

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Publication number
WO2016201752A1
WO2016201752A1 PCT/CN2015/083745 CN2015083745W WO2016201752A1 WO 2016201752 A1 WO2016201752 A1 WO 2016201752A1 CN 2015083745 W CN2015083745 W CN 2015083745W WO 2016201752 A1 WO2016201752 A1 WO 2016201752A1
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Prior art keywords
layer
channel layer
gate
drain
array substrate
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English (en)
French (fr)
Inventor
王质武
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/765,833 priority Critical patent/US9595539B2/en
Publication of WO2016201752A1 publication Critical patent/WO2016201752A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6329—Deposition from the gas or vapour phase using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69391—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present application relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display panel.
  • TFT thin film
  • Etch Stop Layer (English: Etch Stop) Layer, abbreviated as: ESL) is usually composed of silicon monoxide (molecular formula: SiO). Since a hydrogen-containing reaction gas is used in the preparation of SiO, hydrogen is included in the reaction product, that is, the etching barrier layer contains hydrogen.
  • the etch barrier layer contains hydrogen, if the temperature is too high when the etch barrier layer is formed, the adjacent channel layer is reduced, thereby affecting the quality of the channel layer of the TFT. Low, the nitrogen content of the etch barrier will be relatively increased, and holes are prone to occur (English: pin Hole), thereby affecting the film formation quality of the etching barrier layer of the TFT. Therefore, in order to ensure the quality of the TFT, the existing etch barrier layer has high film formation requirements and a low film formation rate.
  • the present application provides an array substrate, a method for fabricating the same, and a display panel, which can ensure the quality of the TFT and increase the film formation rate of the etch barrier layer.
  • a first aspect of the present application provides an array substrate including a substrate and a plurality of thin film transistors including a gate, a gate insulating layer, a channel layer, an etch barrier, a source and a drain disposed on the substrate a gate insulating layer disposed between the gate and the channel layer to insulate the gate and the channel layer, wherein the etch barrier layer, the source and the drain are respectively disposed in the channel And etching the barrier layer disposed between the source and the drain; wherein the etch barrier layer is an AlN film.
  • the AlN film is formed by sputtering using a magnetron sputtering apparatus in which nitrogen gas or a mixed gas including argon gas and nitrogen gas is introduced into an aluminum tank.
  • the ratio of the argon gas to the nitrogen gas is 0-90%.
  • the gate insulating layer is an AlN film.
  • the channel layer is composed of a metal oxide.
  • a second aspect of the present application provides a method of fabricating an array substrate, the method comprising: forming a gate, a gate insulating layer, and a channel layer on a substrate, wherein the gate insulating layer is stacked on the gate and the trench An etch stop layer, a source and a drain are formed on the channel layer, and the etch stop layer is disposed between the source and the drain, wherein the etch stop layer is AlN film.
  • the forming an etch barrier layer on the channel layer comprises: using a magnetron sputtering device, introducing a nitrogen gas or a mixed gas including argon gas and nitrogen gas into the aluminum box to splash on the channel layer The shot forms an AlN film.
  • the ratio of the argon gas to the nitrogen gas is 0-90%.
  • the temperature of the substrate is 25 degrees Celsius to 300 degrees Celsius.
  • a third aspect of the present disclosure provides a display panel including an array substrate, the array substrate including a substrate and a plurality of thin film transistors, the thin film transistor including a gate, a gate insulating layer, a channel layer, and a channel layer disposed on the substrate Etching a barrier layer, a source and a drain, the gate insulating layer being disposed between the gate and the channel layer to insulate the gate and channel layers, the etch barrier layer, the source and the drain
  • the gates are respectively disposed on the channel layer, and the etch barrier layer is disposed between the source and the drain; wherein the etch barrier layer is an aluminum nitride AlN film; wherein the gate
  • the insulating layer is also an AlN film, which is fabricated using a magnetron sputtering device in an aluminum case.
  • the chamber is formed by sputtering with nitrogen gas or a mixed gas including argon gas and nitrogen gas.
  • the ratio of the argon gas to the nitrogen gas is 0-90%.
  • the channel layer is composed of a metal oxide.
  • an AlN film is used as an etch barrier layer of the TFT of the array substrate. Since the AlN film does not contain hydrogen, when the etch barrier layer is formed, the channel layer is not caused even if the temperature is too high or too low. Reducing or etching the barrier layer to form a hole, thereby ensuring the quality of the TFT, and, in the film formation of the AlN film, there is no need to be subjected to temperature limitation, the film formation requirement is lowered, and the film formation rate can be improved.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate of the present application.
  • FIG. 2 is a schematic structural view of an embodiment of a display panel of the present application.
  • FIG. 3 is a flow chart of an embodiment of a method of fabricating an array substrate of the present application.
  • FIG. 1 is a schematic structural diagram of an embodiment of an array substrate of the present application.
  • the array substrate 100 includes a substrate 110 and a plurality of TFTs. 120 (FIG. 1 exemplarily shows one TFT 120 on the substrate 110 for explanation).
  • the substrate 110 may be a transparent substrate made of a glass substrate or other insulating material.
  • TFT 120 includes a gate electrode 121, a gate insulating layer 122, a channel layer 123, a source electrode 124, a drain electrode 125, and an etch barrier layer 126 disposed on the substrate 110.
  • the gate insulating layer 122 is stacked between the gate electrode 121 and the channel layer 123 to insulate the gate electrode 121 and the channel layer 123, the source electrode 124 and the drain electrode 125, and an etch barrier layer. 126 are located in the same layer and are respectively disposed on the channel layer 123 and an etch barrier layer 126 is disposed between the source 124 and the drain 125 to space the source 124 and the drain 125.
  • the gate 121 obtains a voltage greater than or equal to the turn-on voltage
  • the channel layer 123 induces electrons to turn on the source 124 and the drain 125.
  • the etch barrier layer 126 is an aluminum nitride (chemical formula: AlN) film.
  • the AlN film is a good insulating material, so it can provide good insulation between the source 124 and the drain 125.
  • the AlN film has a high breakdown field strength (such as 1.2-1.8 MV/cm for AlN crystal), high thermal conductivity, high chemical and thermal stability, and a transmittance of more than 90% in the visible range. .
  • the film does not contain hydrogen, so that when the etching barrier film is formed, even if the temperature is too high or too low, the channel layer is not reduced or the etching barrier layer is formed with holes, thereby ensuring the quality of the TFT, and
  • the AlN film is formed into a film, it is not required to be subjected to temperature limitation, the film formation requirement is lowered, and the film formation rate can be improved.
  • the channel layer 123 may be composed of a metal oxide, such as indium gallium zinc oxide (English: indium gallium) Zinc oxide, referred to as: IGZO).
  • IGZO indium gallium zinc oxide
  • IGZO indium gallium Zinc oxide
  • the gate insulating layer 121 can also be an AlN film. Since the AlN film does not contain hydrogen, it can be avoided that when the array substrate is in operation, the gate insulating layer contains hydrogen to capture or release electrons, so that the threshold voltage of the TFT exhibits a positive or negative drift. The stability of the TFT is guaranteed.
  • the 120 may also include a passivation layer 127 overlying the source and drain electrodes 124 and 125.
  • a silicide layer may be disposed between the source, the drain, and the passivation layer to prevent Cu ions of the source and drain from diffusing to the passivation layer.
  • the gate electrode 121, the channel layer 123, the source electrode 124, and the drain electrode 125 may be physically vapor deposited (English: Physical: Vapor Deposition (PVD) generation, the passivation layer 127 may be plasma enhanced chemical vapor deposition (English: Plasma Enhanced Chemical) Vapor Deposition, referred to as: PECVD).
  • PVD Physical: Vapor Deposition
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • the above AlN film may be etched by an inductively coupled plasma (abbreviation: ICP) device or by PVD such as magnetron sputtering.
  • ICP inductively coupled plasma
  • PVD magnetron sputtering
  • the AlN film is prepared using a magnetron sputtering apparatus.
  • a magnetron sputtering apparatus for example, in an aluminum case (English: Al
  • the chamber is formed by sputtering with nitrogen gas or a mixed gas including argon gas and nitrogen gas.
  • the ratio of the argon gas to the nitrogen gas is 0-90%, for example, the ratio is 0%, 45% or 90%.
  • the temperature of the substrate is 25 degrees Celsius to 300 degrees Celsius, for example, specifically 25, 85 or 300 degrees Celsius. Therefore, since the AlN film is prepared by magnetron sputtering, high temperature is not required, and it can be performed at normal temperature, so that the damage of the channel layer 123 when the etch barrier layer is prepared can be avoided, thereby avoiding the influence on the electrical properties of the TFT. Moreover, relative to chemical vapor deposition (referred to as CVD), the film formation rate of AlN film prepared by PVD is higher, and the productivity is improved.
  • CVD chemical vapor deposition
  • the array substrate may further include a plurality of data lines, a plurality of scan lines, and a plurality of pixel electrodes (not shown) disposed on the substrate, the data lines and a source of the TFT The pole is connected, the scan line is connected to the gate of the TFT, and the pixel electrode is connected to the drain of the TFT.
  • the scan line inputs a voltage greater than or equal to the startup voltage to the gate of the TFT, the source and the drain of the TFT are turned on, that is, the data line and the pixel electrode are connected, and the pixel electrode obtains the voltage input from the data line.
  • the source, the drain and the pixel electrode may have an integral structure and are composed of a transparent conductive film.
  • FIG. 2 is a schematic structural diagram of an embodiment of a display panel of the present application.
  • the display panel includes an array substrate 210, a color filter substrate 220, and a liquid crystal 230 interposed between the array substrate 210 and the color filter substrate 220.
  • the array substrate 210 is the array substrate described in the above embodiment, and the color filter substrate 220 may include a substrate, and a black matrix and a color filter layer respectively disposed on the substrate (English: Color Filter, referred to as: CF), protective layer and ITO Membrane.
  • CF Color Filter
  • the pixel electrode of the array substrate acquires the display voltage input from the data line, an electric field is formed between the pixel electrode and the ITO film of the color filter substrate, thereby driving the liquid crystal 230 to be deflected to form a display image.
  • FIG. 3 is a flow chart of an embodiment of a method for fabricating an array substrate of the present application. The method includes:
  • 310 forming a gate, a gate insulating layer, and a channel layer on the substrate, wherein the gate insulating layer is stacked between the gate and the channel layer.
  • a gate electrode is formed on a substrate, a gate insulating layer is covered on the gate electrode, and a channel layer is formed on the gate insulating layer.
  • the gate and the channel layer can be generated by PVD.
  • the gate insulating layer may be an AlN film.
  • etch barrier layer forming an etch barrier layer, a source and a drain on the channel layer, and the etch barrier layer is disposed between the source and the drain, wherein the etch barrier layer is an AlN film .
  • an AlN film, a source and a drain are respectively formed on the channel layer, wherein the AlN film serves as an etch barrier and is disposed between the source and the drain.
  • the AlN film can be etched by an ICP device or prepared by PVD such as magnetron sputtering.
  • the AlN film is formed by sputtering using a magnetron sputtering apparatus by introducing nitrogen gas or a mixed gas including argon gas and nitrogen gas into an aluminum tank.
  • the ratio of the argon gas to the nitrogen gas may be 0-90%, for example, the ratio is 0%, 45% or 90%.
  • the temperature of the substrate is 25 degrees Celsius to 300 degrees Celsius, for example, specifically 25, 85 or 300 degrees Celsius.
  • the AlN film is prepared by magnetron sputtering, high temperature is not required, and it can be performed at normal temperature, so that the damage of the channel layer when the etching barrier layer is prepared can be avoided, thereby avoiding the influence on the electrical properties of the TFT. Moreover, relative to chemical vapor deposition (referred to as CVD), the film formation rate of AlN film prepared by PVD is higher, and the productivity is improved. It can be understood that when the gate insulating layer formed in 310 is an AlN thin film, the AlN thin film can be prepared by the same method as described above.
  • a passivation layer can also be formed on the source and drain, respectively.
  • the source and drain may be generated by PVD, and the passivation layer may be formed by PECVD.
  • the fabricating method further includes forming a plurality of scan lines, a plurality of data lines, and a plurality of pixel electrodes on the substrate.
  • the data line is in electrical contact with a source of the TFT
  • the scan line is in electrical contact with a gate of the TFT
  • the pixel electrode is in electrical contact with a drain of the TFT.
  • an AlN film is used as an etch barrier layer of the TFT of the array substrate. Since the AlN film does not contain hydrogen, when the etch barrier layer is formed, the channel layer is not caused even if the temperature is too high or too low. Reducing or etching the barrier layer to form a hole, thereby ensuring the quality of the TFT, and, in the film formation of the AlN film, there is no need to be subjected to temperature limitation, the film formation requirement is lowered, and the film formation rate can be improved.

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  • Thin Film Transistor (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
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Abstract

一种阵列基板(100)及其制成方法、显示面板。其中，该阵列基板(100)，包括基板(110)和多个TFT(120)，所述TFT(120)包括设置在所述基板(110)上的栅极(121)、栅绝缘层(122)、沟道层(123)、蚀刻阻挡层(126)、源极(124)和漏极(125)，所述栅绝缘层(122)叠置在所述栅极(121)和沟道层(123)之间，以将所述栅极(121)和沟道层(123)绝缘，所述蚀刻阻挡层(126)、源极(124)和漏极(125)分别设置在所述沟道层(123)上，且所述刻蚀阻挡层(126)设置在所述源极(124)和漏极(125)之间；其中，所述刻蚀阻挡层(126)为AlN薄膜。通过上述方式，能够保证TFT(120)的质量，且提高刻蚀阻挡层(126)的成膜速率。

Description

一种阵列基板及其制成方法、显示面板
【技术领域】
本申请涉及显示技术领域，特别是涉及一种阵列基板及其制成方法、显示面板。
【背景技术】
目前，主流显示面板的薄膜晶体管（英文：thin film transistor，简称：TFT）的刻蚀阻挡层(英文：Etch Stop Layer，简称：ESL)通常采用一氧化硅（分子式：SiO）构成。由于在制备SiO时需使用含氢的反应气体，故反应生成物中会包括氢，也即刻蚀阻挡层中含有氢。
然而，由于刻蚀阻挡层含氢，故在刻蚀阻挡层成膜时，如果温度过高，则会导致相邻的沟道层的还原，从而影响TFT的沟道层的质量，如果温度过低，则刻蚀阻挡层的氮含量会相对提高，容易出现孔洞(英文：pin hole)，从而影响刻TFT的蚀阻挡层的成膜质量。所以，为保证TFT的质量，现有的刻蚀阻挡层的成膜要求高，且成膜速率低。
【发明内容】
本申请提供一种阵列基板及其制成方法、显示面板，能够保证TFT的质量，且提高刻蚀阻挡层的成膜速率。
本申请第一方面提供一种阵列基板，包括基板和多个薄膜晶体管，所述薄膜晶体管包括设置在所述基板上的栅极、栅绝缘层、沟道层、蚀刻阻挡层、源极和漏极，所述栅绝缘层叠置在所述栅极和沟道层之间，以将所述栅极和沟道层绝缘，所述蚀刻阻挡层、源极和漏极分别设置在所述沟道层上，且所述刻蚀阻挡层设置在所述源极和漏极之间；其中，所述刻蚀阻挡层为AlN薄膜。
其中，所述AlN薄膜是利用磁控溅射设备，在铝箱中通入氮气、或包括氩气和氮气的混合气体，溅射形成的。
其中，所述氩气与氮气的比值为0-90%。
其中，所述栅绝缘层为AlN薄膜。
其中所述沟道层由金属氧化物构成。
本申请第二方面提供一种阵列基板的制成方法，所述方法包括：在基板上形成栅极、栅绝缘层、沟道层，其中，所述栅绝缘层叠置在所述栅极和沟道层之间；在所述沟道层上形成蚀刻阻挡层、源极和漏极，且所述刻蚀阻挡层设置在所述源极和漏极之间，其中，所述蚀刻阻挡层为AlN薄膜。
其中，所述在所述沟道层上形成蚀刻阻挡层，包括：利用磁控溅射设备，在铝箱中通入氮气、或包括氩气和氮气的混合气体，以在沟道层上溅射形成AlN薄膜。
其中，所述氩气与氮气的比值为0-90%。
其中，在AlN薄膜成膜时，所述基板的温度为25摄氏度-300摄氏度。
本申请第三方面提供一种显示面板，包括阵列基板，所述阵列基板包括基板和多个薄膜晶体管，所述薄膜晶体管包括设置在所述基板上的栅极、栅绝缘层、沟道层、蚀刻阻挡层、源极和漏极，所述栅绝缘层叠置在所述栅极和沟道层之间，以将所述栅极和沟道层绝缘，所述蚀刻阻挡层、源极和漏极分别设置在所述沟道层上，且所述刻蚀阻挡层设置在所述源极和漏极之间；其中，所述刻蚀阻挡层为氮化铝AlN薄膜；其中，所述栅绝缘层也为AlN薄膜，所述AlN薄膜是利用磁控溅射设备，在铝箱Al Chamber中通入氮气、或包括氩气和氮气的混合气体，溅射形成的。
其中，所述氩气与氮气的比值为0-90%。
其中，所述沟道层由金属氧化物构成。
上述方案中，采用AlN薄膜作为阵列基板的TFT的刻蚀阻挡层，由于AlN薄膜不含氢，故在刻蚀阻挡层成膜时，即使温度过高或过低，也不会导致沟道层还原或者刻蚀阻挡层出现孔洞的情况，进而保证了TFT的质量，而且，在AlN薄膜成膜时无需受到温度限制，降低了成膜要求，且可提高成膜速率。
【附图说明】
图1是本申请阵列基板一实施方式的结构示意图；
图2是本申请显示面板一实施方式的结构示意图；
图3是本申请阵列基板的制成方法一实施方式的流程图。
【具体实施方式】
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、接口、技术之类的具体细节，以便透彻理解本申请。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施方式中也可以实现本申请。在其它情况中，省略对众所周知的装置、电路以及方法的详细说明，以免不必要的细节妨碍本申请的描述。
请参阅图1，图1是本申请阵列基板一实施方式的结构示意图。本实施方式中，阵列基板100包括基板110和多个TFT 120（图1仅示范性示出基板110上的一个TFT120进行说明）。其中，所述基板110可以为玻璃基板或其他绝缘材料构成的透明基板。TFT 120包括设置在所述基板110上的栅极121、栅绝缘层122、沟道层123、源极124、漏极125和刻蚀阻挡层126。所述栅绝缘层122叠置在所述栅极121和沟道层123之间，以将所述栅极121和沟道层123绝缘，所述源极124和漏极125、刻蚀阻挡层126位于同一层，并分别设置在所述沟道层123上且刻蚀阻挡层126设置在源极124和漏极125之间，以间隔源极124和漏极125。当栅极121获得大于或等于开启电压的电压时，沟道层123感应出电子，使源极124和漏极125导通。
其中，所述刻蚀阻挡层126为氮化铝（化学式：AlN）薄膜。AlN薄膜为良好的绝缘材料，故可对源极124和漏极125间起到很好的绝缘作用。而且，AlN薄膜具有高的击穿场强（如AlN晶体为1.2-1.8MV/cm）、高热导率、高化学和热稳定性、以及在可见光范围可具备90%以上的穿透率等特点。另外，由于AlN 薄膜不含氢，故在刻蚀阻挡层成膜时，即使温度过高或过低，也不会导致沟道层还原或者刻蚀阻挡层出现孔洞的情况，进而保证了TFT的质量，而且，在AlN薄膜成膜时无需受到温度限制，降低了成膜要求，且可提高成膜速率。
在本实施方式中，所述沟道层123可由金属氧化物构成，例如为铟镓锌氧化物（英文：indium gallium zinc oxide，简称：IGZO）。
栅绝缘层121也可为AlN薄膜，由于AlN薄膜不含氢，可避免在阵列基板工作时，栅绝缘层含氢而捕捉或释放电子，使得TFT的阈值电压出现正向或负向漂移，从而保证了TFT的稳定性。
TFT 120还可包括覆盖在所述源极124和漏极125上的钝化层127。在其他实施方式中，在源极、漏极与钝化层之间还可设置硅化物层，以防止源极、漏极的Cu离子扩散到钝化层。
在上述结构中，所述栅极121、沟道层123、源极124和漏极125可采用物理气相沉积（英文：Physical Vapor Deposition，简称：PVD）生成，上述钝化层127可采用等离子体增强化学气相沉积法（英文：Plasma Enhanced Chemical Vapor Deposition，简称：PECVD）生成。
上述AlN薄膜可以由感应耦合等离子体（简称：ICP）设备进行刻蚀、或采用PVD如磁控溅射法制备得到。
在另一实施方式中，AlN薄膜利用磁控溅射设备制备得到。例如，在铝箱（英文：Al Chamber）中通入氮气、或包括氩气和氮气的混合气体，溅射形成的。其中，在通入混合气体的实施方式中，所述氩气与氮气的比值为0-90%，例如比值为0%、45%或90%。
在磁控溅射成膜过程中，基板的温度为25摄氏度-300摄氏度，例如具体为25、85或300摄氏度。故由于制备AlN薄膜如采用磁控溅射制备，无需高温，可在常温下进行，故可避免制备刻蚀阻挡层时对沟道层123的损伤，进而避免对TFT电性造成影响。而且，相对化学气相沉积(英文简称：CVD)，采用PVD制备AlN薄膜的成膜速率更高，产能得到提高。
在再一实施方式中，阵列基板还可包括设置在所述基板上的多条数据线、多条扫描线和多个像素电极（图未示出），所述数据线与所述TFT的源极连接，所述扫描线与所述TFT的栅极连接，像素电极与所述TFT的漏极连接。当扫描线向TFT的栅极输入大于或等于启动电压的电压时，TFT的源极和漏极导通，即数据线和像素电极连接，像素电极获得数据线输入的电压。
其中，为增加像素电极的开口率，源极、漏极和像素电极可是一体结构，由透明导电薄膜构成。
请参阅图2，图2是本申请显示面板一实施方式的结构示意图。本实施方式中，显示面板包括阵列基板210、彩膜基板220和夹置在阵列基板210、彩膜基板220之间的液晶230。其中，所述阵列基板210为上面实施方式描述的阵列基板，彩膜基板220可包括基板，以及分别设置在基板上的黑矩阵、彩色滤光层（英文：Color Filter ，简称：CF）、保护层及 ITO 膜。阵列基板的像素电极获取数据线输入的显示电压时，与彩膜基板的ITO膜之间形成电场，从而驱动液晶230发生偏转，形成显示图像。
请参阅图3，图3是本申请阵列基板的制成方法一实施方式的流程图。所述方法包括：
310：在基板上形成栅极、栅绝缘层、沟道层，其中，所述栅绝缘层叠置在所述栅极和沟道层之间。
本实施方式中，在基板上形成栅极，在栅极上覆盖栅绝缘层，再在栅绝缘层上形成沟道层。其中，所述栅极、沟道层可采用PVD生成。栅绝缘层可以为AlN薄膜。
320：在所述沟道层上形成刻蚀阻挡层、源极和漏极，且所述刻蚀阻挡层设置在所述源极和漏极之间，其中，所述蚀刻阻挡层为AlN薄膜。
在形成沟道层后，在沟道层上分别形成AlN薄膜、源极和漏极，其中，AlN薄膜作为刻蚀阻挡层，设置在源极和漏极之间。
AlN薄膜可以由ICP设备进行刻蚀、或采用PVD如磁控溅射法制备得到。例如，AlN薄膜利用磁控溅射设备，在铝箱中通入氮气、或包括氩气和氮气的混合气体，溅射形成的。其中，在通入混合气体的实施方式中，所述氩气与氮气的比值可为0-90%，例如比值为0%、45%或90%。在磁控溅射成膜过程中，基板的温度为25摄氏度-300摄氏度，例如具体为25、85或300摄氏度。故由于制备AlN薄膜如采用磁控溅射制备，无需高温，可在常温下进行，故可避免制备刻蚀阻挡层时对沟道层的损伤，进而避免对TFT电性造成影响。而且，相对化学气相沉积(英文简称：CVD)，采用PVD制备AlN薄膜的成膜速率更高，产能得到提高。可以理解的是，当310中形成的栅绝缘层为AlN薄膜时，可采用上述同样的方法制备AlN薄膜。
在另一实施方式中，还可分别源极和漏极上形成钝化层。
具体地，所述源极和漏极可采用PVD生成，上述钝化层可采用PECVD生成。
在再一实施方式中，所述制成方法还包括在基板上形成多条扫描线、多条数据线和多个像素电极。其中，所述数据线与所述TFT的源极电接触，所述扫描线与所述TFT的栅极电接触，像素电极与所述TFT的漏极电接触。
上述方案中，采用AlN薄膜作为阵列基板的TFT的刻蚀阻挡层，由于AlN薄膜不含氢，故在刻蚀阻挡层成膜时，即使温度过高或过低，也不会导致沟道层还原或者刻蚀阻挡层出现孔洞的情况，进而保证了TFT的质量，而且，在AlN薄膜成膜时无需受到温度限制，降低了成膜要求，且可提高成膜速率。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (12)

  1. 一种显示面板，其中，包括阵列基板，所述阵列基板包括基板和多个薄膜晶体管，所述薄膜晶体管包括设置在所述基板上的栅极、栅绝缘层、沟道层、蚀刻阻挡层、源极和漏极，所述栅绝缘层叠置在所述栅极和沟道层之间，以将所述栅极和沟道层绝缘，所述蚀刻阻挡层、源极和漏极分别设置在所述沟道层上，且所述刻蚀阻挡层设置在所述源极和漏极之间；其中，所述刻蚀阻挡层为氮化铝AlN薄膜；
    其中，所述栅绝缘层也为AlN薄膜，所述AlN薄膜是利用磁控溅射设备，在铝箱Al Chamber中通入氮气、或包括氩气和氮气的混合气体，溅射形成的。
  2. 根据权利要求1所述的显示面板，其中，所述氩气与氮气的比值为0-90%。
  3. 根据权利要求1所述的显示面板，其中，所述沟道层由金属氧化物构成。
  4. 一种阵列基板，其中，包括基板和多个薄膜晶体管，所述薄膜晶体管包括设置在所述基板上的栅极、栅绝缘层、沟道层、蚀刻阻挡层、源极和漏极，所述栅绝缘层叠置在所述栅极和沟道层之间，以将所述栅极和沟道层绝缘，所述蚀刻阻挡层、源极和漏极分别设置在所述沟道层上，且所述刻蚀阻挡层设置在所述源极和漏极之间；其中，所述刻蚀阻挡层为氮化铝AlN薄膜。
  5. 根据权利要求4所述的阵列基板，其中，所述AlN薄膜是利用磁控溅射设备，在铝箱Al Chamber中通入氮气、或包括氩气和氮气的混合气体，溅射形成的。
  6. 根据权利要求5所述的阵列基板，其中，所述氩气与氮气的比值为0-90%。
  7. 根据权利要求4所述的阵列基板，其中，所述栅绝缘层为AlN薄膜。
  8. 根据权利要求4所述的阵列基板，其中，所述沟道层由金属氧化物构成。
  9. 一种阵列基板的制成方法，其中，所述方法包括：
    在基板上形成栅极、栅绝缘层、沟道层，其中，所述栅绝缘层叠置在所述栅极和沟道层之间；
    在所述沟道层上形成蚀刻阻挡层、源极和漏极，且所述刻蚀阻挡层设置在所述源极和漏极之间，其中，所述蚀刻阻挡层为氮化铝AlN薄膜。
  10. 根据权利要求9所述的方法，其中，所述在所述沟道层上形成蚀刻阻挡层，包括：
    利用磁控溅射设备，在铝箱Al Chamber中通入氮气、或包括氩气和氮气的混合气体，以在沟道层上溅射形成AlN薄膜。
  11. 根据权利要求10所述的方法，其中，所述氩气与氮气的比值为0-90%。
  12. 根据权利要求10所述的方法，其中，在AlN薄膜成膜时，所述基板的温度为25摄氏度-300摄氏度。
PCT/CN2015/083745 2015-06-19 2015-07-10 一种阵列基板及其制成方法、显示面板 Ceased WO2016201752A1 (zh)

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