WO2016200882A1 - Affichage à micro-del sans transfert - Google Patents

Affichage à micro-del sans transfert Download PDF

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Publication number
WO2016200882A1
WO2016200882A1 PCT/US2016/036359 US2016036359W WO2016200882A1 WO 2016200882 A1 WO2016200882 A1 WO 2016200882A1 US 2016036359 W US2016036359 W US 2016036359W WO 2016200882 A1 WO2016200882 A1 WO 2016200882A1
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WO
WIPO (PCT)
Prior art keywords
gan
layer
silicon
silicon substrate
gan layer
Prior art date
Application number
PCT/US2016/036359
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English (en)
Inventor
Timothy James Orsley
Original Assignee
Corning Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Corning Incorporated filed Critical Corning Incorporated
Priority to KR1020187000502A priority Critical patent/KR20180018659A/ko
Priority to JP2017563576A priority patent/JP2018518843A/ja
Priority to CN201680033575.0A priority patent/CN107787527B/zh
Publication of WO2016200882A1 publication Critical patent/WO2016200882A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H01L33/501—Wavelength conversion elements characterised by the materials, e.g. binder
    • H01L33/502—Wavelength conversion materials
    • H01L33/504—Elements with two or more wavelength conversion materials

Definitions

  • Described herein are light emitting diode-based displays and methods of such displays.
  • the devices described herein incorporate micro- LED direct emissive technologies and methods of making such devices directly on LED wafers.
  • LEDs Light emitting diodes
  • an LED incorporates a chip of semiconducting material doped with impurities to create a p-n junction.
  • the electrons and holes usually recombine by a non-radiative transition, which produces no optical emission, because these are indirect band gap materials.
  • the materials used for the LED have a direct band gap with energies corresponding to near-infrared, visible, or near-ultraviolet light.
  • LEDs have many advantages over incandescent light sources, including lower energy consumption, longer lifetime, improved physical robustness, smaller size, and faster switching.
  • Light-emitting diodes are now used in applications diverse lighting applications.
  • LEDs powerful enough for room lighting are still relatively expensive, and require more precise current and heat management than compact fluorescent lamp sources of comparable output.
  • LED technology has continued to expand in a number of different ways. As demand and performance increase with smaller sized LEDs, there will be a continued need for improvements in efficiency, speed of operation, spectral control, and scalability. With reduction in size, fabrication issues become increasingly greater, especially with regard device isolation and global planarization.
  • a first aspect comprises a device comprising a silicon substrate comprising at least one via having a conductor material therein; a structured GaN layer comprising at least one independent GaN element and a void space on the silicon substrate; an optional buffer layer between the silicon substrate and the GaN layer; an optional planarizing layer on the silicon substrate or optional buffer layer and filling the void space between the at least one independent GaN element; a transparent conductor on the GaN layer and the optional planarizing layer; at least one wall element forming a well on the transparent conductor; a quantum dot material located in the well; and a transparent substrate on the wall element and well; wherein the GaN layer or optional buffer layer is exposed to the conductor material through the via.
  • a second aspect comprises a method of making the device of claim 1, the method comprising a. beginning with a silicon substrate optionally coated with a buffer layer and coated with a GaN layer, removing at least part of the GaN to produce a structured GaN layer comprising at least one independent GaN element and a void space on the silicon substrate; b. removing at least part of the silicon substrate under the at least one independent GaN element to form a via that exposes the GaN or optional buffer layer; c. inserting a conductor material into the via; d. optionally inserting a planarizing layer into the void space on the silicon substrate; e. forming a transparent conductor on the GaN layer and the optional planarizing layer; f. forming at least one wall element on the transparent conductor to produce at least one well; g. placing a quantum dot material in the well; and h. placing or forming a transparent substrate on the wall element and well.
  • FIGS. 1A-1G pictorially show an embodied process for forming embodied ⁇ _, ⁇ 05.
  • Fig. 1A shows, in cross section, a GaN layer 110 on a silicon substrate 120 with an optional buffer layer 115, to produce a GaN-on-Si wafer 100. Regions 110A and HOB are optional p-type and n-type regions of the GaN as discussed herein.
  • Fig. IB pictorially shows a cross section of the GaN-on-Si wafer 100 where the GaN 110 has been preferentially etched to produce isolated sections of the GaN 110'. In the step shown in Fig.
  • the silicon 120 is etched under the remaining GaN 110' regions to produce via 125 that allow access to the underside of the GaN 110'. As shown in Fig. ID, these via 125 are then metallized with a conducting material 130.
  • a planarization layer 140 is added around each of the GaN regions 110' and then a transparent conductor 150 is coated along the entire top of the device.
  • Fig. IF shows the fabrication of wall element 160 on the transparent conductor. Element 165 shows that the wall elements may have a vertical dimension much larger than the other components shown.
  • Fig. IF shows the fabrication of wall element 160 on the transparent conductor.
  • Element 165 shows that the wall elements may have a vertical dimension much larger than the other components shown.
  • 1G shows the formation of red, green and blue or blue scattering quantum dot wells 180 in the voids formed by wall elements 160, and then an encapsulation layer 170 is formed over the wall elements 160 and QD wells 180 to produce ⁇ , ⁇ display 190.
  • Ranges may be expressed herein as from “about” one particular value, and/or to "about” another particular value. When such a range is expressed, another aspect includes from the one particular value and/or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent "about,” it will be understood that the particular value forms another aspect. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint.
  • ⁇ ,, ⁇ Devices and Displays [0019] Aspects comprise novel ⁇ , ⁇ devices on GaN-on-silicon structures and methods of making such devices.
  • the ⁇ , ⁇ devices embodied herein are unique in that the silicon structure is retained and incorporated into the device and may provide both an insulative function and/or a support function for the ⁇ , ⁇ device while at the same time providing a very high resolution surface of mLEDs on the substrate.
  • the designs described herein would be unacceptable because using such a large amount of LED material to create a single display would not be economically viable. But in the case of near- eye displays such as those that would be attractive in virtual reality application, the tremendous density of LED material provides for the high resolution necessary when display is so close to the eye because of the magnification needed in order for the human eye to resolve.
  • the ⁇ ]-. ⁇ comprises a silicon substrate 120 comprising vias 125 having conductor materials 130 therein, a structured GaN layer on the silicon substrate, a transparent conductor on the GaN layer, wall elements forming wells on the transparent conductor, quantum dots in the wells, and a transparent substrate on top of the wall elements and wells.
  • the silicon substrate 120 comprises a mono- or polycrystalline silicon, such as a silicon wafer and can have any orientation or crystal structure that works with the GaN 110 or optional buffer layer.
  • the silicon substrate 120 may have a (100), (110), or (111) orientation or a combination of orientations (in the case of polycrystalline silicon.
  • the silicon substrate 120 is doped with small amounts of a dopant.
  • the dopant may comprise any element in any amount that works with the LED device 190, but in particular may comprise boron, phosphorous, arsenic, oxygen, or antimony in amounts from about 10 13 to about 10 16 atoms/cm 3 .
  • the vias 125 in the silicon can be of any size or shape that allows the device 190 to work properly. Based on the device 190 design, as shown in Fig. 1C, the vias 125 are generally of a size such that the silicon substrate 120 adequately supports the GaN material 110 and do not allow contact of the conductor materials outside of the GaN layer 110, as this minimizes the chance of shorting and optimizes conductor material use. In some embodiments, the vias, are just slightly smaller than the footprint of the GaN microLED and can be optimized for light extraction. However, where the optional planarizing layer is present and it can act as an insulator, the size of the via 125 may exceed the size of the GaN 110 in some regions or dimensions. In order to optimize substrate 120 usage, the via may be, in some embodiments, from about 1 ⁇ to about 50 ⁇ along their shortest in-plane dimension (i.e., not thickness).
  • the via, once formed, are then filled with a conductor material 130.
  • the conductor material 130 can be a metal or metal oxide, and especially in the case of a metal, can act as a reflector to enhance light output from the device 190.
  • Metals and metal oxides that can be used for the conductor material 130 can comprise Al, Au, Cu, Ag, Pt, etc.
  • a mirror layer can be coated on the underside of the GaN before filling the via with another conductor, such as a copper paste. This is due in part to the absorbance of silicon. Silicon itself is very absorbing so much so that those who make LEDs based upon GaN- on-Si transfer the GaN off the original wafer and bond another wafer to the top of the GaN after laying down a mirror.
  • an optional buffer layer 115 is present between the silicon and GaN layers. Because of the lattice differences between GaN 110 and silicon 120, it can be difficult to grow GaN on silicon.
  • the buffer layer 115 comprises a material that bridges the lattice difference between GaN 110 and silicon 120 by minimizing the lattice mismatch. The bridging can be done by using a material with a structure that is crystalline or amorphous, that has a structure that changes or varies structurally or compositionally when transitioning from the silicon-facing side to the GaN-facing side.
  • Possible buffer layers 115 comprise, for example, InGaN, AlGaN, Gd 2 03, Ga 2 03, A1N and Si3N4.
  • the buffer layer 115 when present, can be etched away at with the formation of the via, or if conducting, may be retained.
  • Fig. 1C shows the optional buffer layer 115 having been etched away.
  • the GaN layer 110 comprises GaN and may further include dopants such as aluminum or indium.
  • the GaN layer changes compositionally moving away from the silicon layer or buffer layer.
  • the GaN layer is of an n-type near or adjacent to the silicon/buffer layer (Region HOB in Fig. 1A) and has a composition that is doped with silicon or oxygen or other material to make it n-type, while at the region near or at the other face, the GaN is p-type and is doped with Mg or other material to make it p-type (Region 110A in Fig. 1A).
  • the GaN layer is etched starting from the face farthest away from the silicon - the exposed face - and then proceeds down toward the silicon face and silicon layer.
  • the GaN layer 110 is generally on the order of from about 1 ⁇ to about 100 ⁇ thick and can be etched into any reasonable shape with spacing between the etched GaN elements 110 being sufficient to prevent cross-talk or shorting - in some embodiments, from about 500 nm to about 5 ⁇ or more.
  • the optional planarizing layer 140 acts as an insulator to insulate the side walls of the GaN and in some embodiments, can act as a reflector.
  • the planarizing layer 140 can comprise any insulating material that can be easily coated onto the substrate and not cause issues with the operation of the device.
  • the planarizing layer 140 is an optionally photopolymerizable organic or inorganic polymer.
  • the planarizing layer 140 also serves as a reflector, it may further comprise organic or inorganic particles, such as nano- or microparticles, that scatter or reflect light.
  • the transparent conductor 150 is an optically transparent thin film that is electrically conducting, and may comprise a transparent conductive oxide (e.g., ITO, FTO, doped ZnO), organic or inorganic conductive polymer (e.g., PEDOT, PEDOT:PSS,etc), conductive transfer film, metal grid, carbon nanotubes, nanowires, or graphene, or the like.
  • a transparent conductive oxide e.g., ITO, FTO, doped ZnO
  • organic or inorganic conductive polymer e.g., PEDOT, PEDOT:PSS,etc
  • conductive transfer film metal grid, carbon nanotubes, nanowires, or graphene, or the like.
  • Quantum dot elements 180 comprise nanocrystalline semiconductor materials that exhibit quantum mechanical properties.
  • QD materials that can be used in the embodiments described herein generally comprise any known QD materials without limitation.
  • the size, composition, and quantity of QD elements 180 used in each well is within the ability of the skilled artisan, and can be modified for the application.
  • QDs that can be used include, for example, core-type, core-shell, and alloyed QDs of CdSe, CdS, ZnS, CdS x Sei- x /ZnS, InP/ZnS, PbS, etc.
  • the QD elements 180 may further comprise polymers or other carriers or support materials that the QDs are in the wells with.
  • the QD elements may have the same or different emission colors and may be structured or ordered to emit such colors in a particular arrangement.
  • the QD elements 180 shown in Fig. 1G have a repeating pattern of different colors, but could be arranged differently without impacting the embodiments described herein.
  • wall element 160 act to produce wells for the QD materials as well as acting to insulate the wells from each other, and in some embodiments, can act as a reflector.
  • the wall element 160 can comprise any non-conductive material that can be developed into a well like structure, is coatable onto the transparent conductor, and not cause issues with the operation of the device.
  • the wall element 160 is an optionally photopolymerizable organic or inorganic polymer.
  • the wall element 160 also serves as a reflector or scatterer, it may further comprise organic or inorganic particles, such as nano- or microparticles, that scatter or reflect light.
  • transparent substrate 170 may comprise a transparent glass, glass ceramic, polymer, or crystalline material that acts to encapsulate the QD elements.
  • the transparent substrate 170 can be a thin, ultrathin, and/or flexible material, such as a flexible glass substrate with a thickness of 300 um or less.
  • the transparent substrate 170 could be further coated with any number of films, such as anti-reflective, anti-fingerprint, anti-microbial or the like.
  • one or both sides of the transparent substrate 170 could be designed to scatter light via scattering films or by the substrate having a roughened or non-planar surface.
  • microLED are transferred from the source wafer to a separate display backplane. Transferring ⁇ _, ⁇ 05 from a formation substrate can be a difficult process as well as being quite costly.
  • the downside of not transferring the ⁇ ]-. ⁇ is that one wafer is that the formation substrate can't be reused, whereas a transfer approach allows for potentially multiple displays from a single wafer.
  • some applications e.g., virtual reality head mounted displays, may find the expense of an entire wafer per display to be compelling because of the extremely high resolution requirements for VR.
  • the current ⁇ ]-. ⁇ design and processes allow for high resolution ⁇ _, ⁇ 05 to be formed directly on a wafer without a need for transfer or removal of the silicon.
  • Previous methods for using forming ⁇ _, ⁇ 05 on silicon involve removal of the silicon substrate by etching.
  • the proposed invention selectively etches through a patterned photoresist rather than removing the entire substrate. Selective removal of the substrate provides the desired access to contact the bottom n-GaN layer.
  • Such viability is critical to the proposed invention because the invention relies upon creating through-silicon vias to address each subpixel from behind (with a common transparent electrode in front). Unlike sapphire, which is traditionally used for LED formation, silicon can be easily etched.
  • an optional buffer layer 115 is grown or formed on the silicon wafer 120.
  • the buffer layer 115 may be formed via known means including molecular beam epitaxy (MBE), chemical vapor deposition (CVD), etc., using known precursors, such as NH3 and Al or alternative components.
  • MBE molecular beam epitaxy
  • CVD chemical vapor deposition
  • the GaN layer 110 is then coated onto the buffer-coated silicon substrate 120 via known means including MBE, CVD, hydride vapor phase epitaxy, metalorganic vapor phase epitaxy, metal organic CVD, etc. to a desired thickness.
  • the GaN layer 110 is doped in such a way that the GaN layer goes from n-type to p-type moving away from the silicon 120 or optional buffer layer 115.
  • the GaN 110 and optionally, the optional buffer layer 115 are etched away using a mask and etching techniques known in the art, such wet or dry etching, and etchants such as silicon tetrachloride, bases, acids, peroxides, and laser-assisted etching, etc. to produce a GaN structure 110' comprising individual GaN elements of any desired shape, such as pillars, cubes, cylinders, pyramids, etc.
  • the GaN layer is etched starting from the face farthest away from the silicon - the exposed GaN face - and then proceeds down toward the silicon face and silicon layer.
  • the silicon 120 and optionally, the optional buffer layer 115 can be etched away using a mask and etching techniques known in the art, such wet or dry etching, and etchants such nitric acid, hydrofluoric acid, peroxides, bases, ethylene diamine pyrocatechol, amine gallate, TMAH, hydrazine, etc. to form via 125.
  • the silicon 120 is etched starting from the face farthest away from the GaN - the exposed silicon face - and then proceeds down toward the GaN face and GaN structure 110'.
  • the via 125 can be of any desired shape and can mimic the shape of the GaN structures 110' they are under. This step exposes the underside of the GaN structures 110' to allow for the formation of a circuit through the silicon substrate.
  • a conductor material 130 can be inserted into the via 125 by known processes as shown in Fig. ID, including vapor deposition processes optionally under vacuum, films, pastes, liquid coating, blading, or combinations thereof, etc. for example, a reflective metal layer may be deposited on the GaN layer through the via and then a copper paste used to fill the via and form the contact.
  • the conductor material 130 can comprise conducting metals and metal oxides such as Al, Au, Cu, Ag, Pt, etc.
  • Fig. IE shows the step where the optional planarizing layer 140 is coated onto the GaN-on-silicon substrate 100.
  • the planarizing layer 140 is designed to fill the voids around the GaN structures 110' without coating the upper surface that is the contact point for the transparent conductor 150.
  • the planarizing layer 140 may be placed on the device through mechanical or chemical means, including vapor deposition, chemical reaction, blading, etc.
  • a transparent conductor 150 is then placed on the GaN 110' and optional planarizing layer 140.
  • the transparent conductor may be deposited as a film, liquid, or vapor, and then may be allowed to set or crosslink, or undergo other chemical or physical process to adhere and set to the GaN and/or planarizing layer.
  • the transparent conductor might also be carried upon a transparent film.
  • the wall element 160 as shown in Fig. IF can be formed on the transparent conductor from any non-conductive material that can be developed into a well-like structure, is coatable onto the transparent conductor, and will not cause issues with the operation of the device 190.
  • the wall element 160 is formed via polymerization, lithography, etc.
  • a transparent substrate 170 The resulting device 190 is a ⁇ , ⁇ that utilizes and integrates the formation substrate and takes advantage of both micro-scale formation techniques and LED technology as well as the properties of QDs.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Devices (AREA)

Abstract

L'invention concerne des affichages à base de diode électroluminescente et des procédés de fabrication de tels affichages. En particulier, les dispositifs selon l'invention incorporent des technologies d'émission directe à micro-DEL (190) et des procédés de fabrication de tels dispositifs directement sur des plaquettes de DEL. Les dispositifs améliorés comprennent des couches de GaN (110') sur des substrats de silicium (120) dans la structure du dispositif, permettant un contact arrière à travers le silicium et une commande de micro-DEL individuelle tout en évitant l'utilisation de saphir ou la nécessité de transférer la micro-DEL sur un autre substrat.
PCT/US2016/036359 2015-06-08 2016-06-08 Affichage à micro-del sans transfert WO2016200882A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020187000502A KR20180018659A (ko) 2015-06-08 2016-06-08 전달이 없는 마이크로엘이디 디스플레이
JP2017563576A JP2018518843A (ja) 2015-06-08 2016-06-08 転写のないマイクロｌｅｄディスプレイ
CN201680033575.0A CN107787527B (zh) 2015-06-08 2016-06-08 无转移的微led显示器

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201562172393P 2015-06-08 2015-06-08
US62/172,393 2015-06-08

Publications (1)

Publication Number Publication Date
WO2016200882A1 true WO2016200882A1 (fr) 2016-12-15

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JP (1) JP2018518843A (fr)
KR (1) KR20180018659A (fr)
CN (1) CN107787527B (fr)
WO (1) WO2016200882A1 (fr)

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CN107331758A (zh) * 2017-06-27 2017-11-07 南方科技大学 一种Micro LED显示器件的制备方法
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WO2019109200A1 (fr) * 2017-12-04 2019-06-13 东旭集团有限公司 Substrat supérieur destiné à un composant del miniature, composant del miniature et dispositif d'affichage à del miniatures
WO2020260431A1 (fr) * 2019-06-28 2020-12-30 F. Hoffmann-La Roche Ag Procédé de production d'anticorps
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WO2023015257A1 (fr) * 2021-08-05 2023-02-09 Compound Photonics U.S. Corporation Systèmes et procédés de configuration d'un dispositif d'affichage et système d'affichage

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KR102008294B1 (ko) * 2018-04-13 2019-08-14 임성규 칼라 및 무늬 선정이 가능한 자가맞춤형 패션안경
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