WO2016192672A1 - 一种复位电路及电子设备 - Google Patents

一种复位电路及电子设备 Download PDF

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Publication number
WO2016192672A1
WO2016192672A1 PCT/CN2016/084741 CN2016084741W WO2016192672A1 WO 2016192672 A1 WO2016192672 A1 WO 2016192672A1 CN 2016084741 W CN2016084741 W CN 2016084741W WO 2016192672 A1 WO2016192672 A1 WO 2016192672A1
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WIPO (PCT)
Prior art keywords
resistor
circuit
transistor
reset
voltage signal
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Application number
PCT/CN2016/084741
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English (en)
French (fr)
Inventor
苏上丁
Original Assignee
广东欧珀移动通信有限公司
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Filing date
Publication date
Application filed by 广东欧珀移动通信有限公司 filed Critical 广东欧珀移动通信有限公司
Publication of WO2016192672A1 publication Critical patent/WO2016192672A1/zh
Priority to US15/470,411 priority Critical patent/US10014854B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0068—Battery or charger load switching, e.g. concurrent charging and load supply

Definitions

  • the present invention relates to the field of electronic device technologies, and in particular, to a reset circuit and an electronic device.
  • the electronic device generally has a reset function.
  • the reset function needs to be activated, that is, the electronic device can be restored to the initial state under the condition of constant power.
  • the reset in the electronic device mostly adopts a separate reset button or a power-off toggle switch.
  • mobile devices and electronic devices with secondary batteries such as MP3 and MP4 are generally implemented by resetting holes, but this method requires the user to access the reset hole by means of a small tool to complete the reset, if there is no suitable external tool. Unable to trigger reset, very inconvenient to use.
  • the embodiment of the invention provides a reset circuit, which does not need to change the structure and appearance of the electronic device, and can be reset by pressing an existing button, without using an external tool, and effectively avoiding false triggering. , bringing convenience to the user.
  • Embodiments of the present invention provide a reset circuit, including: a charging circuit, a driving circuit, an executing circuit, a control port, and a reset port; the charging circuit, an input end thereof, and the control a port connected, the output end being connected to the driving circuit, configured to generate a second voltage signal after receiving the first voltage signal provided by the control port; the driving circuit, the input end thereof and the output of the charging circuit Connected to the end, the output end is connected to the execution circuit, and configured to: after detecting that the value of the second voltage signal reaches a preset value, amplifying the second voltage signal, and amplifying the second voltage signal Outputting to the execution circuit; the execution circuit has an input end connected to an output end of the driving circuit, and an output end connected to the reset port, configured to generate after the amplified second voltage signal is received A reset signal is transmitted to the reset port.
  • the reset circuit further includes an inverting discharge circuit; the inverting discharge circuit has an input end connected to the control port, and an output end connected to the output end of the charging circuit for receiving the control
  • the fourth voltage signal is generated by the third voltage signal provided by the port.
  • the charging circuit includes: a resistor R4 and a capacitor C1; the resistor R4 and the capacitor C1 are connected in series to form a series branch, one end of the series branch is an input end of the charging circuit, and the other end is the charging circuit The output.
  • the driving circuit includes: a MOS transistor and a first power supply terminal; a gate of the MOS transistor is an input end of the driving circuit, and a source of the MOS transistor is an output end of the driving circuit; the MOS transistor The gate is connected to the output end of the charging circuit and the output end of the inverting discharge circuit, the source is connected to the input end of the execution circuit, the source is also grounded, and the drain is connected to the first power supply end .
  • the execution circuit includes: a transistor Q3, a capacitor C2, and a second power supply terminal; a base of the transistor Q3 is an input end of the execution circuit, and a collector of the transistor Q3 is an output end of the execution circuit; The transistor Q3 has a base connected to an output end of the driving circuit, a collector grounded through the capacitor C2, and an emitter grounded; the second power supply terminal is grounded through the capacitor C2.
  • the inverting discharge circuit includes a transistor Q1, a transistor Q2, and a third power supply terminal; a base of the transistor Q1 is an input end of the inverting discharge circuit, and a collector of the transistor Q2 is the reverse phase discharge.
  • the driving circuit further includes a resistor R6 and a resistor R7; the MOS transistor has a drain The resistor R6 is connected to the first power supply terminal, and the source is grounded through the resistor R7.
  • the execution circuit further includes: a resistor R8 and a resistor R9; the transistor Q3 has a base connected to an output end of the driving circuit via the resistor R8, a collector connected to the reset port, and an emitter grounded; The second power supply terminal is grounded through the resistor R9 and the capacitor C2.
  • the inverting discharge circuit further includes: a resistor R2, a resistor R3, and a resistor R5; the transistor Q1 has a base connected to the control port via the resistor R2, and a collector connected to the resistor via the resistor R5 The base of the transistor Q2 is connected; the third power supply terminal is connected to the collector of the transistor Q1 via the resistor R3.
  • An embodiment of the present invention further provides an electronic device including the above reset circuit, a button, and a microcontroller, wherein the control port provides the first voltage signal when the button is pressed; the reset port receives the When the signal is reset, the microcontroller is reset.
  • the embodiment of the present invention further provides a reset circuit, the reset circuit includes: a charging circuit, a driving circuit, an executing circuit, a control port, and a reset port; the charging circuit, an input end of the charging circuit, and the control port Connected to generate a second voltage signal after receiving the first voltage signal provided by the control port; the driving circuit, the input end of the driving circuit is connected to the output end of the charging circuit, After detecting that the value of the second voltage signal reaches a preset value, amplifying the second voltage signal, and outputting the amplified second voltage signal to the execution circuit; the execution circuit, the performing An input end of the circuit is connected to an output end of the driving circuit, and an output end of the executing circuit is connected to the reset port, and configured to generate a reset signal after receiving the amplified second voltage signal, and The reset signal is transmitted to the reset port.
  • the reset circuit includes: a charging circuit, a driving circuit, an executing circuit, a control port, and a reset port; the charging circuit, an input end
  • the reset circuit further includes an inverting discharge circuit, an input end of the inverting discharge circuit is connected to the control port, an output end of the inverting discharge circuit and the charging circuit The output end is connected to generate a fourth voltage signal after receiving the third voltage signal provided by the control port to discharge the charging circuit.
  • the charging circuit comprises: a resistor R4 and a capacitor C1, the resistor R4 is connected in series with the capacitor C1, one end of the resistor R4 is used as an input end of the charging circuit, and the resistor R4 The other end is connected to one end of the capacitor C1, the other end of the capacitor C1 is grounded, and a node between the other end of the resistor R4 and one end of the capacitor C1 serves as an output end of the charging circuit.
  • the charging circuit further includes a resistor R1, one end of the resistor R1 is connected to one end of the resistor R4, and the other end of the resistor is grounded.
  • the driving circuit comprises: a MOS transistor, a resistor R7 and a first power supply terminal, a gate of the MOS transistor is an input end of the driving circuit, and a source of the MOS transistor is the driving At the output end of the circuit, the source of the MOS transistor is also grounded through the resistor R7, and the drain of the MOS transistor is connected to the first power supply terminal.
  • the driving circuit further includes a resistor R6 connected between the first power supply terminal and the drain of the MOS transistor.
  • the execution circuit comprises: a transistor Q3, a capacitor C2 and a second power supply terminal, the base of the transistor Q3 is an input end of the execution circuit, and the collector of the transistor Q3 is the The output of the transistor is grounded, the emitter of the transistor Q3 is grounded; the collector of the transistor Q3 is grounded through the capacitor C2; and the second power supply terminal is grounded through the capacitor C2.
  • the execution circuit further includes: a resistor R8 and a resistor R9, wherein a base of the transistor Q3 is connected to an output end of the driving circuit via the resistor R8, and a collector of the transistor Q3 passes through the resistor R9 is connected to the second power supply end, and the second power supply end is grounded through the resistor R9 and the capacitor C2.
  • the inverting discharge circuit comprises a transistor Q1, a transistor Q2 and a third power supply terminal; a base of the transistor Q1 is an input end of the inverting discharge circuit, and a collector of the transistor Q2 An output end of the inverting discharge circuit; a collector of the transistor Q1 is connected to a base of the transistor Q2, an emitter of the transistor Q1 is grounded; and a collector of the transistor Q2 is connected to an input of the driving circuit The emitter of the transistor Q2 is grounded; the third power terminal is connected to the collector of the transistor Q1.
  • the inverting discharge circuit further includes: a resistor R2, a resistor R3, and a resistor R5;
  • the base of the transistor Q1 is connected to the control port via the resistor R2, and the collector of the transistor Q1 is connected to the base of the transistor Q2 via the resistor R5;
  • the third power supply terminal is connected to the collector of the transistor Q1 via the resistor R3.
  • the inverting discharge circuit includes: a resistor R2, a resistor R3, a resistor R5, a MOS transistor M1, a transistor Q2, and a third power supply terminal, wherein one end of the resistor R2 Connected to the control port; the gate of the MOS transistor M1 is connected to the other end of the resistor R2, the source of the MOS transistor M1 is grounded; one end of the resistor R5 and the drain of the MOS transistor M1 Connected; the base of the transistor Q2 is connected to the other end of the resistor R5, the emitter of the transistor Q2 is grounded, the collector of the transistor Q2 is connected to the output of the charging circuit; The terminal is connected to the drain of the MOS transistor M1 through the resistor R3.
  • the execution circuit includes: a resistor R8, a resistor R9, a MOS transistor M2, and a capacitor C2, and a second power supply terminal, wherein one end of the resistor R8 is connected to an output end of the driving circuit a gate of the MOS transistor M2 is connected to the other end of the resistor R8, a source of the MOS transistor M2 is grounded, a drain of the MOS transistor M2 is connected to the reset port; and one end of the resistor R9 Connected to the drain of the MOS transistor M2, the other end of the resistor R9 is connected to the second power supply terminal; one end of the capacitor C2 is connected to the drain of the MOS transistor M2, and the other of the capacitor C2 One end is grounded.
  • the first power supply terminal of the driving circuit, the second power supply terminal of the execution circuit, and the third power supply terminal of the inverting discharge circuit share a power source VCC.
  • the first voltage signal is a high level signal and the third voltage signal is a low level signal.
  • control port is associated with a button of an electronic device.
  • control port provides the first voltage signal when the button is triggered.
  • control port is arranged in association with a knob of an electronic device.
  • control port provides the first voltage signal when the knob is rotated to a preset position.
  • Embodiments of the present invention also provide an electronic device including the above reset circuit.
  • Embodiments of the present invention have the following advantageous effects:
  • the present invention devises a reset circuit that is applied to an electronic device including a button/knob and a microcontroller, if the button is pressed or the knob is rotated
  • the control port provides the first voltage signal, and then the charging circuit generates the second voltage signal after receiving the first voltage signal, and after the driving circuit detects that the value of the second voltage signal reaches a preset value, the second voltage signal is amplified and amplified.
  • the second voltage signal is output to the execution circuit, and the execution circuit generates a reset signal after receiving the amplified second voltage signal and transmits the signal to the reset port.
  • the bit port receives the reset signal, it resets the microcontroller to implement the electronic device reset function.
  • the reset operation when the reset operation is required, there is no need to make a large change to the structure and appearance of the electronic device, and it is not necessary to separately occupy a button to perform a reset operation, and the existing button or knob of the electronic device can be utilized.
  • the reset function can be realized by pressing the button or the knob rotation mode, and the external trigger is not needed, and the false trigger is effectively avoided, which brings convenience to the user.
  • FIG. 1 is a schematic structural diagram of a circuit of a first embodiment of a reset circuit according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a circuit principle of a second embodiment of a reset circuit according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a circuit principle of a third embodiment of a reset circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
  • a reset circuit according to an embodiment of the present invention will be described below with reference to FIG. 1 and FIG.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a reset circuit according to an embodiment of the present invention.
  • the reset circuit described in this embodiment includes a charging circuit 101, a driving circuit 102, an executing circuit 103, a control port 110, and a reset port 120. details as follows:
  • the charging circuit 101 has an input end connected to the control port 110, and an output end connected to the driving circuit 102, configured to generate a second voltage signal after receiving the first voltage signal provided by the control port 110;
  • the driving circuit 102 has an input end connected to the output end of the charging circuit 101, and an output end connected to the executing circuit 102 for detecting a voltage corresponding to the second voltage signal, that is, a voltage corresponding to the second voltage signal. After the value reaches a preset value, the second voltage signal is amplified, and the amplified second voltage signal is output to the execution circuit 103;
  • An execution circuit 103 having an input terminal connected to the output end of the driving circuit 102 and an output terminal connected to the reset port 120 for generating a reset signal after receiving the amplified second voltage signal, and The reset signal is transmitted to the reset port 120, and the reset operation is performed on the microcontroller in the electronic device through the reset port 120.
  • the first voltage signal is a high level signal
  • the second voltage signal is a level signal after the capacitor C1 is charged.
  • the control port 110 provided by the present invention can be integrated with the electronic device, and the control port 110 is associated with the button on the electronic device, so that when the button operation is performed on the electronic device, the control port 110 is triggered to provide the first a voltage signal, the charging circuit 101 generates a second voltage signal after receiving the first voltage signal, and when the value of the second voltage signal reaches a preset value, the driving circuit 102 amplifies the second voltage signal and the second amplified signal The voltage signal is output to the execution circuit 103, and the execution circuit 103 generates a reset signal after receiving the amplified second voltage signal and transmits it to the reset port 120.
  • the button operation may be a combination of pressing a certain button to reach a preset time, or simultaneously pressing and holding several buttons. Alternatively, the button operation may be replaced by a knob operation, which is not limited in the present invention.
  • FIG. 2 is a schematic structural diagram of a second embodiment of a reset circuit according to an embodiment of the present invention.
  • the reset circuit described in this embodiment includes a charging circuit 101, a driving circuit 102, an executing circuit 103, a control port 110, and a reset port 120. details as follows:
  • the charging circuit 101 has an input end connected to the control port 110, and an output end connected to the driving circuit 102, configured to generate a second voltage after receiving the first voltage signal provided by the control port 110. signal;
  • the charging circuit 101 includes a resistor R4 and a capacitor C1; wherein the resistor R4 and capacitor C1 are connected in series to form a series branch, one end of which is an input end of the charging circuit 101, and the other end is an output end of the charging circuit 101.
  • the resistor R4 is connected in series with the capacitor C1, one end of the resistor R4 is used as an input end of the charging circuit, and the other end of the resistor R4 is connected to one end of the capacitor C1.
  • the other end of the capacitor C1 is grounded, and a node between the other end of the resistor R4 and one end of the capacitor C1 serves as an output terminal of the charging circuit.
  • the charging circuit 101 further includes a resistor R1, and the control port 110 is grounded through the resistor R1. As shown in FIG. 2, one end of the resistor R1 is connected to one end of the resistor R4, and the other end of the resistor is grounded.
  • the first voltage signal is a high level signal
  • the second voltage signal is a level signal after the capacitor C1 is charged.
  • the control port 110 provided by the present invention can be integrated with the electronic device. When the button operation is performed on the electronic device, the control port 110 is triggered to provide a high level signal, and the capacitor C1 is charged through the resistor R4. The level of the capacitor C1 gradually increases.
  • the button operation may be a combination of pressing a button for a preset time, or simultaneously pressing and holding several buttons. Alternatively, the button operation may be replaced by a knob operation, which is not limited in the present invention.
  • the driving circuit 102 has an input end connected to the output end of the charging circuit 101, and an output end connected to the executing circuit 103 for detecting the level of the second voltage signal, that is, the level of the capacitor C1. After the value reaches a preset value, the second voltage signal is amplified, and the amplified second voltage signal is output to the execution circuit 103;
  • the driving circuit 102 includes: a MOS transistor and a first power supply terminal; a gate of the MOS transistor is an input end of the driving circuit 102, and a source of the MOS transistor is an output end of the driving circuit 102;
  • the MOS transistor has a gate connected to an output end of the charging circuit 101 and an output end of the inverting discharge circuit, a source connected to an input end of the execution circuit 103, and a drain connection of the MOS transistor The first power supply terminal is described.
  • the driving circuit 102 further includes a resistor R6 and a resistor R7; the MOS transistor has a drain connected to the first power supply terminal via the resistor R6, and a source thereof is grounded through the resistor R7.
  • the driving circuit includes: a MOS transistor, a resistor R7, and a first power supply terminal, and a resistor R6.
  • the gate of the MOS transistor is an input end of the driving circuit, and the MOS transistor
  • the source is extremely the output end of the driving circuit, and the source of the MOS transistor is also connected through the resistor R7
  • the drain of the MOS transistor is connected to the first power supply terminal.
  • the resistor R6 is connected between the first power supply terminal and the drain of the MOS transistor.
  • the MOS transistor of the driving circuit 102 when the level value of the capacitor C1 rises to a preset value, the MOS transistor of the driving circuit 102 is turned on, and at this time, the MOS transistor can amplify the level signal of the capacitor C1 reaching the preset value. It is then output to the execution circuit 103.
  • the MOS tube is used to perform threshold detection and amplification level signals.
  • the execution circuit 103 has an input end connected to the output end of the driving circuit 102, and an output end connected to the reset port 120 for generating a reset signal after receiving the amplified second voltage signal. And transmitting the reset signal to the reset port 120.
  • the execution circuit 103 includes a transistor Q3, a capacitor C2, and a second power supply terminal.
  • the base of the transistor Q3 is an input end of the execution circuit 103, and the collector of the transistor Q3 is the execution circuit 103.
  • the output terminal of the transistor Q3 is connected to the output end of the driving circuit 102, and its collector is grounded through the capacitor C2, and its emitter is grounded; the second power supply terminal is grounded through the capacitor C2.
  • the execution circuit 103 further includes: a resistor R8 and a resistor R9; the transistor Q3 has a base connected to the output end of the driving circuit 102 via the resistor R8, and a collector connected to the reset port 120, The emitter is grounded; the second power terminal is grounded through the resistor R9 and the capacitor C2.
  • the execution circuit includes: a transistor Q3, a capacitor C2 and a second power supply terminal, a resistor R8, and a resistor R9.
  • the base of the transistor Q3 is an input end of the execution circuit.
  • the collector of the transistor Q3 is the output terminal of the execution circuit, the emitter of the transistor Q3 is grounded, the collector of the transistor Q3 is grounded through the capacitor C2, and the second power supply terminal is grounded through the capacitor C2.
  • the base of the transistor Q3 is connected to the output end of the driving circuit via the resistor R8, the collector of the transistor Q3 is connected to the second power supply terminal via the resistor R9, and the second power supply terminal passes The resistor R9 and the capacitor C2 are grounded.
  • the second power supply terminal charges the capacitor C2 through the resistor R9; after the control port provides the first voltage signal, the source voltage of the MOS transistor Continue to rise until the transistor Q3 is turned on. At this time, the capacitor C2 is discharged, and after the capacitor C2 is discharged, a low level reset signal is generated, and the reset signal is transmitted to the reset port 120 to perform a reset operation.
  • the reset circuit may further include an inverting discharge circuit 104; the inverting discharge circuit 104 has an input end connected to the control port 110, and an output end thereof The output end of the charging circuit 101 is connected to generate a fourth voltage signal after receiving the third voltage signal provided by the control port 110 to discharge the charging circuit, that is, to discharge the capacitor C1.
  • the inverting discharge circuit 104 includes a transistor Q1, a transistor Q2, and a third power supply terminal; a base of the transistor Q1 is an input end of the inverting discharge circuit 104, and a collector of the transistor Q2 is the An output terminal of the inverting discharge circuit 104; the transistor Q1 has a base connected to the control port 110, a collector connected to the base of the transistor Q2, and an emitter grounded; the transistor Q2 has a base connection The collector of the transistor Q1 has a collector connected to the output end of the charging circuit 101 and an input end of the driving circuit 102, and an emitter thereof is grounded; and the third power supply terminal is connected to the collector of the transistor Q1.
  • the inverting discharge circuit 104 further includes: a resistor R2, a resistor R3, and a resistor R5; the transistor Q1 has a base connected to the control port 110 via the resistor R2, and a collector thereof passes through the resistor R5 Connected to the base of the transistor Q2; the third power supply terminal is connected to the collector of the transistor Q1 via the resistor R3.
  • the inverting discharge circuit includes a transistor Q1, a transistor Q2, and a third power supply terminal, a resistor R2, a resistor R3, and a resistor R5.
  • the base of the transistor Q1 is the input end of the inverting discharge circuit
  • the collector of the transistor Q2 is the output end of the inverting discharge circuit
  • the collector of the transistor Q1 is connected to the base of the transistor Q2
  • the emitter of the transistor Q1 is grounded
  • the collector of the transistor Q2 is connected to the input end of the driving circuit, the emitter of the transistor Q2 is grounded
  • the third power supply terminal is connected to the collector of the transistor Q1.
  • a base of the transistor Q1 is connected to the control port via the resistor R2, a collector of the transistor Q1 is connected to a base of the transistor Q2 via the resistor R5, and the third power supply end is A resistor R3 is connected to the collector of the transistor Q1.
  • the third voltage signal is a low level signal; when the control port provides a high level signal, the transistor Q1 of the inverting discharge circuit is turned on, and the transistor Q2 is turned off, and the inverting discharge circuit is charged.
  • the electric circuit has no effect; when the control port provides a low level signal, the capacitor C1 stops charging. At this time, the transistor Q1 is turned off, the transistor Q2 is turned on, and the inverting discharge circuit generates a fourth voltage signal to the capacitor C1.
  • the level signal value of the capacitor C1 rapidly drops to less than a preset value, so that the MOS transistor and the transistor Q3 are quickly turned off, and the capacitor C2 is continuously charged, gradually recovering to a high level, thereby ending the reset state.
  • the capacitor C1 can be quickly discharged, thereby ending the reset state, enabling the microcontroller to quickly enter the normal operating state after the reset operation is released, eliminating the reset effect.
  • control port may be arranged in association with a button of an electronic device. Wherein, when the button is triggered, the control port provides the first voltage signal.
  • control port may also be arranged in association with a knob of an electronic device. Wherein, the control port provides the first voltage signal when the knob is rotated to a preset position.
  • the first voltage signal is a high level signal
  • the second voltage signal is a level signal after the capacitor C1 is charged
  • the third signal is a low level signal.
  • the control port provides a high level signal
  • the capacitor C1 is charged through the resistor R4, and at this time, the transistor Q1 is turned on, the transistor Q2 is turned off, and the inverting discharge circuit has no effect; when the charged capacitor C1 is charged
  • the MOS transistor of the driving circuit is turned on (specifically, when the voltage difference between the gate of the MOS transistor and the source reaches 1.1V or 1.2V, the MOS can be turned on), the source of the MOS transistor The level continues to rise.
  • the transistor Q3 When the source level of the MOS transistor reaches a certain value (normally 0.5V or more), the transistor Q3 is turned on. At this time, the capacitor C2 is discharged and generates a low-level reset signal, and the reset port is reset. When the reset signal is received, the reset operation is performed; when the control port provides a low level signal, the capacitor C1 stops charging. At this time, the transistor Q1 is turned off, the transistor Q2 is turned on, the capacitor C1 is discharged, and the MOS transistor and the transistor Q3 are quickly turned off. C2 is continuously charged and does not continuously issue a reset signal.
  • a certain value normally 0.5V or more
  • the third voltage signal is a low level signal
  • the inverting discharge circuit 104 has an input end connected to the control port 110, and an output end connected to the output end of the charging circuit 101.
  • the capacitor C1 stops charging, and the inverting discharge circuit 104 discharges the capacitor C1, the level signal value of C1 drops rapidly, and the reset signal is also Release, charge through capacitor C2, and gradually return to high level, thus ending the reset state.
  • FIG. 3 is a schematic structural diagram of a third embodiment of a reset circuit according to the present invention.
  • the reset circuit described in this embodiment includes a charging circuit 101, a driving circuit 102, an executing circuit 103, a control port 110, and a reset port 120. details as follows:
  • the charging circuit 101 has an input end connected to the control port 110, and an output end connected to the driving circuit 102, configured to generate a second voltage after receiving the first voltage signal provided by the control port 110. signal;
  • the charging circuit 101 includes a resistor R4 and a capacitor C1.
  • the resistor R4 and the capacitor C1 are connected in series to form a series branch.
  • One end of the series branch is an input end of the charging circuit 101, and the other end is It is the output of the charging circuit 101.
  • the resistor R4 is connected in series with the capacitor C1, one end of the resistor R4 is used as an input end of the charging circuit, and the other end of the resistor R4 is connected to one end of the capacitor C1.
  • the other end of the capacitor C1 is grounded, and a node between the other end of the resistor R4 and one end of the capacitor C1 serves as an output terminal of the charging circuit.
  • the charging circuit 101 further includes a resistor R1, and the control port 110 is grounded through the resistor R1. As shown in FIG. 2, one end of the resistor R1 is connected to one end of the resistor R4, and the other end of the resistor is grounded.
  • the first voltage signal is a high level signal
  • the second voltage signal is a level signal after the capacitor C1 is charged.
  • the control port 110 provided by the present invention can be integrated with the electronic device. When the button operation is performed on the electronic device, the control port 110 is triggered to provide a high level signal, and the capacitor C1 is charged through the resistor R4. The level of the capacitor C1 gradually increases.
  • the button operation may be a combination of pressing a button for a preset time, or simultaneously pressing and holding several buttons. Alternatively, the button operation may be replaced by a knob operation, which is not limited in the present invention.
  • the driving circuit 102 has an input end connected to the output end of the charging circuit 101, and an output end connected to the executing circuit 103 for detecting the level of the second voltage signal, that is, the level of the capacitor C1. After the value reaches a preset value, the second voltage signal is amplified, and the amplified second voltage signal is output to the execution circuit 103;
  • the driving circuit 102 includes: a MOS transistor Q4 and a first power supply terminal; a gate of the MOS transistor Q4 is an input end of the driving circuit 102, and a source of the MOS transistor Q4 is substantially An output end of the driving circuit 102; the gate of the MOS transistor Q4 is connected to the output end of the charging circuit 101 and the output end of the inverting discharge circuit, and the source thereof is connected to the input end of the executing circuit 103.
  • the drain of the MOS transistor Q4 is connected to the first power supply terminal.
  • the driving circuit 102 further includes a resistor R6 and a resistor R7; the drain of the MOS transistor Q4 is connected to the first power supply terminal via the resistor R6, and a source thereof is grounded through the resistor R7.
  • the MOS transistor Q4 of the driving circuit 102 when the value of the level signal of the capacitor C1 rises to a preset value, the MOS transistor Q4 of the driving circuit 102 is turned on, and at this time, the MOS transistor Q4 can turn on the capacitor C1 that reaches the preset value.
  • the level signal is amplified and output to the execution circuit 103.
  • the MOS tube is used to perform threshold detection and amplification level signals.
  • the execution circuit 103 has an input end connected to the output end of the driving circuit 102, and an output end connected to the reset port 120 for generating a reset signal after receiving the amplified second voltage signal. And transmitting the reset signal to the reset port 120.
  • the execution circuit 103 includes: a field effect transistor M2, a capacitor C2, and a second power supply terminal; a gate of the field effect transistor M2 is an input end of the execution circuit 103, and a drain of the field effect transistor M2 is An output terminal of the execution circuit 103; the FET M2 has a gate connected to an output end of the driving circuit 102, a drain thereof is grounded through the capacitor C2, and a source thereof is grounded; the second power supply terminal Grounded through the capacitor C2.
  • the execution circuit 103 further includes: a resistor R8 and a resistor R9; the FET M2 has a gate connected to an output end of the driving circuit 102 via the resistor R8, and a drain connected to the reset port 120, the source is grounded; the second power supply terminal is grounded through the resistor R9 and the capacitor C2.
  • the execution circuit includes: a resistor R8, a resistor R9, a MOS transistor M2, and a capacitor C2, and a second power supply terminal, wherein one end of the resistor R8 and an output end of the driving circuit Connected; the gate of the MOS transistor M2 is connected to the other end of the resistor R8, the source of the MOS transistor M2 is grounded, the drain of the MOS transistor M2 is connected to the reset port; and the resistor R9 is One end is connected to the drain of the MOS transistor M2, the other end of the resistor R9 is connected to the second power supply terminal; one end of the capacitor C2 is connected to the drain of the MOS transistor M2, the capacitor The other end of C2 is grounded.
  • the second power supply terminal charges the capacitor C2 through the resistor R9; after the control port provides the first voltage signal, the source voltage of the MOS transistor Q4 continues to rise until The FET M2 is turned on, at which time the capacitor C2 is discharged, and after the capacitor C2 is discharged, a low level reset signal is generated, and the reset signal is transmitted to the reset port 120 to perform a reset operation.
  • the reset circuit may further include an inverting discharge circuit 104; the inverting discharge circuit 104 has an input end connected to the control port 110, and an output end thereof The output end of the charging circuit 101 is connected to generate a fourth voltage signal after receiving the third voltage signal provided by the control port 110 to discharge the charging circuit, that is, to discharge the capacitor C1.
  • the inverting discharge circuit 104 includes a field effect transistor M1, a transistor Q2, and a third power supply terminal; a gate of the field effect transistor M1 is an input end of the inversion discharge circuit 104, and a set of the transistor Q2 An electrode is an output end of the inverting discharge circuit 104; a gate of the field effect transistor M1 is connected to the control port 110, a drain thereof is connected to a base of the transistor Q2, and a source thereof is grounded; the transistor is Q2, the base thereof is connected to the drain of the FET M1, the collector is connected to the output end of the charging circuit 101 and the input end of the driving circuit 102, and the emitter thereof is grounded; the third power supply terminal is connected The drain of the field effect transistor M1.
  • the inverting discharge circuit 104 further includes: a resistor R2, a resistor R3, and a resistor R5; the field effect transistor M1 has a gate connected to the control port 110 via the resistor R2, and a drain thereof is A resistor R5 is coupled to the base of the transistor Q2; the third supply terminal is coupled to the drain of the field effect transistor M1 via the resistor R3.
  • the inverting discharge circuit includes: a resistor R2, a resistor R3, a resistor R5, a MOS transistor M1, a transistor Q2, and a third power supply terminal, wherein one end of the resistor R2 is a control port is connected; a gate of the MOS transistor M1 is connected to the other end of the resistor R2, a source of the MOS transistor M1 is grounded; and one end of the resistor R5 is connected to a drain of the MOS transistor M1; The base of the transistor Q2 is connected to the other end of the resistor R5, the emitter of the transistor Q2 is grounded, the collector of the transistor Q2 is connected to the output of the charging circuit; The resistor R3 is connected to the drain of the MOS transistor M1.
  • the third voltage signal is a low level signal; when the control port provides a high level signal, the field effect transistor M1 of the inverting discharge circuit is turned on, and the transistor Q2 is turned off, and the inverting discharge circuit is charged. The circuit has no effect; when the control port provides a low level signal, the capacitor C1 stops charging. At this time, the FET M1 is turned off, the transistor Q2 is turned on, and the inverting discharge circuit generates a fourth voltage signal to the capacitor C1.
  • the capacitor C1 performs a discharge operation, and the level signal value of the capacitor C1 rapidly drops to less than a preset value, so that the MOS transistor Q4 and the field effect transistor M2 are quickly turned off, and the capacitor C2 is continuously charged, gradually recovering to a high level, thereby ending the reset state. .
  • the capacitor C1 can be quickly discharged, thereby ending the reset state, enabling the microcontroller to quickly enter the normal operating state after the reset operation is released, eliminating the reset effect.
  • the first power supply end of the driving circuit, the second power supply end of the execution circuit, and the third power supply end of the inverting discharge circuit share a power supply. VCC.
  • FIG. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
  • An electronic device provided in the embodiment of the present invention includes the reset circuit 100 in the first embodiment or the second embodiment or the third embodiment, further includes a button 200 and a microcontroller 300, and the control port 110 is The first voltage signal is provided when the button 200 is pressed; the reset port 120 performs a reset operation on the microcontroller 300 when receiving the reset signal.
  • the reset circuit 100 When the reset circuit 100 is applied to an electronic device including the button 200 and the microcontroller 300, if the button 200 is operated such that the control port 110 provides the first voltage signal, the charging circuit 101 generates the first voltage signal.
  • the second voltage signal when the value of the second voltage signal reaches a preset value, the driving circuit 102 amplifies the second voltage signal and outputs the amplified second voltage signal to the execution circuit 103, and after the receiving circuit 103 receives the amplification
  • the second voltage signal generates a reset signal and is transmitted to the reset port 120.
  • the reset port 120 can be connected to the component to be reset on the electronic device.
  • the component to be reset is a microcontroller. When the reset port 120 receives the reset signal, it resets the microcontroller.
  • the button 200 can be a tact switch or a combination of several tact switches.
  • the operation of the button 200 may be to press and hold a tact switch for a preset time, or to simultaneously press and hold a combination of a few tact switches, at which time the control port 110 provides the first voltage signal.
  • the button operation may be replaced by a knob operation, which is not limited in the present invention.
  • a high level signal is generated when a button is pressed.
  • a low level signal is generated when the button is released.
  • the reset circuit in the embodiment of the present invention can be applied to different electronic devices.
  • the reset circuit is applied to the headphone power amplifier to perform a reset operation on the microcontroller of the headphone power amplifier.
  • the present invention devises a reset circuit.
  • the reset circuit When the reset circuit is applied to an electronic device including a button and a microcontroller, if the button is pressed, the control port provides the first voltage signal.
  • the charging circuit receives the first voltage signal, a second voltage signal is generated, and after the driving circuit detects that the value of the second voltage signal reaches a preset value, the second voltage signal is amplified and the amplified second voltage signal is output.
  • the execution circuit generates a reset signal after receiving the amplified second voltage signal and transmits the reset signal to the reset port, and the reset port resets the microcontroller when receiving the reset signal.
  • the driving circuit 102 is arranged to amplify the level signal of the capacitor C1 reaching the preset value, so as to avoid the situation that the driving capability of the charging circuit 101 is weak and cannot be driven because the value of the resistor R1 is large.
  • the inverting discharge circuit 104 is provided, and the capacitor C1 can be quickly discharged to end the reset state, and the microcontroller can quickly enter the normal working state after the reset operation is released, thereby eliminating the reset effect.
  • the reset operation when the reset operation needs to be performed, there is no need to make a large change to the structure and appearance of the electronic device, and it is not necessary to separately occupy a button to perform a reset operation exclusively, by using an existing button of the electronic device, by pressing a button
  • the implementation of the embodiment of the present invention is not easy to be triggered by mistake because the reset circuit of the embodiment of the present invention needs to delay the output of the capacitor C1 to output a reset signal. That is to say, when the button is associated with the control port, the button can be tapped and short pressed to achieve its basic function, and a long press will trigger the reset function.
  • the "display power request" function of the electronic device can be realized within 1 second by tapping the button, and the "switching the external power supply state” function of the electronic device can be realized by pressing for about 3 seconds, and the "reset” of the electronic device can be realized by long pressing for more than 15 seconds. Function, so that the reset function can be realized without adding a button, and it is not easy to trigger by mistake, which brings convenience to the user.

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Abstract

本发明提供了一种复位电路，包括：充电电路，用于在接收到控制端口提供的第一电压信号后，产生第二电压信号；驱动电路，用于在检测到第二电压信号的值达到预设值后，放大第二电压信号，并将放大后的第二电压信号输出给所述执行电路；执行电路，用于在接收到放大后的第二电压信号后产生复位信号并将所述复位信号传送给复位端口。本发明还提供了一种电子设备，包括上述复位电路、按键和微控制器，控制端口在按键被按压时提供第一电压信号；复位端口在接收到复位信号时，对微控制器进行复位操作。采用本发明实施例，无需单独占用一个按键来专门进行复位操作，通过按压已有按键的方式即可实现其复位功能，并且无需利用外部工具，也有效避免了误触。

Description

一种复位电路及电子设备
相关申请的交叉引用
本申请要求广东欧珀移动通信有限公司于2015年06月03日提交的、发明名称为“一种复位电路及电子设备”、中国专利申请号“201510300799.0”的优先权。
技术领域
本发明涉及电子设备技术领域，尤其涉及一种复位电路以及电子设备。
背景技术
在电子设备上一般都带有复位功能，当电子设备因操作不当或者产品内部出现问题而死机时，需要启动此复位功能，即能够在不断电的情况下，使电子设备恢复到初始状态。现有技术中，电子设备中的复位多采用单独的复位键或断电的拨动开关这种实现方式。例如手机设备和MP3、MP4等带二次电池的电子设备一般是通过复位孔来实现，但是这种方式需要用户借助细小的工具探入复位孔点触才能完成复位，如果没有合适的外部工具则无法触发复位，使用非常不方便。在有些平板电脑等设备中也尝试通过增加额外的复位键来实现，但是这种方式的缺点是，额外的复位键会影响设备的外观设计，且单独的复位键在日常使用中容易被误触发，不小心碰到就会导致设备重启，给用户带来不便。
发明内容
本发明实施例提供了一种复位电路，无需对电子设备的结构和外观进行较大的改变，可利用已有按键，通过按压按键即可实现复位，无需利用外部工具，且有效避免了误触发，给用户带来了方便。
本发明实施例提供了一种复位电路，所述复位电路包括：充电电路、驱动电路、执行电路、控制端口及复位端口；所述充电电路，其输入端与所述控制 端口相连，输出端与所述驱动电路相连，用于在接收到所述控制端口提供的第一电压信号后，产生第二电压信号；所述驱动电路，其输入端与所述充电电路的输出端相连，输出端与所述执行电路相连，用于在检测到所述第二电压信号的值达到预设值后，放大所述第二电压信号，并将放大后的所述第二电压信号输出给所述执行电路；所述执行电路，其输入端与所述驱动电路的输出端相连，输出端与所述复位端口相连，用于在接收到放大后的所述第二电压信号后产生复位信号并将所述复位信号传送给所述复位端口。
其中，所述复位电路还包括反相放电电路；所述反相放电电路，其输入端与所述控制端口相连，输出端与所述充电电路的输出端相连，用于在接收到所述控制端口提供的第三电压信号后产生第四电压信号。
其中，所述充电电路包括：电阻R4及电容C1；所述电阻R4及电容C1串联形成串联支路，所述串联支路的一端为所述充电电路的输入端，另一端为所述充电电路的输出端。
其中，所述驱动电路包括：MOS管及第一供电端；所述MOS管的栅极为所述驱动电路的输入端，所述MOS管的源极为所述驱动电路的输出端；所述MOS管，其栅极连接所述充电电路的输出端及所述反相放电电路的输出端，源极连接所述执行电路的输入端，所述源极还接地，漏极连接所述第一供电端。
其中，所述执行电路包括：三极管Q3、电容C2及第二供电端；所述三极管Q3的基极为所述执行电路的输入端，所述三极管Q3的集电极为所述执行电路的输出端；所述三极管Q3，其基极连接所述驱动电路的输出端，集电极通过所述电容C2接地，发射极接地；所述第二供电端通过所述电容C2接地。
其中，所述反相放电电路包括三极管Q1、三极管Q2及第三供电端；所述三极管Q1的基极为所述反相放电电路的输入端，所述三极管Q2的集电极为所述反相放电电路的输出端；所述三极管Q1，其基极连接所述控制端口，集电极连接所述三极管Q2的基极，发射极接地；所述三极管Q2，其基极连接所述三极管Q1的集电极，集电极连接所述充电电路的输出端及所述驱动电路的输入端，发射极接地；所述第三供电端连接所述三极管Q1的集电极。
其中，所述驱动电路还包括电阻R6及电阻R7；所述MOS管，其漏极经 所述电阻R6连接至所述第一供电端，源极通过所述电阻R7接地。
其中，所述执行电路还包括：电阻R8及电阻R9；所述三极管Q3，其基极经所述电阻R8连接至所述驱动电路的输出端，集电极连接所述复位端口，发射极接地；所述第二供电端通过所述电阻R9及电容C2接地。
其中，所述反相放电电路还包括：电阻R2、电阻R3、电阻R5；所述三极管Q1，其基极经所述电阻R2连接至所述控制端口，集电极经所述电阻R5连接至所述三极管Q2的基极；所述第三供电端经所述电阻R3连接至所述三极管Q1的集电极。
本发明实施例还提供一种电子设备，包括上述复位电路、按键和微控制器，所述控制端口在所述按键被按压时提供所述第一电压信号；所述复位端口在接收到所述复位信号时，对所述微控制器进行复位操作。
本发明实施例还提出了一种复位电路，所述复位电路包括：充电电路、驱动电路、执行电路、控制端口及复位端口；所述充电电路，所述充电电路的输入端与所述控制端口相连，用于在接收到所述控制端口提供的第一电压信号后，产生第二电压信号；所述驱动电路，所述驱动电路的输入端与所述充电电路的输出端相连，用于在检测到所述第二电压信号的值达到预设值后，放大所述第二电压信号，并将放大后的所述第二电压信号输出给所述执行电路；所述执行电路，所述执行电路的输入端与所述驱动电路的输出端相连，所述执行电路的输出端与所述复位端口相连，用于在接收到放大后的所述第二电压信号后产生复位信号，并将所述复位信号传送给所述复位端口。
根据本发明的一个实施例，所述复位电路还包括反相放电电路，所述反相放电电路的输入端与所述控制端口相连，所述反相放电电路的输出端与所述充电电路的输出端相连，用于在接收到所述控制端口提供的第三电压信号后产生第四电压信号，以对所述充电电路进行放电。
根据本发明的一个实施例，所述充电电路包括：电阻R4及电容C1，所述电阻R4与所述电容C1串联，所述电阻R4的一端作为所述充电电路的输入端，所述电阻R4的另一端与所述电容C1的一端相连，所述电容C1的另一端接地，所述电阻R4的另一端与所述电容C1的一端之间的节点作为所述充电电路的输出端。
并且，所述充电电路还包括：电阻R1，所述电阻R1的一端与所述电阻R4的一端相连，所述电阻的另一端接地。
根据本发明的一个实施例，所述驱动电路包括：MOS管、电阻R7及第一供电端，所述MOS管的栅极为所述驱动电路的输入端，所述MOS管的源极为所述驱动电路的输出端，所述MOS管的源极还通过所述电阻R7接地，所述MOS管的漏极连接所述第一供电端。
并且，所述驱动电路还包括：电阻R6，所述电阻R6连接在所述第一供电端与所述MOS管的漏极之间。
根据本发明的一个实施例，所述执行电路包括：三极管Q3、电容C2及第二供电端，所述三极管Q3的基极为所述执行电路的输入端，所述三极管Q3的集电极为所述执行电路的输出端，所述三极管Q3的发射极接地；所述三极管Q3的集电极通过所述电容C2接地；所述第二供电端通过所述电容C2接地。
并且，所述执行电路还包括：电阻R8及电阻R9，其中，所述三极管Q3的基极经所述电阻R8连接至所述驱动电路的输出端，所述三极管Q3的集电极经所述电阻R9连接至所述第二供电端，所述第二供电端通过所述电阻R9及电容C2接地。
根据本发明的一个实施例，所述反相放电电路包括三极管Q1、三极管Q2及第三供电端；所述三极管Q1的基极为所述反相放电电路的输入端，所述三极管Q2的集电极为所述反相放电电路的输出端；所述三极管Q1的集电极连接所述三极管Q2的基极，所述三极管Q1的发射极接地；所述三极管Q2的集电极连接所述驱动电路的输入端，所述三极管Q2的发射极接地；所述第三供电端连接所述三极管Q1的集电极。
并且，所述反相放电电路还包括：电阻R2、电阻R3、电阻R5；
所述三极管Q1的基极经所述电阻R2连接至所述控制端口，所述三极管Q1的集电极经所述电阻R5连接至所述三极管Q2的基极；
所述第三供电端经所述电阻R3连接至所述三极管Q1的集电极。
根据本发明的另一个实施例，所述反相放电电路包括：电阻R2、电阻R3、电阻R5、MOS管M1、三极管Q2和第三供电端，其中，所述电阻R2的一端 与所述控制端口相连；所述MOS管M1的栅极与所述电阻R2的另一端相连，所述MOS管M1的源极接地；所述电阻R5的一端与所述MOS管M1的漏极相连；所述三极管Q2的基极与所述电阻R5的另一端相连，所述三极管Q2的发射极接地，所述三极管Q2的集电极与所述充电电路的输出端相连；所述第三供电端通过所述电阻R3连接至所述MOS管M1的漏极。
根据本发明的另一个实施例，所述执行电路包括：电阻R8、电阻R9、MOS管M2和电容C2、第二供电端，其中，所述电阻R8的一端与所述驱动电路的输出端相连；所述MOS管M2的栅极与所述电阻R8的另一端相连，所述MOS管M2的源极接地，所述MOS管M2的漏极与所述复位端口相连；所述电阻R9的一端与所述MOS管M2的漏极相连，所述电阻R9的另一端与所述第二供电端相连；所述电容C2的一端与所述MOS管M2的漏极相连，所述电容C2的另一端接地。
根据本发明的一个实施例，所述驱动电路的第一供电端、所述执行电路的第二供电端和所述反相放电电路的第三供电端共用电源VCC。
根据本发明的一个实施例，所述第一电压信号为高电平信号，所述第三电压信号为低电平信号。
根据本发明的一个实施例，所述控制端口与电子设备的按键相关联设置。
并且，当所述按键被触发时，所述控制端口提供所述第一电压信号。
根据本发明的另一个实施例，所述控制端口与电子设备的旋钮相关联设置。
并且，当所述旋钮被旋转至预设位置时，所述控制端口提供所述第一电压信号。
本发明实施例还提出了一种电子设备，其包括上述的复位电路。
实施本发明实施例，具有如下有益效果：本发明设计了一种复位电路，当复位电路被应用到包含按键/旋钮和微控制器的电子设备中，如果按键被按下或旋钮被旋转操作使得控制端口提供第一电压信号，那么充电电路接收到第一电压信号后会产生第二电压信号，利用驱动电路检测到第二电压信号的值达到预设值后，放大第二电压信号并将放大后的第二电压信号输出给执行电路，执行电路在接收到放大后的第二电压信号后产生复位信号并传送给复位端口，复 位端口在接收到复位信号时，对微控制器进行复位操作，实现电子设备复位功能。采用本发明实施例，在需要进行复位操作时，无需对电子设备的结构和外观进行较大的改变，也不必单独占用一个按键来专门进行复位操作，可利用电子设备的已有按键或旋钮，通过按压按键的方式或旋钮旋转方式即可实现其复位功能，并且无需利用外部工具，也有效避免了误触发，给用户带来了方便。
附图说明
为了更清楚地说明本发明实施例技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种复位电路的第一实施例的电路结构示意图；
图2是本发明实施例提供的一种复位电路的第二实施例的电路原理示意图；
图3是本发明实施例提供的一种复位电路的第三实施例的电路原理示意图；
图4是本发明实施例提供的一种电子设备的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
下面将结合图1、图2对本发明实施例提供的一种复位电路进行描述。
请参阅图1，图1是本发明实施例提供的复位电路的第一实施例结构示意图。
本实施例中所描述的复位电路，包括：充电电路101、驱动电路102、执行电路103、控制端口110及复位端口120。具体如下：
充电电路101，其输入端与所述控制端口110相连，其输出端与所述驱动电路102相连，用于在接收到所述控制端口110提供的第一电压信号后，产生第二电压信号；
驱动电路102，其输入端与所述充电电路101的输出端相连，其输出端与所述执行电路102相连，用于在检测到所述第二电压信号的值即第二电压信号对应的电压值达到预设值后，放大所述第二电压信号，并将放大后的所述第二电压信号输出给所述执行电路103；
执行电路103，其输入端与所述驱动电路102的输出端相连，其输出端与所述复位端口120相连，用于在接收到放大后的所述第二电压信号后产生复位信号，并将所述复位信号传送给所述复位端口120，可通过复位端口120对电子设备中的微控制器进行复位操作。
在本发明实施例中，所述第一电压信号为高电平信号，所述第二电压信号为电容C1充电后的电平信号。具体地，可以将本发明提供的控制端口110与电子设备集成于一体，控制端口110与电子设备上的按键相关联设置，这样当在电子设备上进行按键操作时，会触发控制端口110提供第一电压信号，充电电路101接收到第一电压信号后会产生第二电压信号，当第二电压信号的值达到预设值时，驱动电路102会放大第二电压信号并将放大后的第二电压信号输出给执行电路103，执行电路103在接收到放大后的第二电压信号后产生复位信号并传送给复位端口120。具体地，所述按键操作可以是按住某一按键达到预设时间，或者同时按住几个按键的组合。或者，所述按键操作也可以替换为旋钮操作，本发明对此不作限制。
参见图2，图2为本发明实施例提供的复位电路的第二实施例的结构示意图。
本实施例中所描述的复位电路，包括：充电电路101、驱动电路102、执行电路103、控制端口110及复位端口120。具体如下：
所述充电电路101，其输入端与所述控制端口110相连，其输出端与所述驱动电路102相连，用于在接收到所述控制端口110提供的第一电压信号后，产生第二电压信号；
具体的，所述充电电路101，包括电阻R4及电容C1；其中，所述电阻 R4及电容C1串联形成串联支路，所述串联支路的一端为所述充电电路101的输入端，另一端为所述充电电路101的输出端。如图2所示，所述电阻R4与所述电容C1串联，所述电阻R4的一端作为所述充电电路的输入端，所述电阻R4的另一端与所述电容C1的一端相连，所述电容C1的另一端接地，所述电阻R4的另一端与所述电容C1的一端之间的节点作为所述充电电路的输出端。
进一步的，所述充电电路101还包括电阻R1，所述控制端口110通过所述电阻R1接地。如图2所示，所述电阻R1的一端与所述电阻R4的一端相连，所述电阻的另一端接地。
在本发明实施例中，所述第一电压信号为高电平信号，所述第二电压信号为电容C1充电后的电平信号。具体地，可以将本发明提供的控制端口110与电子设备集成于一体，当在电子设备上进行按键操作时，会触发控制端口110提供一个高电平信号，经电阻R4给电容C1充电，使电容C1的电平值逐渐升高。所述按键操作可以是按住某一按键达到预设时间，或者同时按住几个按键的组合。或者，所述按键操作也可以替换为旋钮操作，本发明对此不作限制。
所述驱动电路102，其输入端与所述充电电路101的输出端相连，其输出端与所述执行电路103相连，用于在检测到所述第二电压信号的值即电容C1的电平值达到预设值后，放大所述第二电压信号，并将放大后的所述第二电压信号输出给所述执行电路103；
具体地，所述驱动电路102包括：MOS管及第一供电端；所述MOS管的栅极为所述驱动电路102的输入端，所述MOS管的源极为所述驱动电路102的输出端；所述MOS管，其栅极连接所述充电电路101的输出端及所述反相放电电路的输出端，其源极连接所述执行电路103的输入端，所述MOS管的漏极连接所述第一供电端。
进一步，所述驱动电路102还包括电阻R6及电阻R7；所述MOS管，其漏极经所述电阻R6连接至所述第一供电端，其源极通过所述电阻R7接地。
也就是说，如图2所示，所述驱动电路包括：MOS管、电阻R7及第一供电端、电阻R6，所述MOS管的栅极为所述驱动电路的输入端，所述MOS管的源极为所述驱动电路的输出端，所述MOS管的源极还通过所述电阻R7接 地，所述MOS管的漏极连接所述第一供电端。所述电阻R6连接在所述第一供电端与所述MOS管的漏极之间。
在本发明实施例中，当电容C1的电平值升高到预设值时，驱动电路102的MOS管导通，此时MOS管能够将上述达到预设值的电容C1的电平信号放大后输出给所述执行电路103。通常情况下，因电阻R1的取值较大，充电电路101的驱动能力较弱，所以需要设置驱动电路102将达到预设值的电容C1的电平信号放大后传输给所述执行电路103。在本发明实施例中，是利用MOS管来进行阈值检测及放大电平信号。
所述执行电路103，其输入端与所述驱动电路102的输出端相连，其输出端与所述复位端口120相连，用于在接收到放大后的所述第二电压信号后产生复位信号，并将所述复位信号传送给所述复位端口120。
具体地，所述执行电路103包括：三极管Q3、电容C2及第二供电端；所述三极管Q3的基极为所述执行电路103的输入端，所述三极管Q3的集电极为所述执行电路103的输出端；所述三极管Q3，其基极连接所述驱动电路102的输出端，其集电极通过所述电容C2接地，其发射极接地；所述第二供电端通过所述电容C2接地。
进一步，所述执行电路103还包括：电阻R8及电阻R9；所述三极管Q3，其基极经所述电阻R8连接至所述驱动电路102的输出端，其集电极连接所述复位端口120，其发射极接地；所述第二供电端通过所述电阻R9及电容C2接地。
也就是说，如图2所示，所述执行电路包括：三极管Q3、电容C2及第二供电端、电阻R8及电阻R9，所述三极管Q3的基极为所述执行电路的输入端，所述三极管Q3的集电极为所述执行电路的输出端，所述三极管Q3的发射极接地，所述三极管Q3的集电极通过所述电容C2接地，所述第二供电端通过所述电容C2接地。所述三极管Q3的基极经所述电阻R8连接至所述驱动电路的输出端，所述三极管Q3的集电极经所述电阻R9连接至所述第二供电端，所述第二供电端通过所述电阻R9及电容C2接地。
在本实施例中，在控制端口提供第一电压信号之前，第二供电端通过电阻R9给电容C2充电；在控制端口提供第一电压信号之后，MOS管的源极电压 持续升高直到使三极管Q3导通，此时电容C2放电，而电容C2放电之后会产生低电平复位信号，该复位信号被传送给复位端口120，从而进行复位操作。
作为一个可选的实施方式，本发明实施例中，所述复位电路还可以包括反相放电电路104；所述反相放电电路104，其输入端与所述控制端口110相连，其输出端与所述充电电路101的输出端相连，用于在接收到所述控制端口110提供的第三电压信号后产生第四电压信号，以对所述充电电路进行放电，即对电容C1进行放电操作。
具体地，所述反相放电电路104包括三极管Q1、三极管Q2及第三供电端；所述三极管Q1的基极为所述反相放电电路104的输入端，所述三极管Q2的集电极为所述反相放电电路104的输出端；所述三极管Q1，其基极连接所述控制端口110，其集电极连接所述三极管Q2的基极，其发射极接地；所述三极管Q2，其基极连接所述三极管Q1的集电极，其集电极连接所述充电电路101的输出端及所述驱动电路102的输入端，其发射极接地；所述第三供电端连接所述三极管Q1的集电极。
进一步，所述反相放电电路104还包括：电阻R2、电阻R3、电阻R5；所述三极管Q1，其基极经所述电阻R2连接至所述控制端口110，其集电极经所述电阻R5连接至所述三极管Q2的基极；所述第三供电端经所述电阻R3连接至所述三极管Q1的集电极。
也就是说，如图2所示，所述反相放电电路包括三极管Q1、三极管Q2及第三供电端、电阻R2、电阻R3、电阻R5。所述三极管Q1的基极为所述反相放电电路的输入端，所述三极管Q2的集电极为所述反相放电电路的输出端；所述三极管Q1的集电极连接所述三极管Q2的基极，所述三极管Q1的发射极接地；所述三极管Q2的集电极连接所述驱动电路的输入端，所述三极管Q2的发射极接地；所述第三供电端连接所述三极管Q1的集电极。所述三极管Q1的基极经所述电阻R2连接至所述控制端口，所述三极管Q1的集电极经所述电阻R5连接至所述三极管Q2的基极，所述第三供电端经所述电阻R3连接至所述三极管Q1的集电极。
在本实施例中，第三电压信号为低电平信号；当控制端口提供高电平信号，反相放电电路的三极管Q1导通，而三极管Q2截止，此时反相放电电路对充 电电路无作用；而当控制端口提供低电平信号，电容C1停止充电，此时三极管Q1截止，三极管Q2导通，反相放电电路会对所述电容C1产生一个第四电压信号，对电容C1进行放电操作，电容C1的电平信号值迅速下降到小于预设值，使MOS管和三极管Q3迅速截止，而电容C2被继续充电，逐渐恢复高电平，从而结束复位状态。通过设置反相放电电路104，可以对电容C1进行快速放电，从而结束复位状态，在放开复位操作后使微控制器能够迅速进入正常工作状态，消除复位影响。
根据本发明的一个实施例，所述控制端口可与电子设备的按键相关联设置。其中，当所述按键被触发时，所述控制端口提供所述第一电压信号。
根据本发明的另一个实施例，所述控制端口还可与电子设备的旋钮相关联设置。其中，当所述旋钮被旋转至预设位置时，所述控制端口提供所述第一电压信号。
下面结合图2对本发明实施例提供的一种复位电路的工作原理做一个详细介绍。
所述第一电压信号为高电平信号，所述第二电压信号为电容C1充电后的电平信号，所述第三信号为低电平信号。当控制端口提供高电平信号时，在充电电路中，通过电阻R4给电容C1充电，而此时三极管Q1导通，三极管Q2截止，反相放电电路无作用；当充电后的电容C1的电平值达到预设值时，驱动电路的MOS管导通(具体的，MOS管的栅极比源极的压差达到1.1V或者1.2V时，MOS即可导通)，MOS管的源极电平持续升高，当MOS管的源极电平达到一定值(一般情况下0.5V以上即可)时，三极管Q3导通，此时电容C2会放电并产生低电平复位信号，复位端口接收到复位信号时，会进行复位操作；当控制端口提供低电平信号时，电容C1停止充电，此时三极管Q1截止，三极管Q2导通，电容C1放电，MOS管和三极管Q3迅速截止，电容C2被继续充电，不会持续发出复位信号。
在本实施例中，第三电压信号为低电平信号，反相放电电路104，其输入端与所述控制端口110相连，其输出端与所述充电电路101的输出端相连，当控制端口110提供一个低电平信号时，此时电容C1停止充电，反相放电电路104会对所述电容C1进行放电，C1的电平信号值迅速下降，而复位信号也被 放开，通过电容C2充电，逐渐恢复高电平，从而结束复位状态。
参见图3，图3为本发明提供的复位电路的第三实施例的结构示意图。
本实施例中所描述的复位电路，包括：充电电路101、驱动电路102、执行电路103、控制端口110及复位端口120。具体如下：
所述充电电路101，其输入端与所述控制端口110相连，其输出端与所述驱动电路102相连，用于在接收到所述控制端口110提供的第一电压信号后，产生第二电压信号；
具体的，所述充电电路101，包括电阻R4及电容C1；其中，所述电阻R4及电容C1串联形成串联支路，所述串联支路的一端为所述充电电路101的输入端，另一端为所述充电电路101的输出端。如图3所示，所述电阻R4与所述电容C1串联，所述电阻R4的一端作为所述充电电路的输入端，所述电阻R4的另一端与所述电容C1的一端相连，所述电容C1的另一端接地，所述电阻R4的另一端与所述电容C1的一端之间的节点作为所述充电电路的输出端。
进一步的，所述充电电路101还包括电阻R1，所述控制端口110通过所述电阻R1接地。如图2所示，所述电阻R1的一端与所述电阻R4的一端相连，所述电阻的另一端接地。
在本发明实施例中，所述第一电压信号为高电平信号，所述第二电压信号为电容C1充电后的电平信号。具体地，可以将本发明提供的控制端口110与电子设备集成于一体，当在电子设备上进行按键操作时，会触发控制端口110提供一个高电平信号，经电阻R4给电容C1充电，使电容C1的电平值逐渐升高。所述按键操作可以是按住某一按键达到预设时间，或者同时按住几个按键的组合。或者，所述按键操作也可以替换为旋钮操作，本发明对此不作限制。
所述驱动电路102，其输入端与所述充电电路101的输出端相连，其输出端与所述执行电路103相连，用于在检测到所述第二电压信号的值即电容C1的电平值达到预设值后，放大所述第二电压信号，并将放大后的所述第二电压信号输出给所述执行电路103；
具体地，所述驱动电路102包括：MOS管Q4及第一供电端；所述MOS管Q4的栅极为所述驱动电路102的输入端，所述MOS管Q4的源极为所述 驱动电路102的输出端；所述MOS管Q4，其栅极连接所述充电电路101的输出端及所述反相放电电路的输出端，其源极连接所述执行电路103的输入端，所述MOS管Q4的漏极连接所述第一供电端。
进一步，所述驱动电路102还包括电阻R6及电阻R7；所述MOS管Q4，其漏极经所述电阻R6连接至所述第一供电端，其源极通过所述电阻R7接地。
在本发明实施例中，当电容C1的电平信号的值升高到预设值时，驱动电路102的MOS管Q4导通，此时MOS管Q4能够将上述达到预设值的电容C1的电平信号放大后输出给所述执行电路103。通常情况下，因电阻R1的取值较大，充电电路101的驱动能力较弱，所以需要设置驱动电路102将达到预设值的电容C1的电平信号放大后传输给所述执行电路103。在本发明实施例中，是利用MOS管来进行阈值检测及放大电平信号。
所述执行电路103，其输入端与所述驱动电路102的输出端相连，其输出端与所述复位端口120相连，用于在接收到放大后的所述第二电压信号后产生复位信号，并将所述复位信号传送给所述复位端口120。
具体地，所述执行电路103包括：场效应管M2、电容C2及第二供电端；所述场效应管M2的栅极为所述执行电路103的输入端，所述场效应管M2的漏极为所述执行电路103的输出端；所述场效应管M2，其栅极连接所述驱动电路102的输出端，其漏极通过所述电容C2接地，其源极接地；所述第二供电端通过所述电容C2接地。
进一步，所述执行电路103还包括：电阻R8及电阻R9；所述场效应管M2，其栅极经所述电阻R8连接至所述驱动电路102的输出端，其漏极连接所述复位端口120，其源极接地；所述第二供电端通过所述电阻R9及电容C2接地。
也就是说，如图3所示，所述执行电路包括：电阻R8、电阻R9、MOS管M2和电容C2、第二供电端，其中，所述电阻R8的一端与所述驱动电路的输出端相连；所述MOS管M2的栅极与所述电阻R8的另一端相连，所述MOS管M2的源极接地，所述MOS管M2的漏极与所述复位端口相连；所述电阻R9的一端与所述MOS管M2的漏极相连，所述电阻R9的另一端与所述第二供电端相连；所述电容C2的一端与所述MOS管M2的漏极相连，所述电容 C2的另一端接地。
在本实施例中，在控制端口提供第一电压信号之前，第二供电端通过电阻R9给电容C2充电；在控制端口提供第一电压信号之后，MOS管Q4的源极电压持续升高直到使场效应管M2导通，此时电容C2放电，而电容C2放电之后产生低电平复位信号，该复位信号被传送给所复位端口120，从而进行复位操作。
作为一个可选的实施方式，本发明实施例中，所述复位电路还可以包括反相放电电路104；所述反相放电电路104，其输入端与所述控制端口110相连，其输出端与所述充电电路101的输出端相连，用于在接收到所述控制端口110提供的第三电压信号后产生第四电压信号，以对所述充电电路进行放电，即对电容C1进行放电操作。
具体地，所述反相放电电路104包括场效应管M1、三极管Q2及第三供电端；所述场效应管M1的栅极为所述反相放电电路104的输入端，所述三极管Q2的集电极为所述反相放电电路104的输出端；所述场效应管M1，其栅极连接所述控制端口110，其漏极连接所述三极管Q2的基极，其源极接地；所述三极管Q2，其基极连接所述场效应管M1的漏极，其集电极连接所述充电电路101的输出端及所述驱动电路102的输入端，其发射极接地；所述第三供电端连接所述场效应管M1的漏极。
进一步，所述反相放电电路104还包括：电阻R2、电阻R3、电阻R5；所述场效应管M1，其栅极经所述电阻R2连接至所述控制端口110，其漏极经所述电阻R5连接至所述三极管Q2的基极；所述第三供电端经所述电阻R3连接至所述场效应管M1的漏极。
也就是说，如图3所示，所述反相放电电路包括：电阻R2、电阻R3、电阻R5、MOS管M1、三极管Q2和第三供电端，其中，所述电阻R2的一端与所述控制端口相连；所述MOS管M1的栅极与所述电阻R2的另一端相连，所述MOS管M1的源极接地；所述电阻R5的一端与所述MOS管M1的漏极相连；所述三极管Q2的基极与所述电阻R5的另一端相连，所述三极管Q2的发射极接地，所述三极管Q2的集电极与所述充电电路的输出端相连；所述第三供电端通过所述电阻R3连接至所述MOS管M1的漏极。
在本实施例中，第三电压信号为低电平信号；当控制端口提供高电平信号，反相放电电路的场效应管M1导通，而三极管Q2截止，此时反相放电电路对充电电路无作用；而当控制端口提供低电平信号，电容C1停止充电，此时场效应管M1截止，三极管Q2导通，反相放电电路会对所述电容C1产生一个第四电压信号，对电容C1进行放电操作，电容C1的电平信号值迅速下降到小于预设值，使MOS管Q4和场效应管M2迅速截止，而电容C2被继续充电，逐渐恢复高电平，从而结束复位状态。通过设置反相放电电路104，可以对电容C1进行快速放电，从而结束复位状态，在放开复位操作后使微控制器能够迅速进入正常工作状态，消除复位影响。
在本发明的实施例中，如图2或图3所示，所述驱动电路的第一供电端、所述执行电路的第二供电端和所述反相放电电路的第三供电端共用电源VCC。
参见图4，图4为本发明实施例提供的一种电子设备的结构示意图。
本发明实施例中提供的一种电子设备，包括上述第一实施例或第二实施例或第三实施例中的复位电路100，还包括按键200和微控制器300，所述控制端口110在所述按键200被按压时提供所述第一电压信号；所述复位端口120在接收到所述复位信号时，对所述微控制器300进行复位操作。
当复位电路100被应用到包含按键200和微控制器300的电子设备中，如果对按键200进行操作，使得控制端口110提供第一电压信号，那么充电电路101接收到第一电压信号后会产生第二电压信号，当第二电压信号的值达到预设值时，驱动电路102会放大第二电压信号并将放大后的第二电压信号输出给执行电路103，执行电路103在接收到放大后的第二电压信号后产生复位信号并传送给复位端口120，复位端口120可以与电子设备上的待复位元件连接，在本发明实施例中，待复位元件为微控制器。当复位端口120接收到复位信号时，会对微控制器进行复位操作。其中，按键200可以是轻触开关或者几个轻触开关的组合。对按键200的操作可以是按住某一轻触开关达到预设时间，或者同时按住某几个轻触开关的组合，此时所述控制端口110提供所述第一电压信号。或者，所述按键操作也可以替换为旋钮操作，本发明对此不作限制。
需要说明的是，在本实施例的应用场景中，按下按键时产生高电平信号， 松开按键时产生低电平信号。本发明实施例中的复位电路可以应用到不同的电子设备中，在本实施例中，复位电路是应用于耳机功率放大器上，对耳机功率放大器的微控制器进行复位操作。
实施本发明实施例，具有如下有益效果：本发明设计了一种复位电路，当复位电路被应用到包含按键和微控制器的电子设备中，如果按键被按下使得控制端口提供第一电压信号，那么充电电路接收到第一电压信号后会产生第二电压信号，利用驱动电路检测到第二电压信号的值达到预设值后，放大第二电压信号并将放大后的第二电压信号输出给执行电路，执行电路在接收到放大后的第二电压信号后产生复位信号并传送给复位端口，复位端口在接收到复位信号时，对微控制器进行复位操作。同时，设置驱动电路102将达到预设值的电容C1的电平信号放大，避免出现因电阻R1的取值较大，充电电路101的驱动能力较弱而无法进行驱动的情况。进一步，设置反相放电电路104，可以对电容C1进行快速放电，从而结束复位状态，在放开复位操作后使微控制器能够迅速进入正常工作状态，消除复位影响。采用本发明实施例，在需要进行复位操作时，无需对电子设备的结构和外观进行较大的改变，也不必单独占用一个按键来专门进行复位操作，利用电子设备的已有按键，通过按压按键的方式即可实现其复位功能，并且无需利用外部工具，也有效避免了误触发。
其中，需要说明的是，实施本发明实施例之所以不容易误触发，是因为本发明实施例的复位电路需要通过电容C1充电的方式进行延时来输出复位信号。也就是说，当按键与控制端口相关联时，按键可以轻触、短按实现其基本功能，而长按才会触发复位功能。例如，轻触按键1秒以内实现电子设备“显示电量请求”功能，短按3秒左右可以实现电子设备“切换对外供电状态”功能，而长按15秒以上则可以实现电子设备的“复位”功能，从而无需增加按键就能实现复位功能，同时还不容易误触发，给用户带来方便。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (20)

  1. 一种复位电路，其特征在于，所述复位电路包括：充电电路、驱动电路、执行电路、控制端口及复位端口；
    所述充电电路，所述充电电路的输入端与所述控制端口相连，用于在接收到所述控制端口提供的第一电压信号后，产生第二电压信号；
    所述驱动电路，所述驱动电路的输入端与所述充电电路的输出端相连，用于在检测到所述第二电压信号的值达到预设值后，放大所述第二电压信号，并将放大后的所述第二电压信号输出给所述执行电路；
    所述执行电路，所述执行电路的输入端与所述驱动电路的输出端相连，所述执行电路的输出端与所述复位端口相连，用于在接收到放大后的所述第二电压信号后产生复位信号，并将所述复位信号传送给所述复位端口。
  2. 根据权利要求1所述的复位电路，其特征在于，所述复位电路还包括反相放电电路，所述反相放电电路的输入端与所述控制端口相连，所述反相放电电路的输出端与所述充电电路的输出端相连，用于在接收到所述控制端口提供的第三电压信号后产生第四电压信号，以对所述充电电路进行放电。
  3. 根据权利要求1或2所述的复位电路，其特征在于，所述充电电路包括：电阻R4及电容C1，所述电阻R4与所述电容C1串联，所述电阻R4的一端作为所述充电电路的输入端，所述电阻R4的另一端与所述电容C1的一端相连，所述电容C1的另一端接地，所述电阻R4的另一端与所述电容C1的一端之间的节点作为所述充电电路的输出端。
  4. 根据权利要求1所述的复位电路，其特征在于，所述驱动电路包括：MOS管、电阻R7及第一供电端，所述MOS管的栅极为所述驱动电路的输入端，所述MOS管的源极为所述驱动电路的输出端，所述MOS管的源极还通过所述电阻R7接地，所述MOS管的漏极连接所述第一供电端。
  5. 根据权利要求4所述的复位电路，其特征在于，所述驱动电路还包括：电阻R6，所述电阻R6连接在所述第一供电端与所述MOS管的漏极之间。
  6. 根据权利要求1所述的复位电路，其特征在于，所述执行电路包括：三极管Q3、电容C2及第二供电端，所述三极管Q3的基极为所述执行电路的输入端，所述三极管Q3的集电极为所述执行电路的输出端，所述三极管Q3的发射极接地；
    所述三极管Q3的集电极通过所述电容C2接地；
    所述第二供电端通过所述电容C2接地。
  7. 根据权利要求6所述的复位电路，其特征在于，所述执行电路还包括：电阻R8及电阻R9，其中，所述三极管Q3的基极经所述电阻R8连接至所述驱动电路的输出端，所述三极管Q3的集电极经所述电阻R9连接至所述第二供电端，所述第二供电端通过所述电阻R9及电容C2接地。
  8. 根据权利要求2所述的复位电路，其特征在于，所述反相放电电路包括三极管Q1、三极管Q2及第三供电端；
    所述三极管Q1的基极为所述反相放电电路的输入端，所述三极管Q2的集电极为所述反相放电电路的输出端；
    所述三极管Q1的集电极连接所述三极管Q2的基极，所述三极管Q1的发射极接地；
    所述三极管Q2的集电极连接所述驱动电路的输入端，所述三极管Q2的发射极接地；
    所述第三供电端连接所述三极管Q1的集电极。
  9. 根据权利要求8所述的复位电路，其特征在于，所述反相放电电路还包括：电阻R2、电阻R3、电阻R5；
    所述三极管Q1的基极经所述电阻R2连接至所述控制端口，所述三极管Q1的集电极经所述电阻R5连接至所述三极管Q2的基极；
    所述第三供电端经所述电阻R3连接至所述三极管Q1的集电极。
  10. 根据权利要求3所述的复位电路，其特征在于，所述充电电路还包括：电阻R1，所述电阻R1的一端与所述电阻R4的一端相连，所述电阻的另一端接地。
  11. 根据权利要求2所述的复位电路，其特征在于，所述反相放电电路包括：电阻R2、电阻R3、电阻R5、MOS管M1、三极管Q2和第三供电端，其中，
    所述电阻R2的一端与所述控制端口相连；
    所述MOS管M1的栅极与所述电阻R2的另一端相连，所述MOS管M1的源极接地；
    所述电阻R5的一端与所述MOS管M1的漏极相连；
    所述三极管Q2的基极与所述电阻R5的另一端相连，所述三极管Q2的发射极接地，所述三极管Q2的集电极与所述充电电路的输出端相连；
    所述第三供电端通过所述电阻R3连接至所述MOS管M1的漏极。
  12. 根据权利要求1所述的复位电路，其特征在于，所述执行电路包括：电阻R8、电阻R9、MOS管M2和电容C2、第二供电端，其中，
    所述电阻R8的一端与所述驱动电路的输出端相连；
    所述MOS管M2的栅极与所述电阻R8的另一端相连，所述MOS管M2的源极接地，所述MOS管M2的漏极与所述复位端口相连；
    所述电阻R9的一端与所述MOS管M2的漏极相连，所述电阻R9的另一端与所述第二供电端相连；
    所述电容C2的一端与所述MOS管M2的漏极相连，所述电容C2的另一端接地。
  13. 根据权利要求2所述的复位电路，其特征在于，所述驱动电路的第一供电端、所述执行电路的第二供电端和所述反相放电电路的第三供电端共用电 源VCC。
  14. 根据权利要求2所述的复位电路，其特征在于，所述第一电压信号为高电平信号，所述第三电压信号为低电平信号。
  15. 根据权利要求1-14中任一项所述的复位电路，其特征在于，所述控制端口与电子设备的按键相关联设置。
  16. 根据权利要求15所述的复位电路，其特征在于，当所述按键被触发时，所述控制端口提供所述第一电压信号。
  17. 根据权利要求1-14中任一项所述的复位电路，其特征在于，所述控制端口与电子设备的旋钮相关联设置。
  18. 根据权利要求17所述的复位电路，其特征在于，当所述旋钮被旋转至预设位置时，所述控制端口提供所述第一电压信号。
  19. 一种电子设备，其特征在于，包括根据权利要求1-18中任一项所述的复位电路。
  20. 一种电子设备，其特征在于，包括：
    根据权利要求1至16中任一项所述的复位电路；
    按键和微控制器；
    所述控制端口在所述按键被按压时提供所述第一电压信号；
    所述复位端口在接收到所述复位信号时，对所述微控制器进行复位操作。
PCT/CN2016/084741 2015-06-03 2016-06-03 一种复位电路及电子设备 WO2016192672A1 (zh)

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