WO2019015110A1 - 芯片烧录电路及系统 - Google Patents

芯片烧录电路及系统 Download PDF

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Publication number
WO2019015110A1
WO2019015110A1 PCT/CN2017/103765 CN2017103765W WO2019015110A1 WO 2019015110 A1 WO2019015110 A1 WO 2019015110A1 CN 2017103765 W CN2017103765 W CN 2017103765W WO 2019015110 A1 WO2019015110 A1 WO 2019015110A1
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Prior art keywords
circuit
chip
switch
usb
control circuit
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PCT/CN2017/103765
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English (en)
French (fr)
Inventor
霍东建
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广州视源电子科技股份有限公司
广州睿鑫电子科技有限公司
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Publication of WO2019015110A1 publication Critical patent/WO2019015110A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/61—Installation

Definitions

  • the utility model relates to the field of electronic technology, in particular to a chip burning circuit and system.
  • the processing chip on the electronic device determines the processing performance of the electronic device.
  • Most of the existing electronic devices such as a tablet computer, a smart TV, a TV set-top box and the like use a domestic chip, for example, an intelligent processing chip of a Rockchip (RK) platform.
  • RK Rockchip
  • the processing chips of the existing Ruixin Micro (PK) platform are mostly applied to electronic devices such as mobile phones, tablet computers, smart TVs, set-top boxes, etc.
  • the one end of the USB brush cable needs to be connected first. Go to the USB port on the computer, and then use the tweezers, toothpicks or paper clips to hold the reset button on the chip board of the electronic device, and then plug the other end of the dual male USB cable into the chip of the electronic device.
  • the USB interface on the motherboard when the brush tool on the computer shows red light, release the reset button, then the brush tool on the computer will appear low, then write the program, and finally finish the RK platform chip burning.
  • the external part of the fuselage reduces the device opening, and when the chip board of the RK platform is installed inside the electronic device, there is still a chip burning.
  • this makes it impossible for the user to press the reset button on the chip motherboard inside the fuselage to realize the burning of the chip, which causes the chip of the electronic device to be unable to be burned.
  • the electronic device needs to be disassembled and removed to take the motherboard. Burn.
  • the purpose of the present invention is to provide a chip burning circuit and system, which solves the problem that the chip cannot be burned inside the electronic device.
  • the embodiment of the present invention provides a chip burning circuit, and the specific technical solutions are as follows:
  • the utility model provides a chip burning circuit, which is applied to a main board of a chip burning device, A first switch is disposed on an outer surface of the chip burning device, the first switch controls the chip burning device to be turned on or off, and the first switch is connected to a system power supply circuit, and the circuit includes:
  • switch control circuit wherein the switch control circuit is respectively connected to the first switch and the USB circuit, wherein the USB circuit is connected to the programming host through a USB connection circuit;
  • a second switch disposed inside the chip burning device, wherein the second switch is respectively connected to the switch control circuit and the processing chip;
  • chip power supply circuit wherein the chip power supply circuit is respectively connected to the USB circuit and the processing chip, and when the USB circuit is connected, the chip power supply circuit starts to work to supply power to the processing chip;
  • the switch control circuit controls the second switch to be closed to cause the processing chip to perform chip burning.
  • the chip programming circuit provided by the utility model provides the same effect of closing the first switch by pressing and closing the first switch when the switch control circuit and the chip power supply circuit are set in the burning state, when in the normal power-on state Pressing closes the first switch and the second switch remains open.
  • the first switch of the chip burning circuit simultaneously realizes the multiplexing of the booting and the burning function, and solves the problem that the electronic device cannot be burned due to the inability of the second switch (reset switch) to be pressed inside the chip burning device. . It satisfies the requirement that the electronic device does not need to be opened in the electronic device due to the waterproof requirement, thereby solving the problem that the chip cannot be burned inside the electronic device.
  • chip programming circuit provided by the present invention may further have the following additional technical features:
  • the switch control circuit includes:
  • first sub-switch control circuit wherein the first sub-switch control circuit is respectively connected to the first switch and the USB circuit, and when the first switch is closed and the USB circuit is in a connected state, the first The output of the sub-switch control circuit is at a high level;
  • a second sub-switch control circuit wherein the second sub-switch control circuit is respectively connected to an output end of the first sub-switch control circuit and the second switch, when an output end of the first sub-switch control circuit is high At the level, the second switch is closed.
  • the first sub-switch control circuit includes a first FET and the first field effect
  • the first resistor connected to the first field effect transistor is a MOS transistor, and the drain, the gate and the source of the first field effect transistor are sequentially connected to the first resistor, the first switch, and the ground Connecting, the first resistor is connected to the USB circuit, and one end of the first switch connected to the first FET is further connected to a second resistor, and the second resistor is connected to the system power supply circuit. The other end of the first switch is connected to the ground.
  • the second sub-switch control circuit includes a second FET and a third resistor connected to the second FET, the second FET is a MOS transistor, and the second FET a gate and a source are sequentially connected to a drain and a ground of the first field effect transistor, and a drain of the second field effect transistor is respectively connected to the third resistor and the second switch, wherein the A three resistor is coupled to the system power supply circuit, and the other end of the second switch is coupled to ground.
  • chip power supply circuit is further connected to the system power supply circuit, and is configured to supply power to the processing chip by using the system power supply circuit, where the chip power supply circuit includes:
  • USB power supply control circuit is connected to the USB circuit, and when the USB circuit is in a connected state, controlling the chip power supply circuit to operate;
  • USB switch control circuit wherein the USB switch control circuit is respectively connected to the USB circuit and the third sub-switch control circuit, and when the third sub-switch control circuit stops working, the USB circuit is controlled to stop working.
  • the USB power supply control circuit includes a Zener diode, an anode of the Zener diode is connected to the USB circuit, and a cathode of the Zener diode is connected to an output end of the chip power supply circuit.
  • the third sub-switch control circuit includes a fourth resistor connected to the processing chip, a triode connected to the fourth resistor, a fifth resistor connected to the triode, a base of the triode, The collector and the emitter are sequentially connected to the fourth resistor, the fifth resistor, and the ground, and the fifth resistor is connected to the output end of the chip power supply circuit.
  • the USB switch control circuit includes a third FET, a first capacitor connected to a drain of the third FET, a sixth resistor, and a source connected to the third FET.
  • a second capacitor, the second capacitor and the seventh resistor connected to a gate of the third field effect transistor, the first The other end of the capacitor and the sixth resistor are grounded, the other end of the seventh resistor is connected to the collector of the transistor, and the drain of the third field effect transistor is also connected to the USB circuit, the third field The source of the effect transistor is also coupled to the output of the chip supply circuit.
  • first FET and the second FET are both N-channel depletion MOS transistors.
  • Another embodiment of the present invention provides a chip burning system, including a chip burning device, a burning host, and a USB connecting circuit respectively connected to the chip burning device and the burning host, the burning
  • the recording host is configured to perform chip burning for the chip burning device, and the chip burning device includes the chip burning circuit described above.
  • FIG. 1 is a schematic structural diagram of a chip burning system according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a connection environment circuit of a switch control circuit in a chip burning circuit in a chip burning system according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a connection environment circuit of a chip power supply circuit in a chip burning circuit in a chip burning system according to an embodiment of the present invention.
  • the terms “installation”, “connected”, “connected”, “fixed” and the like shall be understood broadly, and may be fixed or detachable, for example, unless otherwise explicitly defined and defined. Connected, or integrally connected; can be mechanical or electrical; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of the two components.
  • Connected, or integrally connected can be mechanical or electrical; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of the two components.
  • the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.
  • the term “and/or” used herein includes any and all combinations of one or more of the associated listed items.
  • a chip burning system 10 includes a chip burning device 100 , a programming host 200 (computer), and a chip burning device 100 and a programming host 200 respectively.
  • a USB connection circuit 300 USB connector
  • the programming host 200 is used for chip burning of the chip burning device 100, wherein the chip in the chip burning device 100 adopts a processing chip of a Rockchip (PK) platform
  • PK Rockchip
  • the reset switch second switch 113
  • the chip burning device 100 includes a chip burning circuit 110, a USB circuit 120, and a first switch 130.
  • the USB circuit 120 is connected to the chip burning circuit 110 for USB signal communication and power supply requirements are provided for the chip programming circuit 110.
  • the USB circuit 120 is also connected to the USB connection circuit 300.
  • the USB connection circuit 300 is connected to the programming host 200 for signal communication between the programming host 200 and the chip burning device 100.
  • the first switch 130 (power switch) is disposed on the outer surface of the chip burning device 100. The first switch 130 is pressed to control the power on or off of the chip burning device 100.
  • FIG. 2 and FIG. 3 are schematic diagrams showing a part of the circuit structure of the chip burning device 100 in the chip burning system 10 of FIG. 1 , wherein the chip programming circuit 110 includes a system power supply circuit 111 , a switch control circuit 112 , and a second switch . 113.
  • the chip programming circuit 110 is applied to the main board of the chip burning device 100 for implementing the chip burning function on the main board.
  • the system power supply circuit 111 starts to work as the main board. Power is supplied, and the first switch 130 is connected to the system power supply circuit 111.
  • the USB circuit 120 is connected to the USB interface of the chip burning device 100 for connecting to the USB interface and the USB interface of the programming host 200 through the USB connection circuit 300 to implement the chip burning circuit 110 and the programming host 200. Signal communication between.
  • the switch control circuit 112 is connected to the first switch 130 and the USB circuit 120, respectively, and the second switch 113 is connected to the switch control circuit 112 and the processing chip 115, respectively.
  • the switch control circuit 112 includes a first sub-switch control circuit 1121 and a second sub-switch control circuit 1122.
  • the first sub-switch control circuit 1121 is respectively connected to the first switch 130 and the USB circuit 120, and the first sub-switch controls the electric
  • the circuit 1121 includes a first field effect transistor Q1 and a first resistor R1 connected to the first field effect transistor Q1.
  • the first field effect transistor Q1 is a MOS transistor, and the drain d, the gate g, and the source of the first field effect transistor Q1.
  • the pole s is sequentially connected to the first resistor R1, the first switch 130, and the ground.
  • the first resistor R1 is connected to the USB circuit 120, and the end of the first switch 130 connected to the first field effect transistor Q1 is further connected to the second resistor R2.
  • the second resistor R2 is connected to the system power supply circuit 111, and the other end of the first switch 130 is connected to the ground.
  • the second sub-switch control circuit 1122 is respectively connected to the output end of the first sub-switch control circuit 1121 and the second switch 113.
  • the second sub-switch control circuit 1122 includes a second FET Q2 and is connected to the second FET Q2.
  • the second field effect transistor Q2 is a MOS transistor, and the gate g and the source s of the second field effect transistor Q2 are sequentially connected to the drain d and ground of the first field effect transistor Q1, and the drain d of the second field effect transistor Q2. It is connected to the third resistor R3 and the second switch 113, respectively.
  • the third resistor R3 is connected to the system power supply circuit 111, and the other end of the second switch 113 is connected to the ground.
  • the chip power supply circuit 114 is respectively connected to the USB circuit 120, the system power supply circuit 111, and the processing chip 115.
  • the chip power supply circuit 114 can supply power to the processing chip 115 through the system power supply circuit 111 or the USB circuit 120.
  • the chip power supply circuit 114 includes a USB.
  • the USB power supply control circuit 1141 includes a Zener diode D.
  • the anode of the Zener diode D is connected to the USB circuit 120, and the cathode of the Zener diode D is connected to the output terminal 1144 of the chip power supply circuit 114.
  • the USB power supply control circuit 1141 is connected to the USB circuit 120.
  • the chip power supply circuit 114 is controlled by the one-way conduction of the Zener diode D, so that the output terminal 1144 of the chip power supply circuit 114 is powered.
  • the flat output controls the operation of the chip power supply circuit 114 to supply power to the processing chip 115.
  • the third sub-switch control circuit 1142 is connected to the processing chip 115.
  • the third sub-switch control circuit 1142 includes a fourth resistor R11 connected to the processing chip 115, a transistor T connected to the fourth resistor R11, and a fifth resistor R12 connected to the transistor T.
  • the base b, the collector c, and the emitter e of the transistor T are sequentially connected to the fourth resistor R11, the fifth resistor R12, and the ground.
  • the fifth resistor R12 is connected to the output terminal 1144 of the chip power supply circuit 114.
  • the USB switch control circuit 1143 is respectively connected to the USB circuit 120 and the third sub-switch control circuit 1142.
  • the USB switch control circuit 1143 includes a third FET Q3 and a third FET. a first capacitor C11 connected to the drain d of Q3, a sixth resistor R13, a second capacitor C12 connected to the source s of the third field effect transistor Q3, and a second connected to the gate g of the third field effect transistor Q3.
  • Capacitor C12 and seventh resistor R14 Capacitor C12 and seventh resistor R14.
  • the other end of the first capacitor C11 and the sixth resistor R13 are grounded, the other end of the seventh resistor R14 is connected to the collector c of the transistor T, and the drain d of the third field effect transistor Q3 is also connected to the USB circuit 120.
  • the source s of the three field effect transistor Q3 is also coupled to the output 1144 of the chip supply circuit 114.
  • the first field effect transistor Q1 and the second field effect transistor Q2 are both N-channel depletion MOS transistors (D-shaped NMOS transistors).
  • the USB circuit 120 is connected to the USB connection circuit 300, the USB connection circuit 300 is connected to the programming host 200, so that when the USB circuit 120 is in the on state, the USB circuit 120 outputs a high level, thus causing the first FET Q1 to be guided. Therefore, the drain d of the first field effect transistor Q1 is connected to the source s, and the voltage is 0; when the USB circuit 120 is not in operation, its output voltage is 0, so the drain d of the first field effect transistor Q1 The voltage is also zero.
  • the first switch 130 When the first switch 130 is pressed and closed, the voltage of one end connected to the first resistor R1 is 0, so the voltage of the gate g of the first field effect transistor Q1 is also 0, and at this time, when the USB circuit 120 is in the on state When the USB circuit 120 outputs a high level, the first field effect transistor Q1 is turned off, so the drain d of the first field effect transistor Q1 is at a high level. Therefore, when the first switch 130 is closed and the USB circuit 120 is in the on state, the output of the first sub-switch control circuit 1121 is at a high level, due to the drain d of the first FET Q1 and the second FET Q2.
  • the gate g is connected, so the gate g of the second field effect transistor Q2 is also at a high level, so that the second field effect transistor Q2 is turned on at this time, and the drain d voltage of the second field effect transistor Q2 is 0.
  • both ends of the second switch 113 are respectively connected to the ground and the drain d of the second field effect transistor Q2. Therefore, when the voltage of the drain d of the second field effect transistor Q2 is 0, the voltage across the second switch 113 is When it is 0, the second switch 113 is controlled to be closed, thereby achieving the effect of pressing and closing the first switch 130 to close the second switch 113. Therefore, when the output of the first sub-switch control circuit 1121 is at a high level, the second switch 113 is controlled to be closed.
  • USB connection circuit 300 USB connector
  • second switch 113 reset switch
  • the chip programming circuit 110 passes through the USB connection circuit 300.
  • the data transfer is performed to burn the firmware on the computer into the processing chip 115. This operation is called a line brush.
  • the chip burning circuit 110 When the chip burning circuit 110 in the embodiment performs the operation of burning or switching, the chip burning circuit 110 starts to be in a shutdown state.
  • the chip burning circuit 110 When the user needs to perform the programming upgrade of the chip burning circuit 110, the chip burning circuit 110 is not connected to the power adapter, and the USB interface of the programming host 200 is connected to the USB interface of the chip burning circuit 110 through the USB connector.
  • the USB circuit 120 receives the 5v voltage of the computer in an on state, and it should be noted that the USB circuit 120 is connected to the system power supply circuit 111, and the system power supply circuit 111 also receives the 5v voltage.
  • the user presses the first switch 130 to close the first switch 130, and the chip burning circuit 110 controls the second switch 113 to close after passing through a series of responses of the switch control circuit 112.
  • the Zener diode D in the USB power supply control circuit 1141 in the chip power supply circuit 114 is unidirectionally turned on, so that the output terminal 1144 of the chip power supply circuit 114 also receives the 5V voltage of the USB circuit 120, and starts to work to supply power to the processing chip 115.
  • the processing chip 115 receives the power supply of the chip power supply circuit 114, receives the closing signal of the second switch 113, and the user controls the programming upgrade command sent by the computer, the burning upgrade is started.
  • the first switch 130 When the user determines that the programming is completed in the computer, the first switch 130 is released, and the gate g of the first field effect transistor Q1 connected to the first switch 130 becomes a high level, and the first field effect transistor Q1 is turned on, so the voltage of the gate g of the first field effect transistor Q1 becomes 0, so the voltage of the output terminal of the first switch 130 control circuit is 0, so the second field effect transistor Q2 is turned off, and the second field effect at this time
  • the drain d of the tube Q2 becomes a high level, so the second switch 113 is turned off, so the completion of the upgrade is completed.
  • the chip burning circuit 110 When the user needs to boot the chip burning circuit 110 normally without burning the upgrade, the chip burning circuit 110 is connected to the power adapter at this time, and is not connected to the USB interface of the programming host 200.
  • the connection of the power supply causes the system power supply circuit 111 on the main board to start working.
  • the chip burning circuit 110 starts to work in the power-on state, and at this time, the chip power supply circuit 114 receives the power supply of the system power supply circuit 111 to start working, because the source of the third field effect transistor Q3 s is connected to the chip power supply circuit 114, so the source s of the third field effect transistor Q3 is at a high level.
  • the processing chip 115 Since the processing chip 115 has not started to work when it is turned on, it is connected to the processing chip 115 at this time.
  • the input voltage of the third sub-switch control circuit 1142 is 0, so the voltage of the base b of the transistor T is 0, and the transistor T is in an off state at this time, so the collector c of the transistor T is at a high level, so the third field effect
  • the gate g of the tube Q3 is at a high level.
  • the third FET Q3 in the USB switch control circuit 1143 is a P-channel depletion MOS transistor (D-shaped PMOS transistor), due to the gate g and the source of the third FET Q3.
  • the chip power supply circuit 114 cannot supply voltage to the USB circuit 120, and the USB circuit 120 stops working.
  • the processing chip 115 does not start working, that is, the third sub-function
  • the switch control circuit 1142 stops operating, it controls the USB circuit 120 to stop operating through the USB switch control circuit 1143.
  • the voltage of one end of the first switch 130 connected to the first resistor R1 is 0. Since the USB circuit 120 does not start to operate, its voltage is 0, so the first field effect transistor Q1 is turned off. The drain d voltage of the first field effect transistor Q1 is made 0, so the output voltage of the first sub-switch control circuit 1121 is 0, so that the second field effect transistor Q2 is turned off, so the drain d of the second field effect transistor Q2. It is high, so that the second switch 113 is kept in an off state. Therefore, the chip burning circuit 110 does not perform the burn-up upgrade state, and the power is normally turned on at this time.
  • the processing chip 115 After the user releases the first switch 130, since the chip burning circuit 110 is normally turned on, the processing chip 115 starts normal operation, and therefore the input terminal of the third sub-switch control circuit 1142 connected to the processing chip 115 is at a high level, and the third The sub-switch control circuit 1142 starts to be in an active state.
  • the base b of the transistor T becomes a high level, so the transistor T is turned on, and at this time, the collector c voltage of the transistor T is 0, so the third field effect transistor Q3
  • the gate g voltage is 0, and at this time, the third field effect transistor Q3 is turned on, so the USB circuit 120 connected to the drain d of the third field effect transistor Q3 becomes a high level, and thus the USB circuit 120 starts operating.
  • the gate g of the first FET Q1 is at a high level, and at this time, since the USB circuit 120 starts to operate, the first FET Q1 is turned on.
  • the drain d voltage of one effect transistor Q1 is 0, so the voltage of the gate g of the second field effect transistor Q2 connected to the output terminal of the first sub-switch control circuit 1121 is 0, and the second field effect transistor Q2 at this time Turning off, therefore, the drain d of the second field effect transistor Q2 is at a high level, so that the second switch 113 remains in an off state. Therefore, after the power is turned on, the second switch 113 provided inside the chip burning device 100 will not be closed.
  • the chip programming circuit 110 provided by the present invention provides the same effect of closing the second switch 113 by pressing the first switch 130 when the switch control circuit 112 and the chip power supply circuit 114 are in the burned state, when In the normal on state, the first switch 130 is closed and the second switch 113 remains in the off state.
  • the first switch 130 of the chip burning circuit 110 is simultaneously realized to realize the multiplexing of the power-on and the burning function, and the electronic device does not need to be opened in the electronic device due to the waterproof requirement, thereby solving the problem that the chip cannot be inside the electronic device. Burning problem.
  • portions of the invention may be implemented in hardware, software, firmware or a combination thereof.
  • it may be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system.
  • it can be implemented by any one or combination of the following techniques well known in the art: having logic gates for implementing logic functions on data signals. Discrete logic circuits, application specific integrated circuits with suitable combinational logic gates, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

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Abstract

一种芯片烧录电路（110）及系统（10），该电路(110)应用于电子设备的主板上，电子设备外表面设有第一开关（130），第一开关（130）与系统供电电路（111）连接，控制电子设备开机或关机，该电路(110)包括：开关控制电路（112），分别与第一开关（130）和USB电路（120）连接，其中USB电路（120）通过USB连接电路（300）与烧录主机（200）连接；第二开关（113），分别与开关控制电路（112）和处理芯片（115）连接；芯片供电电路（114），分别与USB电路（120）和处理芯片（115）连接，当USB电路（120）连通时为处理芯片（115）供电，当第一开关（130）闭合且USB电路（120）处于连通状态时，开关控制电路（112）控制第二开关（113）闭合，以使处理芯片（115）进行芯片烧录。芯片烧录电路(110)通过设置开关控制电路（112）和芯片供电电路（114），使得第一开关（130）实现开机以及烧录功能的复用，解决了芯片在电子设备的内部无法烧录的问题。

Description

芯片烧录电路及系统 技术领域
本实用新型涉及电子技术领域，特别是涉及一种芯片烧录电路及系统。
背景技术
随着电子技术的发展，电子设备朝着小型化、轻便化和多样化的方向发展，电子设备现能够集成越来越多的功能。其中电子设备上的处理芯片决定了电子设备的处理性能，现有的大多平板电脑、智能电视、电视机顶盒等电子设备均采用国产芯片，例如，瑞芯微(RK)平台的智能处理芯片。
现有的瑞芯微(PK)平台的处理芯片大都应用于手机、平板电脑、智能电视、机顶盒等电子设备上，当电子设备上的芯片需要固件升级时，需要先将USB刷机线的一端连接到电脑上的USB接口，然后用镊子、牙签或者曲别针等顶住电子设备的芯片主板上的复位按钮(Recovery key)不松手，然后将双公头USB数据线的另一端插到电子设备的芯片主板上的USB接口，当电脑上的刷机工具显示红灯亮时，松开复位按钮，然后电脑上的刷机工具会出现正在低格，然后写入程序，最终完成RK平台芯片的烧录。
然而现有的一些电子设备中，由于防水性等方面的需求，其机身的外部减少了设备开孔，而当RK平台的芯片主板装到电子设备的内部后，却仍有芯片烧录的需求，这使得用户无法长按机身内部的芯片主板上的复位按钮来实现芯片的烧录，导致电子设备的芯片无法进行烧录，此时需要将电子设备进行拆解取出主板才能对其进行烧录。
实用新型内容
基于此，本实用新型的目的在于提出一种芯片烧录电路及系统，解决芯片在电子设备的内部无法烧录的问题。
本实用新型的实施例提供一种芯片烧录电路，具体技术方案如下：
本实用新型提供一种芯片烧录电路，应用于芯片烧录装置的主板上，所述 芯片烧录装置的外表面上设有第一开关，所述第一开关控制所述芯片烧录装置开机或关机，所述第一开关与系统供电电路连接，所述电路包括：
开关控制电路，所述开关控制电路分别与所述第一开关和USB电路连接，其中，所述USB电路通过USB连接电路与烧录主机连接；
第二开关，设置在所述芯片烧录装置的内部，所述第二开关分别与所述开关控制电路和处理芯片连接；
芯片供电电路，所述芯片供电电路分别与所述USB电路和所述处理芯片连接，当所述USB电路连通时，所述芯片供电电路开始工作，为所述处理芯片供电；
当所述第一开关闭合且所述USB电路处于连通状态时，所述开关控制电路控制所述第二开关闭合，以使所述处理芯片进行芯片烧录。
本实用新型提供的芯片烧录电路，通过设置开关控制电路以及芯片供电电路，当处于烧录状态时，通过按压闭合第一开关而实现第二开关闭合的相同的效果，当处于正常开机状态时，按压闭合第一开关而第二开关保持断开状态。使得将芯片烧录电路的第一开关同时实现了开机以及烧录功能的复用，解决了第二开关(复位开关)在芯片烧录装置的内部而无法按压导致的电子设备无法烧录的问题。满足了电子设备由于防水性的需求而不必在电子设备上开孔，解决了芯片在电子设备的内部无法烧录的问题。
另外，根据本实用新型提供的芯片烧录电路，还可以具有如下附加的技术特征：
进一步地，所述开关控制电路包括：
第一子开关控制电路，所述第一子开关控制电路分别与所述第一开关和所述USB电路连接，当所述第一开关闭合且所述USB电路处于连通状态时，所述第一子开关控制电路的输出端为高电平；
第二子开关控制电路，所述第二子开关控制电路分别与所述第一子开关控制电路的输出端和所述第二开关连接，当所述第一子开关控制电路的输出端为高电平时，所述第二开关闭合。
进一步地，所述第一子开关控制电路包括第一场效应管和与所述第一场效 应管连接的第一电阻，所述第一场效应管为MOS管，所述第一场效应管的漏极、栅极、源极依次与所述第一电阻、所述第一开关、地连接，所述第一电阻与所述USB电路连接，所述第一开关与所述第一场效应管连接的一端还与第二电阻连接，所述第二电阻与所述系统供电电路连接，所述第一开关的另一端与地连接。
进一步地，所述第二子开关控制电路包括第二场效应管和与所述第二场效应管连接的第三电阻，所述第二场效应管为MOS管，所述第二场效应管的栅极、源极依次与所述第一场效应管的漏极、地连接，所述第二场效应管的漏极分别与所述第三电阻以及所述第二开关连接，所述第三电阻与所述系统供电电路连接，所述第二开关的另一端与地连接。
进一步地，所述芯片供电电路还与所述系统供电电路连接，用于通过所述系统供电电路为所述处理芯片供电，所述芯片供电电路包括：
USB供电控制电路，所述USB供电控制电路与所述USB电路连接，当所述USB电路处于连通状态时，控制所述芯片供电电路工作；
第三子开关控制电路，所述第三子开关控制电路与所述处理芯片连接；
USB开关控制电路，所述USB开关控制电路分别与所述USB电路和所述第三子开关控制电路连接，当所述第三子开关控制电路停止工作时，控制所述USB电路停止工作。
进一步地，所述USB供电控制电路包括一稳压二极管，所述稳压二极管的阳极与所述USB电路连接，所述稳压二极管的阴极与所述芯片供电电路的输出端连接。
进一步地，所述第三子开关控制电路包括与所述处理芯片连接的第四电阻、与所述第四电阻连接的三极管、与所述三极管连接的第五电阻，所述三极管的基极、集电极、发射极依次与所述第四电阻、所述第五电阻、地连接，所述第五电阻与所述芯片供电电路的输出端连接。
进一步地，所述USB开关控制电路包括第三场效应管、与所述第三场效应管的漏极连接的第一电容、第六电阻、与所述第三场效应管的源极连接的第二电容、与所述第三场效应管的栅极连接的所述第二电容、第七电阻，所述第一 电容和第六电阻的另一端接地，所述第七电阻的另一端与所述三极管的集电极连接，所述第三场效应管的漏极还与所述USB电路连接，所述第三场效应管的源极还与所述芯片供电电路的输出端连接。
进一步地，所述第一场效应管和所述第二场效应管均为N沟道耗尽型MOS管。
本实用新型的另一实施例提供一种芯片烧录系统，包括芯片烧录装置、烧录主机、以及分别与所述芯片烧录装置和所述烧录主机连接的USB连接电路，所述烧录主机用于为所述芯片烧录装置进行芯片烧录，所述芯片烧录装置包括上述的芯片烧录电路。
附图说明
图1为本实用新型一实施例提出的芯片烧录系统的结构示意图。
图2为本实用新型一实施例提出的芯片烧录系统中的芯片烧录电路中开关控制电路的连接环境电路结构示意图。
图3为本实用新型一实施例提出的芯片烧录系统中的芯片烧录电路中芯片供电电路的连接环境电路结构示意图。
具体实施方式
为使本实用新型的上述目的、特征和优点能够更加明显易懂，下面结合附图对本实用新型的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本实用新型。但是本实用新型能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本实用新型内涵的情况下做类似改进，因此本实用新型不受下面公开的具体实施的限制。
在本实用新型中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本实用新型中的具体含义。 本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
请参阅图1，本实用新型的一实施例提供的芯片烧录系统10，包括芯片烧录装置100、烧录主机200(计算机)、以及分别与芯片烧录装置100和烧录主机200连接的USB连接电路300(USB连接器)，其中烧录主机200用于为芯片烧录装置100进行芯片烧录，其中芯片烧录装置100中的芯片采用瑞芯微(PK)平台的处理芯片，其进行芯片烧录时需要长按芯片烧录装置100中内部主板上的复位开关(第二开关113)，当烧录主机200通过USB连接电路300将升级固件烧录到芯片烧录装置100后，松开复位按钮，最终完成RK平台芯片的烧录，其中芯片烧录装置100包括芯片烧录电路110、USB电路120、第一开关130，其中USB电路120与芯片烧录电路110连接，用于为芯片烧录电路110提供USB信号通讯以及供电需求。USB电路120还与USB连接电路300连接，USB连接电路300与烧录主机200连接，用于为烧录主机200和芯片烧录装置100之间通过信号通讯。芯片烧录装置100的外表面上设有第一开关130(电源开关)，通过按压第一开关130实现控制芯片烧录装置100的开机或关机。
请参阅图2和图3，为图1中芯片烧录系统10中的芯片烧录装置100的部分电路结构示意图，其中芯片烧录电路110包括系统供电电路111、开关控制电路112、第二开关113、芯片供电电路114以及处理芯片115。其中芯片烧录电路110应用于芯片烧录装置100的主板上，用以实现主板上的芯片烧录功能，当芯片烧录装置100通过电源适配器与电源连接时，系统供电电路111开始工作为主板提供供电，第一开关130与系统供电电路111连接。其中USB电路120连接芯片烧录装置100的USB接口，用于通过USB连接电路300分别与该USB接口和烧录主机200上USB接口的连接，以实现该芯片烧录电路110与烧录主机200之间的信号通讯。
进一步地，开关控制电路112分别与第一开关130和USB电路120连接，第二开关113分别与开关控制电路112和处理芯片115连接。其中开关控制电路112包括第一子开关控制电路1121和第二子开关控制电路1122。其中第一子开关控制电路1121分别与第一开关130和USB电路120连接，第一子开关控制电 路1121包括第一场效应管Q1和与第一场效应管Q1连接的第一电阻R1，第一场效应管Q1为MOS管，第一场效应管Q1的漏极d、栅极g、源极s依次与第一电阻R1、第一开关130、地连接，第一电阻R1与USB电路120连接，第一开关130与第一场效应管Q1连接的一端还与第二电阻R2连接，第二电阻R2与系统供电电路111连接，第一开关130的另一端与地连接。其中第二子开关控制电路1122分别与第一子开关控制电路1121的输出端和第二开关113连接，第二子开关控制电路1122包括第二场效应管Q2和与第二场效应管Q2连接的第三电阻R3。第二场效应管Q2为MOS管，第二场效应管Q2的栅极g、源极s依次与第一场效应管Q1的漏极d、地连接，第二场效应管Q2的漏极d分别与第三电阻R3以及第二开关113连接。其中第三电阻R3与系统供电电路111连接，第二开关113的另一端与地连接。
进一步地，芯片供电电路114分别与USB电路120、系统供电电路111以及处理芯片115连接，芯片供电电路114通过系统供电电路111或USB电路120均可为处理芯片115供电，芯片供电电路114包括USB供电控制电路1141、第三子开关控制电路1142以及USB开关控制电路1143。
其中USB供电控制电路1141包括一稳压二极管D，该稳压二极管D的阳极与USB电路120连接，稳压二极管D的阴极与芯片供电电路114的输出端1144连接。USB供电控制电路1141与USB电路120连接，当USB电路120处于导通状态时，由于稳压二极管D的单向导通作用控制芯片供电电路114工作，以使芯片供电电路114的输出端1144有电平输出，控制该芯片供电电路114工作，为处理芯片115供电。
其中，第三子开关控制电路1142与处理芯片115连接。第三子开关控制电路1142包括与处理芯片115连接的第四电阻R11、与第四电阻R11连接的三极管T、与三极管T连接的第五电阻R12。该三极管T的基极b、集电极c、发射极e依次与第四电阻R11、第五电阻R12、地连接。其中第五电阻R12与芯片供电电路114的输出端1144连接。
其中，USB开关控制电路1143分别与USB电路120和第三子开关控制电路1142连接，USB开关控制电路1143包括第三场效应管Q3、与第三场效应管 Q3的漏极d连接的第一电容C11、第六电阻R13、与第三场效应管Q3的源极s连接的第二电容C12、与第三场效应管Q3的栅极g连接的第二电容C12、第七电阻R14。其中第一电容C11和第六电阻R13的另一端均接地，第七电阻R14的另一端与三极管T的集电极c连接，第三场效应管Q3的漏极d还与USB电路120连接，第三场效应管Q3的源极s还与芯片供电电路114的输出端1144连接。
其中，由于第一开关130的两端分别与地和第一电阻R1连接，当第一开关130没有按压闭合时，其与第一电阻R1连接的一端为高电平，因此第一场效应管Q1的栅极g也为高电平，需要指出的是，第一场效应管Q1和第二场效应管Q2均为N沟道耗尽型MOS管(D形NMOS管)。当USB电路120与USB连接电路300连接，USB连接电路300与烧录主机200连接，使得USB电路120处于导通状态时，其USB电路120输出高电平，因此使得第一场效应管Q1导通，因此第一场效应管Q1的漏极d与源极s连接，电压为0；当USB电路120不处于工作状态时，其输出电压为0，因此第一场效应管Q1的漏极d的电压也为0。
当第一开关130按压闭合时，其与第一电阻R1连接的一端电压为0，因此第一场效应管Q1的栅极g的电压也为0，且此时当USB电路120处于导通状态时，其USB电路120输出高电平，此时第一场效应管Q1截止，因此第一场效应管Q1的漏极d为高电平。因此当第一开关130闭合且USB电路120处于导通状态时，第一子开关控制电路1121的输出端为高电平，由于第一场效应管Q1的漏极d与第二场效应管Q2的栅极g连接，因此第二场效应管Q2的栅极g也为高电平，因此此时第二场效应管Q2导通，此时第二场效应管Q2的漏极d电压为0，同时第二开关113的两端分别与地和第二场效应管Q2的漏极d连接，因此第二场效应管Q2的漏极d电压为0时，第二开关113的两端电压均为0，控制第二开关113闭合，从而实现了按压闭合第一开关130而使第二开关113闭合的效果。因此当第一子开关控制电路1121的输出端为高电平时，控制第二开关113闭合。
同时，需要指出的是，当芯片烧录电路110需要进行芯片烧录时，其需要 将主板上的USB接口与烧录主机200的USB接口通过USB连接器(USB连接电路300)连接，且需要按压第二开关113(复位开关)，此时芯片烧录电路110通过USB连接电路300进行数据传输将计算机上的固件烧录到处理芯片115中，此操作过程称为线刷。
其中，本实施例中的芯片烧录电路110进行烧录或开关机的操作时，其芯片烧录电路110均开始处于关机状态。当用户需对芯片烧录电路110进行烧录升级时，其芯片烧录电路110不连接电源适配器，此时通过USB连接器将烧录主机200的USB接口与芯片烧录电路110的USB接口连接，此时USB电路120接收到计算机的5v电压处于导通状态，同时需要指出的是，USB电路120与系统供电电路111相连，此时系统供电电路111也接收到5v电压。此时用户按压第一开关130使得第一开关130闭合，其芯片烧录电路110通过上述开关控制电路112的一系列响应后，控制第二开关113闭合。同时芯片供电电路114中的USB供电控制电路1141中的稳压二极管D单向导通，使得芯片供电电路114的输出端1144也接收到USB电路120的5v电压，开始工作为处理芯片115供电，此时由于处理芯片115接收到芯片供电电路114的供电，接收到第二开关113的闭合信号，以及用户控制计算机发送的烧录升级指令时，开始进行烧录升级。当用户确定计算机中提示烧录完成时，松开第一开关130，此时与第一开关130连接的第一场效应管Q1的栅极g变为高电平，此时第一场效应管Q1导通，因此第一场效应管Q1的栅极g的电压变为0，因此第一开关130控制电路的输出端电压为0，因此第二场效应管Q2截止，此时第二场效应管Q2的漏极d变为高电平，因此第二开关113断开，因此升级完成结束烧录。
当用户需对芯片烧录电路110进行正常开机而不需烧录升级时，此时将芯片烧录电路110连接电源适配器，且不与烧录主机200的USB接口连接，此时通过电源适配器与电源的连接，使得主板上的系统供电电路111开始工作。此时当用户按压闭合第一开关130时，芯片烧录电路110处于开机状态开始工作，此时芯片供电电路114接收到系统供电电路111的供电开始工作，由于第三场效应管Q3的源极s与芯片供电电路114连接，因此第三场效应管Q3的源极s为高电平。由于开机时处理芯片115还未开始工作，此时与处理芯片115连接的 第三子开关控制电路1142的输入端电压为0，因此三极管T的基极b电压为0，此时三极管T处于截止状态，因此三极管T的集电极c为高电平，因此第三场效应管Q3的栅极g为高电平。其中，需要指出的是，USB开关控制电路1143中的第三场效应管Q3为P沟道耗尽型MOS管(D形PMOS管)，由于第三场效应管Q3的栅极g和源极s均为高电平，因此第三场效应管Q3截止，因此第三场效应管Q3的漏极d电压为0，因此与第三场效应管Q3的漏极d连接的USB电路120的电压为0。同时由于USB供电控制电路1141中稳压二极管的单向导通功能，使得芯片供电电路114无法为USB电路120提供电压，USB电路120停止工作，此时当处理芯片115未开始工作，即第三子开关控制电路1142停止工作时，其通过USB开关控制电路1143控制USB电路120停止工作。
此时由于用户按压闭合第一开关130，因此第一开关130与第一电阻R1连接的一端电压为0，由于USB电路120未开始工作，其电压为0，因此第一场效应管Q1截止，使得第一场效应管Q1的漏极d电压为0，因此第一子开关控制电路1121的输出端电压为0，使得第二场效应管Q2截止，因此第二场效应管Q2的漏极d为高电平，使得第二开关113保持断开状态。因此芯片烧录电路110不会进行烧录升级状态，此时正常开机。当用户松开第一开关130后，由于芯片烧录电路110正常开机，处理芯片115开始正常工作，因此与处理芯片115连接的第三子开关控制电路1142的输入端为高电平，第三子开关控制电路1142开始处于工作状态，此时三极管T的基极b变为高电平，因此三极管T导通，此时三极管T的集电极c电压为0，因此第三场效应管Q3的栅极g电压为0，此时第三场效应管Q3导通，因此与第三场效应管Q3的漏极d连接的USB电路120变为高电平，因此USB电路120开始工作。此时由于用户松开第一开关130，因此第一场效应管Q1的栅极g为高电平，且此时由于USB电路120开始工作，因此第一场效应管Q1导通，此时第一场效应管Q1的漏极d电压为0，因此与第一子开关控制电路1121的输出端连接的第二场效应管Q2的栅极g的电压为0，此时第二场效应管Q2截止，因此第二场效应管Q2的漏极d为高电平，使得第二开关113保持断开状态。因此开机后，设于芯片烧录装置100内部的第二开关113将不会闭合。
本实用新型提供的芯片烧录电路110通过设置开关控制电路112以及芯片供电电路114，当处于烧录状态时，通过按压闭合第一开关130而实现第二开关113闭合的相同的效果，当处于正常开机状态时，按压闭合第一开关130而第二开关113保持断开状态。使得将芯片烧录电路110的第一开关130同时实现了开机以及烧录功能的复用，满足电子设备由于防水性的需求而不必在电子设备上开孔，解决了芯片在电子设备的内部无法烧录的问题。
应当理解，本实用新型的各部分可以用硬件、软件、固件或它们的组合来实现。在上述实施方式中，可以用存储在存储器中且由合适的指令执行系统执行的软件或固件来实现。例如，如果用硬件来实现，和在另一实施方式中一样，可用本领域公知的下列技术中的任一项或他们的组合来实现：具有用于对数据信号实现逻辑功能的逻辑门电路的离散逻辑电路，具有合适的组合逻辑门电路的专用集成电路，可编程门阵列(PGA)，现场可编程门阵列(FPGA)等。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述实施例仅表达了本实用新型的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本实用新型专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本实用新型构思的前提下，还可以做出若干变形和改进，这些都属于本实用新型的保护范围。因此，本实用新型专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种芯片烧录电路，应用于芯片烧录装置的主板上，所述芯片烧录装置的外表面上设有第一开关，所述第一开关控制所述芯片烧录装置开机或关机，所述第一开关与系统供电电路连接，其特征在于，所述电路包括：
    开关控制电路，所述开关控制电路分别与所述第一开关和USB电路连接，其中，所述USB电路通过USB连接电路与烧录主机连接；
    第二开关，设置在所述芯片烧录装置的内部，所述第二开关分别与所述开关控制电路和处理芯片连接；
    芯片供电电路，所述芯片供电电路分别与所述USB电路和所述处理芯片连接，当所述USB电路连通时，所述芯片供电电路开始工作，为所述处理芯片供电；
    当所述第一开关闭合且所述USB电路处于连通状态时，所述开关控制电路控制所述第二开关闭合，以使所述处理芯片进行芯片烧录。
  2. 根据权利要求1所述的芯片烧录电路，其特征在于，所述开关控制电路包括：
    第一子开关控制电路，所述第一子开关控制电路分别与所述第一开关和所述USB电路连接，当所述第一开关闭合且所述USB电路处于连通状态时，所述第一子开关控制电路的输出端为高电平；
    第二子开关控制电路，所述第二子开关控制电路分别与所述第一子开关控制电路的输出端和所述第二开关连接，当所述第一子开关控制电路的输出端为高电平时，所述第二开关闭合。
  3. 根据权利要求2所述的芯片烧录电路，其特征在于，所述第一子开关控制电路包括第一场效应管和与所述第一场效应管连接的第一电阻，所述第一场效应管为MOS管，所述第一场效应管的漏极、栅极、源极依次与所述第一电阻、所述第一开关、地连接，所述第一电阻与所述USB电路连接，所述第一开关与所述第一场效应管连接的一端还与第二电阻连接，所述第二电阻与所述系统供电电路连接，所述第一开关的另一端与地连接。
  4. 根据权利要求3所述的芯片烧录电路，其特征在于，所述第二子开关控制电路包括第二场效应管和与所述第二场效应管连接的第三电阻，所述第二场 效应管为MOS管，所述第二场效应管的栅极、源极依次与所述第一场效应管的漏极、地连接，所述第二场效应管的漏极分别与所述第三电阻以及所述第二开关连接，所述第三电阻与所述系统供电电路连接，所述第二开关的另一端与地连接。
  5. 根据权利要求1所述的芯片烧录电路，其特征在于，所述芯片供电电路还与所述系统供电电路连接，用于通过所述系统供电电路为所述处理芯片供电，所述芯片供电电路包括：
    USB供电控制电路，所述USB供电控制电路与所述USB电路连接，当所述USB电路处于连通状态时，控制所述芯片供电电路工作；
    第三子开关控制电路，所述第三子开关控制电路与所述处理芯片连接；
    USB开关控制电路，所述USB开关控制电路分别与所述USB电路和所述第三子开关控制电路连接，当所述第三子开关控制电路停止工作时，控制所述USB电路停止工作。
  6. 根据权利要求5所述的芯片烧录电路，其特征在于，所述USB供电控制电路包括一稳压二极管，所述稳压二极管的阳极与所述USB电路连接，所述稳压二极管的阴极与所述芯片供电电路的输出端连接。
  7. 根据权利要求5所述的芯片烧录电路，其特征在于，所述第三子开关控制电路包括与所述处理芯片连接的第四电阻、与所述第四电阻连接的三极管、与所述三极管连接的第五电阻，所述三极管的基极、集电极、发射极依次与所述第四电阻、所述第五电阻、地连接，所述第五电阻与所述芯片供电电路的输出端连接。
  8. 根据权利要求7所述的芯片烧录电路，其特征在于，所述USB开关控制电路包括第三场效应管、与所述第三场效应管的漏极连接的第一电容、第六电阻、与所述第三场效应管的源极连接的第二电容、与所述第三场效应管的栅极连接的所述第二电容、第七电阻，所述第一电容和第六电阻的另一端接地，所述第七电阻的另一端与所述三极管的集电极连接，所述第三场效应管的漏极还与所述USB电路连接，所述第三场效应管的源极还与所述芯片供电电路的输出端连接。
  9. 根据权利要求4所述的芯片烧录电路，其特征在于，所述第一场效应管和所述第二场效应管均为N沟道耗尽型MOS管。
  10. 一种芯片烧录系统，包括芯片烧录装置、烧录主机、以及分别与所述芯片烧录装置和所述烧录主机连接的USB连接电路，所述烧录主机用于为所述芯片烧录装置进行芯片烧录，其特征在于，所述芯片烧录装置包括权利要求1至9任意一项所述的芯片烧录电路。
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