US10014854B2 - Reset circuit and electronic device - Google Patents

Reset circuit and electronic device Download PDF

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US10014854B2
US10014854B2 US15/470,411 US201715470411A US10014854B2 US 10014854 B2 US10014854 B2 US 10014854B2 US 201715470411 A US201715470411 A US 201715470411A US 10014854 B2 US10014854 B2 US 10014854B2
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circuit
resistor
reset
transistor
voltage signal
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US20170201249A1 (en
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Shangding Su
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Guangdong Oppo Mobile Telecommunications Corp Ltd
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Guangdong Oppo Mobile Telecommunications Corp Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0052—
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0068—Battery or charger load switching, e.g. concurrent charging and load supply

Definitions

  • the present disclosure relates to the field of electronic devices, and particularly to a reset circuit and an electronic device.
  • An electric device generally has a reset function, when the electronic device crashes due to improper operation or internal product problems, it is needed to start this reset function, that is, in the case of uninterruptible power supply, the electronic device can be restored to an initial state.
  • the reset in the electric device is usually implemented in a manner of a separate reset button or a toggle switch that is powered off.
  • the reset is generally implemented via a reset hole, however, this approach requires the user to insert a small tool into the reset hole to tap to complete the reset, that is, the reset cannot be triggered without an appropriate external tool, and therefore is inconvenient.
  • FIG. 1 is a schematic circuit structure diagram of a reset circuit of a first implementation of the present disclosure
  • FIG. 2 is a schematic circuit principle diagram of a reset circuit of a second implementation of the present disclosure
  • FIG. 3 is a schematic circuit principle diagram of another reset circuit of the second implementation of the present disclosure.
  • FIG. 4 is a schematic circuit principle diagram of a reset circuit of a third implementation of the present disclosure.
  • FIG. 5 is a schematic circuit principle diagram of another reset circuit of the third implementation of the present disclosure.
  • FIG. 6 is a schematic circuit principle diagram of a reset circuit of another implementation of the present disclosure.
  • FIG. 7 is a schematic circuit principle diagram of a reset circuit of another implementation of the present disclosure.
  • FIG. 8 is a schematic structure diagram of an electric device of an implementation of the present disclosure.
  • FIG. 1 is a schematic circuit structure diagram of a reset circuit of an implementation of the present disclosure.
  • the reset circuit of the implementation of the present disclosure includes: a charging circuit 101 , a driving circuit 102 , an execution circuit 103 , a control port 110 , and a reset port 120 .
  • the charging circuit 101 has an input end connected with the control port 110 , an output end connected with the driving circuit 102 , and is configured to generate a second voltage signal after a first voltage signal provided by the control port 110 is received.
  • the driving circuit 102 has an input end connected with the output end of the charging circuit 101 , an output end connected with the execution circuit 103 , and is configured to amplify the second voltage signal after it is detected that the value of the second voltage signal (that is, the voltage value corresponding to the second voltage signal) reaches a preset value and output the amplified second voltage signal to the execution circuit 103 .
  • the execution circuit 103 has an input end connected with the output end of the driving circuit 102 , an output end connected with the reset port 120 , and is configured to generate a reset signal after the amplified second voltage signal is received and transfer the reset signal to the reset port 120 ; a reset operation can be performed on a microcontroller of an electric device through the reset port 120 .
  • the first voltage signal is a high level signal and the second voltage signal is a level signal after a capacitor C 1 is charged.
  • the control port 110 provided in the present disclosure can be integrated with the electric device, and the control port 110 can be set in associate with a button of the electric device; in this way, when a button operation is performed on the electric device, the control port 110 can be triggered to provide the first voltage signal, and the charging circuit 101 can generate the second voltage signal after the first voltage signal is received; the driving circuit 102 amplifies the second voltage signal and transfer the amplified second voltage signal to the execution circuit 103 when the value of the second voltage signal reaches a preset value; the execution circuit 103 generates a reset signal after the amplified second voltage signal is received and transfer the reset signal to the reset port 120 .
  • the button operation can be to press and hold a button for a preset time or press and hold a combination of a plurality of buttons simultaneously. Alternatively, the button operation can be replaced with a knob operation, and the present
  • FIG. 2 is a schematic structure diagram of a preset circuit of a second implementation of the present disclosure.
  • the reset circuit of the implementation includes a charging circuit 101 , a driving circuit 102 , an execution circuit 103 , a control port 110 , and a reset port 120 .
  • the charging circuit 101 has an input end connected with the control port 110 , an output end connected with the driving circuit 102 , and is configured to generate a second voltage signal after a first voltage signal provided by the control port 110 is received.
  • the charging circuit 101 includes a resistor R 4 and a capacitor C 1 ; the resistor R 4 and the capacitor C 1 are connected in series to form a series branch, wherein the series branch has one end as an input end of the charging circuit 101 and the other end as an output end of the charging circuit 101 .
  • the resistor R 4 and the capacitor C 1 are connected in series; the resistor R 4 has one end as the input end of the charging circuit and the other end connected with one end of the capacitor C 1 , and the capacitor C 1 has the other end grounded; a node between the other end of the resistor R 4 and the one end of the capacitor C 1 acts as the output end of the charging circuit.
  • the charging circuit 101 further includes a resistor R 1 , and the control port 110 is grounded via the resistor R 1 .
  • the resistor R 1 has one end connected with one end of the resistor R 4 and the other end grounded.
  • the first voltage signal is a high level signal and the second voltage signal is a level signal after the capacitor C 1 is charged.
  • the control port 110 provided in the implementation of the present disclosure can be integrated with an electric device, when a button operation is performed on the electric device, the control port 110 is triggered to provide a high level signal, and the capacitor C 1 can be charged via the resistor R 4 such that the level value of the capacitor C 1 can rise gradually.
  • the button operation can be to press and hold a button for a preset time or press and hold a combination of a plurality of buttons simultaneously. Alternatively, the button operation can be replaced with a knob operation, and the present disclosure is not limited thereto.
  • the driving circuit 102 has an input end connected with the output end of the charging circuit 101 , an output end connected with the execution circuit 103 , and is configured to amplify the second voltage signal after it is detected that the value of the second voltage signal (that is, the level value of the capacitor C 1 ) reaches a preset value and output the amplified second voltage signal to the execution circuit 103 .
  • the driving circuit 102 includes a MOS transistor and a first power supply end; the MOS transistor has a gate which is the input end of the driving circuit 102 , and the MOS transistor has a source which is the output end of the driving circuit 102 ; the gate of the MOS transistor is connected with the output end of the charging circuit 101 and the output end of the reverse discharge circuit, the source of the MOS transistor is connected with the input end of the execution circuit 103 , and the MOS transistor has a drain connected with the first power supply end.
  • the driving circuit 102 further includes a resistor R 6 and a resistor R 7 ; the drain of the MOS transistor is connected to the first power supply end via the resistor R 6 , and the source of the MOS transistor is grounded via the resistor R 7 .
  • the driving circuit includes the MOS transistor, the resistor R 7 , the first power supply end, and the resistor R 6 ; the gate of the MOS transistor is the input end of the driving circuit, the source of the MOS transistor is the output end of the driving circuit and is grounded via the resistor R 7 , the drain of the MOS transistor is connected with the first power supply end.
  • the resistor R 6 is connected between the first power supply end and the drain of the MOS transistor.
  • the MOS transistor of the driving circuit 102 when the level value of the capacitor C 1 rises to a preset value, the MOS transistor of the driving circuit 102 is turned on; at this point, the MOS transistor can amplify the level signal of the capacitor C 1 which has reached the preset value and output the amplified signal to the execution circuit 103 .
  • the driving circuit 102 can amplify the level signal of the capacity C 1 which has reached the preset value and transfer the amplified signal to the execution circuit 103 .
  • the MOS transistor is used for threshold detection and level signal amplification.
  • the execution circuit 103 has an input end connected with the output end of the driving circuit 102 , an output end connected with the reset port 120 , and is configured to generate a reset signal after the amplified second voltage signal is received and transfer the reset signal to the reset port 120 .
  • the execution circuit 103 includes a transistor Q 3 , a capacitor C 2 , and a second power supply end; the transistor Q 3 has a base which is the input end of the execution circuit 103 , the transistor Q 3 has a collector which is the output end of the execution circuit 103 ; the base of the transistor Q 3 is connected with the output end of the driving circuit 102 , the collector of the transistor Q 3 is grounded via the capacitor C 2 , and the transistor Q 3 has an emitter grounded; the second power supply end is grounded via the capacitor C 2 .
  • the execution circuit 103 further includes a resistor R 8 and a resistor R 9 ; the base of the transistor Q 3 is connected with the output end of the driving circuit 102 via the resistor R 8 , the collector of the transistor Q 3 is connected with the reset port 120 , and the emitter of the transistor Q 3 is grounded; the second power supply is grounded via the resistor R 9 and the capacitor C 2 .
  • This circuit has an advantage that the cost is relatively low.
  • the execution circuit includes the transistor Q 3 , the capacitor C 2 , the second power supply end, the resistor R 8 , and the resistor R 9 , the base of the transistor Q 3 is the input end of the execution circuit, the collector of the transistor Q 3 is the output end of the execution circuit, the emitter of the transistor Q 3 is grounded, and the collector of the transistor Q 3 is grounded via the capacitor C 2 ; the second power supply end is grounded via the capacitor C 2 .
  • the base of the transistor Q 3 is connected to the output end of the driving circuit via the resistor R 8 , the collector of the transistor Q 3 is connected to the second power supply end via the resistor R 9 , and the second power supply end is grounded via the resistor R 9 and the capacitor C 2 .
  • the second power supply end charges the capacitor C 2 via the resistor R 9 ; after the control port provides the first voltage signal, a source voltage of the MOS transistor continues to rise until the transistor Q 3 is turned on, at this point, the capacitor C 2 is discharged, and a low level reset signal will be generated after the capacitor C 2 is discharged; the low level reset signal is transferred to the reset port 120 for the reset operation.
  • the reset circuit can further include a reverse discharge circuit 104 ; the reverse discharge circuit 104 has an input end connected with the control port 110 , an output end connected with the output end of the charging circuit, and is configured to generate a fourth voltage signal after a third voltage signal provided by the control port 110 is received, so as to discharge the charging circuit, that is, discharge the capacitor C 1 .
  • the reverse discharge circuit 104 includes a transistor Q 1 , a transistor Q 2 , and a third power supply end; the transistor Q 1 has a base which is the input end of the reverse discharge circuit 104 , and the transistor Q 2 has a collector which is the output end of the reverse discharge circuit 104 ; the base of the transistor Q 1 is connected with the control port 110 , the transistor Q 1 has a collector connected with a base of the transistor Q 2 , and the transistor Q 1 has an emitter grounded; the base of the transistor Q 2 is connected with the collector of the transistor Q 1 , the collector of the transistor Q 2 is connected with the output end of the charging circuit 101 and the input end of the driving circuit 102 , the emitter of the transistor Q 2 is grounded; the third power supply end is connected with the collector of the transistor Q 1 .
  • the reverse discharge circuit 104 further includes a resistor R 2 , a resistor R 3 , a resistor R 5 ; the base of the transistor Q 1 is connected to the control port 110 via the resistor R 2 , the collector of the transistor Q 1 is connected to the base of the transistor Q 2 via the resistor R 5 ; the third power supply end is connected to the collector of the transistor Q 1 via the resistor R 3 .
  • the reverse discharge circuit includes the transistor Q 1 , the transistor Q 2 and the third power supply end, the resistor R 2 , the resistor R 3 , and the resistor R 5 .
  • the base of the transistor Q 1 is the input end of the reverse discharge circuit
  • the collector of the transistor Q 2 is the output end of the reverse discharge circuit
  • the collector of the transistor Q 1 is connected with the base of the transistor Q 2 , and the emitter of the transistor Q 1 is grounded
  • the collector of the transistor Q 2 is connected with the input end of the driving circuit, and the emitter of the transistor Q 2 is grounded
  • the third power supply end is connected with the collector of the transistor Q 1 .
  • the base of the transistor Q 1 is connected to the control port via the resistor R 2
  • the collector of the transistor Q 1 is connected to the base of the transistor Q 2 via the resistor R 5
  • the third power supply end is connected to the collector of the transistor Q 1 via the resistor R 3 .
  • the third voltage signal is a low level signal; when the control port provides a high level signal, the transistor Q 1 of the reverse discharge circuit is turned on while the transistor Q 2 is turned off, at this point, the reverse discharge circuit has no effect on the charging circuit; on the other hand, when the control port provides a low level signal and the capacitor C 1 stops charging, at this point, the transistor Q 1 is turned off while the transistor Q 2 is turned on, and the reverse discharge circuit will generate a fourth voltage signal for the capacitor C 1 and perform discharge operation on the capacitor C 1 ; the value of the level signal of the capacitor C 1 rapidly drops below the preset value, such that the MOS transistor and the transistor Q 3 can be turned off rapidly while the capacitor C 2 continues to be charged and gradually returns to high level, so as to end the reset state.
  • the reverse discharge circuit 104 the capacitor C 1 can be discharged rapidly so as to end the reset state; after the reset operation is released, the microcontroller can enter a normal working state quickly, thereby eliminating reset effects.
  • control port can be set in associate with a button of an electric device.
  • the control port provides the first voltage signal.
  • control port can be set in associate with a knob of an electric device.
  • the control port provides the first voltage signal.
  • the first voltage signal is a high level signal
  • the second voltage signal is a level signal after the capacitor C 1 is charged
  • the third signal is a low level signal.
  • the control port provides a high level signal
  • the capacitor C 1 can be charged via the resistor R 4 , however, at this point, the transistor Q 1 is turned on while the transistor Q 2 is turned off, and the driving circuit has no effect;
  • the MOS transistor of the driving circuit is turned on (to be specific, the MOS transistor can be turned on if the voltage difference between the gate and the source thereof reaches 1.1 V or 1.2V); the source level of the MOS transistor continues to rise, and when the source level of the MOS transistor reaches a certain value (generally, greater than 0.5V), the transistor Q 3 is turned on, at this point, the capacitor C 2 will be discharged and generate a low level reset signal, and the reset port will perform the reset operation upon receiving the reset signal; when the control port provides a low
  • the third voltage signal is a low level signal
  • the input end of the reverse discharge circuit 104 is connected with the control port 110
  • the output end of the reverse discharge circuit 104 is connected with the output end of the charging circuit 101 ;
  • FIG. 4 is a schematic structure diagram of a reset circuit of the third implementation of the present disclosure.
  • the reset circuit of the implementation includes a charging circuit 101 , a driving circuit 102 , an execution circuit 103 , a control port 110 , and a reset port 120 .
  • the charging circuit 101 has an input end connected with the control port 110 , an output end connected with the driving circuit 102 , and is configured to generate a second voltage signal after a first voltage signal provided by the control port 110 is received.
  • the charging circuit 101 includes a resistor R 4 and a capacitor C 1 ; the resistor R 4 and the capacitor C 1 are connected in series to form a series branch, among which the series branch has one end as the input end of the charging circuit 101 and the other end as the output end of the charging circuit 101 .
  • the resistor R 4 is connected in series with the capacitor C 1 , the resistor R 4 has one end as the input end of the charging circuit and the other end connected with one end of the capacitor C 1 , and the capacitor C 1 has the other end grounded; a node between the other end of the resistor R 4 and one end of the capacitor C 1 acts as the output end of the charging circuit.
  • the charging circuit 101 further includes a resistor R 1 , and the control port 110 is grounded via the resistor R 1 .
  • the resistor R 1 has one end connected with one end of the resistor R 3 and the other end grounded.
  • the first voltage signal is a high level signal and the second voltage signal is a level signal after the capacitor C 1 is charged.
  • the control port 110 provided in the implementation of the present disclosure can be integrated with an electric device, when a button operation is performed on the electric device, the control port 110 is triggered to provide a high level signal, and the capacitor C 1 can be charged via the resistor R 4 and the level value of the capacitor C 1 can rise gradually.
  • the button operation can be to press and hold a button for a preset time or press and hold a combination of a plurality of buttons simultaneously.
  • the button operation can be replaced with a knob operation, and the present disclosure is not limited thereto.
  • the driving circuit 102 has an input end connected with the output end of the charging circuit 101 , an output end connected with the execution circuit 103 , and is configured to amplify the second voltage signal after it is detected that the value of the second voltage signal (that is, the level value of the capacitor C 1 ) reaches a preset value and output the amplified second voltage signal to the execution circuit 103 .
  • the driving circuit 102 includes a MOS transistor Q 4 and a first power supply end; the MOS transistor Q 4 has agate which is the input end of the driving circuit 102 , and the MOS transistor Q 4 has a source which is the output end of the driving circuit 102 ; the gate of the MOS transistor Q 4 is connected with the output end of the charging circuit 101 and an output end of the reverse discharge circuit, and the source of the MOS transistor Q 4 is connected with an input end of the execution circuit 103 ; the MOS transistor Q 4 has a drain connected with the first power supply end.
  • This reset circuit has low power consumption and can be advantageously applied to occasions requiring a high-frequency/high-speed circuit or high-current as well as occasions sensitive to the base or drain control current.
  • the driving circuit 102 further includes a resistor R 6 and a resistor R 7 ; the drain of the MOS transistor Q 4 is connected with the first power supply end via the resistor R 6 , and the source of the MOS transistor Q 4 is grounded via the resistor R 7 .
  • the MOS transistor Q 4 of the driving circuit 102 when the value of the level signal of the capacitor C 1 reaches a preset value, the MOS transistor Q 4 of the driving circuit 102 is turned on, at this point, the MOS transistor Q 4 can amplify the level signal of the capacitor C 1 which has reached the preset vale and transfer the amplified signal to the execution circuit 103 .
  • the driving circuit 102 can be provided so as to amplify the level signal of the capacitor C 1 which has reached the preset value and transfer the amplified signal to the execution circuit 103 .
  • the MOS transistor is used for threshold detection and level signal amplification.
  • the execution circuit 103 has an input end connected with the output end of the driving circuit 102 , an output end connected with the reset port 120 , and is configured to generate a reset signal after the amplified second voltage signal is received and transfer the reset signal to the reset port 120 .
  • the execution circuit 103 includes a field effect transistor M 2 , a capacitor C 2 , and a second power supply end; the field effect transistor M 2 has a gate which is the input end of the execution circuit 103 , the field effect transistor M 2 has a drain which is the output end of the execution circuit 103 ; the gate of the field effect transistor M 2 is connected with the output end of the driving circuit 102 , the drain of the field effect transistor M 2 is grounded via the capacitor C 2 , and the field effect transistor M 2 has a source grounded; the second power supply end is grounded via the capacitor C 2 .
  • the execution circuit 103 further includes a resistor R 8 and a resistor R 9 ; the gate of the field effect transistor M 2 is connected to the output end of the driving circuit 102 via the resistor R 8 , and the drain of the field effect transistor M 2 is connected with the reset port 120 , and the source of the field effect transistor M 2 is grounded; the second power supply end is grounded via the resistor R 9 and the capacitor C 2 .
  • the execution circuit includes the resistor R 8 , the resistor R 9 , the MOS transistor M 2 and the capacitor C 2 , and the second power supply end; among them, the resistor R 8 has one end connected with the output end of the driving circuit; the gate of the MOS transistor M 2 is connected with the other end of the resistor R 8 , the source of the MOS transistor M 2 is grounded, and the drain of the MOS transistor M 2 is connected with the reset port; the resistor R 9 has one end connected with the drain of the MOS transistor M 2 and the other end connected with the second power supply end; the capacitor C 2 has one end connected with the drain of the MOS transistor M 2 and the other end grounded.
  • the second power supply end charges the capacitor C 2 via the resistor R 9 ; after the control port provides the first voltage signal, the source voltage of the MOS transistor Q 4 continues to rise to turn on the field effect transistor M 2 , at this point, the capacitor C 2 is discharged, and a low level reset signal is generated after the capacitor C 2 is discharged; the reset signal is transferred to the reset port 120 for a reset operation.
  • the reset circuit can further includes a reverse discharge circuit 104 ; the reverse discharge circuit 104 has an input end connected with the control port 110 , an output end connected with the output end of the charging circuit 101 , and is configured to generate a fourth voltage signal after a third voltage signal provided by the control port 110 is received, so as to discharge the charging circuit, that is, discharge the capacitor C 1 .
  • the reverse discharge circuit 104 includes a filed effect transistor M 1 , a transistor Q 2 , and a third power supply end;
  • the field effect transistor M 1 has a gate which is the input end of the reverse discharge circuit 104
  • the transistor Q 2 has a collector which is the output end of the reverse discharge circuit 104 ;
  • the gate of the field effect transistor M 1 is connected with the control port 110 , and the field effect transistor M 1 has a drain which is connected with a base of the transistor Q 2 , and the field effect transistor M 1 has a source grounded;
  • the base of the transistor Q 2 is connected with the drain of the field effect transistor M 1 , the transistor Q 2 has a collector connected with the output end of the charging circuit 101 and the input end of the driving circuit 102 , and the transistor Q 2 has an emitter grounded;
  • the third power supply end is connected with the drain of the field effect transistor M 1 .
  • the reverse discharge circuit 104 further includes a resistor R 2 , a resistor R 3 , and a resistor R 5 ; the gate of the field effect transistor M 1 is connected to the control port 110 via the resistor R 2 , the drain of the field effect transistor M 1 is connected to the base of the transistor Q 2 via the resistor R 5 ; the third power supply end is connected to the drain of the field effect transistor M 1 via the resistor R 3 .
  • the reverse discharge circuit includes the resistor R 2 , the resistor R 3 , the resistor R 5 , the MOS transistor M 1 , the transistor Q 2 , and the third power supply end; among them, the resistor R 2 has one end connected with the control port; the gate of the MOS transistor M 1 is connected with the other end of the resistor R 2 , and the source of the MOS transistor M 1 is grounded; the resistor R 5 has one end connected with the drain of the MOS transistor M 1 ; the base of the transistor Q 2 is connected with the other end of the resistor R 5 , the emitter of the transistor Q 2 is grounded, and the collector of the transistor Q 2 is connected with the output end of the charging circuit; the third power supply end is connected to the drain of the MOS transistor M 1 via the resistor R 3 .
  • the third voltage signal is a low level signal; when the control port provides a high level signal, the field effect transistor M 1 of the reverse discharge circuit is turned on while the transistor Q 2 is turned off, at this point, the reverse discharge circuit has no effect on the charging circuit; however, the capacitor C 1 stops charging when the control port provides a low level signal, at this point, the field effect transistor M 1 is turned off and the transistor Q 2 is turned on, and the reverse discharge circuit will generate a fourth voltage signal for the capacitor C 1 and perform discharge operation on the capacitor C 1 ; the value of the level signal of the capacitor C 1 drops below a preset value rapidly, such that the MOS transistor Q 4 and the field effect transistor M 2 turn off rapidly, the capacitor C 2 continues to be charged and returns to a high level gradually to end the reset state.
  • the reverse discharge circuit 104 the capacitor C 1 can be discharged rapidly to end the reset state, when the reset operation is released, the microcontroller can enter a normal work state quickly and reset effects can be eliminated.
  • the first power supply end of the driving circuit, the second power supply end of the execution circuit, and the third power supply end of the reverse discharge circuit share a power supply VCC.
  • FIG. 2 or FIG. 3 can be exchanged with the one illustrated in FIG. 4 or FIG. 5
  • the reverse discharge circuit illustrated in FIG. 3 can be exchanged with the one illustrated in FIG. 5
  • FIG. 6 and FIG. 7 illustrate another structure of the reset circuit of the present disclosure respectively and the details thereof will not be repeated here.
  • the present disclosure has no restriction on the use of the MOS transistor and the transistor.
  • FIG. 8 is a schematic structure diagram of an electronic device according to an implementation of the present disclosure.
  • the electric device provided in this implementation of the present disclosure includes the reset circuit 100 of the above-mentioned first implementation, the second implementation, or the third implementation as well as a button 200 and a microcontroller 300 .
  • the control port 110 is configured to provide the first voltage signal when the button 200 is pressed; the reset port 120 is configured to perform a reset operation on the microcontroller 300 when the reset port 120 receives the reset signal.
  • the control port 110 can be caused to provide the first voltage signal, and the charging circuit 101 can generate a second voltage signal after the first voltage signal is received; when the value of the second voltage signal reaches a preset value, the driving circuit 102 will amplify the second voltage signal and output the amplified second voltage signal to the execution circuit 103 ; after receiving the amplified second voltage signal, the execution circuit 103 can generate a rest signal and transfer the same to the reset port 120 ; the reset port 120 can be connected with an element to be reset on the electric device, and in this implementation, the element to be reset is a microcontroller.
  • the button 200 can be a tact switch or a combination of several tact switches.
  • the operation performed on the button 200 can be to press and hold a touch switch for a preset time, or press and hold a combination of several touch switches at the same time, at this point, the control port 110 provides the first voltage signal.
  • the button operation can be replaced with a knob operation, and the present disclosure is not limited thereto.
  • a high level signal is generated when the button is pressed, and a low level signal is generated when the button is released.
  • the reset circuit of the implementation of the present disclosure can be applied to different electronic devices, and in an implementation, the reset circuit is applied to a headphone power amplifier and is configured to perform reset operation on a microcontroller of the headphone power amplifier.
  • Implementations of the present disclosure have the following advantageous effects: the present disclosure designs a reset circuit; when the reset circuit is applied to an electric device including a button and a microcontroller, if the button is pressed to cause the control port to provide the first voltage signal, the charging circuit will generate the second voltage signal after the first voltage signal is received; if the driving circuit detects that the value of the second voltage signal reaches a preset value, the second voltage signal will be amplified and the amplified second voltage signal will be output to the execution circuit; the execution circuit generates a reset signal after the second voltage signal is received and transfer the reset signal to the reset port, and the reset port performs a reset operation on the microcontroller to achieve the reset function of the electric device.
  • the driving circuit 102 can amplify a level signal of the capacitor C 1 which has reached a preset value, so as to avoid the case that it is unable to drive because of the large value of the resistor R 1 and the weak drive capacity of the charging circuit 101 . Furthermore, by providing the reverse discharge circuit 104 , the capacitor C 1 can be discharged rapidly so as to end the reset state, and the microcontroller can enter a normal work state after the reset operation is released, whereby reset effects can be eliminated.
  • a reset operation when a reset operation is required, it is not necessary to make a large change in the structure and appearance of the electronic device and no dedicated button is needed to be separately occupied to perform the reset operation; a reset function can be achieved in a manner of pressing an existing button without the use of any external tool, thereby avoiding false triggering effectively.
  • the implementation of the present disclosure is not susceptible to false trigger because the reset circuit of the implementation of the present disclosure needs to be delayed by charging the capacitor C 1 to output the reset signal. That is to say, when the button is associated with the control port, the button can be touched or short pressed to achieve basic functions thereof, or can be long-pressed to trigger the reset function.
  • the button can be touched within 1 second to achieve a “show power request” function of an electronic device, or, the button can be short pressed for about 3 seconds to achieve a “switch the external power supply status” function of the electronic device, or, the button can be long-pressed for more than 15 seconds to achieve a “reset” function of the electric device, therefore, the reset function can be achieved without adding any button, at the same time, it is not susceptible to false trigger and is user-friendly.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
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US15/470,411 2015-06-03 2017-03-27 Reset circuit and electronic device Active US10014854B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201510300799.0 2015-06-03
CN201510300799.0A CN104953992B (zh) 2015-06-03 2015-06-03 一种复位电路及电子设备
CN201510300799 2015-06-03
PCT/CN2016/084741 WO2016192672A1 (zh) 2015-06-03 2016-06-03 一种复位电路及电子设备

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CN104953992B (zh) 2015-06-03 2017-08-08 广东欧珀移动通信有限公司 一种复位电路及电子设备
WO2020082737A1 (zh) * 2018-10-24 2020-04-30 宁波飞芯电子科技有限公司 复位方法、复位装置、以及应用其的复位系统和像素阵列
WO2020133246A1 (zh) * 2018-12-28 2020-07-02 福建联迪商用设备有限公司 一种分时复用的复位装置、方法、及终端
CN111200425A (zh) * 2020-01-23 2020-05-26 华为技术有限公司 一种复位电路及相关电子设备
CN111615029A (zh) * 2020-04-23 2020-09-01 深圳市豪恩声学股份有限公司 无线耳机复位电路、无线耳机及复位方法
CN114063481B (zh) * 2020-07-30 2024-05-17 广东美的厨房电器制造有限公司 控制电路、用电设备和控制方法
CN113708467B (zh) * 2021-10-29 2022-02-22 苏州浪潮智能科技有限公司 一种上电电路、电池备份单元及存储服务器系统
CN114115043B (zh) * 2021-11-27 2024-08-30 沃太能源股份有限公司 一种mcu复位系统及具有其的后备电源
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