WO2016192217A1 - 一种apb总线桥 - Google Patents

一种apb总线桥 Download PDF

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Publication number
WO2016192217A1
WO2016192217A1 PCT/CN2015/088294 CN2015088294W WO2016192217A1 WO 2016192217 A1 WO2016192217 A1 WO 2016192217A1 CN 2015088294 W CN2015088294 W CN 2015088294W WO 2016192217 A1 WO2016192217 A1 WO 2016192217A1
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Prior art keywords
clock
apb
signal
clock side
module
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PCT/CN2015/088294
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English (en)
French (fr)
Inventor
杨海波
张庆
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深圳市中兴微电子技术有限公司
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Publication of WO2016192217A1 publication Critical patent/WO2016192217A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/38—Universal adapter
    • G06F2213/3852—Converter between protocols

Definitions

  • the present invention relates to the field of chip design, and in particular, to an APB (Advanced Peripheral Bus) bus bridge.
  • APB Advanced Peripheral Bus
  • An on-chip integrated system generally includes a plurality of functional modules, such as a processor (CPU), a direct memory access (DMA), a GPU (Graphic Processing Unit), a high-speed interface module, a multimedia module, and the like.
  • Each function module can modify its internal control registers via CPU access to control the operation of the module and even the entire chip system.
  • the SoC refers to a part of a bus interconnection, including a master device, such as a CPU, a DMA, or another port bus, which is an AXI (Advanced eXtensible Interface) or an AHB. (Advanced High performance Bus) and other types of master devices, the number of master devices depends on the application requirements of different chips; slave devices, such as port bus is AXI bus, AHB or APB protocol type slave devices, slave devices The number also depends on the application requirements of different chips; the interconnection matrix implements the route arbitration of the read/write request of the master device, the bus protocol conversion, the bus bit width conversion, and the cross clock processing. In general, when the CPU accesses the control register of the slave device, it does not need much data throughput, and only needs to be accessed through the APB bus, that is, the slave device at this time corresponds to the APB slave device in FIG.
  • a master device such as a CPU, a DMA, or another port bus, which is an AXI (Advance
  • the interconnection matrix includes a pre-processing module (pre_process), a routing module (router), and a post-processing module (post_process).
  • pre_process pre-processing module
  • routing module router
  • post_process post-processing module
  • the pre-processing module is externally connected to the main device, and performs functions such as bus protocol conversion and bit width conversion, and is based on a private protocol (PP, Private Protocol) and a routing module.
  • PP Private Protocol
  • the post-processing module is connected to the slave device externally, and performs functions such as bus protocol conversion and bit width conversion.
  • the PP is connected to the routing module.
  • FIG. 3 is a schematic diagram of a bus interconnect matrix architecture and a clock in the prior art. Referring to FIG. 3, FIG. 3 is a clock and an APB slave device added on the basis of FIG.
  • each interface clock (router_clk) of the routing module may be the same or different, and pclk is an APB bus clock.
  • the frequency of router_clk is much larger than the frequency of pclk. Therefore, the post-processing module needs to complete clock conversion and protocol conversion. However, in the past, it pays more attention to the cross-clock domain processing between asynchronous clocks. There is no APB bus between synchronous clocks. The processing scheme for the conversion.
  • embodiments of the present invention are expected to provide an APB bus bridge.
  • An embodiment of the present invention provides an APB bus bridge, where the APB bus bridge is disposed between an interconnecting matrix and a slave device, and the master device can pass the APB bus bridge through an APB interface working on the first clock through the interconnect matrix.
  • the APB bus bridge includes The APB request cache module, the APB request output module, the APB response cache module, and the APB response output module; wherein the APB request cache module is configured to read the APB of the input first clock side based on the clock enable signal.
  • the write request signal, the chip select signal on the first clock side, and the enable signal on the first clock side are buffered on the first clock, and the input is performed.
  • a buffered first chip side chip select signal and a buffered first clock side enable signal wherein the first clock side APB
  • the read/write request signal, the chip select signal on the first clock side, and the enable signal on the first clock side are transmitted by the interconnect matrix, and the clock enable signal has a set interval of N a first clock cycle, and the effective time is a first clock cycle, and the timing path length for controlling the register-to-register between the APB request buffer module and the APB request output module is maintained as a second clock cycle;
  • the APB request output module is configured to respectively input the read APB read/write request signal on the cached first clock side, the cached first clock side chip select signal, and the cached first
  • the enable signal on the clock side is buffered on the second clock, and outputs an APB read/write request signal on the second clock side, a
  • the APB request cache module has an idle state, an established state, and a transmission state; the APB requests a cache module, configured to be in the idle state, and the clock enable signal and the first When the chip select signal on the clock side is set to the first value, the idle state enters the set state, and the chip select signal on the first clock side and the read/write request signal on the first clock side are performed.
  • the APB request output module has an idle state, an established state, a transmission state, and an end state; the APB request output module is configured to: when the user is in the idle state, the first after the cache The APB read/write request signal on the clock side and the buffered chip select signal on the first clock side are sample buffered on the second clock to obtain the chip select signal on the second clock side and the second An APB read/write request signal on the clock side, and outputting the chip select signal and the APB read/write request signal on the second clock side to the slave device; when the chip select signal on the second clock side is set to third When the value is entered, the setup state is entered, and the buffered first clock side enable signal is buffered on the second clock, and the second clock side enable signal is obtained, and the transmission is entered. When the APB transmission end flag of the second clock side is set, the chip select signal of the second clock side and the enable signal of the second clock side are set to a fourth value, and the end state is entered.
  • the APB request output module is further configured to enter the idle state when the APB transmission end identifier is revoked on the second clock side, and read the APB on the cached first clock side/ The write request signal and the buffered chip select signal on the first clock side are sample buffered on the second clock.
  • the APB bus bridge further includes: an APB transmission end identifier generating module on the second clock side, configured to generate an APB transmission end identifier on the second clock side to control logic of the APB request output module State jump.
  • the APB response buffer module is configured to perform logical operation on the second clock side preparation indication signal and the second clock side enable signal input by the slave device, Two beats are buffered on the second clock, and the buffered second clock side preparation indication signal is obtained and output.
  • the APB response buffer module is further configured to sample the buffered second clock side preparation indication signal on the first clock, and take the sampled signal And performing a logical AND operation with the cached second clock side preparation indication signal to obtain an APB transmission response identifier on the first clock, where the APB transmission response identifier on the first clock is a valid one time. Clock cycle.
  • the APB response output module is configured to: when the APB transmission response identifier on the first clock is set, input the buffered second clock side preparation indication signal on the first clock Sampling is performed to obtain and output a preparation indication signal on the first clock side.
  • the APB response output module is further configured to set the preparation indication signal of the first clock side when the next first clock cycle after the preparation indication signal of the first clock side is set It is the fifth value.
  • the APB response buffer module is further configured to buffer two beats on the second clock on the input second clock side error indication signal, and obtain and output the buffered second clock side error indication.
  • the APB response output module is further configured to: when the APB transmission response identifier on the first clock is set, the error indication signal of the buffered second clock side is sampled on the first clock, and obtained And outputting an error indication signal on the first clock side.
  • An embodiment of the present invention provides an APB bus bridge, which is disposed between an interconnecting matrix and a slave device, wherein the first clock and the second clock are synchronous clocks, and the frequency ratio is a positive integer N, when the master device works on the interconnect matrix.
  • the clock enable signal, the register-to-register timing path length between the APB request buffer module and the APB request output module in the APB bus bridge is maintained for a second clock cycle, that is, N first clock cycles, and thus, the timing path As a multi-cycle path, the implementation difficulty of the back end is reduced, and the APB bus bridge can be converted between two synchronous clocks whose clock frequency ratio is an arbitrary integer, thereby improving the design efficiency of the front end.
  • FIG. 1 is a schematic diagram of a SoC chip system architecture in the prior art
  • FIG. 2 is a schematic diagram of a bus interconnect matrix structure in the prior art
  • FIG. 3 is a schematic diagram of a bus interconnect matrix structure and a clock in the prior art
  • FIG. 4 is a schematic diagram of an interconnect matrix structure and a clock with an APB bus bridge according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of an interface of an APB bus bridge in an embodiment of the present invention.
  • FIG. 6 is a timing diagram when the ratio of pclk_m to pclk_s is 4:1 in the embodiment of the present invention
  • FIG. 7 is a timing diagram of a ratio of a pclk_m to a pclk_s frequency ratio of 1:1 in an embodiment of the present invention
  • FIG. 8 is a schematic diagram of an internal structure of an APB bus bridge according to an embodiment of the present invention.
  • FIG. 9 is a write timing diagram of an APB bus in an embodiment of the present invention.
  • FIG. 10 is a read timing diagram of an APB bus in an embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of an APB bus bridge according to an embodiment of the present invention.
  • FIG. 13 is a write timing diagram of an APB bus bridge when the ratio of pclk_m to pclk_s is 4:1 in the embodiment of the present invention
  • FIG. 14 is a read timing diagram of an APB bus bridge when a ratio of a pclk_m to a pclk_s frequency is 1:1 according to an embodiment of the present invention
  • FIG. 15 is a write timing diagram of an APB bus bridge when the ratio of pclk_m to pclk_s is 1:1 in the embodiment of the present invention.
  • the APB request buffer module of the APB bus bridge is based on a clock enable signal, and respectively inputs an APB read/write request signal on the first clock side and a chip select signal on the first clock side.
  • the enable signal of the first clock side is buffered on the first clock, and the output buffer is The APB read/write request signal on the first clock side, the chip select signal on the first clock side after buffering, and the enable signal on the first clock side after buffering, wherein the APB read on the first clock side/ The write request signal, the chip select signal on the first clock side, and the enable signal on the first clock side are transmitted by the interconnect matrix, and the set interval of the clock enable signal is N first a clock cycle, and the effective time is a first clock cycle, configured to control a register-to-register timing path length between the APB request cache module and the APB request output module to be a second clock cycle; the APB The bus bridge APB request output module respectively inputs, to the input, the APB read/write
  • Embodiments of the present invention provide an interconnection matrix.
  • 4 is a schematic diagram of an interconnect matrix structure and a clock with an APB bus bridge in an embodiment of the present invention.
  • the interconnection matrix includes: a pre-processing module 41, a routing module 42, a post-processing module 43, and an APB bus bridge 44.
  • the pre-processing module 41 is connected to the master device through a bus such as AXI or AHB, and the routing module 42 passes
  • the PP is interconnected with the pre-processing module 42 and the post-processing module 43, respectively, the post-processing module 43 is connected to the APB bus bridge 44 via the APB bus, and the APB bus bridge 44 is connected to the slave device via the APB bus.
  • the master device working on any clock can read/write the slave device working on the second clock via the APB bus bridge through the APB interface working on the first clock on the interconnect matrix.
  • the first clock and the second clock are synchronous clocks, and the frequency ratio is N:1, that is, the N first clock periods are equal to one second clock period, the first clock is a fast clock, and the second clock is slow. clock.
  • the APB bus bridge in the above interconnection matrix is specifically described below.
  • FIG. 5 is a schematic diagram of an interface of an APB bus bridge according to an embodiment of the present invention.
  • the interface of the APB bus bridge includes a first clock signal (pclk_m) and a second clock signal (pclk_s).
  • the APB bus bridge has the following control signals on the first clock: a clock enable signal (pclk_en), a chip select signal on the first clock side (psel_m), an enable signal on the first clock side (penable_m), and a first clock side.
  • a clock enable signal pclk_en
  • psel_m chip select signal on the first clock side
  • penable_m enable signal on the first clock side
  • a first clock side a clock enable signal on the first clock side
  • Read/write request signal (pwrite_m) preparation instruction signal (pready_m) on the first clock side
  • presence of the following data signals address signal on the first clock side (paddr_m), write data signal on the first clock side (pwdata_m) The read data signal (prdata_m) on the first clock side.
  • control signals exist on the second clock: a chip select signal (psel_s) on the second clock side, an enable signal (penable_s) on the second clock side, a read/write request signal (pwrite_s) on the second clock side, and a second a preparation instruction signal (pready_s) on the clock side; and the following data signals: an address signal (paddr_s) on the second clock side, a write data signal (pwdata_s) on the second clock side, and a read data signal (prdata_s) on the second clock side .
  • pclk_en can set the settling interval to N first clock cycles, and the effective time is one first clock cycle.
  • the frequency ratio of pclk_m to pclk_s is 4:1
  • the timing relationship between pclk_en, pclk_m, and pclk_s is as shown in FIG. 6; when the ratio of pclk_m to pclk_s is 1:1, pclk_en, pclk_m
  • the timing relationship between pclk_s is shown in Figure 7.
  • pclk_en there may be other timing relationships between pclk_en, pclk_m, and pclk_s.
  • the setup interval of pclk_en is a pclk_s period
  • the effective time is a pclk_m period
  • pclk_en is set.
  • the sampled clock may be in the early pclk_m period, which is not specifically limited in the embodiment of the present invention.
  • the APB bus bridge includes: an APB request cache module 81, an APB request output module 82, an APB response buffer module 83, and an APB response output module. 84; among them,
  • the APB request cache module 81 is configured to buffer the input pwrite_m, psel_m, and penable_m on the first clock based on pclk_en, and output the buffered first clock side APB read/write request signal (pwrite_m_dly), cached a chip select signal (psel_m_dly) on the first clock side and an enable signal (penable_m_dly) on the first clock side after buffering;
  • the APB request output module 82 is configured to perform sampling buffering on the second clock for the input pwrite_m_dly, psel_m_dly, and penable_m_dly, respectively, and output pwrite_s, psel_s, and penable_s, wherein pwrite_s is used to indicate a read/write operation of the slave device;
  • the APB response buffer module 83 is configured to buffer the input preready_s on the second clock, and output the buffered second clock side preparation indication signal (pready_s_dly);
  • the APB response output module 84 is configured to perform sampling buffering on the first clock for the input pasty_s_dly, and output preready_m, wherein the preready_m is used to instruct the master device to complete the read/write operation on the slave device.
  • the APB request cache module has an idle state, an established state, and a transport state.
  • the APB request cache module is initially in an idle state, and when both pclk_en and psel_m are set to the first value (such as 1), the APB requests the cache module to enter the setup state from the idle state, buffers pwrite_m and psel_m, and outputs pwrite_m_dly and psel_m_dly; After a pclk_m period, the APB requests the cache module to enter the transfer state, buffers the penable_m, and outputs the penable_m_dly until the past_m of the APB response output module is set, ending the buffering of the psel_m and penable_m, and setting the psel_m_dly and penable_m_dly to the second value. (such as 0), at this time, the APB request is slow The memory module enters the idle state from the transmission state.
  • the APB request output module has an idle state, an established state, a transmitted state, and an ended state.
  • the APB requests the output module to be in the idle state
  • the APB requests the output module to perform sampling buffering on the second clock for pwrite_m_dly and psel_m_dly, that is, buffering a second clock cycle for the above two signals, obtaining pwrite_s and psel_s, and outputting to the slave.
  • the device when the psel_s is the third value (such as 1), indicates that the slave device starts receiving the read/write request.
  • the APB requests the output module to enter the setup state, and samples the penable_m_dly on the second clock, which is also the buffer for the penable_m_dly.
  • a second clock cycle acquires and outputs penable_s.
  • the APB requests the output module to enter the transmission state.
  • the APB request output module is in the transmission state, if the input APB transmission end identifier (s_transfer_end) of the second clock side is set, the sampling of psel_m_dly and penable_m_dly is ended, and psel_s and penable_s are set to the fourth value (for example) 0), at the same time APB requests the output module to enter the end state.
  • the APB request output module is further configured to enter an idle state when the s_transfer_end is revoked, and sample the psel_m_dly and pwrite_m_dly on the second clock.
  • s_transfer_end In order to ensure the correctness of the APB bus bridge processing, s_transfer_end needs to meet the following conditions:
  • the revocation time of the predry_m is no later than the revocation time of the s_trans_end, that is, the APB request cache module jumps to the idle state no later than the time when the APB requests the output module to jump to the idle state, so that the APB request cache module can be completed.
  • the APB request output module can only complete the output of the APB transmission request (completed from the idle state, the established state, and the transmission). State to end state jump);
  • the setup_m is set earlier than the setup time of s_trans_end, so that the APB request cache module has jumped to the end state before the APB request cache module jumps to the idle state, that is, the APB request cache module starts the next time.
  • APB transmission request is delivered, APB please The output module has completed the output of the current APB transmission request.
  • the APB bus bridge may further include: an APB transmission end identifier generating module on the second clock side configured to generate s_transfer_end to control the APB to request a jump of the logic state of the output module.
  • the interconnect matrix requests the cache to the APB while transmitting the above control signal.
  • the module transfers a data signal that needs to be written to the slave device, that is, an address signal (paddr_m) on the first clock side and a write data signal (pwdata_m) on the first clock side.
  • the APB request buffer module buffers paddr_m and pwdata_m on the first clock, obtains paddr_m_dly and pwdata_m_dly, and outputs the same to the APB request output module; further, like the above control signal, the APB requests the output module to paddr_m_dly And pwdata_m_dly performs sampling buffer on the second clock, obtains paddr_s and pwdata_s, and outputs to the slave device, after receiving the data signals from the device, writes pwdata_s to the corresponding storage unit according to paddr_s; as shown in FIG. 10, when pwrite_m When set to 0, it indicates that the master device makes a read request to the slave device. Then, the interconnect matrix transmits only the paddr_m while transmitting the above control signal to inform the slave device where the data is to be read.
  • the APB response buffer module is connected to the slave device, can input the ready_s from the slave device, and is also connected to the APB request output module, and can input the penable_s by the APB request output module.
  • the two beats are buffered on the second clock.
  • the two beats of the cache are two beats (Re-timing) on the second clock, that is, the second clock is extended. At the second two clock cycles, the obtained_s_dly is obtained and output.
  • the APB response buffer module may also perform sampling buffering on the first clock on the past_s_dly, that is, delaying a first clock cycle, and inverting the sampled signal and performing a logical AND operation with the past_s_dly to obtain a transfer_rsp, where Said transfer_rsp The continuation effective time is a first clock cycle.
  • the APB response buffer module may also be connected to the APB transmission end identifier generation module on the second clock side. After the logical_operation between the past_s and the penable_s, and before the beat, the result of the operation is output to the second.
  • the APB transmission end identifier generation module on the clock side, and the above s_transfer_end is generated by the module.
  • the APB response output module samples the input pasty_s_dly on the first clock, that is, delays a first clock cycle to obtain preready_m, and then outputs preready_m to the interconnect matrix to inform the interconnect matrix to read/write. The operation is completed, and at the same time, the ready_m output APB request cache module to control the APB request cache module to enter the idle state.
  • the preready_m is set to a fifth value (such as 0).
  • the APB response buffer module caches two beats on the second clock for prdata_s, obtains prdata_s_dly, and outputs it to the APB response output module when transfer_rsp is set.
  • the APB response output module samples prdata_s_dly on the first clock, obtains prdata_m, and outputs it to the interconnect matrix to complete the read operation.
  • a signal for error reporting is also provided on the slave device side, that is, there is also an error indication signal (pslverr_s) on the second clock side, then, when the slave device After an error occurs in the read/write process, the slave device inputs pslverr_s to the APB response buffer module, and the APB response buffer module caches the signal twice on the second clock to obtain Pslverr_s_dly, and output the APB response output module, the APB response output module samples the signal on the first clock when the transfer_rsp is set, obtains the error indication signal (pslverr_m) of the first clock side, and outputs the error indication signal to the interconnection matrix to Reported an error to the master device.
  • pslverr_s error indication signal
  • the design of the APB bus bridge in the past is focused on reducing the access delay of the APB bus system, reducing the dynamic power consumption of the APB bus system, or processing the cross-clock domain between the asynchronous clocks.
  • the APB bus bridge focuses on the construction of its internal timing path to facilitate the physical implementation of the conversion process between the APB bus signals and the synchronous clock.
  • the timing path in the APB bus bridge is short, and when the clock of the first clock and the second clock is delayed, the clock channel and the data channel of the register are adjusted.
  • the delay can well realize the synchronous conversion of the input and output signals, which also reduces the difficulty of physical implementation.
  • the APB bus bridge described in one or more embodiments may be specifically as shown in FIG. 11.
  • the APB request cache module includes a logical AND gate, data selectors MUX1, MUX2, MUX3, MUX4, and MUX5.
  • MUX6 also includes registers Reg1, Reg2 and Reg3 operating on the first clock;
  • the APB request output module includes data selectors MUX7, MUX8, MUX9, MUX10 and MUX11, and also includes registers Reg4, Reg5 operating on the second clock.
  • APB response buffer module includes two logical AND gates, a logic NOT gate, registers Reg7, Reg8 and Reg9 operating on the second clock, and a register Reg10 operating on the first clock;
  • APB response output module The data selectors MUX12, MUX13, MUX14, and MUX15 are included, and further include registers Reg11, Reg12, and Reg13 operating on the first clock.
  • Reg7 ⁇ 9 are two registers cascaded together, which delays the signal by two clock cycles.
  • the bus bridge performs the read operation as follows:
  • the interconnect matrix passes the APB bus signals psel_m, penable_m, pwrite_m, and paddr_m to the APB request cache module, and other modules (such as the clock management module) pass the pclk_en signal to the APB request cache module.
  • the APB request cache module is initially in an idle state. When pclk_en and psel_m are set to 1, the APB requests the cache module to enter the setup state from the idle state, and caches pwrite_m and psel_m. Pclk_en and psel_m are logically ANDed by logic AND gate. The calculated signal is used as the selection signal of MUX1 and MUX2.
  • pwrite_m is output through MUX1, and then through Reg1, buffering a first clock cycle, obtaining pwrite_m_dly, and outputting to MUX7
  • psel_m passes through MUX2, MUX3, MUX4, and then through Reg2, buffers a first clock cycle, obtains psel_m_dly, and outputs to MUX8.
  • the APB requests the cache module to enter the transmission state after entering a setup state of a pclk_m period.
  • Penable_m passes through MUX5, MUX6, and then through Reg3, buffers a first clock cycle, obtains penable_m_dly, and outputs it to MUX10.
  • pwrite_m_dly is output by MUX7, after Reg4, buffering a second clock cycle, and obtaining pwrite_s output to the slave device; meanwhile, psel_m_dly is output by MUX8, and then extended by MUX9 and Reg5, psel_m_dly When a second clock cycle is obtained, the psel_s is obtained and output to the slave device.
  • the APB requests the output module to enter the setup state; at this time, the penable_m_dly is output by the MUX10, and sequentially passes through the MUX11 and Reg6, and the penable_m_dly caches one. In the second clock cycle, penable_s is obtained and output to the slave device.
  • the slave device sets up the preready_s and returns the read data via the prdata_s.
  • the APB response buffer module receives the pasty_s and prdata_s; the pasty_s and the above penable_s perform a logical AND operation through a logical AND gate, after the operation
  • the signal is divided into two paths, and the signal after the operation is input to the second clock transmission identifier generation module, which generates s_transfer_end, controls the output of MUX9 and MUX11, and then sets the psel_s and penable_s.
  • the APB requests the output module to enter the end state, and ends the read request to the slave device; and the other channel and the calculated signal are input to Reg7, buffering two beats on the second clock, that is, delaying two second clock cycles, Get preready_s_dly, predry_s_dly is also divided into three signals, the first signal is input into Reg10, after a delay of one first clock cycle, after the logic NOT gate, then input another logic AND gate, the second signal is directly input into the logic and the gate, After the two signals are logically ANDed, transfer_rsp is obtained, and the third signal is directly input to MUX12.
  • prdata_s passes Reg9 and buffers two beats on the second clock, that is, after two second clock cycles are delayed, prdata_s_dly is obtained and output to MUX15.
  • the fourth step when transfer_resp is set, the ready_s_dly is output by MUX12, which is sequentially passed through MUX13 and Reg11. After buffering for a first clock cycle, it is divided into two paths. One signal is output to MUX4 and MUX6, and MUX4 and MUX6 are outputted to 0. Psel_m_dly, The penable_m_dly is set to 0. At this time, the APB requests the cache module to enter the idle state; the other signal is output to the interconnect matrix to inform the master that the slave device has completed the read operation and is ready to receive the corresponding read data. At this time, prdata_s_dly is output by MUX15. After Reg13, after a first clock cycle is cached, pdata_m is obtained and output to the master device.
  • the implementation flow of the input signal paddr_m to the output signal paddr_s is exactly the same as the implementation flow of pwrite_m to pwrites_s, and will not be described here or below.
  • the bit conversion process of prdata_s to prdata_m is completely identical and independent of each other. Therefore, the bit width of the read data is not described above.
  • the slave device when the slave device is in the process of performing a read operation, the slave device outputs pslverr_s to Reg8, buffers two beats on the second clock, delays two second clock cycles, obtains pslverr_s_dly, and outputs the signal to MUX14.
  • transfer_rsp is set, pslverr_s_dly passes through MUX14 and Reg12 in sequence, buffers a first clock cycle, obtains pslverr_m, and outputs it to the interconnect matrix to report an error to the master device.
  • the APB bus bridge performs reading. The process of operation ends.
  • the APB bus bridge When the frequency ratio of the first clock to the second clock is 4:1, in conjunction with FIG. 13, the APB bus bridge performs a write operation as follows:
  • the interconnect matrix passes the APB bus signals psel_m, penable_m, pwrite_m, paddr_m, and pwdata_m to the APB request cache module, and other modules (such as the clock management module) pass the pclk_en signal to the APB request cache module.
  • the APB request cache module is initially in an idle state. When pclk_en and psel_m are set to 1, the APB requests the cache module to enter the setup state from the idle state, and caches pwrite_m and psel_m. Pclk_en and psel_m perform logical AND operation through logic AND gate. The calculated signal is used as the selection signal of MUX1 and MUX2.
  • pwrite_m is output through MUX1, and then a first clock cycle is obtained by Reg1 buffer, and pwrite_m_dly is obtained and output to MUX7;
  • Psel_m is output through MUX2, MUX3, MUX4, and then through Reg2, buffering a first clock cycle, obtaining psel_m_dly, and outputting to MUX8.
  • the APB request cache module enters the transfer state after entering a setup state of a pclk_m cycle.
  • the penable_m passes through MUX5 and MUX6 in sequence, and then registers a first clock cycle through Reg3 to obtain penable_m_dly and outputs it to MUX10.
  • pwrite_m_dly is output by MUX7, and then a second clock cycle is obtained by Reg4 buffering to obtain pwrite_s, which is output to the slave device; meanwhile, psel_m_dly is output via MUX8, MUX9, and then cached via Reg5.
  • the second clock cycle obtains psel_s and outputs to the slave device.
  • the psel_s is set to 1
  • the APB requests the output module to enter the setup state; at this time, the penable_m_dly is output through the MUX10 and the MUX11, and then a second clock cycle is buffered by the Reg6. Get the penable_s and output it to the slave so that the slave can write.
  • the slave device sets the preready_s, and the APB responds to the buffer module to receive the pasty_s; the past_s and the penable_s perform a logical AND operation through a logical AND gate, and the calculated signal is divided into two paths, one operation and one operation.
  • the input identifier generation module generates s_transfer_end, controls MUX9 and MUX11 to output 0, and then sets psel_s and penable_s to 0.
  • the APB requests the output module to enter the end state; and the other and the processed signals pass the register group Reg7. Two beats are buffered on the second clock, and the ready_s_dly is obtained.
  • the preed_s_dly is also divided into three signals.
  • the first signal is input to Reg10, after a delay of one first clock cycle, after the logical NOT gate, another logical AND gate is input, and the second The signal is directly input to the logic AND gate. After the two signals are logically ANDed, the transfer_rsp is obtained, and the third signal is directly input to the MUX12.
  • the fourth step after the transfer_rsp is set, the ready_s_dly is output by the MUX12, which is sequentially passed through the MUX13 and Reg11. After the first clock cycle is buffered, it is divided into two paths. One signal is output to the MUX4 and MUX6, and the MUX4 and MUX6 outputs 0, that is, the psel_m_dly, The penable_m_dly is set to 0. At this time, the APB requests the cache module to enter the idle state; the other signal is output to the interconnect matrix to inform the master that the slave device has completed the write operation.
  • the slave device when the slave device is in the process of performing a write operation, the slave device outputs pslverr_s to Reg8, buffers two beats on the second clock, delays two second clock cycles, obtains pslverr_s_dly, and outputs MUX14.
  • transfer_rsp is set, pslverr_s_dly passes through MUX14 and Reg12 in sequence, buffers a first clock cycle, obtains pslverr_m, and outputs it to the interconnect matrix to report an error to the master device.
  • the first clock and the second clock may also be the same frequency clock, that is, the frequency ratio is 1:1.
  • the read/write timing of the APB bus bridge is shown in FIG. 14 and FIG. I will not go into details one by one.
  • the pclk_en signal is such that the reg2reg (register to register) path from the APB request buffer module to the APB request output module can be set to a multi-cycle path, and the number of cycles is a multiple relationship between the fast and slow clock frequencies.
  • the data delay of the reg2reg path of the APB requesting the cache module to the APB request output module is small, and there is no need to set the multi-cycle path.
  • the input signal pclk_en of the APB bus bridge can be connected to the constant value 1.
  • the path length of the reg2reg path between the APB request buffer module and the APB request output module is a first clock cycle.
  • the APB bus bridge in the embodiment of the present invention does not change the function of the APB bus bridge, and does not affect the validity and consistency of the protocol.
  • the bus interface timing fully conforms to the APB bus protocol standard, and the beats through the input/output will be more
  • the periodic path is constrained within the APB bus bridge, which facilitates the design of the back end.
  • the APB bus bridge in the embodiment of the present invention supports signal conversion between the fast and slow clocks of the APB bus in an integer multiple frequency relationship, and also supports signal conversion between the same frequency clocks or on the same clock.
  • the chip interconnect matrix (including the APB bus bridge described in the embodiment of the present invention) is not required to be designed. To change, you can naturally adapt to this change.

Abstract

本发明公开了一种外围总线(APB)总线桥，设置在互联矩阵与从设备之间，主设备能够通过互联矩阵上工作在第一时钟的APB接口经由APB总线桥对工作在第二时钟上的从设备进行读/写操作，第一时钟与第二时钟为同步时钟，且频率比为正整数N；APB总线桥中的APB请求缓存模块基于时钟使能信号，对输入的第一时钟侧的信号在第一时钟上进行缓存，并向APB总线桥中的APB请求输出模块输出缓存后的信号，以使所述APB请求输出模块在第二时钟上进行缓存，输出第二时钟侧的信号；所述时钟使能信号的置起间隔为N个第一时钟周期，有效时间为一个第一时钟周期，用于控制APB请求缓存模块与APB请求输出模块之间的寄存器到寄存器的时序路径长度保持为一个第二时钟周期。

Description

一种APB总线桥 技术领域
本发明涉及芯片设计领域，尤其涉及一种外围总线(APB，Advanced Peripheral Bus)总线桥。
背景技术
片上集成系统(SoC)一般包括多个功能模块，如处理器(CPU)、存储器直接访问(DMA，Direct Memory Access)、图形处理器(GPU，Graphic Processing Unit)、高速接口模块、多媒体模块等。各个功能模块都可以经由CPU访问修改其内部的控制寄存器来控制模块乃至整个芯片系统的运行。
图1为现有技术中的SoC的典型系统架构示意图，参见图1所示，SoC涉及总线互联的部分，包括主设备，如CPU、DMA、或者其他端口总线为AXI(Advanced eXtensible Interface)或者AHB(Advanced High performance Bus)等协议类型的主设备，主设备的个数取决于不同芯片的应用需求；从设备，如端口总线为AXI总线、AHB或者APB等协议类型的从设备，从设备的个数也取决于不同芯片的应用需求；互联矩阵，实现对主设备的读/写请求的路由仲裁、总线协议转换、总线位宽转换、跨时钟处理等功能。一般来说，CPU访问配置从设备的控制寄存器时，不需要太大的数据吞吐量，只需通过APB总线访问即可，即此时的从设备对应图1中的APB从设备。
图2为现有技术中基于互联矩阵的总线架构示意图。参见图2所示，互联矩阵包括预处理模块(pre_process)、路由模块(router)以及后处理模块(post_process)。其中，预处理模块对外与主设备相连，完成总线协议转换、位宽转换等功能，基于私有协议(PP，Private Protocol)与路由模块相 连互通；后处理模块对外与从设备相连，完成总线协议转换、位宽转换等功能，同样，基于PP与路由模块相连互通。由于很多应用的高带宽要求，AXI、AHB协议工作的时钟频率越来越高，同样地要求路由模块的工作频率也越来越高，以满足越来越大的数据吞吐量需求。但需要特别指出的是，许多从设备的吞吐量却不大。比如，CPU通过从设备的APB总线接口访问其控制寄存器时，所产生的吞吐量非常小，需要的带宽并不大，而且对于控制寄存器的访问延时也一般没有特别的需求。因此，APB总线的时钟频率相对来说都是比较小的。图3为现有技术中的总线互联矩阵架构及时钟示意图。参见图3所示，图3是在图2的基础上添加了时钟以及一个APB从设备，其中，路由模块各个接口时钟(router_clk)可以相同，也可以不同，pclk为APB总线时钟，一般情况下，router_clk的频率比pclk的频率大很多，因此，后处理模块需要完成时钟转换和协议转换，但以往比较注重异步时钟之间的跨时钟域处理，并不存在一种APB总线在同步时钟之间转换的处理方案。
发明内容
有鉴于此，本发明实施例期望提供一种APB总线桥。
为达到上述目的，本发明实施例的技术方案是这样实现的：
本发明实施例提供一种APB总线桥，所述APB总线桥设置在互联矩阵与从设备之间，主设备能够通过所述互联矩阵上的工作在第一时钟的APB接口经由所述APB总线桥对工作在第二时钟上的所述从设备进行读/写操作，所述第一时钟与所述第二时钟为同步时钟，且频率比为N，N为正整数；所述APB总线桥包括：APB请求缓存模块、APB请求输出模块、APB响应缓存模块及APB响应输出模块；其中，所述APB请求缓存模块，配置为基于时钟使能信号，分别对输入的第一时钟侧的APB读/写请求信号、第一时钟侧的片选信号及第一时钟侧的使能信号在第一时钟上进行缓存，输 出缓存后的第一时钟侧的APB读/写请求信号、缓存后的第一时钟侧的片选信号及缓存后的第一时钟侧的使能信号，其中，所述第一时钟侧的APB读/写请求信号、所述第一时钟侧的片选信号及所述第一时钟侧的使能信号是由所述互联矩阵传递过来的，所述时钟使能信号的置起间隔为N个第一时钟周期，且有效时间为一个第一时钟周期，用于控制所述APB请求缓存模块与所述APB请求输出模块之间的寄存器到寄存器的时序路径长度保持为一个第二时钟周期；所述APB请求输出模块，配置为分别对输入的所述缓存后的第一时钟侧的APB读/写请求信号、所述缓存后的第一时钟侧的片选信号及所述缓存后的第一时钟侧的使能信号在第二时钟上进行缓存，输出第二时钟侧的APB读/写请求信号、第二时钟侧的片选信号及第二时钟侧的使能信号，其中，所述第二时钟侧的APB读/写请求信号用于指示所述从设备进行读/写操作；所述APB响应缓存模块，配置为对输入的第二时钟侧的准备指示信号在所述第二时钟上进行缓存，输出缓存后的第二时钟侧的准备指示信号；所述APB响应输出模块，配置为对输入的所述缓存后的第二时钟侧的准备指示信号在所述第一时钟上进行缓存，输出第一时钟侧的准备指示信号，其中，所述第一时钟侧的准备指示信号用于指示所述主设备完成对所述从设备的读/写操作。
在上述方案中，所述APB请求缓存模块具有空闲态，建立态和传输态；所述APB请求缓存模块，配置为在自身处于所述空闲态，且所述时钟使能信号及所述第一时钟侧的片选信号均置为第一值时，由所述空闲态进入所述建立态，对所述第一时钟侧的片选信号及所述第一时钟侧的读/写请求信号进行缓存，输出所述缓存后的第一时钟侧的片选信号及所述缓存后的第一时钟侧的APB读/写请求信号；在一个第一时钟周期后，进入所述传输态，对所述第一时钟侧的使能信号进行缓存，输出所述缓存后的第一时钟侧的使能信号，直至所述APB响应输出模块输出的所述第一时钟侧准备指示信 号置起，将所述缓存后的第一时钟侧的片选信号及所述缓存后的第一时钟侧的使能信号置为第二值，由所述传输态进入所述空闲态。
在上述方案中，所述APB请求输出模块具有空闲态、建立态、传输态及结束态；所述APB请求输出模块，配置为在自身处于所述空闲态时，对所述缓存后的第一时钟侧的APB读/写请求信号及所述缓存后的第一时钟侧的片选信号在所述第二时钟上进行采样缓存，获得所述第二时钟侧的片选信号及所述第二时钟侧的APB读/写请求信号，并将所述第二时钟侧的片选信号及APB读/写请求信号输出给所述从设备；当所述第二时钟侧的片选信号置第三值时，进入所述建立态，对所述缓存后的第一时钟侧的使能信号在所述第二时钟上采样缓存，获得所述第二时钟侧的使能信号，并进入所述传输态；当第二时钟侧的APB传输结束标识置起时，将所述第二时钟侧的片选信号及所述第二时钟侧的使能信号置为第四值，进入所述结束态。
在上述方案中，所述APB请求输出模块，还配置为在所述第二时钟侧的APB传输结束标识撤销时，进入所述空闲态，对所述缓存后的第一时钟侧的APB读/写请求信号、所述缓存后的第一时钟侧的片选信号在所述第二时钟上进行采样缓存。
在上述方案中，所述APB总线桥还包括：第二时钟侧的APB传输结束标识生成模块，配置为生成所述第二时钟侧的APB传输结束标识，以控制所述APB请求输出模块的逻辑状态的跳转。
在上述方案中，所述APB响应缓存模块，配置为将所述从设备输入的将所述第二时钟侧的准备指示信号与所述第二时钟侧的使能信号进行逻辑运算后在所述第二时钟上缓存两拍，获得并输出所述缓存后的第二时钟侧准备指示信号。
在上述方案中，所述APB响应缓存模块，还配置为对所述缓存后的第二时钟侧准备指示信号在所述第一时钟上进行采样，并将采样后的信号取 反与所述缓存后的第二时钟侧准备指示信号做逻辑与运算，得到第一时钟上的APB传输响应标识，其中，所述第一时钟上的APB传输响应标识持续有效时间为一个第一时钟周期。
在上述方案中，所述APB响应输出模块，配置为当第一时钟上的APB传输响应标识置起时，对输入的所述缓存后的第二时钟侧准备指示信号在所述第一时钟上进行采样，获得并输出所述第一时钟侧的准备指示信号。
在上述方案中，所述APB响应输出模块，还配置为在所述第一时钟侧的准备指示信号置起后的下一个第一时钟周期时，将所述第一时钟侧的准备指示信号置为第五值。
在上述方案中，所述APB响应缓存模块，还配置为对输入的第二时钟侧的错误指示信号在所述第二时钟上缓存两拍，获得并输出缓存后的第二时钟侧的错误指示信号；所述APB响应输出模块，还配置为当第一时钟上的APB传输响应标识置起时，对所述缓存后的第二时钟侧的错误指示信号在所述第一时钟上采样，获得并输出第一时钟侧的错误指示信号。
本发明实施例提供了一种APB总线桥，设置在互联矩阵与从设备之间，第一时钟与第二时钟为同步时钟，且频率比为正整数N，当主设备通过互联矩阵上工作在第一时钟的APB接口经由APB总线桥对工作在第二时钟上的从设备进行读/写操作时，由于设置了置起间隔为N个第一时钟周期，有效时间为1个第一时钟周期的时钟使能信号，APB总线桥中的APB请求缓存模块与APB请求输出模块之间的寄存器到寄存器的时序路径长度保持为一个第二时钟周期，即N个第一时钟周期，这样，该时序路径就为多周期路径，降低了后端的实现难度，且使得APB总线桥能够在时钟频率比为任意整数的两个同步时钟之间进行转换，提高了前端的设计效率。
附图说明
图1为现有技术中的SoC芯片系统架构示意图；
图2为现有技术中的总线互联矩阵架构示意图；
图3为现有技术中的总线互联矩阵架构及时钟示意图；
图4为本发明实施例中的具有APB总线桥的互联矩阵架构及时钟示意图；
图5为本发明实施例中的APB总线桥的接口示意图；
图6为本发明实施例中的pclk_m与pclk_s频率比为4:1时的时序图；
图7为本发明实施例中的pclk_m与pclk_s频率比为1:1时的时序图；
图8为本发明实施例中的APB总线桥内部结构示意图；
图9为本发明实施例中的APB总线的写时序图；
图10为本发明实施例中的APB总线的读时序图；
图11为本发明实施例中的APB总线桥的结构示意图；
图12为本发明实施例中的pclk_m与pclk_s频率比为4:1时的APB总线桥的读时序图；
图13为本发明实施例中的pclk_m与pclk_s频率比为4:1时的APB总线桥的写时序图；
图14为本发明实施例中的pclk_m与pclk_s频率比为1:1时的APB总线桥的读时序图；
图15为本发明实施例中的pclk_m与pclk_s频率比为1:1时的APB总线桥的写时序图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
在本发明的各种实施例中：所述APB总线桥的APB请求缓存模块基于时钟使能信号，分别对输入的第一时钟侧的APB读/写请求信号、第一时钟侧的片选信号及第一时钟侧的使能信号在第一时钟上进行缓存，输出缓存 后的第一时钟侧的APB读/写请求信号、缓存后的第一时钟侧的片选信号及缓存后的第一时钟侧的使能信号，其中，所述第一时钟侧的APB读/写请求信号、所述第一时钟侧的片选信号及所述第一时钟侧的使能信号是由所述互联矩阵传递过来的，所述时钟使能信号的置起间隔为N个第一时钟周期，且有效时间为一个第一时钟周期，配置为控制所述APB请求缓存模块与所述APB请求输出模块之间的寄存器到寄存器的时序路径长度保持为一个第二时钟周期；所述APB总线桥APB请求输出模块分别对输入的所述缓存后的第一时钟侧的APB读/写请求信号、所述缓存后的第一时钟侧的片选信号及所述缓存后的第一时钟侧的使能信号在第二时钟上进行缓存，输出第二时钟侧的APB读/写请求信号、第二时钟侧的片选信号及第二时钟侧的使能信号，其中，所述第二时钟侧的APB读/写请求信号配置为指示所述从设备进行读/写操作；所述APB总线桥的APB响应缓存模块，对输入的第二时钟侧的准备指示信号在所述第二时钟上进行缓存，输出缓存后的第二时钟侧的准备指示信号；所述APB总线桥的APB响应输出模块对输入的所述缓存后的第二时钟侧的准备指示信号在所述第一时钟上进行缓存，输出第一时钟侧的准备指示信号，其中，所述第一时钟侧的准备指示信号配置为指示所述主设备完成对所述从设备的读/写操作。
本发明实施例提供一种互联矩阵。图4为本发明实施例中的具有APB总线桥的互联矩阵架构及时钟示意图。参见图4所示，该互联矩阵中包括：预处理模块41、路由模块42、后处理模块43以及APB总线桥44；预处理模块41通过AXI、AHB等总线与主设备连接，路由模块42通过PP分别与预处理模块42以及后处理模块43连接互通，后处理模块43与APB总线桥44通过APB总线连接，APB总线桥44通过APB总线与从设备连接。
其中，工作在任意时钟上的主设备能够通过互联矩阵上工作在第一时钟上的APB接口经由APB总线桥对工作在第二时钟上的从设备进行读/写 操作，第一时钟与第二时钟为同步时钟，且频率比为N:1，也就是说，N个第一时钟周期等于一个第二时钟周期，第一时钟为快时钟，第二时钟为慢时钟。
下面具体介绍上述互联矩阵中的APB总线桥。
图5为本发明实施例中的APB总线桥的接口示意图，参见图5所示，该APB总线桥的接口包括第一时钟信号(pclk_m)，第二时钟信号(pclk_s)。
该APB总线桥在第一时钟上存在以下控制信号：时钟使能信号(pclk_en)、第一时钟侧的片选信号(psel_m)、第一时钟侧的使能信号(penable_m)、第一时钟侧的读/写请求信号(pwrite_m)、第一时钟侧的准备指示信号(pready_m)；以及存在以下数据信号：第一时钟侧的地址信号(paddr_m)、第一时钟侧的写数据信号(pwdata_m)、第一时钟侧的读数据信号(prdata_m)。
在第二时钟上存在以下控制信号：第二时钟侧的片选信号(psel_s)、第二时钟侧的使能信号(penable_s)、第二时钟侧的读/写请求信号(pwrite_s)、第二时钟侧的准备指示信号(pready_s)；以及存在以下数据信号：第二时钟侧的地址信号(paddr_s)、第二时钟侧的写数据信号(pwdata_s)、第二时钟侧的读数据信号(prdata_s)。
需要说明的是，为了使APB总线能够在时钟频率比为任意整数的两个同步时转换，pclk_en可将置起时间间隔设置为N个第一时钟周期，且有效时间为1个第一时钟周期。比如，当pclk_m与pclk_s的频率比为4:1时，pclk_en、pclk_m、pclk_s三者之间的时序关系如图6所示；当pclk_m与pclk_s的频率比为1:1时，pclk_en、pclk_m、pclk_s三者之间的时序关系如图7所示。当然，pclk_en、pclk_m、pclk_s三者之间还可以存在其他时序关系，只要pclk_m与pclk_s的频率比为N，pclk_en的置起间隔为一个pclk_s周期，有效时间为一个pclk_m周期，且pclk_en置起时间较时钟pclk_s用于 采样的时钟沿早一个pclk_m周期即可，本发明实施例不做具体限定。
图8为本发明实施例中的APB总线桥内部结构示意图，参见图8所示，该APB总线桥包括：APB请求缓存模块81、APB请求输出模块82、APB响应缓存模块83及APB响应输出模块84；其中，
APB请求缓存模块81，配置为基于pclk_en，分别对输入的pwrite_m、psel_m以及penable_m在第一时钟上进行缓存，输出缓存后的第一时钟侧的APB读/写请求信号(pwrite_m_dly)、缓存后的第一时钟侧的片选信号(psel_m_dly)以及缓存后的第一时钟侧的使能信号(penable_m_dly)；
APB请求输出模块82，配置为分别对输入的pwrite_m_dly、psel_m_dly以及penable_m_dly在第二时钟上进行采样缓存，输出pwrite_s、psel_s以及penable_s，其中，pwrite_s用于指示从设备进行读/写操作；
APB响应缓存模块83，配置为对输入pready_s在第二时钟上进行缓存，输出缓存后的第二时钟侧的准备指示信号(pready_s_dly)；
APB响应输出模块84，配置为对输入的pready_s_dly在第一时钟上进行采样缓存，输出pready_m，其中，pready_m用于指示主设备完成对从设备的读/写操作。
下面对于上述各个模块进行分别介绍。
首先，介绍APB请求缓存模块。
APB请求缓存模块具有空闲态、建立态和传输态。APB请求缓存模块初始处于空闲态，且当pclk_en以及psel_m均置为第一值(比如1)时，APB请求缓存模块由空闲态进入建立态，对pwrite_m和psel_m进行缓存，输出pwrite_m_dly和psel_m_dly；在1个pclk_m周期后，APB请求缓存模块进入传输态，对penable_m进行缓存，输出penable_m_dly，直至APB响应输出模块输出的pready_m置起，结束对psel_m和penable_m的缓存，将psel_m_dly以及penable_m_dly置为第二值(比如0)，此时，APB请求缓 存模块由传输态进入空闲态。
其次，介绍APB请求输出模块。
APB请求输出模块具有空闲态、建立态、传输态以及结束态。当APB请求输出模块处于空闲态时，APB请求输出模块对pwrite_m_dly以及psel_m_dly在第二时钟上进行采样缓存，也就是对上述两个信号缓存一个第二时钟周期，获得pwrite_s和psel_s，并输出给从设备，当psel_s为第三值(比如1)时，表示从设备开始接收读/写请求，此时，APB请求输出模块进入建立态，并对penable_m_dly在第二时钟上采样，同样是对penable_m_dly缓存一个第二时钟周期，获得并输出penable_s，此时，APB请求输出模块进入传输态。在APB请求输出模块处于传输态的过程中，若输入的第二时钟侧的APB传输结束标识(s_transfer_end)置起时，结束对psel_m_dly及penable_m_dly的采样，将psel_s以及penable_s置为第四值(比如0)，同时APB请求输出模块进入结束态。
进一步地，APB请求输出模块，还配置为在s_transfer_end撤销时，进入空闲态，对psel_m_dly、pwrite_m_dly在第二时钟上进行采样。
为了保证APB总线桥处理的正确性，s_transfer_end需满足以下条件：
1、pready_m的撤销时间不晚于s_trans_end的撤销时间，即APB请求缓存模块跳转到空闲态的时间不得晚于APB请求输出模块跳转到空闲态的时间，这样就可以保证APB请求缓存模块完成一次APB传输请求传递(完成从空闲态、建立态、传输态再到空闲态的跳转)时，APB请求输出模块也只能完成一次APB传输请求的输出(完成从空闲态、建立态、传输态再到结束态的跳转)；
2、pready_m的置起时间不早于s_trans_end的置起时间，这样就可以保证APB请求缓存模块跳转到空闲态之前，APB请求输出模块已跳转到结束态，即APB请求缓存模块开始下一次APB传输请求的传递时，APB请 求输出模块已完成当次APB传输请求的输出。
在另一实施例中，上述APB总线桥还可以包括：第二时钟侧的APB传输结束标识生成模块，配置为生成s_transfer_end，以控制APB请求输出模块的逻辑状态的跳转。
需要说明的是，在实际应用中，如图9所示，当pwrite_m置为1时，表明主设备对从设备进行写请求，那么，互联矩阵在传递上述控制信号的同时还会向APB请求缓存模块传递需要写入从设备的数据信号，即第一时钟侧的地址信号(paddr_m)和第一时钟侧的写数据信号(pwdata_m)。与上述控制信号一样，APB请求缓存模块对paddr_m和pwdata_m在第一时钟上进行缓存，获得paddr_m_dly和pwdata_m_dly，并输出给APB请求输出模块；进一步地，与上述控制信号一样，APB请求输出模块对paddr_m_dly和pwdata_m_dly在第二时钟上进行采样缓存，获得paddr_s和pwdata_s，并向从设备输出，从设备接收到这些数据信号后，根据paddr_s将pwdata_s写入相应的存储单元；如图10所示，当pwrite_m置为0时，表明主设备对从设备进行读请求，那么，互联矩阵在传递上述控制信号的同时，仅传递paddr_m，以告知从设备将要读取数据的存储位置。
再次，介绍APB响应缓存模块。
APB响应缓存模块与从设备连接，能够由从设备输入pready_s，同时还与APB请求输出模块连接，能够由APB请求输出模块输入penable_s。将pready_s与penable_s进行逻辑与运算后，在第二时钟上缓存两拍，这里所说的缓存两拍，就是在第二时钟上打两拍(Re-timing)，也就是在第二时钟上延时两个第二时钟周期，获得pready_s_dly，并输出。
进一步地，APB响应缓存模块还可以对pready_s_dly在第一时钟上进行采样缓存，也就是延时一个第一时钟周期，并将采样后的信号取反与pready_s_dly做逻辑与运算，得到transfer_rsp，这里所说的transfer_rsp持 续有效时间为一个第一时钟周期。
在实际应用中，APB响应缓存模块还可以与第二时钟侧的APB传输结束标识生成模块连接，当pready_s与penable_s进行逻辑与运算之后，且在打拍之前，将与运算的结果输出给第二时钟侧的APB传输结束标识生成模块，由该模块生成上述s_transfer_end。
最后，介绍APB响应输出模块。
若transfer_rsp置起，APB响应输出模块则对输入的pready_s_dly在第一时钟上进行采样，即延时一个第一时钟周期，获得pready_m，然后，将pready_m输出给互联矩阵，以告知互联矩阵读/写操作已完成，同时，还将pready_m输出APB请求缓存模块，以控制APB请求缓存模块进入空闲态。
进一步地，在pready_m置起后的下一个第一时钟周期时，将pready_m置为第五值(比如0)。
需要说明的是，在实际应用中，如图9所示，当pwrite_m置为1时，表明主设备对从设备进行写请求，那么，从设备在将互联矩阵传递来的需要写入的数据写入以后，仅向APB响应缓存模块输入pready_s，表明写操作已完成；而如图10所示，当pwrite_m置为0时，表明主设备对从设备进行读请求，从设备除了向APB响应缓存模块输入pready_s以外，还会输入第二时钟侧的读数据信号(prdata_s)，APB响应缓存模块对prdata_s在第二时钟上缓存两拍，获得prdata_s_dly，并输出给APB响应输出模块，当transfer_rsp置起时，APB响应输出模块在第一时钟上对prdata_s_dly进行采样，获得prdata_m，输出给互联矩阵，完成读操作。
在另一实施例中，为了确保整个读/写过程的可靠性，在从设备侧还设置有用于报错的信号，即还存在第二时钟侧的错误指示信号(pslverr_s)，那么，当从设备在读/写过程中出错后，从设备向APB响应缓存模块输入pslverr_s，APB响应缓存模块在第二时钟上对该信号缓存两拍，获得 pslverr_s_dly，并输出APB响应输出模块，APB响应输出模块在transfer_rsp置起时，对该信号在第一时钟上进行采样，获得第一时钟侧的错误指示信号(pslverr_m)，并输出给互联矩阵，以向主设备报错。
从上述各个实施例可以看出，以往APB总线桥的设计注重在减少APB总线系统的访问延时、降低APB总线系统的动态功耗、或异步时钟之间的跨时钟域处理等方面，而上述APB总线桥，则注重自身内部时序路径的构造以方便在APB总线信号在同步时钟之间的转换处理的物理实现。
进一步地，由于采用了输入/输出皆打拍的方式，APB总线桥内的时序路径很短，当第一时钟和第二时钟的时钟树延迟较大时，通过调节寄存器的时钟通道和数据通道延时能够很好地实现输入输出信号的同步转换，同样降低了物理实现的难度。
下面通过具体实例来对上述APB总线桥的工作过程进行说明。
例如，上述一个或者多个实施例中所述的APB总线桥具体可以如图11所示，那么，APB请求缓存模块中包括一个逻辑与门、数据选择器MUX1、MUX2、MUX3、MUX4、MUX5以及MUX6，还包括工作在第一时钟上的寄存器Reg1、Reg2以及Reg3；APB请求输出模块中包括数据选择器MUX7、MUX8、MUX9、MUX10以及MUX11，还包括工作在第二时钟上的寄存器Reg4、Reg5以及Reg6；APB响应缓存模块包括两个逻辑与门、一个逻辑非门、工作在第二时钟上的寄存器Reg7、Reg8以及Reg9，还包括工作在第一是时钟上的寄存器Reg10；APB响应输出模块中包括数据选择器MUX12、MUX13、MUX14以及MUX15，还包括工作在第一时钟上的寄存器Reg11、Reg12以及Reg13。
其中，Reg7～9各为级联在一起的2个寄存器，实现将信号延时两个时钟周期。
那么，当第一时钟与第二时钟的频率比为4：1时，结合图12，该APB 总线桥执行读操作的过程如下：
首先，互联矩阵传递APB总线信号psel_m、penable_m、pwrite_m和paddr_m给APB请求缓存模块，其他模块(如时钟管理模块)传递pclk_en信号给APB请求缓存模块。APB请求缓存模块初始处于空闲态，当pclk_en以及psel_m置为1时，APB请求缓存模块由空闲态进入建立态，对pwrite_m和psel_m进行缓存。pclk_en和psel_m通过逻辑与门进行逻辑与运算，运算后的信号作为MUX1和MUX2的选择信号，此时，pwrite_m经MUX1输出，再经过Reg1，缓存一个第一时钟周期，获得pwrite_m_dly，并输出给MUX7；同时，psel_m依次通过MUX2、MUX3、MUX4，再经过Reg2，缓存一个第一时钟周期，获得psel_m_dly，输出给MUX8，APB请求缓存模块在进入建立态一个pclk_m周期后进入传输态。penable_m依次通过MUX5、MUX6，再经过Reg3，缓存一个第一时钟周期，获得penable_m_dly，并输出给MUX10。
然后，当APB请求输出模块自身处于空闲态时，pwrite_m_dly由MUX7输出，经过Reg4，缓存一个第二时钟周期，获得pwrite_s输出给从设备；同时，psel_m_dly由MUX8输出，再经由MUX9和Reg5，psel_m_dly延时一个第二时钟周期，获得psel_s，输出给从设备，其中，当psel_s置为1时，APB请求输出模块进入建立态；此时，penable_m_dly由MUX10输出，并依次经过MUX11和Reg6，penable_m_dly缓存一个第二时钟周期，获得penable_s，并输出给从设备。
第三步，当从设备完成读操作后，从设备置起pready_s，并经由prdata_s返回读数据，APB响应缓存模块接收pready_s和prdata_s；pready_s与上述penable_s通过一个逻辑与门进行逻辑与运算，运算后的信号分成两路，一路与运算后的信号输入第二时钟传输标识生成模块，由其生成s_transfer_end，控制MUX9、MUX11输出0，进而将psel_s、penable_s置 0，如此，APB请求输出模块进入结束态，结束对从设备的读请求；而另一路与运算后的信号输入Reg7，在第二时钟上缓存两拍，即延时两个第二时钟周期，获得pready_s_dly，pready_s_dly也分成三路信号，第一路信号输入Reg10，延时一个第一时钟周期后，经过逻辑非门后，再输入另一个逻辑与门，第二路信号直接输入逻辑与门，这两路信号进行逻辑与运算后，获得transfer_rsp，第三路信号直接输入至MUX12。在上述过程中，prdata_s经过Reg9，在第二时钟上缓存两拍，即延时两个第二时钟周期后，获得prdata_s_dly，并输出至MUX15。
第四步，transfer_resp置起时，pready_s_dly由MUX12输出，依次经过MUX13、Reg11，缓存一个第一时钟周期后，分成两路，一路信号输出至MUX4、MUX6，控制MUX4、MUX6输出0，将psel_m_dly、penable_m_dly置为0，此时，APB请求缓存模块进入空闲态；另一路信号输出给互联矩阵，以告知主设备从设备已完成读操作，准备接收相应的读数据。此时，prdata_s_dly由MUX15输出，经过Reg13，缓存一个第一时钟周期后，获得pdata_m，并输出给主设备。
另外，输入信号paddr_m到输出信号paddr_s的实现流程同pwrite_m到pwrites_s的实现流程完全一致，在此处以及下文不在赘述。prdata_s到prdata_m的各个比特转换过程完全一致，且相互独立，因此，上文没有按照读数据的位宽一一描述。
可选地，当从设备在进行读操作的过程中出错时，从设备输出pslverr_s至Reg8，在第二时钟上缓存两拍，延时两个第二时钟周期后，获得pslverr_s_dly，并输出给MUX14，在transfer_rsp置起时，pslverr_s_dly依次经过MUX14和Reg12，缓存一个第一时钟周期，获得pslverr_m，并输出给互联矩阵，以向主设备报错。
至此，当第一时钟与第二时钟的频率比为4：1时，APB总线桥执行读 操作的过程结束。
当第一时钟与第二时钟的频率比为4：1时，结合图13，该APB总线桥执行写操作的过程如下：
首先，互联矩阵传递APB总线信号psel_m、penable_m、pwrite_m、paddr_m和pwdata_m给APB请求缓存模块，其他模块(如时钟管理模块)传递pclk_en信号给APB请求缓存模块。APB请求缓存模块初始处于空闲态，当pclk_en以及psel_m置为1时，APB请求缓存模块由空闲态进入建立态，对pwrite_m和psel_m进行缓存。pclk_en和psel_m通过逻辑与门进行逻辑与运算，运算后的信号作为MUX1和MUX2的选择信号，此时，pwrite_m经MUX1输出，再经过Reg1缓存一个第一时钟周期，获得pwrite_m_dly，并输出给MUX7；psel_m经MUX2、MUX3、MUX4输出，再经过Reg2，缓存一个第一时钟周期，获得psel_m_dly，输出给MUX8。APB请求缓存模块在进入建立态一个pclk_m周期后进入传输态，penable_m依次经过MUX5、MUX6，再经过Reg3缓存一个第一时钟周期，获得penable_m_dly，并输出给MUX10。
然后，当APB请求输出模块自身处于空闲态时，pwrite_m_dly由MUX7输出，再经过Reg4缓存一个第二时钟周期，获得pwrite_s，输出给从设备；同时，psel_m_dly经由MUX8、MUX9输出，再经由Reg5缓存一个第二时钟周期，获得psel_s，输出给从设备，其中，当psel_s置为1时，APB请求输出模块进入建立态；此时，penable_m_dly经由MUX10、MUX11输出，再经过Reg6缓存一个第二时钟周期，获得penable_s，并输出给从设备，如此，从设备就能够进行写操作了。
第三步，当从设备完成写操作后，从设备置起pready_s，APB响应缓存模块接收pready_s；pready_s与上述penable_s通过一个逻辑与门进行逻辑与运算，运算后的信号分成两路，一路与运算后的信号输入第二时钟传 输标识生成模块，由其生成s_transfer_end，控制MUX9、MUX11输出0，进而将psel_s、penable_s置为0，如此，APB请求输出模块进入结束态；而另一路与运算后的信号经由寄存器组Reg7，在第二时钟上缓存两拍，获得pready_s_dly，pready_s_dly也分成三路信号，第一路信号输入Reg10，延时一个第一时钟周期后，经过逻辑非门后，再输入另一个逻辑与门，第二路信号直接输入逻辑与门，这两路信号进行逻辑与运算后，获得transfer_rsp，第三路信号直接输入至MUX12。
第四步，transfer_rsp置起后，pready_s_dly由MUX12输出，依次经过MUX13、Reg11，缓存一个第一时钟周期后，分成两路，一路信号输出至MUX4、MUX6，控制MUX4、MUX6输出0，即将psel_m_dly、penable_m_dly置为0，此时，APB请求缓存模块进入空闲态；另一路信号输出给互联矩阵，以告知主设备从设备已完成写操作。
可选地，当从设备在进行写操作的过程中出错时，从设备输出pslverr_s至Reg8，在第二时钟上缓存两拍，延时两个第二时钟周期后，获得pslverr_s_dly，并输出MUX14，在transfer_rsp置起时，pslverr_s_dly依次经过MUX14和Reg12，缓存一个第一时钟周期，获得pslverr_m，并输出给互联矩阵，以向主设备报错。
另外，从pwdata_m到pwdata_s的转换过程同从pwrite_m到pwrite_s的转换过程完全一致，此处不再赘述。
至此，当第一时钟与第二时钟的频率比为4：1时，APB总线桥执行写操作的过程结束。
在实际应用中，第一时钟与第二时钟还可以是同频时钟，即频率比为1：1，此时，APB总线桥的读/写时序参见图14及图15所示，在此就不再一一赘述了。
由上述可知，由于本发明实施例所提供的APB总线桥中创新性地引入 了pclk_en信号，使得从APB请求缓存模块到APB请求输出模块的reg2reg(寄存器到寄存器)路径，可以设为多周期路径，周期数为快慢时钟频率之间的倍数关系。
特别地，在芯片物理实现时，若互联矩阵与从设备摆放位置比较近时，APB请求缓存模块到APB请求输出模块的reg2reg路径的数据端延迟较小，此时便没有必要设置多周期路径，此时可将APB总线桥的输入信号pclk_en接常值1，进而，APB请求缓存模块到APB请求输出模块之间的reg2reg路径的路径长度为一个第一时钟周期。当pclk_m，pclk_s的时钟树时延(Clock Tree Latency)差异相对比较大时，调节APB请求缓存模块到APB请求输出模块之间存在时序路径的2个寄存器的时钟端和数据端的延迟，即可方便实现信号同步转换。
另外，由于从APB从设备输入的信号，在APB响应缓存模块内均打了两拍，当pclk_m，pclk_s的时钟树时延差异较大时，由于这两拍寄存器之间的数据端延迟较小，将第2拍寄存器的时钟端与第一时钟侧的寄存器的时钟端做好平衡(blance)，调节这2拍寄存器之间的数据通道延迟也可方便实现响应信号的同步处理。
进一步地，本发明实施例中的APB总线桥不改变APB总线桥的功能，不影响其协议的有效性和一致性，总线接口时序完全符合APB总线协议标准，通过输入/输出皆打拍将多周期路径约束在APB总线桥内，这样，方便后端设计实现。
进一步地，本发明实施例中的APB总线桥即支持APB总线在满足整数倍频关系的快慢时钟之间的信号转换，也支持同频时钟之间或者相同时钟上的信号转换。
进一步地，在芯片设计过程中，芯片总线使用的快慢时钟频率比变化时，芯片互联矩阵(包括本发明实施例中所述的APB总线桥)的设计不需 要改变，可自然适应这种变化。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

  1. 一种外围总线APB总线桥，所述APB总线桥设置在互联矩阵与从设备之间，主设备能够通过所述互联矩阵上的工作在第一时钟的APB接口经由所述APB总线桥对工作在第二时钟上的所述从设备进行读/写操作，所述第一时钟与所述第二时钟为同步时钟，且频率比为N，N为正整数；
    所述APB总线桥包括：APB请求缓存模块、APB请求输出模块、APB响应缓存模块及APB响应输出模块；其中，
    所述APB请求缓存模块，配置为基于时钟使能信号，分别对输入的第一时钟侧的APB读/写请求信号、第一时钟侧的片选信号及第一时钟侧的使能信号在第一时钟上进行缓存，输出缓存后的第一时钟侧的APB读/写请求信号、缓存后的第一时钟侧的片选信号及缓存后的第一时钟侧的使能信号，其中，所述第一时钟侧的APB读/写请求信号、所述第一时钟侧的片选信号及所述第一时钟侧的使能信号是由所述互联矩阵传递过来的，所述时钟使能信号的置起间隔为N个第一时钟周期，且有效时间为一个第一时钟周期，用于控制所述APB请求缓存模块与所述APB请求输出模块之间的寄存器到寄存器的时序路径长度保持为一个第二时钟周期；
    所述APB请求输出模块，配置为分别对输入的所述缓存后的第一时钟侧的APB读/写请求信号、所述缓存后的第一时钟侧的片选信号及所述缓存后的第一时钟侧的使能信号在第二时钟上进行缓存，输出第二时钟侧的APB读/写请求信号、第二时钟侧的片选信号及第二时钟侧的使能信号，其中，所述第二时钟侧的APB读/写请求信号用于指示所述从设备进行读/写操作；
    所述APB响应缓存模块，配置为对输入的第二时钟侧的准备指示信号在所述第二时钟上进行缓存，输出缓存后的第二时钟侧的准备指示信号；
    所述APB响应输出模块，配置为对输入的所述缓存后的第二时钟侧的 准备指示信号在所述第一时钟上进行缓存，输出第一时钟侧的准备指示信号，其中，所述第一时钟侧的准备指示信号用于指示所述主设备完成对所述从设备的读/写操作。
  2. 根据权利要求1所述的APB总线桥，其中，所述APB请求缓存模块具有空闲态，建立态和传输态；
    所述APB请求缓存模块，配置为在自身处于所述空闲态，且所述时钟使能信号及所述第一时钟侧的片选信号均置为第一值时，由所述空闲态进入所述建立态，对所述第一时钟侧的片选信号及所述第一时钟侧的读/写请求信号进行缓存，输出所述缓存后的第一时钟侧的片选信号及所述缓存后的第一时钟侧的APB读/写请求信号；在一个第一时钟周期后，进入所述传输态，对所述第一时钟侧的使能信号进行缓存，输出所述缓存后的第一时钟侧的使能信号，直至所述APB响应输出模块输出的所述第一时钟侧准备指示信号置起，将所述缓存后的第一时钟侧的片选信号及所述缓存后的第一时钟侧的使能信号置为第二值，由所述传输态进入所述空闲态。
  3. 根据权利要求1所述的APB总线桥，其中，所述APB请求输出模块具有空闲态、建立态、传输态及结束态；
    所述APB请求输出模块，配置为在自身处于所述空闲态时，对所述缓存后的第一时钟侧的APB读/写请求信号及所述缓存后的第一时钟侧的片选信号在所述第二时钟上进行采样缓存，获得所述第二时钟侧的片选信号及所述第二时钟侧的APB读/写请求信号，并将所述第二时钟侧的片选信号及APB读/写请求信号输出给所述从设备；当所述第二时钟侧的片选信号置第三值时，进入所述建立态，对所述缓存后的第一时钟侧的使能信号在所述第二时钟上采样缓存，获得所述第二时钟侧的使能信号，并进入所述传输态；当第二时钟侧的APB传输结束标识置起时，将所述第二时钟侧的片选信号及所述第二时钟侧的使能信号置为第四值，进入所述结束态。
  4. 根据权利要求3所述的APB总线桥，其中，所述APB请求输出模块，还配置为在所述第二时钟侧的APB传输结束标识撤销时，进入所述空闲态，对所述缓存后的第一时钟侧的APB读/写请求信号、所述缓存后的第一时钟侧的片选信号在所述第二时钟上进行采样缓存。
  5. 根据权利要求3或4所述的APB总线桥，其中，所述APB总线桥还包括：第二时钟侧的APB传输结束标识生成模块，配置为生成所述第二时钟侧的APB传输结束标识，以控制所述APB请求输出模块的逻辑状态的跳转。
  6. 根据权利要求1所述的APB总线桥，其中，所述APB响应缓存模块，配置为将所述从设备输入的将所述第二时钟侧的准备指示信号与所述第二时钟侧的使能信号进行逻辑运算后在所述第二时钟上缓存两拍，获得并输出所述缓存后的第二时钟侧准备指示信号。
  7. 根据权利要求6所述的APB总线桥，其中，所述APB响应缓存模块，还配置为对所述缓存后的第二时钟侧准备指示信号在所述第一时钟上进行采样，并将采样后的信号取反与所述缓存后的第二时钟侧准备指示信号做逻辑与运算，得到第一时钟上的APB传输响应标识，其中，所述第一时钟上的APB传输响应标识持续有效时间为一个第一时钟周期。
  8. 根据权利要求1所述的APB总线桥，其中，所述APB响应输出模块，配置为当第一时钟上的APB传输响应标识置起时，对输入的所述缓存后的第二时钟侧准备指示信号在所述第一时钟上进行采样，获得并输出所述第一时钟侧的准备指示信号。
  9. 根据权利要求8所述的APB总线桥，其中，所述APB响应输出模块，还配置为在所述第一时钟侧的准备指示信号置起后的下一个第一时钟周期时，将所述第一时钟侧的准备指示信号置为第五值。
  10. 根据权利要求1所述的APB总线桥，其中，所述APB响应缓存模 块，还配置为对输入的第二时钟侧的错误指示信号在所述第二时钟上缓存两拍，获得并输出缓存后的第二时钟侧的错误指示信号；
    所述APB响应输出模块，还配置为当第一时钟上的APB传输响应标识置起时，对所述缓存后的第二时钟侧的错误指示信号在所述第一时钟上采样，获得并输出第一时钟侧的错误指示信号。
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