WO2015117524A1 - 一种时钟树实现方法、系统芯片及计算机存储介质 - Google Patents

一种时钟树实现方法、系统芯片及计算机存储介质 Download PDF

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WO2015117524A1
WO2015117524A1 PCT/CN2014/095001 CN2014095001W WO2015117524A1 WO 2015117524 A1 WO2015117524 A1 WO 2015117524A1 CN 2014095001 W CN2014095001 W CN 2014095001W WO 2015117524 A1 WO2015117524 A1 WO 2015117524A1
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Prior art keywords
bus
bridge
configuration
protocol
frequency
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PCT/CN2014/095001
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English (en)
French (fr)
Inventor
张庆
李剑
刘贵生
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深圳市中兴微电子技术有限公司
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Priority to US15/328,219 priority Critical patent/US20170212861A1/en
Priority to JP2017503136A priority patent/JP2017523518A/ja
Priority to KR1020177003932A priority patent/KR20170030620A/ko
Priority to EP14881692.9A priority patent/EP3173895B1/en
Publication of WO2015117524A1 publication Critical patent/WO2015117524A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package

Definitions

  • the present invention relates to the field of system-on-chip (SoC) design, and in particular, to a clock tree implementation method, a system chip, and a computer storage medium.
  • SoC system-on-chip
  • system chip design is the core technology for the development of the communication industry.
  • the system chip design needs to consider the requirements of performance, power, time-to-market, and area, namely the PPTA standard.
  • the generation of the Clock Tree has an important influence on the above factors, especially when the frequency of the system chip is high and the area is large, these effects may be decisive.
  • the SoC uses Advanced Microcontroller Bus Architecture 3.0 (AMBA 3.0), that is, the data bus mainly uses the Advanced eXtensible Interface (AXI) bus, and the configuration bus is an advanced high-performance bus ( Advanced High Performance Bus (AHB) or Advanced Peripheral Bus (APB).
  • AMBA 3.0 Advanced Microcontroller Bus Architecture 3.0
  • AXI Advanced eXtensible Interface
  • AXI Advanced High Performance Bus
  • API Advanced Peripheral Bus
  • a core module is separately provided, including a matrix, a bus bridge, and a frequency divider (ie, a clock generating unit (Top CRM Unit)).
  • the data bus uses the AXI bus, the frequency is higher; the configuration bus uses the AHB/APB bus, the frequency is lower; and the AHB/APB bus passes the AXI bus to the AXI-to-AHB or AXI-to-APB.
  • Conversion bridge implementation Inside the core module, multiple configuration buses are generated through a plurality of similar conversion bridges, and are respectively connected to the configuration bus of other external modules of the system chip. At the same time, multiple data buses of the core module are also connected to the data buses of other external modules.
  • the interconnect matrix in the core module is connected to two external modules through two AXI-to-APB conversion bridges.
  • the bus conversion bridge can adopt a synchronous bridge, that is, the APB bus frequency is obtained by frequency division of the AXI bus frequency, as shown in FIG. 2, the interconnection matrix in the core module passes through a 1-to-2.
  • the AXI-to-APB conversion bridge is connected to two external modules.
  • each IP function module is also synchronized; from the logic design point of view, all the buses in the entire system chip are logically synchronized, as shown in FIG. Thus, from a physical implementation point of view, this requires the clock tree to achieve full chip synchronization.
  • the interface circuit may be in the same clock domain or across the clock domain, on the other hand, for the same clock domain interface circuit (p3).
  • the configuration bus of each IP function module is required. If they are not distinguished from each other, they will all work under the same APB clock.
  • the cross-clock interface circuit (p2) the back-end physical design is still implemented synchronously. The way is to converge under the same AXI clock.
  • the system bus of the entire system chip will perform timing closure under the high frequency AXI clock, which includes the data bus and the configuration bus.
  • an asynchronous bridge can be used instead of the synchronous bridge to implement conversion between different protocol buses, as shown in FIG.
  • asynchronous bridges introduces different side logic And physical design issues, such as complex synthesis and static timing analysis (Static Timing Analysis) problems; and the area and power consumption of the conversion bridge will increase accordingly.
  • the embodiment of the invention provides a clock tree implementation method, a system chip and a computer storage medium, which can realize global asynchronous and local synchronization of the configuration bus while maintaining global synchronization of the data bus, thereby achieving PPTA optimization of the system chip design.
  • An embodiment of the present invention provides a clock tree implementation method, which is applied to a system chip including a core module and an external connection module; the interconnection matrix in the core module passes through a bus conversion bridge including a protocol bridge and a down bridge, and the outer Connected to the module; the method includes:
  • the frequency of the first configuration bus is the protocol bridge frequency
  • the first configuration bus is converted into a second configuration bus by a down bridge; the frequency of the second configuration bus is a configuration bus frequency of the external module.
  • the protocol bridge adopts a single-level protocol bridge; when there are N external connection modules, the protocol bridge includes N single-level protocol bridges of the same frequency;
  • Converting the data bus to the first configuration bus through the protocol bridge includes:
  • the N data bus is respectively converted into N first configuration buses by N single-stage protocol bridges of the same frequency; wherein N is a positive integer greater than or equal to 2.
  • the protocol bridge adopts an N-level protocol bridge; when the number of external modules is N, the N-level protocol bridge is composed of a single-level protocol bridge and a 1-to-N conversion bridge;
  • Converting the data bus to the first configuration bus through the protocol bridge includes:
  • the one-way data bus is converted into a first configuration bus by a single-stage protocol bridge; and the first configuration bus is synchronously divided into N first configuration buses by a 1-to-N conversion bridge.
  • the protocol bridge is a synchronous bridge.
  • the data bus is an AXI bus; the first configuration bus and the second configuration bus are both an AHB bus or an APB bus.
  • An embodiment of the present invention further provides a system chip, where the system chip includes a core module and an external connection module, where the core module includes a frequency divider, an interconnection matrix, and a bus conversion bridge, and the interconnection matrix passes through the bus conversion bridge and The external connection module is connected, and the bus conversion bridge is composed of a protocol bridge and a frequency reduction bridge; wherein
  • the protocol bridge is configured to convert the data bus into a first configuration bus; the frequency of the first configuration bus is the protocol bridge frequency;
  • the down-conversion bridge is configured to convert the first configuration bus into a second configuration bus; the frequency of the second configuration bus is a configuration bus frequency of the external connection module.
  • the protocol bridge adopts a single-level protocol bridge; when there are N external connection modules, the protocol bridge includes N single-level protocol bridges of the same frequency;
  • the N single-stage protocol bridges of the same frequency are configured to respectively convert N data buses into N first configuration buses.
  • the protocol bridge adopts an N-level protocol bridge; when the number of external modules is N, the N-level protocol bridge is composed of a single-level protocol bridge and a 1-to-N conversion bridge; ,
  • the single-stage protocol bridge is configured to convert one data bus into one first configuration bus
  • the 1-to-N conversion bridge is configured to synchronously divide one first configuration bus into N first configuration buses.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the clock tree implementation method according to the embodiment of the invention.
  • the clock tree implementation method, the system chip and the computer storage medium provided by the embodiment of the present invention convert the data bus into a first configuration bus through a protocol bridge; the frequency of the first configuration bus is the protocol bridge frequency; The bridge converts the first configuration bus to the second configuration bus; The frequency of the second configuration bus is the configured bus frequency of the external module.
  • the global asynchronous and local synchronization of the configuration bus can be realized while maintaining the global synchronization of the data bus, thereby achieving the PPTA optimization of the system chip design, thereby improving the design flexibility and the competitiveness of the system chip.
  • 1 is a system chip architecture diagram with two conversion bridges in the related art
  • FIG. 2 is a system chip architecture diagram of a related art having a 1-to-2 conversion bridge
  • FIG. 3 is a schematic diagram of a chip clock structure in which the clock is fully synchronized in the related art
  • FIG. 4 is a main timing path diagram of a system chip architecture as shown in FIG. 1 or FIG. 2 in the related art;
  • FIG. 5 is a schematic diagram of a chip clock structure in which the data bus is fully synchronized in the related art, and the bus is asynchronous;
  • FIG. 6 is a schematic flowchart of an implementation process of a clock tree implementation method according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a system chip according to an embodiment of the present invention.
  • protocol bridge 8 is a system chip architecture diagram when the protocol bridge is a single-level protocol bridge and the external connection module is two according to an embodiment of the present invention
  • FIG. 9 is a schematic diagram of a system chip architecture when the protocol bridge is a two-level protocol bridge and the external modules are two according to an embodiment of the present disclosure
  • FIG. 10 is a main timing path diagram 1 of the system chip architecture shown in FIG. 8 or FIG. 9 according to an embodiment of the present invention
  • FIG. 11 is a second timing diagram of the system chip architecture shown in FIG. 8 or FIG. 9 according to an embodiment of the present invention.
  • the system chip includes a core module and an external module, and the core module
  • the interconnect matrix in the block is connected to the external module through a bus conversion bridge.
  • the bus conversion bridge is composed of a protocol bridge and a down bridge; when the bus conversion bridge implements bus frequency conversion, the data bus is first converted into the first configuration bus through the protocol bridge.
  • the frequency of the first configuration bus is the protocol bridge frequency; the first configuration bus is converted into a second configuration bus by a down bridge; the frequency of the second configuration bus is a configuration bus of the external module frequency.
  • the protocol bridge is a synchronous bridge.
  • the system chip can adopt the advanced microcontroller bus architecture AMBA3.0, that is, the data bus mainly adopts the AXI bus, and the first configuration bus and the second configuration bus are both the AHB bus or the APB bus.
  • FIG. 6 is a schematic flowchart of an implementation process of a clock tree implementation method according to an embodiment of the present invention, which is applied to a system chip including a core module and an external connection module; and the interconnection matrix in the core module passes through a bus conversion bridge including a protocol bridge and a down bridge.
  • the method for implementing the clock tree in the embodiment of the present invention includes:
  • Step S100 Convert the data bus into a first configuration bus by using a protocol bridge, and the frequency of the first configuration bus is the protocol bridge frequency;
  • the protocol bridge may adopt a single-level protocol bridge or an N-level protocol bridge; where N is a positive integer greater than or equal to 2.
  • the protocol bridge When the protocol bridge adopts a single-level protocol bridge and assumes that there are N external connection modules, the protocol bridge includes N single-level protocol bridges of the same frequency. As shown in FIG. 8, N is equal to 2, and the protocol bridge includes Two single-stage protocol bridges of the same frequency; converting the data bus to the first configuration bus through the protocol bridge includes: converting N data busses into N first configuration buses by N single-stage protocol bridges of the same frequency .
  • the N-level protocol bridge is composed of a single-level protocol bridge and a 1-to-N conversion bridge, as shown in FIG. Equal to 2,
  • the N-level protocol bridge includes a single-level protocol bridge and a 1-to-2 conversion bridge;
  • the converting the data bus to the first configuration bus through the protocol bridge includes: converting one data bus to a single-level protocol bridge
  • the first configuration bus is connected all the way; the first configuration bus is synchronously divided into the N first configuration bus by the 1-to-N conversion bridge.
  • Step S101 Converting the first configuration bus into a second configuration bus by using a down bridge; the frequency of the second configuration bus is a configuration bus frequency of the external module.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the clock tree implementation method according to the embodiment of the invention.
  • FIG. 7 is a schematic structural diagram of a system chip according to an embodiment of the present invention.
  • the system chip of the embodiment of the present invention includes a core module 10 and an external module 20, and the core module 10 includes a frequency divider 13 and an interconnection matrix 12
  • the bus conversion bridge 11, the interconnection matrix 12 is connected to each of the external modules 20 through the bus conversion bridge 11, and the bus conversion bridge 11 is composed of a protocol bridge 111 and one or more down-conversion bridges 112;
  • the protocol bridge 111 is configured to convert the data bus into a first configuration bus; the frequency of the first configuration bus is the protocol bridge frequency;
  • the protocol bridge 111 may be composed of more than one single-level protocol bridge, and the single-level protocol bridge corresponds to the down-conversion bridge 112; the protocol bridge may also be a single-level protocol bridge and a 1-to -N conversion bridge, the output port of the conversion bridge is in one-to-one correspondence with the down-conversion bridge 112;
  • the down bridge 112 is configured to convert the first configuration bus into a second configuration bus; the frequency of the second configuration bus is a configuration bus frequency of the external module.
  • the protocol bridge 111 when the protocol bridge 111 adopts a single-level protocol bridge and the number of external modules is N, the protocol bridge 111 includes N single-level protocol bridges of the same frequency; the N single-level protocol bridges of the same frequency respectively
  • the N data bus is converted into an N first configuration bus; wherein N is a positive integer greater than or equal to 2.
  • FIG. 8 shows a system chip architecture in which the protocol bridge 111 adopts a single-level protocol bridge and the external connection module is two according to an embodiment of the present invention, and the data bus is an AXI bus, and the first configuration bus is used.
  • the second configuration bus is an APB bus.
  • two AXI buses are respectively converted into two first APB buses through two single-stage protocol bridges of the same frequency, so that the two first APB bus frequencies are protocol bridge frequencies;
  • the first APB bus is converted to the second APB bus by the down bridge; the frequency of the second APB bus is the configured bus frequency of the external module.
  • the global asynchronous and local synchronization of the configuration bus can be realized while maintaining the global synchronization of the data bus, thereby achieving the PPTA optimization desired by the system chip design.
  • the protocol bridge 111 adopts an N-level protocol bridge and the number of external modules is N
  • the N-level protocol bridge is composed of a single-level protocol bridge and a 1-to-N conversion bridge
  • the single-stage protocol bridge is configured to convert one data bus into one first configuration bus
  • the 1-to-N conversion bridge is configured to synchronously divide one first configuration bus into N first configuration buses; wherein N is a positive integer greater than or equal to 2.
  • FIG. 9 shows a system chip architecture when the protocol bridge 111 is a two-level protocol bridge and two external modules are two, and the data bus is an AXI bus, and the first configuration bus is shown in FIG.
  • the second configuration bus is an APB bus.
  • the protocol bridge 111 is composed of a single-level protocol bridge and a 1-to-2 conversion bridge. In the interconnection matrix, one AXI bus is converted into one first APB bus through a single-stage protocol bridge; then one first APB bus is synchronously divided into two first APB buses through a 1-to-2 conversion bridge.
  • the frequency of the two first APB buses is the protocol bridge frequency; further, the first APB bus is converted into the second APB bus by the down bridge; the frequency of the second APB bus is the configuration of the external module Bus frequency.
  • FIG. 10 is a main timing path diagram of the system chip architecture shown in FIG. 8 or FIG. 9 according to an embodiment of the present invention.
  • the data bus (AXI bus) of the entire system chip is still globally synchronized, and therefore,
  • the global synchronous register (FF) is relatively large, and the position is dispersed in the range of the whole chip, so that the AXI clock delay Laxi is large;
  • the configuration bus of each down-conversion bridge and the external module (such as the APB bus) Maintaining a synchronization relationship respectively, thereby forming a plurality of locally synchronized APB buses;
  • each buffer TapbN is followed by a separate APB synchronization bus.
  • a local synchronous bus apbN the number of registers requiring local synchronization is small and the position is relatively local and concentrated.
  • the delay LapbN of the local synchronous bus apbN is small, namely: Laxi>Lapb1; wherein, N is from 1 The number of abb clock domains to use.
  • the local synchronous clock domain abp1 is taken as an example to briefly describe how the core module's main timing path implements timing adjustment.
  • the bus write operation in the core block includes the conversion of the protocol and the down-clocking of the clock, such as the timing path p1 shown in FIG. 10, which is a cross-clock path from AXI to APB.
  • the timing path p1 although the multi-cycle path can be used to weaken the relevant timing constraints, since the logic of this part of the bus protocol is simple, and the physical position of the back-end implementation is relatively concentrated, the timing is relatively easy to satisfy, so it is still in a single cycle. (AXI clock cycle) path to constrain.
  • timing constraints of the timing path p1 are as follows:
  • Laxi+Dck-q+Dp1+Dsetup ⁇ Paxi+Lapb1 is required; and for the timing of the hold time, Laxi+Dck-q+Dp1>Lapb1+Dhold is required;
  • Laxi represents AXI clock delay (latency of AXI clock);
  • Lapb1 represents APB1 clock delay (latency of APB1clock);
  • Dck-q represents delay of pin CK to pin Q of Flip Flop;
  • Dp1 represents path 1 combination delay of path of Path1;
  • Dsetup means set time of Flip Flop;
  • Dhold means hold time of Flip Flop;
  • Paxi means AXI clock period (period of AXI clock) .
  • the clock corresponding to the abb1 clock terminal can be pushed back at the point 1 position shown in FIG. 10, specifically, the register clock terminal delay at the point 1 is increased, that is, the buffer T1 is added to implement the timing. Adjustment. If the adjustment level is insufficient to meet the timing, the main timing path shown in Figure 11 can be used, and further similar adjustments can be made at point 3 until all timing paths of the write operation meet the requirements.
  • timing paths p2 and p3 shown in FIG. 10 in the local clock domain ab1. Since the timing paths p2 and p3 are both in the same clock domain, and the clock frequency of the local clock domain ab1 is lower than the AXI clock frequency, that is, the AXI clock frequency is divided by two or less, as long as the clock tree is balanced, The timing of the timing paths p2 and p3 is easily converged.
  • timing path p4 of Figure 10.
  • Lapb1+Dck-q+Dp4+Dsetup ⁇ Paxi+Laxi is required; and for the timing of the hold time, Lapb1+Dck-q+Dp4>Laxi+Dhold is required. Therefore, if a timing violation occurs, the dynamic adjustment can be made at the position of the point 2, specifically, the delay of the register clock terminal at the point 2 is reduced, that is, the clock of the apb1 clock terminal is appropriately shortened, that is, the buffer T2 is reduced; Timing, you can use the main timing path shown in Figure 11, and continue to make similar adjustments at points 4 and 5 until reading All timing paths for operation meet the requirements.
  • the clock tree implementation method and apparatus can realize the clock tree synthesis independently of each configuration bus while maintaining the synchronous logic design as compared with the existing conventional design method;
  • the bus is independently integrated by the clock tree, so that the number of registers and the localization of the physical placement area can effectively reduce the clock tree delay, resulting in power consumption and area reduction, congestion reduction, and the global asynchronous effect of the configuration bus, effectively saving the bus.
  • the area and power consumption of the clock tree improves the controllability of the physical implementation of the back end and also shortens the design cycle.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • the embodiment of the present invention converts the data bus into a first configuration bus by using a protocol bridge; the frequency of the first configuration bus is the protocol bridge frequency; and converting the first configuration bus to the second configuration bus by using a down bridge; The frequency of the second configuration bus is the configured bus frequency of the external module.

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Abstract

一种时钟树实现方法、系统芯片及计算机存储介质，应用于包括核心模块（10）和外连模块（20）的系统芯片中；所述核心模块（10）中的互联矩阵（12）通过包括协议桥（111）和降频桥（112）的总线转换桥（11）与所述外连模块（20）连接；通过协议桥（111）将数据总线转换为第一配置总线（S100）；所述第一配置总线的频率为所述协议桥频率；再通过降频桥（112）将第一配置总线转换为第二配置总线（S101）；所述第二配置总线的频率为所述外连模块的配置总线频率。

Description

一种时钟树实现方法、系统芯片及计算机存储介质 技术领域
本发明涉及系统芯片(System-on-Chip，SoC)设计领域，尤其涉及一种时钟树实现方法、系统芯片及计算机存储介质。
背景技术
目前，系统芯片设计是通讯产业发展的核心技术。系统芯片设计需要同时考虑性能(Performance)、功耗(Power)、设计周期(Time-to-Market)、以及面积(Area)等因素的要求，即PPTA标准。而在系统芯片设计中，时钟树(Clock Tree)的生成对上述因素有着重要的影响，尤其当系统芯片的频率很高且面积很大时，这些影响可能是决定性的。
相关技术中，以物理易实现性为基础进行模块的划分。SoC采用先进微控制器总线架构(Advanced Microcontroller Bus Architecture3.0，AMBA3.0)，即：数据总线主要采用先进可扩展接口(Advanced eXtensible Interface，AXI)总线，而配置总线为先进的高性能总线(Advanced High performance Bus，AHB)或先进的外围总线(Advanced Peripheral Bus，APB)。
具体地，在系统芯片中，单独设置一个核心模块，包括互联矩阵(Matrix)、总线转换桥(Bridge)、以及分频器(即时钟产生单元(Top CRM Unit))等。在互联矩阵中，数据总线采用AXI总线，其频率较高；配置总线则采用AHB/APB总线，其频率较低；且AHB/APB总线由AXI总线通过AXI-to-AHB或AXI-to-APB转换桥实现。在核心模块内部，通过多个类似的转换桥会产生多个配置总线，并分别与系统芯片的其它外连模块的配置总线同步相连。同时，核心模块的多个数据总线也分别与其它外连模块的数据总线相连。
如图1所示，核心模块中的互联矩阵通过两个AXI-to-APB转换桥分别与两个外连模块相连。进一步地，为了简化逻辑设计，总线转换桥可采用同步桥，即：APB总线频率由AXI总线频率同步分频而得，如图2所示，核心模块中的互联矩阵通过一个1-to-2的AXI-to-APB转换桥与两外连模块相连。这样，从互联矩阵的角度看，所有与之相连的总线都是同步的，即：与核心模块相连接的各个知识产权(Intellectual Property，IP)功能模块的数据总线与配置总线都是同步的，各个IP功能模块的数据总线和配置总线之间也是同步的；从逻辑设计来看，整个系统芯片中的所有总线在逻辑上都是同步的，如图3所示。如此，从物理实现的角度看，这就要求时钟树要达到全芯片同步。
然而，当系统芯片频率增高，面积变大后，这种设计对后端物理实现的挑战非常大，不但导致整个时钟树所需面积及功耗变大，而且使得设计周期延长。以图1或图2所表示的系统芯片架构的主要时序路径为例，如图4所示，接口电路可以是同时钟域或跨时钟域的，一方面，对于同时钟域接口电路(p3)，各IP功能模块的配置总线都需要，若彼此不加区分，则它们都将工作在相同的APB时钟下；另一方面，对于跨时钟接口电路(p2)，后端物理设计仍采用同步实现方式，即在同一AXI时钟下收敛。因而，整个系统芯片的系统总线都将在高频AXI时钟下进行时序收敛，这里所说系统总线包括数据总线和配置总线。
当寄存器数量过多，且物理位置分布比较零散时，时钟树延迟(latency)会很大；相应地，芯片波动(On Chip Variation，OCV)影响变大、功耗变大、拥塞(congestion)也变大；若再加上接口电路任由工具自由放置，则会带来进一步的时序收敛问题。
为了解决上述问题，可以采用异步桥代替同步桥来实现不同协议总线之间的转换，如图5所示。然而，异步桥的使用又引入了不同侧面的逻辑 和物理设计问题，如复杂的综合(Synthesis)和静态时序分析(Static Timing Analysis)问题；并且，转换桥的面积和功耗也会相应增加。
发明内容
本发明实施例提供一种时钟树实现方法、系统芯片及计算机存储介质，能够在维持数据总线全局同步的同时，实现配置总线的全局异步和局部同步，从而达到系统芯片设计的PPTA最优化。
本发明实施例的技术方案是这样实现的：
本发明实施例提供一种时钟树实现方法，应用于包括核心模块和外连模块的系统芯片中；所述核心模块中的互联矩阵通过包括协议桥和降频桥的总线转换桥与所述外连模块连接；所述方法包括：
通过协议桥将数据总线转换为第一配置总线；所述第一配置总线的频率为所述协议桥频率；
通过降频桥将第一配置总线转换为第二配置总线；所述第二配置总线的频率为所述外连模块的配置总线频率。
在一实施例中，所述协议桥采用单级协议桥；当外连模块为N个时，所述协议桥包括N个相同频率的单级协议桥；
所述通过协议桥将数据总线转换为第一配置总线包括：
通过N个相同频率的单级协议桥分别将N路数据总线转换为N路第一配置总线；其中，N为大于等于2的正整数。
在一实施例中，所述协议桥采用N级协议桥；当外连模块为N个时，所述N级协议桥由一个单级协议桥和一个1-to-N的转换桥组成；
所述通过协议桥将数据总线转换为第一配置总线包括：
通过单级协议桥将一路数据总线转换为一路第一配置总线；再通过1-to-N的转换桥将一路第一配置总线同步分为N路第一配置总线。
在一实施例中，所述协议桥为同步桥。
在一实施例中，所述数据总线为AXI总线；所述第一配置总线、第二配置总线均为AHB总线或APB总线。
本发明实施例还提供一种系统芯片，所述系统芯片包括核心模块和外连模块，所述核心模块包括分频器、互联矩阵和总线转换桥，所述互联矩阵通过所述总线转换桥与所述外连模块相连，所述总线转换桥由协议桥和降频桥组成；其中，
所述协议桥，配置为将数据总线转换为第一配置总线；所述第一配置总线的频率为所述协议桥频率；
所述降频桥，配置为将第一配置总线转换为第二配置总线；所述第二配置总线的频率为所述外连模块的配置总线频率。
在一实施例中，所述协议桥采用单级协议桥；当外连模块为N个时，所述协议桥包括N个相同频率的单级协议桥；
所述N个相同频率的单级协议桥，配置为分别将N路数据总线转换为N路第一配置总线。
在一实施例中，所述协议桥采用N级协议桥；当外连模块为N个时，所述N级协议桥由一个单级协议桥和一个1-to-N的转换桥组成；其中，
所述单级协议桥，配置为将一路数据总线转换为一路第一配置总线；
所述1-to-N的转换桥，配置为将一路第一配置总线同步分为N路第一配置总线。
本发明实施例还提供一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行本发明实施例所述的时钟树实现方法。
本发明实施例所提供的时钟树实现方法、系统芯片及计算机存储介质，通过协议桥将数据总线转换为第一配置总线；所述第一配置总线的频率为所述协议桥频率；通过降频桥将第一配置总线转换为第二配置总线；所述 第二配置总线的频率为所述外连模块的配置总线频率。如此，能够在维持数据总线全局同步的同时，实现配置总线的全局异步和局部同步，从而达到系统芯片设计的PPTA最优化，进而提高系统芯片的设计灵活性和实现竞争力。
附图说明
图1为相关技术中具有两个转换桥的系统芯片架构图；
图2为相关技术中具有一个1-to-2转换桥的系统芯片架构图；
图3为相关技术中时钟全同步的芯片时钟结构示意图；
图4为相关技术中如图1或图2所示的系统芯片架构的主要时序路径图；
图5为相关技术中数据总线全同步，且配置总线异步的芯片时钟结构示意图；
图6为本发明实施例时钟树实现方法的实现流程示意图；
图7为本发明实施例系统芯片的组成结构示意图；
图8为本发明实施例所述协议桥为单级协议桥且外连模块为两个时的系统芯片架构图；
图9为本发明实施例所述协议桥为两级协议桥且外连模块为两个时的系统芯片架构图；
图10为本发明实施例中如图8或图9所示的系统芯片架构的主要时序路径图一；
图11为本发明实施例中如图8或图9所示的系统芯片架构的主要时序路径图二。
具体实施方式
在本发明实施例中，系统芯片包括核心模块和外连模块，所述核心模 块中的互联矩阵通过总线转换桥连接外连模块，所述总线转换桥由协议桥和降频桥组成；总线转换桥实现总线频率转换时，先通过协议桥将数据总线转换为第一配置总线；所述第一配置总线的频率为所述协议桥频率；再通过降频桥将第一配置总线转换为第二配置总线；所述第二配置总线的频率为所述外连模块的配置总线频率。
这里，所述协议桥为同步桥。
需要说明的是，系统芯片可以采用先进微控制器总线架构AMBA3.0，即：所述数据总线主要采用AXI总线，而第一配置总线和第二配置总线均为AHB总线或APB总线。
下面结合附图及具体实施例对本发明再作进一步详细的说明。
图6为本发明实施例时钟树实现方法的实现流程示意图，应用于包括核心模块和外连模块的系统芯片中；所述核心模块中的互联矩阵通过包括协议桥和降频桥的总线转换桥与所述外连模块连接；如图6所示，本发明实施例时钟树实现方法包括：
步骤S100：通过协议桥将数据总线转换为第一配置总线，所述第一配置总线的频率为所述协议桥频率；
这里，所述协议桥可以采用单级协议桥，也可以采用N级协议桥；其中，N为大于等于2的正整数。
当所述协议桥采用单级协议桥且假设外连模块为N个时，所述协议桥包括N个相同频率的单级协议桥，如图8所示，N等于2，所述协议桥包括两个相同频率的单级协议桥；所述通过协议桥将数据总线转换为第一配置总线包括：通过N个相同频率的单级协议桥分别将N路数据总线转换为N路第一配置总线。
当所述协议桥采用N级协议桥且假设外连模块为N个时，所述N级协议桥由一个单级协议桥和一个1-to-N转换桥组成，如图9所示，N等于2， 所述N级协议桥包括一个单级协议桥和一个1-to-2的转换桥；所述通过协议桥将数据总线转换为第一配置总线包括：通过单级协议桥将一路数据总线转换为一路第一配置总线；再通过1-to-N的转换桥将一路第一配置总线同步分为N路第一配置总线。
步骤S101：通过降频桥将第一配置总线转换为第二配置总线；所述第二配置总线的频率为所述外连模块的配置总线频率。
本发明实施例还提供了一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行本发明实施例所述的时钟树实现方法。
图7为本发明实施例系统芯片的组成结构示意图，如图7所示，本发明实施例系统芯片包括核心模块10和外连模块20，所述核心模块10包括分频器13、互联矩阵12和总线转换桥11，所述互联矩阵12通过所述总线转换桥11与各个外连模块20相连，所述总线转换桥11由协议桥111和一个以上降频桥112组成；其中，
所述协议桥111，配置为将数据总线转换为第一配置总线；所述第一配置总线的频率为所述协议桥频率；
在实际应用中，所述协议桥111可以由一个以上单级协议桥组成，单级协议桥与降频桥112一一对应；所述协议桥也可以由一个单级协议桥和一个1-to-N转换桥，转换桥的输出端口与降频桥112一一对应；
所述降频桥112，配置为将第一配置总线转换为第二配置总线；所述第二配置总线的频率为所述外连模块的配置总线频率。
这里，当所述协议桥111采用单级协议桥且外连模块为N个时，所述协议桥111包括N个相同频率的单级协议桥；所述N个相同频率的单级协议桥分别将N路数据总线转换为N路第一配置总线；其中，N为大于等于2的正整数。
举例来说，图8所示为本发明实施例所述协议桥111采用单级协议桥且外连模块为两个时的系统芯片架构，所述数据总线为AXI总线，所述第一配置总线、第二配置总线均为APB总线。如图8所示，在互联矩阵中，通过两个同频率的单级协议桥分别将两路AXI总线转换为两路第一APB总线，使得两路第一APB总线频率均为协议桥频率；进一步地，通过降频桥将第一APB总线转换为第二APB总线；所述第二APB总线的频率为所述外连模块的配置总线频率。如此，从系统芯片的角度来看，能够在维持数据总线全局同步的同时，实现配置总线的全局异步和局部同步，从而达到系统芯片设计所期望的PPTA最优化。
这里，当所述协议桥111采用N级协议桥且外连模块为N个时，所述N级协议桥由一个单级协议桥和一个1-to-N转换桥组成；其中，
所述单级协议桥，配置为将一路数据总线转换为一路第一配置总线；
所述1-to-N转换桥，配置为将一路第一配置总线同步分为N路第一配置总线；其中，N为大于等于2的正整数。
举例来说，图9所示为本发明实施例所述协议桥111为两级协议桥且外连模块为两个时的系统芯片架构，所述数据总线为AXI总线，所述第一配置总线、第二配置总线均为APB总线。如图9所示，所述协议桥111由一个单级协议桥和一个1-to-2的转换桥组成。在互连矩阵中，通过一个单级协议桥将一路AXI总线转换为一路第一APB总线；再通过一个1-to-2转换桥将一路第一APB总线同步分为两路第一APB总线，使得两路第一APB总线的频率均为协议桥频率；进一步地，通过降频桥将第一APB总线转换为第二APB总线；所述第二APB总线的频率为所述外连模块的配置总线频率。如此，从系统芯片的角度来看，能够在维持数据总线全局同步的同时，实现配置总线的全局异步和局部同步，从而达到系统芯片设计所期望的PPTA最优化。
需要补充说明的是，为了方便后端物理实现，在寄存器传输级(Register Transfer Level，RTL)的代码设计时，在核心模块的分频器(即时钟产生单元)中，每个配置总线的时钟均会附上特别命名的缓冲器，以方便后端辩识，如图8和9中的缓冲器Tapb,Tapb1和Tapb2。此外，还需要给出降频桥中各组配置总线(APB总线)在APB时钟域一侧的寄存器信息。
下面对图8或图9所示的系统芯片架构的物理实现过程加以详细描述。
图10为本发明实施例中图8或图9所示的系统芯片架构的主要时序路径图一，如图10所示，整个系统芯片的数据总线(AXI总线)仍为全局同步，因此，需要全局同步的寄存器(FF)比较多，且位置分散在全芯片的范围内，这样，AXI时钟延迟Laxi较大；在核心模块中，各个降频桥与外连模块的配置总线(如APB总线)分别保持同步关系，从而形成多个局部同步的APB总线；
具体地，在配置总线(如APB总线)中，每个缓冲器TapbN后面分别形成一个独立的APB同步总线。对于某个局部同步总线apbN而言，需要局部同步的寄存器数量少且位置相对局部且集中，相对于AXI总线，局部同步总线apbN的延迟LapbN较小，即：Laxi>Lapb1；其中，N从1到所使用的apb时钟域个数。
下面以局部同步时钟域apb1为例，对核心模块的主要时序路径如何实现时序调节加以简要描述。
首先，考虑核心摸块中的总线写操作包括协议的转换和时钟的降频，如图10所示的时序路径p1，所述时序路径p1是一个从AXI到APB的跨时钟路径。对于时序路径p1而言，虽然可以用多周期路径来弱化相关时序约束，但由于总线协议中这部分逻辑简单，且后端实现时物理位置较为集中，其时序比较容易满足，故仍按单周期(AXI时钟周期)路径来约束。
具体地，时序路径p1的时序约束条件如下：
对于建立(setup)时间的时序，要求Laxi+Dck-q+Dp1+Dsetup<Paxi+Lapb1；而对于保持(hold)时间的时序，则要求Laxi+Dck-q+Dp1>Lapb1+Dhold；其中，Laxi表示AXI时钟延迟(latency of AXI clock)；Lapb1表示APB1时钟延迟(latency of APB1clock)；Dck-q表示寄存器时钟端到输出端延迟(delay of pin CK to pin Q of Flip Flop)；Dp1表示路径1的组合逻辑延迟(delay of combination of Path1)；Dsetup表示寄存器建立时间(setup time of Flip Flop)；Dhold表示寄存器建立时间(hold time of Flip Flop)；Paxi表示AXI时钟周期(period of AXI clock)。因此，如果发生时序违例，可以在图10所示的点1位置，通过将apb1时钟端所对应时钟推后，具体可以是加大点1处寄存器时钟端延迟，即增加缓冲器T1来实现时序的调节。若调整一级不足以满足时序，可采用图11所示的主要时序路径，进一步继续在点3处做类似调整，直至写操作的所有时序路径满足要求。
其次，考虑局部时钟域apb1中如图10所示的时序路径p2和p3。由于所述时序路径p2和p3路径都在同一时钟域，且局部时钟域apb1的时钟频率较AXI时钟频率为低，即在AXI时钟频率的二分频及以下，因此，只要时钟树平衡，所述时序路径p2和p3的时序就很容易收敛。
最后，考虑核心模块内的总线读操作，如图10所示的时序路径p4。考虑时序路径p4的时序约束条件如下：
对于建立(setup)时间的时序，要求Lapb1+Dck-q+Dp4+Dsetup<Paxi+Laxi；而对于保持(hold)时间的时序，则要求Lapb1+Dck-q+Dp4>Laxi+Dhold。因此，如果发生时序违例，可在点2位置做动态调整，具体地，减小点2处寄存器时钟端延迟，即将apb1时钟端的时钟适当缩短，即减少缓冲器T2；若调整一级不足以满足时序，可采用图11所示的主要时序路径，进一步继续在点4和点5处做类似调整，直至读 操作的所有时序路径满足要求。
综上所述，采用本发明实施例时钟树实现方法和装置，与现有传统设计方法相比，能够在保持同步逻辑设计的同时，实现各个配置总线独立进行时钟树综合；另外，由于各个配置总线独立进行时钟树综合，使得较少的寄存器数量及物理放置区域的局部化能够有效减小时钟树延迟，从而导致功耗和面积减少，拥塞降低，达到配置总线全局异步的效果，有效节省总线时钟树的面积和功耗，提高后端物理实现的可控性，同时也使得设计周期缩短。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述仅是本发明实施例的实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明实施例原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明实施例的保护范围。
工业实用性
本发明实施例通过协议桥将数据总线转换为第一配置总线；所述第一配置总线的频率为所述协议桥频率；通过降频桥将第一配置总线转换为第二配置总线；所述第二配置总线的频率为所述外连模块的配置总线频率。如此，能够在维持数据总线全局同步的同时，实现配置总线的全局异步和局部同步，从而达到系统芯片设计的PPTA最优化，进而提高系统芯片的设计灵活性和实现竞争力。

Claims (11)

  1. 一种时钟树实现方法，应用于包括核心模块和外连模块的系统芯片中；所述核心模块中的互联矩阵通过包括协议桥和降频桥的总线转换桥与所述外连模块连接；所述方法包括：
    通过协议桥将数据总线转换为第一配置总线；所述第一配置总线的频率为所述协议桥频率；
    通过降频桥将第一配置总线转换为第二配置总线；所述第二配置总线的频率为所述外连模块的配置总线频率。
  2. 根据权利要求1所述的方法，其中，所述协议桥采用单级协议桥；当外连模块为N个时，所述协议桥包括N个相同频率的单级协议桥；
    所述通过协议桥将数据总线转换为第一配置总线包括：
    通过N个相同频率的单级协议桥分别将N路数据总线转换为N路第一配置总线；其中，N为大于等于2的正整数。
  3. 根据权利要求1所述的方法，其中，所述协议桥采用N级协议桥；当外连模块为N个时，所述N级协议桥由一个单级协议桥和一个1-to-N的转换桥组成；
    所述通过协议桥将数据总线转换为第一配置总线包括：
    通过单级协议桥将一路数据总线转换为一路第一配置总线；再通过1-to-N的转换桥将一路第一配置总线同步分为N路第一配置总线；其中，N为大于等于2的正整数。
  4. 根据权利要求1至3任一项所述的方法，其中，所述协议桥为同步桥。
  5. 根据权利要求1至3任一项所述的方法，其中，所述数据总线为先进可扩展接口总线；所述第一配置总线、第二配置总线均为先进的高性能总线或先进的外围总线。
  6. 一种系统芯片，所述系统芯片包括核心模块和外连模块，所述核心模块包括分频器、互联矩阵和总线转换桥，所述互联矩阵通过所述总线转换桥与所述外连模块相连，所述总线转换桥由协议桥和降频桥组成；
    所述协议桥，配置为将数据总线转换为第一配置总线；所述第一配置总线的频率为所述协议桥频率；
    所述降频桥，配置为将第一配置总线转换为第二配置总线；所述第二配置总线的频率为所述外连模块的配置总线频率。
  7. 根据权利要求6所述的系统芯片，其中，所述协议桥采用单级协议桥；当外连模块为N个时，所述协议桥包括N个相同频率的单级协议桥；
    所述N个相同频率的单级协议桥，配置为分别将N路数据总线转换为N路第一配置总线；其中，N为大于等于2的正整数。
  8. 根据权利要求6所述的系统芯片，其中，所述协议桥采用N级协议桥；当外连模块为N个时，所述N级协议桥由一个单级协议桥和一个1-to-N的转换桥组成；
    所述单级协议桥，配置为将一路数据总线转换为一路第一配置总线；
    所述1-to-N的转换桥，配置为将一路第一配置总线同步分为N路第一配置总线；其中，N为大于等于2的正整数。
  9. 根据权利要求6至8任一项所述的系统芯片，其中，所述协议桥为同步桥。
  10. 根据权利要求6至8任一项所述的系统芯片，其中，所述数据总线为先进可扩展接口总线；所述第一配置总线、第二配置总线均为先进的高性能总线或先进的外围总线。
  11. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求1至5任一项所述的时钟树实现方法。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108153699A (zh) * 2017-12-21 2018-06-12 郑州云海信息技术有限公司 一种ahb转axi协议转换控制器设计方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10860761B1 (en) * 2018-06-11 2020-12-08 Ansys, Inc. Systems and methods for enhanced clock tree power estimation at register transfer level

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101063894A (zh) * 2006-06-13 2007-10-31 威盛电子股份有限公司 动态同步化处理器时钟与总线时钟前缘的方法与系统
CN101183347A (zh) * 2006-11-14 2008-05-21 智多微电子（上海）有限公司 一种自适应速率匹配总线的桥接电路
US20080133800A1 (en) * 2005-10-04 2008-06-05 Tilman Gloekler High Speed On-Chip Serial Link Apparatus
CN102207920A (zh) * 2010-03-30 2011-10-05 比亚迪股份有限公司 一种bvci总线到ahb总线的转换桥

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10161973A (ja) * 1996-11-29 1998-06-19 Hitachi Ltd バス制御装置およびバスユニット
JP2001051748A (ja) * 1999-08-12 2001-02-23 Hitachi Ltd 情報処理装置
JP2002318782A (ja) * 2001-04-20 2002-10-31 Nec Corp バスシステム
JP4298437B2 (ja) * 2003-08-28 2009-07-22 パナソニック株式会社 バスブリッジ回路
KR101086401B1 (ko) * 2004-06-02 2011-11-25 삼성전자주식회사 서로 다른 속도로 동작하는 버스들을 인터페이싱하는 방법및 장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080133800A1 (en) * 2005-10-04 2008-06-05 Tilman Gloekler High Speed On-Chip Serial Link Apparatus
CN101063894A (zh) * 2006-06-13 2007-10-31 威盛电子股份有限公司 动态同步化处理器时钟与总线时钟前缘的方法与系统
CN101183347A (zh) * 2006-11-14 2008-05-21 智多微电子（上海）有限公司 一种自适应速率匹配总线的桥接电路
CN102207920A (zh) * 2010-03-30 2011-10-05 比亚迪股份有限公司 一种bvci总线到ahb总线的转换桥

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108153699A (zh) * 2017-12-21 2018-06-12 郑州云海信息技术有限公司 一种ahb转axi协议转换控制器设计方法

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