WO2016179853A1 - 阵列基板结构及其制作方法 - Google Patents

阵列基板结构及其制作方法 Download PDF

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WO2016179853A1
WO2016179853A1 PCT/CN2015/079661 CN2015079661W WO2016179853A1 WO 2016179853 A1 WO2016179853 A1 WO 2016179853A1 CN 2015079661 W CN2015079661 W CN 2015079661W WO 2016179853 A1 WO2016179853 A1 WO 2016179853A1
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layer
insulating layer
disposed
source
drain
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French (fr)
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虞晓江
杜海波
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Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/764,176 priority Critical patent/US9785023B2/en
Publication of WO2016179853A1 publication Critical patent/WO2016179853A1/zh
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/09—Materials and properties inorganic glass

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate structure and a method of fabricating the same.
  • the touch screen display allows the user to operate the host by gently touching the icon or text on the computer display with a finger. This frees the keyboard and mouse operation and makes the human-computer interaction more straightforward.
  • the products are mainly divided into three types: capacitive touch screen, resistive touch screen and surface acoustic wave touch screen.
  • Array substrates are an important part of touch display panels.
  • FIG. 1 is a cross-sectional view of a conventional array substrate structure for a touch display panel.
  • the array substrate includes a substrate 100, a buffer layer 200 disposed on the substrate 100, a semiconductor layer 300 disposed on the buffer layer 200, and a gate insulating layer disposed on the buffer layer 200 and the semiconductor layer 300.
  • a first via 510 is disposed on the gate insulating layer 410 and the interlayer dielectric layer 420 corresponding to the semiconductor layer 300.
  • the first insulating layer 810 is disposed above the second metal layer 700.
  • the second via 520, the flat layer 600, the first insulating layer 810, and the second insulating layer 820 corresponding to the source / drain 500 is provided with a third via 530;
  • a source/drain contact region 310 is disposed on the semiconductor layer 300, and the source/drain 500 is in contact with the source/drain contact region 310 of the semiconductor layer 300 via the first via 510,
  • the common electrode 910 is in contact with the second metal layer 700 via the second via 520, and the pixel electrode 920 is in contact with the source/drain 500 via the third via 530.
  • the second metal layer 700 is used to connect the touch sensing electrodes.
  • the material of the second insulating layer 820 is SiNx
  • the material of the common electrode 910 is ITO (indium tin oxide).
  • the second insulating layer 820 (SiN x layer) is prepared by plasma enhanced chemical vapor deposition, and the reaction principle is as follows:
  • the SiH 4 , NH 3 , and N 2 react under the electromagnetic field generated by the RF power (radio frequency power) to form SiN x :H and H 2 , and the H 2 atmosphere generated by the reaction is reductive, which is easy.
  • the surface layer region of the common electrode 910 is reduced.
  • a reduced ITO layer 912 is formed on the surface of the common electrode 910, and the ITO layer 914 is below the reduced ITO layer 912 due to the reduced ITO layer.
  • the light transmittance of the 912 is poor, so that the overall light transmittance of the common electrode 910 is greatly reduced, thereby making the overall light transmittance of the touch display panel low, which affects the display effect (such as brightness) of the panel.
  • Another object of the present invention is to provide a method for fabricating an array substrate structure, which can reduce the influence on the transmittance of the common electrode when depositing the insulating layer on the common electrode, ensure the high transmittance of the common electrode, and improve the display effect.
  • the present invention provides an array substrate structure including a substrate, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, and a gate disposed on the buffer layer and the semiconductor layer.
  • a first insulating layer, an interlayer dielectric layer disposed on the gate insulating layer, a source/drain disposed on the interlayer dielectric layer, and a source/drain and an interlayer dielectric layer a flat layer thereon, a second metal layer disposed on the flat layer, a first insulating layer disposed on the second metal layer and the flat layer, and a common electrode disposed on the first insulating layer
  • a first via hole is disposed on the gate insulating layer and the interlayer dielectric layer corresponding to the semiconductor layer, and a second via hole is disposed on the first insulating layer corresponding to the second metal layer.
  • a third via hole is disposed on the flat layer, the first insulating layer, the anti-reduction layer, and the second insulating layer corresponding to the source/drain;
  • a source/drain contact region is disposed on the semiconductor layer, and the source/drain contacts the source/drain contact region of the semiconductor layer via the first via, the common electrode via the first Two via holes are in contact with the second metal layer, and the pixel electrode is connected to the source/drain via the third via hole contact.
  • the material of the anti-reduction layer is a compositionally graded SiN x O y , x ⁇ 0, 0 ⁇ y ⁇ 2, and from the direction of the common electrode to the second insulating layer, x gradually increases from 0, and y starts from 2. Gradually reduce to zero.
  • the materials of the first insulating layer and the second insulating layer are both SiN x and x>0.
  • the material of the source/drain contact region of the semiconductor layer is N-type heavily doped silicon; the material of the common electrode and the pixel electrode is ITO.
  • the present invention also provides an array substrate structure, including a substrate, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a gate insulating layer disposed on the buffer layer and the semiconductor layer, An interlayer dielectric layer disposed on the gate insulating layer, a source/drain disposed on the interlayer dielectric layer, and a planar layer disposed on the source/drain and the interlayer dielectric layer a second metal layer disposed on the flat layer, a first insulating layer disposed on the second metal layer and the flat layer, and a common electrode disposed on the first insulating layer, disposed in the public An anti-reduction layer on the electrode and the first insulating layer, a second insulating layer disposed on the anti-reduction layer, and a pixel electrode disposed on the second insulating layer;
  • a first via hole is disposed on the gate insulating layer and the interlayer dielectric layer corresponding to the semiconductor layer, and a second via hole is disposed on the first insulating layer corresponding to the second metal layer.
  • a third via hole is disposed on the flat layer, the first insulating layer, the anti-reduction layer, and the second insulating layer corresponding to the source/drain;
  • a source/drain contact region is disposed on the semiconductor layer, and the source/drain contacts the source/drain contact region of the semiconductor layer via the first via, the common electrode via the first Two via holes are in contact with the second metal layer, and the pixel electrode is in contact with the source/drain via the third via hole;
  • the material of the anti-reduction layer is a compositionally graded SiN x O y , x ⁇ 0, 0 ⁇ y ⁇ 2, and from the direction of the common electrode to the second insulating layer, x gradually increases from 0, and y 2 begins to gradually decrease to 0;
  • the material of the first insulating layer and the second insulating layer are both SiN x , x>0;
  • the material of the source/drain contact region of the semiconductor layer is N-type heavily doped silicon; the material of the common electrode and the pixel electrode is ITO.
  • Step 1 providing a substrate, depositing a buffer layer on the substrate;
  • Step 3 sequentially depositing a gate insulating layer and an interlayer dielectric layer on the semiconductor layer, and simultaneously patterning the gate insulating layer and the interlayer dielectric layer, and the gate insulating layer and the layer Intermedia Forming a first via on the electrical layer above the source/drain contact region of the semiconductor layer;
  • the materials of the first insulating layer and the second insulating layer are both SiN x and x>0.
  • Step 2 As shown in FIG. 6, a semiconductor layer 3 is deposited on the buffer layer 2, and after patterning, a portion of the semiconductor layer 3 is heavily doped with an N-type to form a design and source/ A drain/drain contact source/drain contact region 31.
  • Step 8 as shown in FIG. 12, depositing a first oxide conductive layer over the first insulating layer 81 and patterning it to form a common electrode 91 via which the common electrode 91 passes 52 is in contact with the second metal layer 7.
  • Step 9 As shown in FIG. 13, an anti-reduction layer 82 is deposited over the common electrode 91 and the first insulating layer 81.
  • the anti-reduction layer 82 is formed by plasma enhanced chemical vapor deposition.
  • Step 11 as shown in FIG. 3, depositing a second oxide conductive layer on the second insulating layer 83 and patterning it to form a pixel electrode 92 via the third via hole 53 is in contact with the source/drain 5.

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Abstract

一种阵列基板结构及其制作方法，该方法通过在形成公共电极(91)后，沉积第二绝缘层(83)前，在公共电极(91)上形成一抗还原层(82)，避免了在公共电极(91)上直接沉积第二绝缘层(83)的过程中，产生的还原性气氛改变公共电极(91)的膜层质量，减少了在公共电极(91)上沉积第二绝缘层(83)时对公共电极(91)透过率的影响，保证了公共电极(91)具有较高的透过率，提升了显示效果。

Description

阵列基板结构及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板结构及其制作方法。
背景技术
触摸屏显示器(Touch Screen)可以让使用者只要用手指轻轻地碰计算机显示屏上的图符或文字就能实现对主机操作，这样摆脱了键盘和鼠标操作，使人机交互更为直截了当。主要应用于公共场所大厅信息查询、领导办公、电子游戏、点歌点菜、多媒体教学、机票、火车票预售等。产品主要分为电容式触控屏、电阻式触控屏和表面声波触摸屏三类。
阵列基板(Array substrate)是触控显示面板中的重要组成部分。
请参阅图1，为一种现有的用于触控显示面板的阵列基板结构的剖面示意图。所述阵列基板包括基板100、设于所述基板100上的缓冲层200、设于所述缓冲层200上的半导体层300、设于所述缓冲层200与半导体层300上的栅极绝缘层410、设于所述栅极绝缘层410上的层间介电层420、设于所述层间介电层420上的源/漏极500、设于所述源/漏极500与层间介电层420上的平坦层600、设于所述平坦层600上的第二金属层700、设于所述第二金属层700与平坦层600上的第一绝缘层810、设于所述第一绝缘层810上的公共电极910、设于所述公共电极910与第一绝缘层810上的第二绝缘层820、及设于所述第二绝缘层820上的像素电极920；
所述栅极绝缘层410、及层间介电层420上对应所述半导体层300上方设有第一过孔510，所述第一绝缘层810上对应所述第二金属层700上方设有第二过孔520，所述平坦层600、第一绝缘层810、及第二绝缘层820上对应所述源/漏极500上方设有第三过孔530；
所述半导体层300上设有源/漏极接触区310，所述源/漏极500经由所述第一过孔510与所述半导体层300的源/漏极接触区310相接触，所述公共电极910经由所述第二过孔520与所述第二金属层700相接触，所述像素电极920经由所述第三过孔530与所述源/漏极500相接触。
其中，所述第二金属层700用于连接触控感应电极。
具体的，所述第二绝缘层820的材料为SiNx，所述公共电极910的材料为ITO(氧化铟锡)。
具体的，通过等离子体增强化学气相沉积法来制备所述第二绝缘层820 (SiNx层)，其反应原理如下：
Figure PCTCN2015079661-appb-000001
即所述SiH4、NH3、及N2在射频电源(RF power,radio frequency power)产生的电磁场作用下反应生成SiNx:H及H2，反应产生的H2气氛具有还原性，很容易使得所述公共电极910的表层区域被还原，如图2所示，在所述公共电极910表面形成一还原ITO层912，所述还原ITO层912下方为ITO层914，由于所述还原ITO层912的透光性差，从而使得所述公共电极910的整体透光性大大降低，进而使得触控显示面板的整体光线透过率变低，影响了面板的显示效果(如亮度等)。
因此，有必要提供一种阵列基板结构及其制作方法，以解决上述问题。
发明内容
本发明的目的在于提供一种阵列基板结构，公共电极的膜层质量较好，具有较高的透过率。
本发明的目的还在于提供一种阵列基板结构的制作方法，可减少在公共电极上沉积绝缘层时对公共电极透过率的影响，保证公共电极具有较高的透过率，提升显示效果。
为实现上述目的，本发明提供一种阵列基板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的半导体层、设于所述缓冲层与半导体层上的栅极绝缘层、设于所述栅极绝缘层上的层间介电层、设于所述层间介电层上的源/漏极、设于所述源/漏极与层间介电层上的平坦层、设于所述平坦层上的第二金属层、设于所述第二金属层与平坦层上的第一绝缘层、设于所述第一绝缘层上的公共电极、设于所述公共电极与第一绝缘层上的抗还原层、设于所述抗还原层上的第二绝缘层、及设于所述第二绝缘层上的像素电极；
所述栅极绝缘层、及层间介电层上对应所述半导体层上方设有第一过孔，所述第一绝缘层上对应所述第二金属层上方设有第二过孔，所述平坦层、第一绝缘层、抗还原层、及第二绝缘层上对应所述源/漏极上方设有第三过孔；
所述半导体层上设有源/漏极接触区，所述源/漏极经由所述第一过孔与所述半导体层的源/漏极接触区相接触，所述公共电极经由所述第二过孔与所述第二金属层相接触，所述像素电极经由所述第三过孔与所述源/漏极相 接触。
所述抗还原层的材料为成分渐变的SiNxOy，x≥0，0≤y≤2，从公共电极至第二绝缘层的方向上，x从0开始逐渐增大，y从2开始逐渐减小至0。
所述第一绝缘层、及第二绝缘层的材料均为SiNx，x＞0。
所述半导体层的源/漏极接触区的材料为N型重掺杂硅；所述公共电极、及像素电极的材料均为ITO。
本发明还提供一种阵列基板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的半导体层、设于所述缓冲层与半导体层上的栅极绝缘层、设于所述栅极绝缘层上的层间介电层、设于所述层间介电层上的源/漏极、设于所述源/漏极与层间介电层上的平坦层、设于所述平坦层上的第二金属层、设于所述第二金属层与平坦层上的第一绝缘层、设于所述第一绝缘层上的公共电极、设于所述公共电极与第一绝缘层上的抗还原层、设于所述抗还原层上的第二绝缘层、及设于所述第二绝缘层上的像素电极；
所述栅极绝缘层、及层间介电层上对应所述半导体层上方设有第一过孔，所述第一绝缘层上对应所述第二金属层上方设有第二过孔，所述平坦层、第一绝缘层、抗还原层、及第二绝缘层上对应所述源/漏极上方设有第三过孔；
所述半导体层上设有源/漏极接触区，所述源/漏极经由所述第一过孔与所述半导体层的源/漏极接触区相接触，所述公共电极经由所述第二过孔与所述第二金属层相接触，所述像素电极经由所述第三过孔与所述源/漏极相接触；
其中，所述抗还原层的材料为成分渐变的SiNxOy，x≥0，0≤y≤2，从公共电极至第二绝缘层的方向上，x从0开始逐渐增大，y从2开始逐渐减小至0；
其中，所述第一绝缘层、及第二绝缘层的材料均为SiNx，x＞0；
其中，所述半导体层的源/漏极接触区的材料为N型重掺杂硅；所述公共电极、及像素电极的材料均为ITO。
本发明还提供一种阵列基板结构的制作方法，其包括如下步骤：
步骤1、提供基板，在所述基板上沉积缓冲层；
步骤2、在所述缓冲层上沉积半导体层，对其进行图案化后，对所述半导体层上的部分区域进行N型重掺杂，形成设计与源/漏极相接触的源/漏极接触区；
步骤3、在所述半导体层上依次沉积栅极绝缘层、及层间介电层，同时对栅极绝缘层、及层间介电层进行图案化，在所述栅极绝缘层、及层间介 电层上对应所述半导体层的源/漏极接触区上方形成第一过孔；
步骤4、在所述层间介电层上方沉积第一金属层，并对其进行图案化，形成源/漏极，所述源/漏极经由所述第一过孔与所述半导体层的源/漏极接触区相接触；
步骤5、在所述源/漏极、及层间介电层上方沉积平坦层；
步骤6、在所述平坦层上方沉积第二金属层，并对其进行图案化；
步骤7、在所述第二金属层、及平坦层上方沉积第一绝缘层，并对其进行图案化，在所述第一绝缘层上对应所述第二金属层上方形成第二过孔；
步骤8、在所述第一绝缘层上方沉积第一氧化物导电层，并对其进行图案化，形成公共电极，所述公共电极经由所述第二过孔与所述第二金属层相接触；
步骤9、在所述公共电极、及第一绝缘层上方沉积抗还原层；
步骤10、在所述抗还原层上沉积第二绝缘层，同时对所述第二绝缘层、抗还原层、第一绝缘层、及平坦层进行图案化，在所述第二绝缘层、抗还原层、第一绝缘层、及平坦层对应所述源/漏极上方形成第三过孔；
步骤11、在所述第二绝缘层上沉积第二氧化物导电层，并对其进行图案化，形成像素电极，所述像素电极经由所述第三过孔与所述源/漏极相接触。
所述步骤9采用等离子体增强化学气相沉积法形成所述抗还原层。
所述步骤9具体包括：
步骤91、在所述公共电极表面通入沉积SiO2的气体，生成一SiO2薄层；
步骤92、缓慢关闭沉积SiO2的气体的同时逐渐通入沉积SiNx的气体，所述沉积SiO2的气体通入的量逐渐减少至零，同时沉积SiNx的气体通入的量逐渐增多，从而在所述公共电极上得到成分渐变的SiNxOy层，x≥0，0≤y≤2，从公共电极开始向上生长的方向上，x从0开始逐渐增大，y从2开始逐渐减小至0，所述成分渐变的SiNxOy层即为抗还原层。
所述沉积SiO2的气体为TEOS和O2，所述沉积SiNx的气体为SiH4、NH3、及N2。
所述第一绝缘层、及第二绝缘层的材料均为SiNx，x＞0。
所述半导体层的源/漏极接触区的材料为N型重掺杂硅；所述公共电极、及像素电极的材料均为ITO。
本发明的有益效果：本发明的阵列基板结构，公共电极上设有抗还原层，避免了在公共电极上直接沉积第二绝缘层的过程中，产生的还原性气氛改变公共电极的膜层质量，使公共电极具有较高的透过率。本发明的阵 列基板结构的制作方法，在形成公共电极后，沉积第二绝缘层前，在公共电极上形成一抗还原层，避免了在公共电极上直接沉积第二绝缘层的过程中，产生的还原性气氛改变公共电极的膜层质量，减少了在公共电极上沉积第二绝缘层时对公共电极透过率的影响，保证了公共电极具有较高的透过率，提升了显示效果。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为一种现有的用于触控显示面板的阵列基板结构的剖面示意图；
图2为图1中的区域A的局部放大示意图；
图3为本发明的阵列基板结构的剖面示意图；
图4为图3中的区域A’的局部放大示意图；
图5为本发明的阵列基板结构的制作方法步骤1的示意图；
图6为本发明的阵列基板结构的制作方法步骤2的示意图；
图7为本发明的阵列基板结构的制作方法步骤3的示意图；
图8为本发明的阵列基板结构的制作方法步骤4的示意图；
图9为本发明的阵列基板结构的制作方法步骤5的示意图；
图10为本发明的阵列基板结构的制作方法步骤6的示意图；
图11为本发明的阵列基板结构的制作方法步骤7的示意图；
图12为本发明的阵列基板结构的制作方法步骤8的示意图；
图13为本发明的阵列基板结构的制作方法步骤9的示意图；
图14为本发明的阵列基板结构的制作方法步骤10的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3和图4，本发明提供一种用于触控显示面板的阵列基板结构，其包括基板1、设于所述基板1上的缓冲层2、设于所述缓冲层2上的半导体层3、设于所述缓冲层2与半导体层3上的栅极绝缘层41、设于所 述栅极绝缘层41上的层间介电层42、设于所述层间介电层42上的源/漏极5、设于所述源/漏极5与层间介电层42上的平坦层6、设于所述平坦层6上的第二金属层7、设于所述第二金属层7与平坦层6上的第一绝缘层81、设于所述第一绝缘层81上的公共电极91、设于所述公共电极91与第一绝缘层81上的抗还原层82、设于所述抗还原层82上的第二绝缘层83、及设于所述第二绝缘层83上的像素电极92；
所述栅极绝缘层41、及层间介电层42上对应所述半导体层3上方设有第一过孔51，所述第一绝缘层81上对应所述第二金属层7上方设有第二过孔52，所述平坦层6、第一绝缘层81、抗还原层82、及第二绝缘层83上对应所述源/漏极5上方设有第三过孔53；
所述半导体层3上设有源/漏极接触区31，所述源/漏极5经由所述第一过孔51与所述半导体层3的源/漏极接触区31相接触，所述公共电极91经由所述第二过孔52与所述第二金属层7相接触，所述像素电极92经由所述第三过孔53与所述源/漏极5相接触。
具体的，所述第一绝缘层81、及第二绝缘层83的材料均为SiNx，x＞0。
所述抗还原层82的材料为成分渐变的SiNxOy(氮氧化硅)，x≥0，0≤y≤2，从公共电极91至第二绝缘层83的方向上，x从0开始逐渐增大，y从2开始逐渐减小至0，即抗还原层82的成分由公共电极91的界面开始逐步改变至和第二绝缘层83的成分相同，有利于提升抗还原层82和第二绝缘层83之间的结合力。
所述半导体层3的源/漏极接触区31的材料为N型重掺杂硅(N+Si)。
所述公共电极91、及像素电极92的材料均为ITO(氧化铟锡)。
具体的，所述第二金属层7用于连接触控感应电极。
上述阵列基板结构，公共电极上沉积第二绝缘层之前沉积一抗还原层，避免了在公共电极上直接沉积第二绝缘层的过程中，产生的还原性气氛改变公共电极的膜层质量，使公共电极具有较高的透过率。
请参阅图3，结合图5-图14，本发明还提供一种阵列基板结构的制作方法，包括如下步骤：
步骤1、如图5所示，提供基板1，在所述基板1上沉积缓冲层2。
步骤2、如图6所示，在所述缓冲层2上沉积半导体层3，对其进行图案化后，对所述半导体层3上的部分区域进行N型重掺杂，形成设计与源/漏极相接触的源/漏极接触区31。
具体的，所述半导体层3的源/漏极接触区31的材料为N型重掺杂硅(N+Si)。
步骤3、如图7所示，在所述半导体层3上依次沉积栅极绝缘层41、及层间介电层42，同时对栅极绝缘层41、及层间介电层42进行图案化，在所述栅极绝缘层41、及层间介电层42上对应所述半导体层3的源/漏极接触区31上方形成第一过孔51。
步骤4、如图8所示，在所述层间介电层42上方沉积第一金属层，并对其进行图案化，形成源/漏极5，所述源/漏极5经由所述第一过孔51与所述半导体层3的源/漏极接触区31相接触。
步骤5、如图9所示，在所述源/漏极5、及层间介电层42上方沉积平坦层6。
步骤6、如图10所示，在所述平坦层6上方沉积第二金属层7，并对其进行图案化。
具体的，所述第二金属层7用于连接触控感应电极。
步骤7、如图11所示，在所述第二金属层7、及平坦层6上方沉积第一绝缘层81，并对其进行图案化，在所述第一绝缘层81上对应所述第二金属层7上方形成第二过孔52。
具体的，采用等离子体增强化学气相沉积法(PECVD)形成所述第一绝缘层81。
具体的，所述第一绝缘层81的材料为SiNx，x＞0。
步骤8、如图12所示，在所述第一绝缘层81上方沉积第一氧化物导电层，并对其进行图案化，形成公共电极91，所述公共电极91经由所述第二过孔52与所述第二金属层7相接触。
具体的，所述公共电极91的材料为ITO(氧化铟锡)。
步骤9、如图13所示，在所述公共电极91、及第一绝缘层81上方沉积抗还原层82。
具体的，采用等离子体增强化学气相沉积法形成所述抗还原层82。
具体的，所述步骤9包括以下步骤：
步骤91、在所述公共电极91表面通入沉积SiO2的气体，生成一SiO2薄层；
步骤92、缓慢关闭沉积SiO2的气体的同时逐渐通入沉积SiNx的气体，所述沉积SiO2的气体通入的量逐渐减少至零，同时沉积SiNx的气体通入的量逐渐增多，从而在所述公共电极91上得到成分渐变的SiNxOy层，x≥0，0≤y≤2，从公共电极91开始向上生长的方向上，x从0开始逐渐增大，y从2开始逐渐减小至0，所述成分渐变的SiNxOy层即为抗还原层82。
具体地，所述沉积SiO2的气体为TEOS(正硅酸乙酯)和O2(氧气)， 所述TEOS和O2在射频电源(RF power,radio frequency power)产生的电磁场作用下反应生成SiO2的反应原理如下：
Figure PCTCN2015079661-appb-000002
具体的，所述沉积SiNx的气体为SiH4(甲硅烷)、NH3(氨气)、及N2(氮气)，所述SiH4、NH3、及N2在射频电源(RF power,radio frequency power)产生的电磁场作用下反应生成SiNx的反应原理如下：
Figure PCTCN2015079661-appb-000003
步骤10、如图14所示，在所述抗还原层82上沉积第二绝缘层83，同时对所述第二绝缘层83、抗还原层82、第一绝缘层81、及平坦层6进行图案化，在所述第二绝缘层83、抗还原层82、第一绝缘层81、及平坦层6对应所述源/漏极5上方形成第三过孔53。
具体的，采用等离子体增强化学气相沉积法形成所述第二绝缘层83。
具体地，所述第二绝缘层83的材料为SiNx，x＞0。
值得一提的是，所述第二绝缘层83也可以和所述抗还原层82一次性制备完成，有利于获得高的生产效率。
步骤11、如图3所示，在所述第二绝缘层83上沉积第二氧化物导电层，并对其进行图案化，形成像素电极92，所述像素电极92经由所述第三过孔53与所述源/漏极5相接触。
具体的，所述像素电极92的材料为ITO(氧化铟锡)。
上述阵列基板结构的制作方法，在形成公共电极后，沉积第二绝缘层前，在公共电极上形成一抗还原层，避免了在公共电极上沉积第二绝缘层的过程中，产生的还原性气氛改变公共电极的膜层质量，减少了在公共电极上沉积绝缘层时对公共电极透过率的影响，保证了公共电极具有较高的透过率，提升了显示效果。
综上所述，本发明的阵列基板结构，公共电极上设有抗还原层，避免了在公共电极上直接沉积第二绝缘层的过程中，产生的还原性气氛改变公共电极的膜层质量，使公共电极具有较高的透过率。本发明的阵列基板结构的制作方法，在形成公共电极后，沉积第二绝缘层前，在公共电极上形成一抗还原层，避免了在公共电极上直接沉积第二绝缘层的过程中，产生的还原性气氛改变公共电极的膜层质量，减少了在公共电极上沉积第二绝缘层时对公共电极透过率的影响，保证了公共电极具有较高的透过率，提 升了显示效果。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (11)

  1. 一种阵列基板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的半导体层、设于所述缓冲层与半导体层上的栅极绝缘层、设于所述栅极绝缘层上的层间介电层、设于所述层间介电层上的源/漏极、设于所述源/漏极与层间介电层上的平坦层、设于所述平坦层上的第二金属层、设于所述第二金属层与平坦层上的第一绝缘层、设于所述第一绝缘层上的公共电极、设于所述公共电极与第一绝缘层上的抗还原层、设于所述抗还原层上的第二绝缘层、及设于所述第二绝缘层上的像素电极；
    所述栅极绝缘层、及层间介电层上对应所述半导体层上方设有第一过孔，所述第一绝缘层上对应所述第二金属层上方设有第二过孔，所述平坦层、第一绝缘层、抗还原层、及第二绝缘层上对应所述源/漏极上方设有第三过孔；
    所述半导体层上设有源/漏极接触区，所述源/漏极经由所述第一过孔与所述半导体层的源/漏极接触区相接触，所述公共电极经由所述第二过孔与所述第二金属层相接触，所述像素电极经由所述第三过孔与所述源/漏极相接触。
  2. 如权利要求1所述的阵列基板结构，其中，所述抗还原层的材料为成分渐变的SiNxOy，x≥0，0≤y≤2，从公共电极至第二绝缘层的方向上，x从0开始逐渐增大，y从2开始逐渐减小至0。
  3. 如权利要求1所述的阵列基板结构，其中，所述第一绝缘层、及第二绝缘层的材料均为SiNx，x＞0。
  4. 如权利要求1所述的阵列基板结构，其中，所述半导体层的源/漏极接触区的材料为N型重掺杂硅；所述公共电极、及像素电极的材料均为ITO。
  5. 一种阵列基板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的半导体层、设于所述缓冲层与半导体层上的栅极绝缘层、设于所述栅极绝缘层上的层间介电层、设于所述层间介电层上的源/漏极、设于所述源/漏极与层间介电层上的平坦层、设于所述平坦层上的第二金属层、设于所述第二金属层与平坦层上的第一绝缘层、设于所述第一绝缘层上的公共电极、设于所述公共电极与第一绝缘层上的抗还原层、设于所述抗还原层上的第二绝缘层、及设于所述第二绝缘层上的像素电极；
    所述栅极绝缘层、及层间介电层上对应所述半导体层上方设有第一过孔，所述第一绝缘层上对应所述第二金属层上方设有第二过孔，所述平坦 层、第一绝缘层、抗还原层、及第二绝缘层上对应所述源/漏极上方设有第三过孔；
    所述半导体层上设有源/漏极接触区，所述源/漏极经由所述第一过孔与所述半导体层的源/漏极接触区相接触，所述公共电极经由所述第二过孔与所述第二金属层相接触，所述像素电极经由所述第三过孔与所述源/漏极相接触；
    其中，所述抗还原层的材料为成分渐变的SiNxOy，x≥0，0≤y≤2，从公共电极至第二绝缘层的方向上，x从0开始逐渐增大，y从2开始逐渐减小至0；
    其中，所述第一绝缘层、及第二绝缘层的材料均为SiNx，x＞0；
    其中，所述半导体层的源/漏极接触区的材料为N型重掺杂硅；所述公共电极、及像素电极的材料均为ITO。
  6. 一种阵列基板结构的制作方法，包括如下步骤：
    步骤1、提供基板，在所述基板上沉积缓冲层；
    步骤2、在所述缓冲层上沉积半导体层，对其进行图案化后，对所述半导体层上的部分区域进行N型重掺杂，形成设计与源/漏极相接触的源/漏极接触区；
    步骤3、在所述半导体层上依次沉积栅极绝缘层、及层间介电层，同时对栅极绝缘层、及层间介电层进行图案化，在所述栅极绝缘层、及层间介电层上对应所述半导体层的源/漏极接触区上方形成第一过孔；
    步骤4、在所述层间介电层上方沉积第一金属层，并对其进行图案化，形成源/漏极，所述源/漏极经由所述第一过孔与所述半导体层的源/漏极接触区相接触；
    步骤5、在所述源/漏极、及层间介电层上方沉积平坦层；
    步骤6、在所述平坦层上方沉积第二金属层，并对其进行图案化；
    步骤7、在所述第二金属层、及平坦层上方沉积第一绝缘层，并对其进行图案化，在所述第一绝缘层上对应所述第二金属层上方形成第二过孔；
    步骤8、在所述第一绝缘层上方沉积第一氧化物导电层，并对其进行图案化，形成公共电极，所述公共电极经由所述第二过孔与所述第二金属层相接触；
    步骤9、在所述公共电极、及第一绝缘层上方沉积抗还原层；
    步骤10、在所述抗还原层上沉积第二绝缘层，同时对所述第二绝缘层、抗还原层、第一绝缘层、及平坦层进行图案化，在所述第二绝缘层、抗还原层、第一绝缘层、及平坦层对应所述源/漏极上方形成第三过孔；
    步骤11、在所述第二绝缘层上沉积第二氧化物导电层，并对其进行图案化，形成像素电极，所述像素电极经由所述第三过孔与所述源/漏极相接触。
  7. 如权利要求6所述的阵列基板结构的制作方法，其中，所述步骤9采用等离子体增强化学气相沉积法形成所述抗还原层。
  8. 如权利要求7所述的阵列基板结构的制作方法，其中，所述步骤9具体包括：
    步骤91、在所述公共电极表面通入沉积SiO2的气体，生成一SiO2薄层；
    步骤92、缓慢关闭沉积SiO2的气体的同时逐渐通入沉积SiNx的气体，所述沉积SiO2的气体通入的量逐渐减少至零，同时沉积SiNx的气体通入的量逐渐增多，从而在所述公共电极上得到成分渐变的SiNxOy层，x≥0，0≤y≤2，从公共电极开始向上生长的方向上，x从0开始逐渐增大，y从2开始逐渐减小至0，所述成分渐变的SiNxOy层即为抗还原层。
  9. 如权利要求8所述的阵列基板结构的制作方法，其中，所述沉积SiO2的气体为TEOS和O2，所述沉积SiNx的气体为SiH4、NH3、及N2。
  10. 如权利要求6所述的阵列基板结构的制作方法，其中，所述第一绝缘层、及第二绝缘层的材料均为SiNx，x＞0。
  11. 如权利要求6所述的阵列基板结构的制作方法，其中，所述半导体层的源/漏极接触区的材料为N型重掺杂硅；所述公共电极、及像素电极的材料均为ITO。
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