WO2016176807A1 - 一种dram刷新方法、装置和系统 - Google Patents

一种dram刷新方法、装置和系统 Download PDF

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Publication number
WO2016176807A1
WO2016176807A1 PCT/CN2015/078224 CN2015078224W WO2016176807A1 WO 2016176807 A1 WO2016176807 A1 WO 2016176807A1 CN 2015078224 W CN2015078224 W CN 2015078224W WO 2016176807 A1 WO2016176807 A1 WO 2016176807A1
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Prior art keywords
refresh
refreshed
block
dram
refreshing
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PCT/CN2015/078224
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English (en)
French (fr)
Inventor
肖世海
黄永兵
何睿
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华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2015/078224 priority Critical patent/WO2016176807A1/zh
Priority to EP15891059.6A priority patent/EP3279899B1/en
Priority to CN201580001215.8A priority patent/CN107077882B/zh
Publication of WO2016176807A1 publication Critical patent/WO2016176807A1/zh
Priority to US15/802,781 priority patent/US10586608B2/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/783—Masking faults in memories by using spares or by reconfiguring using programmable devices with refresh of replacement cells, e.g. in DRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40622—Partial refresh of memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40607—Refresh operations in memory devices with an internal cache or data buffer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618—Refresh operations over multiple banks or interleaving
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the embodiments of the present invention relate to the field of memory, and in particular, to a method, an apparatus, and a system for refreshing a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • a DRAM memory cell uses a capacitor to represent a data bit by means of whether or not to store power.
  • the amount of capacitance stored in the capacitor leaks over time, causing a change in data bits, so DRAM needs
  • the capacitance of the stored data is periodically refreshed to ensure the integrity of the memory data.
  • the refresh interval of each DRAM cell needs to meet the requirements of the DRAM standard, and the specific time of the refresh interval is determined by the type of DRAM and the operating temperature.
  • DRAM When DRAM is refreshed, it takes up system time and generates a lot of power, which is contrary to the demand for faster processing speed and lower power consumption in today's computers.
  • embodiments of the present invention provide a DRAM refresh method, apparatus, and system, which can implement refreshing of a specified location of a DRAM memory array, and a refresh region of a DRAM memory array to be refreshed can be specified in a refresh command.
  • an embodiment of the present invention provides a dynamic random access memory DRAM refresh method.
  • the DRAM memory array includes at least two bank banks, and the row of the DRAM memory array includes bank rows corresponding to the at least two banks, and the DRAM
  • the storage array is divided into at least two refresh block blocks, each block including at least two rows of the DRAM storage array, including: the DRAM refresh device receives a refresh command from the memory controller, the refresh command including an identifier of the block to be refreshed And refresh information for indicating an area to be refreshed, the refresh instruction is used to instruct the DRAM refreshing device to refresh the area to be refreshed in the block to be refreshed; the DRAM refreshing device is based on the identifier And generating, by the refresh information, an address of a bank row to be refreshed in the block to be refreshed; The DRAM refresh device refreshes a location corresponding to an address of the bank row in the block to be refreshed.
  • the refresh information includes first indication information and second indication information, where the first indication information is used to indicate a block to be refreshed in the block to be refreshed.
  • the second indication information is used to indicate a bank to be refreshed.
  • the DRAM refreshing device refreshing a location corresponding to an address of the bank row in the block to be refreshed includes: The DRAM refreshing device refreshes the location corresponding to the address of the bank row in N refresh stages according to the number M of block rows to be refreshed in the block to be refreshed, where the locations of the same block row are in the same location Parallel refresh in the refresh phase, where M is a positive integer greater than 0 and N is a positive integer greater than 0 and less than or equal to M.
  • the refresh information further includes a row merge identifier, configured to indicate that the DRAM refresh device refreshes in the same refresh phase At least two block lines in the refreshed block are mentioned, the N being less than M.
  • the refresh information further includes a termination identifier, where the termination identifier is used to indicate that the DRAM refresh device is in the indicated block After the refresh of the row ends, the refresh of the block to be refreshed is terminated; the method further includes: the DRAM refreshing device terminates refreshing the block to be refreshed according to the termination identifier.
  • the refresh information further includes a suspension identifier, where the suspension identifier is used to indicate that the DRAM refresh device is in the indicated block After the refresh of the row is completed, the refresh of the block to be refreshed is suspended; the method further includes: the DRAM refreshing device suspending refreshing of the block to be refreshed according to the suspension identifier.
  • the method further includes: the DRAM refreshing device recovers the suspended refresh of the to-be-refreshed block, and continues Refresh the remaining block lines to be refreshed.
  • an embodiment of the present invention provides a dynamic random access memory DRAM refreshing method, where a DRAM memory array includes at least two bank banks, and rows of the DRAM memory array include bank rows corresponding to the at least two banks, and DRAM
  • the storage array is divided into at least two refresh block blocks, each block containing at least two rows of the DRAM storage array, including: the memory controller determines to be refreshed a block, and an area to be refreshed in the block to be refreshed; the memory controller sends a refresh command to the DRAM refreshing device, where the refresh command includes an identifier of the block to be refreshed, and refresh information for indicating an area to be refreshed.
  • the refresh information includes first indication information and second indication information, where the first indication information is used to indicate a block to be refreshed in the block to be refreshed.
  • the second indication information is used to indicate a bank to be refreshed.
  • the refresh information further includes a row merge identifier, configured to indicate that the DRAM refresh device is refreshed in parallel in the same refresh phase At least two block lines in the block to be refreshed.
  • the refresh information further includes a termination identifier, where the termination identifier is used to indicate that the DRAM refresh device is in the indicated block After the refresh of the row ends, the refresh of the block to be refreshed is terminated.
  • the refresh information further includes a suspension identifier, where the suspension identifier is used to indicate that the DRAM refresh device is in the indicated block After the refresh of the row ends, the refresh of the block to be refreshed is suspended.
  • an embodiment of the present invention provides a dynamic random access memory DRAM refreshing apparatus, where a DRAM memory array includes at least two banks, and a row of the DRAM memory array includes a bank row corresponding to each of the at least two banks, and a DRAM
  • the storage array is divided into at least two refresh block blocks, each block including at least two rows of the DRAM storage array, including: a receiving unit, configured to receive a refresh instruction from a memory controller, where the refresh command includes a block to be refreshed And the refreshing information for indicating the area to be refreshed, the refreshing instruction is used to instruct the DRAM refreshing device to refresh the area to be refreshed in the block to be refreshed, and a generating module, configured to The identifier and the refresh information are generated, and the address of the bank row to be refreshed in the block to be refreshed is generated; and the refreshing unit is configured to refresh the location corresponding to the address of the bank row in the block to be refreshed.
  • the refresh information includes first indication information and second indication information, where the first indication information is used to indicate a block to be refreshed in the block to be refreshed.
  • the second indication information is used to indicate a bank to be refreshed.
  • the refreshing unit is configured to refresh a location corresponding to an address of the bank row in the to-be-refreshed block, including: The refreshing unit refreshes the location corresponding to the address of the bank row in N refresh stages according to the number M of block rows to be refreshed in the block to be refreshed, the location is in the middle position The positions of the same block row are refreshed in parallel in the same refresh phase, where M is a positive integer greater than 0, and N is a positive integer greater than 0 and less than or equal to M.
  • the refresh information further includes a line merge identifier, where the refresh unit is configured to refresh the At least two block lines in the block to be refreshed, the N being less than M.
  • the refreshing information further includes a termination identifier, where the termination identifier is used to indicate that the refreshing unit is in the indicated block row After the refreshing is completed, the refreshing of the block to be refreshed is terminated; the refreshing unit is further configured to terminate the refreshing of the block to be refreshed according to the termination identifier.
  • the refresh information further includes a suspension identifier, where the suspension identifier is used to indicate that the refresh unit is in the indicated block row After the refreshing is completed, the refreshing of the block to be refreshed is suspended; the refreshing unit is further configured to suspend the refreshing of the block to be refreshed according to the suspension identifier indication.
  • the refreshing unit is further configured to resume the suspended refresh of the to-be-refreshed block, and continue to refresh the remaining to-be-supplied Refreshed block line.
  • an embodiment of the present invention provides a dynamic random access memory (DRAM) DRAM chip, comprising: a DRAM memory array, and a DRAM refresh device according to any one of the third aspect or the third aspect, wherein the DRAM refresh A device is configured to refresh the DRAM memory array.
  • DRAM dynamic random access memory
  • an embodiment of the present invention provides a DRAM refresh control apparatus, where a DRAM memory array includes at least two bank banks, and a row of the DRAM memory array includes respective bank rows of the at least two banks, and the DRAM storage array is divided into At least two refresh block blocks, each block comprising at least two rows of the DRAM memory array, comprising: a determining unit, configured to determine a block to be refreshed, and an area to be refreshed in the block to be refreshed; a sending unit, And a method for transmitting a refresh instruction to the DRAM refreshing device, where the refresh instruction includes an identifier of a block to be refreshed, and refresh information for indicating an area to be refreshed.
  • the refresh information includes first indication information and second indication information, where the first indication information is used to indicate a block to be refreshed in the block to be refreshed.
  • the second indication information is used to indicate a bank to be refreshed.
  • the refresh information further includes a row merge identifier, where the DRAM refresh device is in the same At least two block lines in the block to be refreshed are refreshed in parallel in the refresh phase.
  • the refresh information further includes a termination identifier, where the termination identifier is used to indicate that the DRAM refresh device is in the indicated block After the refresh of the row ends, the refresh of the block to be refreshed is terminated.
  • the refresh information further includes a suspension identifier, where the suspension identifier is used to indicate that the DRAM refresh device is in the indicated block After the refresh of the row ends, the refresh of the block to be refreshed is suspended.
  • an embodiment of the present invention provides a DRAM refresh system, including a memory controller, a DRAM refresh device, and a DRAM memory array.
  • the DRAM memory array includes at least two bank banks, and the row of the DRAM memory array includes the at least two Each bank row corresponding to the bank, the DRAM memory array is divided into at least two refresh block blocks, each block containing at least two rows of the DRAM memory array,
  • the memory controller is configured to determine a block to be refreshed, and an area to be refreshed in the block to be refreshed, and send a refresh instruction to the DRAM refreshing device, where the refresh instruction includes an identifier of a block to be refreshed, and And the DRAM refreshing device is configured to generate, according to the identifier and the refresh information, an address of a bank row to be refreshed in the block to be refreshed, and refresh the to-be-refreshed The location of the address of the bank row in the block.
  • the refresh information includes first indication information and second indication information, where the first indication information is used to indicate a block to be refreshed in the block to be refreshed.
  • the second indication information is used to indicate a bank to be refreshed.
  • the DRAM refreshing device refreshing a location corresponding to an address of the bank row in the block to be refreshed includes: The DRAM refreshing device refreshes the location corresponding to the address of the bank row in N refresh stages according to the number M of block rows to be refreshed in the block to be refreshed, where the locations of the same block row are in the same location Parallel refresh in the refresh phase, where M is a positive integer greater than 0 and N is a positive integer greater than 0 and less than or equal to M.
  • the refresh information further includes a row merge identifier, configured to indicate that the DRAM refresh device refreshes in the same refresh phase At least two block lines in the refreshed block are mentioned, the N being less than M.
  • the refresh information further includes a termination identifier, where the termination identifier is used to indicate the DRAM refresh loading After the refresh of the indicated block row ends, the refresh of the block to be refreshed is terminated; the method further includes: the DRAM refreshing device terminates refreshing the block to be refreshed according to the termination identifier .
  • the refresh information further includes a suspension identifier, where the suspension identifier is used to indicate that the DRAM refresh device is in the indicated block After the refresh of the row is completed, the refresh of the block to be refreshed is suspended; the method further includes: the DRAM refreshing device suspending refreshing of the block to be refreshed according to the suspension identifier.
  • the DRAM refreshing apparatus is further configured to resume the suspension of the suspended block to be refreshed, and continue to refresh the remaining The block line to be refreshed.
  • the memory controller can refresh the specified position of the DRAM storage column, thereby implementing a more reasonable configuration DRAM refresh operation, shortening the refresh time of the DRAM memory, and reducing the refresh power consumption. Moreover, the refresh operation is more flexible, and the data integrity is saved, thereby saving system resource consumption.
  • Figure 1 is a block diagram of a DRAM refresh system
  • FIG. 2 is a schematic structural view of a DRAM memory array of the present invention.
  • FIG. 3 is a schematic structural diagram of a DRAM refresh system according to an embodiment of the invention.
  • FIG. 4 is a schematic diagram of a refresh information format according to an embodiment of the invention.
  • FIG. 5 is a schematic diagram of a refresh information format according to an embodiment of the invention.
  • FIG. 6 is a timing chart of DRAM refresh according to an embodiment of the invention.
  • FIG. 7 is a schematic diagram of a refresh information format according to an embodiment of the invention.
  • FIG. 8 is a timing chart of DRAM refresh according to an embodiment of the invention.
  • FIG. 9 is an exemplary flowchart of a DRAM refresh method according to an embodiment of the invention.
  • FIG. 10 is an exemplary flowchart of a DRAM refresh method according to an embodiment of the invention.
  • FIG. 11 is an exemplary flowchart of a DRAM refresh method according to an embodiment of the invention.
  • FIG. 12 is a schematic diagram showing the logical structure of a DRAM refresh device according to an embodiment of the invention.
  • FIG. 13 is a schematic diagram showing the logical structure of a DRAM refresh device according to an embodiment of the invention.
  • DRAM refresh system 100 is comprised of memory array 116, control logic 106, row address decoder 112, column address decoder 114, data column multiplexer 118, control interface 102, address interface 104, and data interface. 120 composition.
  • Figure 1 only provides a relatively simplified DRAM refresh system, and DRAM refresh system 100 is merely an example of a DRAM refresh system.
  • Refresh system 100 may include more or fewer components than shown in Figure 1, or may be different. The way components are configured.
  • the various components shown in Figure 2 can be implemented in hardware, software, or a combination of hardware and software.
  • the memory array 116 shown in FIG. 1 shows only a simple two-dimensional distributed bank, but those skilled in the art will appreciate that the memory array 116 can have multiple implementations, including at least two. Bank, or by configuring a storage array to achieve the same functionality as at least two banks.
  • Each bank of DRAM memory array 116 has its own row address decoder 112 and column address decoder 114 and data column multiplexer 118 and the like.
  • Control interface 102, address interface 104, and data interface 120 collectively provide a communication interface between DRAM refresh system 100 and peripheral devices (not shown) of refresh system 100.
  • Refresh system 100 receives operational instructions for read, write or other operations on the DRAM memory array through control interface 102 coupled to control logic 106.
  • the refresh system 100 receives address information through an address interface 104 coupled to the control logic 106 for indicating which one or which of the DRAM memory arrays to read, write or otherwise operate.
  • the refresh system 100 transfers data stored in the memory array 116 to an external device through at least the data interface 120 coupled to the data column multiplexer 118, or receives data from the external device for storage in the memory array 116.
  • Control logic 106 is used to combine (or not combine) address information received through address interface 104 And/or other information that controls and executes the operational instructions received from control interface 102, the memory cells of memory array 100 are organized in a two-dimensional manner in rows and columns, so control logic passes through row address decoder 112. The row address is transferred, and the column address is transferred to the column address decoder 114 to perform read, write or other operations on a portion of the memory cells of the memory array 116, wherein the row address decoder 112 and the column address decoder 114 are respectively associated with the control logic. 106 coupled. Row address decoder 112 decodes the row address received from control logic 106 and selects a row of memory cells in memory array 116 for access using the decoded row address.
  • column address decoder 114 decodes the column address received from control logic 106 and uses the decoded column address to control data column multiplexer 118 (data column multiplexer 118 and column address decoder). 114 is coupled to select one (or some) of the memory cells from the row selected by the row address decoder 112 for access.
  • the DRAM refresh device 108 controls the components of the logic 106. Upon receiving the refresh command, the DRAM refresh device 108 refreshes the memory row in the memory array 116 indicated by the refresh command in accordance with the instruction of the refresh command. In one refresh operation, the DRAM refresh device 108 only refreshes the refresh line to indicate the memory line to be refreshed, skips the memory line that is not to be refreshed, and thus avoids unnecessary consumption caused by refreshing the line that is not to be refreshed. For the row to be refreshed in a refresh operation, the DRAM refresh device 108 uses the row address decoder 112 to select the row to be refreshed from the memory array 116. In a refresh operation, which rows in the memory array 116 need to be refreshed and which rows do not need to be refreshed are specified in a refresh instruction by an external device (not shown) coupled to the DRAM refresh system 100. dispatched.
  • the one-time refresh operation is completed by the following steps: the DRAM refresh system 100 receives the refresh instruction through the control interface 102 and the address interface 104, and the information transmitted by the control interface is used to indicate that the instruction is a refresh instruction, and the address interface The communicated information is used to indicate location information that needs to be refreshed, the refresh instruction indicating refreshing one or more rows of memory cells in the memory array 116.
  • the DRAM refresh system 100 receives the refresh command through the address interface 104.
  • the DRAM refresh system 100 is in the form of a refresh command, and determines that the instruction is a refresh command.
  • the refresh command is used to indicate location information that needs to be refreshed, and the refresh command indicates refresh.
  • the DRAM refresh system can receive the refresh command through other channels or bus interfaces (not shown), which is not limited by the embodiment of the present invention.
  • an address information is generated by the counter 110, and the generated address information is sent to the DRAM refresh device 108.
  • the refresh control logic refreshes all the rows indicated by the address information, and the counter 110 performs an increment operation to indicate in the next cycle. Refresh another portion of the storage row.
  • the memory array 116 includes at least two banks, which are logically arranged by at least two banks, for convenience of description. 2 is illustrated by taking four banks as an example, but the embodiment of the present invention is not limited thereto, the storage array 116 may include more or less banks, and the four banks included in the storage array 116 are arranged in a two-dimensional manner, and the storage array 116 is arranged.
  • the first row contains the first row of bank0, the first row of bank1, the first row of bank2, and the first row of bank3.
  • the second row of storage array 116 contains the second row of bank0, the second row of bank1, and bank2. The second line and the second line of bank3, and so on.
  • the storage array 116 is divided into at least two refresh blocks. As shown in FIG. 2, the refresh block includes multiple rows of the storage array 116. For convenience of description, one refresh block in FIG. 2 includes four rows of the storage array 116, but the present invention is not limited thereto. Thus, one refresh block can contain more or fewer storage rows of the storage array 116. Each refresh block has its own address identifier, and the refresh system 100 refreshes the memory array 116 in units of refresh blocks.
  • the DRAM refresh device 108 includes a refresh block from the refresh command received by the memory controller coupled to the DRAM refresh system 100.
  • the address identifier optionally, the address identifier of the refresh block may be indicated by the address of the first bank row in the first row of the refresh block.
  • the DRAM refresh system 300 includes a memory controller 302, a DRAM refresh device 108, and a DRAM memory array 116.
  • the DRAM memory array 116 is at least The two banks are logically arranged horizontally.
  • the row of the DRAM memory array includes respective bank rows of the at least two banks, and the DRAM memory array is divided into at least two refresh block blocks, each block containing at least two of the DRAM memory arrays. Two lines.
  • the memory controller 302 maintains refresh operation related information of the DRAM storage array 116, and is configured to determine a block to be refreshed according to the refresh operation related information, and an area to be refreshed in the block to be refreshed.
  • the area to be refreshed includes a block line to be refreshed in the block to be refreshed, and a bank line to be refreshed in the block line to be refreshed.
  • the memory controller 302 is further configured to generate a refresh instruction, where the refresh instruction includes an identifier of the block to be refreshed, and refresh information for indicating an area to be refreshed, where the refresh instruction is used to instruct the DRAM refresh device to refresh the to-be refreshed The area to be refreshed in the block.
  • the refresh operation related information includes whether the storage unit of the storage array 116 has data retention and/or storage unit retention time, and the DRAM without data may not be refreshed, and the DRAM unit with a long retention time may be smaller.
  • the refresh frequency is refreshed, and the DRAM memory cell with short retention time can be refreshed with a large refresh frequency, thereby achieving a more reasonable configuration of the DRAM refresh operation, shortening the refresh time of the DRAM memory, reducing the refresh power consumption, and Refresh operation is more Flexible, and ensure data integrity, saving system resources.
  • the generated refresh command is transmitted to the DRAM refresh device 108.
  • the DRAM refreshing device 108 After receiving the refresh command from the memory controller 302, the DRAM refreshing device 108 generates an address of the bank row to be refreshed in the block to be refreshed according to the identifier and the refresh information, and refreshes the block to be refreshed. The location of the address of the bank row in the corresponding location.
  • the refresh information includes first indication information and second indication information, where the first indication information is used to indicate a block row to be refreshed in the block to be refreshed, and the second indication information is used to indicate The bank to be refreshed.
  • the DRAM refresh device 108 can receive the refresh command through the control interface 102 and the address interface 104 as shown in FIG. 1, and receive the instruction identifier through the control interface 102, where the instruction identifier is used to indicate that the command is a refresh command and passes
  • the address interface receives the identifier of the block and the refresh information.
  • the refresh information is as shown in FIG. 4, and the refresh information includes the block internal address identifier, and which bank lines in each block row need to be refreshed, and which bank lines are not to be refreshed, as shown in FIG. 4,
  • the refresh information indicates that the row corresponding to bank0 and bank2 in the first row of the block does not need to be refreshed, and the row corresponding to bank1 and bank3 needs to be refreshed;
  • the bank0 and bank2 corresponding to the second row of the block correspond to The row needs to be refreshed, and the row corresponding to bank1 and bank3 does not need to be refreshed;
  • the address information of the third row of the block is not included in the refresh information, indicating that all bank rows in the third row of the block do not need to be refreshed; all in the fourth row of the block The row corresponding to the bank needs to be refreshed.
  • FIG. 4 is only an exemplary format of the refresh information, and the purpose is to indicate the bank row to be refreshed in the block, but the format of the refresh information in the embodiment of the present invention is not limited
  • FIG. 5 is another form of refresh information.
  • the refresh information may be in the format shown in FIG. 5.
  • the refresh information is a logical 2-dimensional array, and its structure is similar to that of the block. As shown in FIG. 5, it is still described based on the embodiment of FIG. 2, and the refresh information indicates bank0 and bank2 in the first row of the block.
  • FIG. 5 is only an exemplary format of the refresh information, and the purpose is to indicate the bank row to be refreshed in the block.
  • the format of the refresh information in the embodiment of the present invention is not limited thereto, and more or less technologies may be used. feature.
  • the DRAM storage array 116 can be selectively refreshed by the memory controller to maintain the refresh information.
  • the bank row can be refreshed.
  • the interval of the refresh operation can be increased, thereby greatly reducing the power consumption and performance overhead of the memory refresh.
  • at least two bank rows to be refreshed can be indicated in one refresh instruction at a time, and compression of the refresh command is implemented, and the overhead of the address bus is reduced.
  • the DRAM refreshing device refreshing the location corresponding to the address of the bank row in the block to be refreshed includes: the number of block rows to be refreshed by the DRAM refreshing device according to the block to be refreshed Refreshing the location corresponding to the address of the bank row in N refresh phases, where the locations of the same block row are refreshed in parallel in the same refresh phase, where M is a positive integer greater than 0, and N is greater than 0. And a positive integer less than or equal to M.
  • the one-time refresh information may carry the refresh information of multiple rows in one block, thereby realizing the compression of the refresh address and saving the pressure of the address bus.
  • the memory controller can refresh the specified position of the DRAM storage column, thereby realizing a more reasonable configuration DRAM refresh operation, shortening the refresh time of the DRAM memory, reducing the refresh power consumption, and making the refresh operation more flexible and ensuring data. Under the premise of integrity, the consumption of system resources is saved.
  • FIG. 6 is a timing chart of a DRAM refresh according to an embodiment of the present invention. For convenience of description, the present embodiment is described by taking the refresh information shown in FIG. 4 as an example.
  • the DRAM refresh device 108 After receiving the refresh command, the DRAM refresh device 108 first according to the Determining an identifier of the refreshed block and the refresh information, and generating an address of the bank row to be refreshed in the block to be refreshed.
  • the DRAM refresh device 108 refreshes the first row of the block. Specifically, the DRAM refresh device 108 transmits the addresses of the bank rows corresponding to bank1 and bank3 in the first row of the block respectively.
  • the row address decoder 112 for bank1 and bank3 refreshes the bank rows corresponding to bank1 and bank3 in the first block row in parallel in the first refresh phase.
  • the DRAM refresh device 108 sends the refresh address of the second refresh phase, that is, the DRAM refresh device 108 blocks.
  • the bank row addresses corresponding to bank0 and bank2 in the second row are respectively sent to the row address decoders 112 of bank0 and bank2, and the bank rows corresponding to bank0 and bank2 in the second block row are refreshed in parallel in the second refresh phase.
  • the DRAM refresh device skips the block row that is not to be refreshed, and refreshes the fourth row of the block in the third refresh phase, according to
  • the refresh information indicates that all the bank lines in the fourth block row need to be refreshed, and the DRAM refresh device sends the addresses of all the bank rows corresponding to the fourth row of the block to the row address decoder 112 corresponding to each bank, in the third refresh.
  • the stage refreshes all bank lines in the fourth row of the block in parallel.
  • the first refresh phase and the last refresh phase in one block may take slightly longer than other refresh phases.
  • the DRAM refreshing device sends the bank row address in each block row of the block to the corresponding row address decoder 112, and further selects according to the refresh information.
  • the refresh of the bank row is enabled, and the bank row to be refreshed is refreshed, and the bank row that is not to be refreshed is not refreshed.
  • the DRAM refreshing device 108 can skip the block that is not to be refreshed, thereby saving the refresh time and the refresh power consumption. Moreover, in a refresh phase, since the refresh information is sent to the information of whether each bank is refreshed in the block row, the DRAM refresh device 108 can also skip the bank row in the block row that is not to be refreshed, thereby saving power consumption.
  • the refresh information further includes a row merge identifier, configured to instruct the DRAM refresh device to refresh at least two block rows in the block to be refreshed in a same refresh phase, where N is less than M.
  • a row merge identifier configured to instruct the DRAM refresh device to refresh at least two block rows in the block to be refreshed in a same refresh phase, where N is less than M.
  • the DRAM refreshing device further merges and refreshes the at least two block rows to be refreshed according to the row merge identifier indication, and refreshes the at least two block rows to be refreshed in a refresh phase in parallel to be refreshed. Bank line.
  • FIG. 7 is a refresh information format according to an embodiment of the present invention.
  • a refresh phase number is added on the basis of FIG. 4, and a refresh phase number is used as a row merge identifier to indicate that the DRAM refresh device will have at least two to be refreshed.
  • Block line merge refresh As shown in Figure 7, because the bank row corresponding to bank1 and bank3 of the first block row needs to be refreshed, and the bank0 and bank2 pairs of the second block are The bank line should be refreshed, because the banks of the bank row to be refreshed in the first block row and the second block row do not overlap, then the two block rows can be merged and refreshed, according to the refresh phase number indication, at the first The first row and the second row of the block are refreshed in parallel during the refresh phase.
  • FIG. 7 is only an exemplary description of the refresh information format with the line merge identifier. However, the format of the refresh information in the embodiment of the present invention is not limited thereto, and there may be more or less technical features or other manners.
  • the DRAM refresh timing chart corresponding to FIG. 7 is as shown in FIG. 8.
  • the DRAM refresh device 108 After receiving the refresh command with the refresh information shown in FIG. 7 from the memory controller 302, the DRAM refresh device 108 firstly according to the block identifier and the buffer identifier included in the refresh command.
  • the refresh information generates a bank row address to be refreshed, and according to the refresh information indication, the DRAM refresh device sends the address of the bank row corresponding to bank1 and bank3 in the first row of the first block to the row address of bank1 and bank3 in the first refresh phase.
  • the encoder 112 sends the addresses of the bank lines corresponding to bank0 and bank2 in the first row of the first block to the row address decoder 112 of bank0 and bank2, respectively, and completes the first row and the first block in the first refresh phase.
  • the second line of the second block is refreshed. Because the identifier of the third row of the row block is not reported in the refresh information, it indicates that all the bank rows in the third row of the third block do not need to be refreshed in the current refresh operation, and the DRAM refresh device 108 skips the third row of the third block. Refresh the fourth line of the fourth block.
  • the bank row address to be refreshed in the fourth row of the fourth block can be sent to the corresponding row address decoder 112 before the first refresh phase is not actually completed.
  • the address of the bank row corresponding to bank0, bank1, bank2, and bank3 in the fourth row of the fourth block is sent to the row address decoder 112 of bank0, bank1, bank2, and bank3, respectively, and the fourth block is completed in the second refresh phase. The refresh of the line.
  • At least two block rows that do not coincide with the bank row corresponding to the bank row to be refreshed can be merged and refreshed, thereby saving the refresh phase, thereby reducing the power consumption and delay of the refresh operation.
  • the refresh information further includes a termination identifier, where the termination identifier is used to indicate that the refresh of the block to be refreshed is terminated after the indicated refresh phase ends; the DRAM refresh device 108 is further configured to perform according to the Ending the identification, and after the refresh phase of the indication ends, the refresh of the block to be refreshed is terminated.
  • the memory controller 302 controls the refresh operation and the read and write operations on the DRAM storage array 116, and performs unified time planning on the operation of the DRMA storage array 116. Since the priority of the read and write operations is generally higher than the refresh operation, the memory controller 302 can Flexible planning of operation of the DRAM memory array 116, The refresh of the DRAM memory array 116 may be terminated after a refresh phase of the block refresh process is completed, and the clock cycle is given to the read and write operations.
  • the memory controller 302 may add a termination identifier after a refresh phase in the refresh information of the refresh command, and the DRAM refresh device 108 terminates the refresh of the block after the indicated refresh phase ends according to the termination identifier.
  • the clock cycle is given to the DRAM read and write operations.
  • the memory controller 302 can resend the DRAM refresh device 108 a new refresh command to instruct to refresh the remaining block lines that have not been refreshed.
  • the refresh of the block may be ended before the end of a certain refreshing phase, so that the memory can be accessed normally, and after the read and write operations are finished,
  • the refresh command is resent by the memory controller 302 to the DRAM refresh device 108, instructing to refresh the block line that the block has not refreshed.
  • the refresh information further includes a suspension identifier, where the suspension identifier is used to indicate that the refresh of the block to be refreshed is suspended after the indicated refresh phase ends;
  • the DRAM refreshing device 108 is further configured to: according to the suspension identifier indication, suspend refreshing of the block to be refreshed after the refresh phase of the indication ends.
  • the DRAM refresh device 108 is further configured to resume the suspended refresh of the block to be refreshed, and continue to refresh the remaining block rows to be refreshed.
  • the memory controller 302 may add a suspension identifier after a refresh phase in the refresh information of the refresh command, and the DRAM refresh device 108 stops the refresh of the block after the indicated refresh phase ends according to the suspension identifier.
  • the clock cycle is given to the DRAM read and write operations.
  • the memory controller 302 can send a resume instruction to the DRAM refresh device 108, instructing to resume the refresh of the block, and refreshing the remaining block lines that are not refreshed. It is also possible for the DRAM refresh device 108 to autonomously resume the refresh of the block after waiting for a specific clock cycle, and refresh the remaining block lines that are not refreshed.
  • the refresh of the block may be suspended, so that the memory can be accessed normally, and after the read and write operations are finished, the DRAM is refreshed.
  • Device 108 resumes refreshing the block and continues to flush block lines that have not been refreshed.
  • the refresh information also includes a block merge identifier. If there are fewer bank rows to be refreshed in the adjacent two blocks, the two blocks may be merged and refreshed when refreshed.
  • the offset of the next block can be added to the refresh information, in turn To locate the next block, and add the refresh information of the next block, in order to merge and refresh the two adjacent blocks. This saves a refresh cycle time.
  • FIG. 9 is an exemplary flowchart of a method for refreshing a DRAM according to an embodiment of the present invention.
  • the DRAM memory array includes at least two bank banks, and rows of the DRAM memory array include bank rows corresponding to the at least two banks, and DRAM storage.
  • the array is divided into at least two refresh block blocks, each block containing a plurality of rows of the DRAM memory array, as shown in FIG. 9, the method includes:
  • the DRAM refreshing device receives a refresh command from the memory controller, where the refresh command includes an identifier of a block to be refreshed, and refresh information for indicating an area to be refreshed, where the refresh command is used to indicate the DRAM refreshing device. Refreshing the area to be refreshed in the block to be refreshed;
  • the DRAM refreshing device generates, according to the identifier and the refresh information, an address of a bank row to be refreshed in the block to be refreshed;
  • the DRAM refreshing device refreshes a location corresponding to an address of the bank row in the block to be refreshed.
  • the refresh information includes first indication information and second indication information, where the first indication information is used to indicate a block row to be refreshed in the block to be refreshed, and the second indication information is used to indicate The bank to be refreshed.
  • the DRAM refreshing device can receive the refresh instruction through the control interface 102 and the address interface 104 as shown in FIG. 1, and receive the instruction identifier through the control interface 102.
  • the instruction identifier is used to indicate that the instruction is a refresh command and passes the address.
  • the interface receives the identifier of the block and the refresh information.
  • the DRAM refreshing device refreshing the location corresponding to the address of the bank row in the block to be refreshed includes: the DRAM refreshing device is divided into N according to the number M of block rows to be refreshed in the block to be refreshed
  • the refresh phase refreshes the location corresponding to the address of the bank row, where the location of the same block row is refreshed in parallel in the same refresh phase, where M is a positive integer greater than 0, and N is greater than 0 and less than or equal to M Positive integer.
  • the DRAM refreshing device receives a refresh command from the memory controller, where the refresh command includes an address of the block to be refreshed and refresh information of the block, and the refresh information includes an indication identifier of the block row to be refreshed, and the block row to be refreshed is to be refreshed.
  • the indicator of the refreshed bank line includes
  • the DRAM refresh device latches the refresh address of the block address and the block according to the refresh instruction. interest.
  • the DRAM refresh device searches for the refresh information, determines whether there is a block line to be refreshed, and if yes, executes step 1008. If not, executes step 1012 to end the current refresh operation.
  • the DRAM refresh device searches for a block line to be refreshed according to the address sequence of the block row.
  • the DRAM refreshing device combines the block address and the identifier of the block row, and generates a bank row address to be refreshed in the block row according to the indication of the bank row to be refreshed in the block row.
  • the DRAM refresh device sends the generated bank row address to the row address decoder of each corresponding bank, refreshes the bank row to be refreshed in the block row in parallel, completes refreshing the block row, and deletes the latched Regarding the refresh information of the block line, the process returns to step 1006.
  • the refresh information further includes a row merge identifier, configured to instruct the DRAM refresh device to refresh at least two block rows in the block to be refreshed in a same refresh phase, where M is greater than 0.
  • M is greater than 0.
  • a positive integer, N is a positive integer greater than 0 and less than M.
  • the refresh information further includes a termination identifier, where the termination identifier is used to instruct the DRAM refreshing device to terminate refreshing the block to be refreshed after the refresh of the indicated block row ends;
  • the method further includes: the DRAM refreshing device terminating refreshing of the block to be refreshed according to the termination identifier.
  • the refresh information further includes a suspension identifier, where the suspension identifier is used to instruct the DRAM refreshing device to suspend refreshing the block to be refreshed after the refresh of the indicated block row ends;
  • the method further includes: the DRAM refreshing device suspending refreshing of the block to be refreshed according to the suspension identifier.
  • the method 900 further includes the DRAM refresh device restoring the suspended refresh of the block to be refreshed, and continuing to refresh the remaining block rows to be refreshed.
  • the DRAM memory array includes at least two bank banks, and rows of the DRAM memory array include respective bank rows of the at least two banks, and DRAM storage.
  • the array is divided into at least two refresh block blocks, each block containing a plurality of rows of the DRAM memory array, as shown in FIG. 11, the method includes:
  • the memory controller determines a block to be refreshed, and an area to be refreshed in the block to be refreshed;
  • the memory controller maintains refresh operation related information of the DRAM storage array, and is configured to determine a block to be refreshed according to the refresh operation related information, and an area to be refreshed in the block to be refreshed.
  • the area to be refreshed may include a block line to be refreshed in the block to be refreshed, and a bank line to be refreshed in the block line to be refreshed.
  • the refresh operation related information includes whether the storage unit of the storage array has data retention and/or a retention time of the storage unit, and the bank row without data may not be refreshed, and the storage unit with a long retention time may be smaller.
  • the refresh rate is refreshed, and the memory cell with short retention time can be refreshed with a large refresh frequency, thereby achieving a more reasonable configuration of the DRAM refresh operation, shortening the refresh time of the DRAM memory, reducing the refresh power consumption, and refreshing
  • the operation is more flexible, and the data resource consumption is saved under the premise of ensuring data integrity.
  • the memory controller sends a refresh instruction to the DRAM refresh device, where the refresh command includes an identifier of the block to be refreshed, and refresh information for indicating an area to be refreshed.
  • the refresh information includes first indication information and second indication information, where the first indication information is used to indicate a block row to be refreshed in the block to be refreshed, and the second indication information is used to indicate The bank to be refreshed.
  • the refresh information further includes a row merge identifier, configured to instruct the DRAM refresh device to refresh at least two block rows in the block to be refreshed in parallel in the same refresh phase.
  • a row merge identifier configured to instruct the DRAM refresh device to refresh at least two block rows in the block to be refreshed in parallel in the same refresh phase.
  • the refresh information further includes a termination identifier, where the termination identifier is used to instruct the DRAM refreshing device to terminate refreshing the block to be refreshed after the refresh of the indicated block row ends.
  • the refresh information further includes a suspension identifier, where the suspension identifier is used to instruct the DRAM refreshing device to suspend refreshing of the block to be refreshed after the refresh of the indicated block row ends.
  • FIG. 12 is a schematic diagram showing the logical structure of a DRAM refresh device 1200 according to an embodiment of the present invention.
  • the DRAM memory array includes at least two banks, and the rows of the DRAM memory array include bank rows corresponding to the at least two banks, and the DRAM memory array.
  • the receiving unit 1202 is configured to receive a refresh instruction from the memory controller, where the refresh instruction includes an identifier of a block to be refreshed, and refresh information for indicating an area to be refreshed, where the refresh instruction is used to indicate the DRAM refresh
  • the device refreshes the area to be refreshed in the block to be refreshed;
  • a generating unit 1204 configured to generate, according to the identifier and the refresh information, an address of a bank row to be refreshed in the block to be refreshed;
  • the refreshing unit 1206 is configured to refresh a location corresponding to an address of the bank row in the block to be refreshed.
  • the refresh information includes first indication information and second indication information, where the first indication information is used to indicate a block row to be refreshed in the block to be refreshed, and the second indication information is used to indicate The bank to be refreshed.
  • the receiving unit 1202 can receive the refresh instruction through the control interface 102 and the address interface 104 as shown in FIG. 1, and receive the instruction identifier through the control interface 102.
  • the instruction identifier is used to indicate that the instruction is a refresh instruction and passes the address.
  • the interface receives the identifier of the block and the refresh information.
  • the refreshing unit 1206 is configured to refresh the location of the address of the bank row in the block to be refreshed, and the refreshing unit 1206 is configured according to the number M of block rows to be refreshed in the block to be refreshed.
  • N refresh phases refresh the locations corresponding to the addresses of the bank rows, where the locations of the same block row are refreshed in parallel in the same refresh phase, where M is a positive integer greater than 0, and N is greater than 0 and less than A positive integer equal to M.
  • the refresh information further includes a row merge identifier, where the refresh unit is configured to refresh at least two block rows in the block to be refreshed in the same refresh phase, where M is greater than 0.
  • An integer, N is a positive integer greater than 0 and less than M.
  • the refreshing unit 1206 is configured to refresh the block to be refreshed according to the address of the bank row to be refreshed, further comprising: the refreshing unit 1206, according to the row merge identifier indication, the at least two to be refreshed The block row merges and refreshes, and in a refresh phase, the bank rows to be refreshed in the at least two block rows to be refreshed are refreshed in parallel.
  • the refresh information further includes a termination identifier, where the termination identifier is used to instruct the refresh unit to terminate refreshing the block to be refreshed after the refresh of the indicated block row ends; 1206 is further configured to terminate refreshing the block to be refreshed according to the termination identifier.
  • the refresh information further includes a suspension identifier, where the suspension identifier is used to instruct the refresh unit to suspend refreshing the block to be refreshed after the refresh of the indicated block row ends; 1206 is further configured to suspend refreshing the block to be refreshed according to the suspension identifier indication. The refresh unit 1206 is further configured to resume the suspended block to be refreshed. Refresh and continue to refresh the remaining block lines to be refreshed.
  • FIG. 13 is a schematic diagram showing the logical structure of a DRAM refresh device 1300 according to an embodiment of the present invention.
  • the DRAM memory array includes at least two banks.
  • the row of the DRAM memory array includes bank rows corresponding to the at least two banks, and the DRAM memory array.
  • Divided into at least two refresh block blocks, each block containing a plurality of rows of the DRAM memory array, DRAM refreshing means, as shown in FIG. 13, the data transmission device 1300 may include: a determining unit 1302, a transmitting unit 1304.
  • a determining unit 1302 configured to determine a block to be refreshed, and an area to be refreshed in the block to be refreshed;
  • the sending unit 1304 is configured to send a refresh command to the DRAM refreshing device, where the refresh command includes an identifier of the block to be refreshed, and refresh information for indicating an area to be refreshed.
  • the refresh information includes first indication information and second indication information, where the first indication information is used to indicate a block row to be refreshed in the block to be refreshed, and the second indication information is used to indicate The bank to be refreshed.
  • the refresh information further includes a row merge identifier, configured to instruct the DRAM refresh device to refresh at least two block rows in the block to be refreshed in parallel in the same refresh phase.
  • a row merge identifier configured to instruct the DRAM refresh device to refresh at least two block rows in the block to be refreshed in parallel in the same refresh phase.
  • the refresh information further includes a termination identifier, where the termination identifier is used to instruct the DRAM refreshing device to terminate refreshing the block to be refreshed after the refresh of the indicated block row ends.
  • the refresh information further includes a suspension identifier, where the suspension identifier is used to instruct the DRAM refreshing device to suspend refreshing of the block to be refreshed after the refresh of the indicated block row ends.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the modules is only a logical function division, and may be implemented in another manner, for example, multiple modules or components may be combined or may be Integrate into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or module, and may be electrical, mechanical or otherwise.
  • the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, may be located in one place. Or it can be distributed to multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or in the form of hardware plus software function modules.
  • the above-described integrated module implemented in the form of a software function module can be stored in a computer readable memory medium.
  • the software function module described above resides in a memory medium and includes instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform some of the steps of the methods described in various embodiments of the present invention.
  • the foregoing memory medium includes: a mobile hard disk, a read-only memory (English: Read-Only Memory, ROM for short), a random access memory (English: Random Access Memory, RAM), a magnetic disk or an optical disk, and the like.
  • the media for the memory program code includes: a mobile hard disk, a read-only memory (English: Read-Only Memory, ROM for short), a random access memory (English: Random Access Memory, RAM), a magnetic disk or an optical disk, and the like.
  • the media for the memory program code includes: a mobile hard disk, a read-only memory (English: Read-Only Memory, ROM for short

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Abstract

一种DRAM刷新方法、装置和系统，通过在刷新指令中指定一个刷新块block中需要刷新的区域，从而实现对DRAM存储整列的指定位置进行刷新，该方法包括：DRAM刷新装置接收来自内存控制器的刷新指令，所述刷新指令包括待刷新的block的标识，以及用于指示待刷新的区域的刷新信息（S902），所述刷新指令用于指示所述DRAM刷新装置刷新所述待刷新的block中的所述待刷新的区域；所述DRAM刷新装置根据所述标识和所述刷新信息，生成所述待刷新的block中待刷新的bank行的地址（S904）；所述DRAM刷新装置刷新所述待刷新的block中所述bank行的地址对应的位置（S906）。从而缩短了DRAM存储器的刷新时间，降低了刷新功耗，且使刷新操作更加灵活，保证数据完整性的前提下，节省了系统资源的消耗。

Description

一种DRAM刷新方法、装置和系统 技术领域
本发明实施例涉及存储器领域，尤其涉及一种动态随机存取存储器(Dynamic Random Access Memory，DRAM)刷新方法、装置和系统。
背景技术
当今，计算机的主存储器主要采用DRAM存储技术，DRAM存储单元使用一个电容通过是否存储电量的方式表征一个数据位，电容存储的电量会随着时间而泄露，从而造成数据位的变化，所以DRAM需要周期性的对存储数据的电容进行刷新，以保证存储器数据的完整性。
每一个DRAM单元的刷新间隔时间都需要满足DRAM标准的要求，其刷新间隔的具体时间由DRAM的类型和工作温度决定。当DRAM被刷新的时候，会占用系统时间，且会产生大量的功耗，这与当今计算机追求更快的处理速度和更低的功耗的需求相违背。
随着集成电路集成密度的增加，DRAM存储器的存储单元的规模也越来越大，DRAM刷新的延时和功耗问题日益严峻。
发明内容
有鉴于此，本发明实施例提供了一种DRAM刷新方法、装置和系统，可以实现DRAM存储阵列指定位置的刷新，在刷新指令中可以指定待刷新的DRAM存储阵列的刷新区域。
第一方面，本发明实施例提供了一种动态随机存取存储器DRAM刷新方法，DRAM存储阵列包括至少两个库bank，DRAM存储阵列的行包括所述至少两个bank各自对应的bank行，DRAM存储阵列分为至少两个刷新块block，每个block包含所述DRAM存储阵列的至少两行，包括：DRAM刷新装置接收来自内存控制器的刷新指令，所述刷新指令包括待刷新的block的标识，以及用于指示待刷新的区域的刷新信息，所述刷新指令用于指示所述DRAM刷新装置刷新所述待刷新的block中的所述待刷新的区域；所述DRAM刷新装置根据所述标识和所述刷新信息，生成所述待刷新的block中待刷新的bank行的地址； 所述DRAM刷新装置刷新所述待刷新的block中所述bank行的地址对应的位置。
结合第一方面，在第一种可能的实现方式中，所述刷新信息包括第一指示信息和第二指示信息，所述第一指示信息用于指示所述待刷新的block中待刷新的block行，所述第二指示信息用于指示待刷新的bank。
结合第一方面或以上任一种可能的实现方式，在第二种可能的实现方式中，所述DRAM刷新装置刷新所述待刷新的block中所述bank行的地址所对应的位置包括：所述DRAM刷新装置根据所述待刷新的block中待刷新的block行的数目M，分N个刷新阶段刷新所述bank行的地址对应的位置，所述位置中位于同一block行的位置在同一个刷新阶段中并行刷新，其中，M是大于0的正整数，N是大于0并且小于等于M的正整数。
结合第一方面或以上任一种可能的实现方式，在第三种可能的实现方式中，所述刷新信息还包含行合并标识，用于指示所述DRAM刷新装置在同一个刷新阶段中刷新所述待刷新的block中的至少两个block行，所述N小于M。
结合第一方面或以上任一种可能的实现方式，在第四种可能的实现方式中，所述刷新信息还包含终止标识，所述终止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，终止对所述待刷新的block的刷新；所述方法还包括：所述DRAM刷新装置根据所述终止标识，终止对所述待刷新的block的刷新。
结合第一方面或以上任一种可能的实现方式，在第五种可能的实现方式中，所述刷新信息还包含中止标识，所述中止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，中止对所述待刷新的block的刷新；所述方法还包括：所述DRAM刷新装置根据所述中止标识，中止对所述待刷新的block的刷新。
结合第一方面或以上任一种可能的实现方式，在第六种可能的实现方式中，所述方法还包括：所述DRAM刷新装置恢复中止的对所述待刷新的block的刷新，并继续刷新剩余的待刷新的block行。
第二方面，本发明实施例提供了一种动态随机存取存储器DRAM刷新方法，DRAM存储阵列包括至少两个库bank，DRAM存储阵列的行包括所述至少两个bank各自对应的bank行，DRAM存储阵列分为至少两个刷新块block，每个block包含所述DRAM存储阵列的至少两行，包括：内存控制器确定待刷新的 block，以及所述待刷新的block中待刷新的区域；内存控制器向DRAM刷新装置发送刷新指令，所述刷新指令包括待刷新的block的标识，以及用于指示待刷新的区域的刷新信息。
结合第二方面，在第一种可能的实现方式中，所述刷新信息包括第一指示信息和第二指示信息，所述第一指示信息用于指示所述待刷新的block中待刷新的block行，所述第二指示信息用于指示待刷新的bank。
结合第二方面或以上任一种可能的实现方式，在第二种可能的实现方式中，所述刷新信息还包含行合并标识，用于指示所述DRAM刷新装置在同一个刷新阶段中并行刷新所述待刷新的block中的至少两个block行。
结合第二方面或以上任一种可能的实现方式，在第三种可能的实现方式中，所述刷新信息还包含终止标识，所述终止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，终止对所述待刷新的block的刷新。
结合第二方面或以上任一种可能的实现方式，在第四种可能的实现方式中，所述刷新信息还包含中止标识，所述中止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，中止对所述待刷新的block的刷新。
第三方面，本发明实施例提供了一种动态随机存取存储器DRAM刷新装置，DRAM存储阵列包括至少两个库bank，DRAM存储阵列的行包括所述至少两个bank各自对应的bank行，DRAM存储阵列分为至少两个刷新块block，每个block包含所述DRAM存储阵列的至少两行，包括：接收单元，用于接收来自内存控制器的刷新指令，所述刷新指令包括待刷新的block的标识，以及用于指示待刷新的区域的刷新信息，所述刷新指令用于指示所述DRAM刷新装置刷新所述待刷新的block中的所述待刷新的区域；生成模块，用于根据所述标识和所述刷新信息，生成所述待刷新的block中待刷新的bank行的地址；刷新单元，用于刷新所述待刷新的block中所述bank行的地址对应的位置。
结合第三方面，在第一种可能的实现方式中，所述刷新信息包括第一指示信息和第二指示信息，所述第一指示信息用于指示所述待刷新的block中待刷新的block行，所述第二指示信息用于指示待刷新的bank。
结合第三方面或以上任一种可能的实现方式，在第二种可能的实现方式中，所述刷新单元用于刷新所述待刷新的block中所述bank行的地址所对应的位置包括：所述刷新单元根据所述待刷新的block中待刷新的block行的数目M，分N个刷新阶段刷新所述bank行的地址对应的位置，所述位置中位 于同一block行的位置在同一个刷新阶段中并行刷新，其中，M是大于0的正整数，N是大于0并且小于等于M的正整数。
结合第三方面或以上任一种可能的实现方式，在第三种可能的实现方式中，所述刷新信息还包含行合并标识，用于指示所述刷新单元在同一个刷新阶段中刷新所述待刷新的block中的至少两个block行，所述N小于M。
结合第三方面或以上任一种可能的实现方式，在第四种可能的实现方式中，所述刷新信息还包含终止标识，所述终止标识用于指示所述刷新单元在对指示的block行的刷新结束后，终止对所述待刷新的block的刷新；所述刷新单元还用于根据所述终止标识，终止对所述待刷新的block的刷新。
结合第三方面或以上任一种可能的实现方式，在第五种可能的实现方式中，所述刷新信息还包含中止标识，所述中止标识用于指示所述刷新单元在对指示的block行的刷新结束后，中止对所述待刷新的block的刷新；所述刷新单元还用于根据所述中止标识指示，中止对所述待刷新的block的刷新。
结合第三方面或以上任一种可能的实现方式，在第六种可能的实现方式中，所述刷新单元还用于恢复中止的对所述待刷新的block的刷新，并继续刷新剩余的待刷新的block行。
第四方面，本发明实施例提供了一种动态随机存取存储器DRAM芯片，包含DRAM存储阵列和第三方面或第三方面任一种可能的实现方式所述的DRAM刷新装置，所述DRAM刷新装置用于对所述DRAM存储阵列进行刷新。
第五方面，本发明实施例提供了一种DRAM刷新控制装置，DRAM存储阵列包括至少两个库bank，DRAM存储阵列的行包括所述至少两个bank各自对应的bank行，DRAM存储阵列分为至少两个刷新块block，每个block包含所述DRAM存储阵列的至少两行，包括：确定单元，用于确定待刷新的block，以及所述待刷新的block中待刷新的区域；发送单元，用于向DRAM刷新装置发送刷新指令，所述刷新指令包括待刷新的block的标识，以及用于指示待刷新的区域的刷新信息。
结合第五方面，在第一种可能的实现方式中，所述刷新信息包括第一指示信息和第二指示信息，所述第一指示信息用于指示所述待刷新的block中待刷新的block行，所述第二指示信息用于指示待刷新的bank。
结合第五方面或以上任一种可能的实现方式，在第二种可能的实现方式中，所述刷新信息还包含行合并标识，用于指示所述DRAM刷新装置在同一个 刷新阶段中并行刷新所述待刷新的block中的至少两个block行。
结合第五方面或以上任一种可能的实现方式，在第三种可能的实现方式中，所述刷新信息还包含终止标识，所述终止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，终止对所述待刷新的block的刷新。
结合第五方面或以上任一种可能的实现方式，在第四种可能的实现方式中，所述刷新信息还包含中止标识，所述中止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，中止对所述待刷新的block的刷新。
第六方面，本发明实施例提供了一种DRAM刷新系统，包括内存控制器，DRAM刷新装置和DRAM存储阵列，DRAM存储阵列包括至少两个库bank，DRAM存储阵列的行包括所述至少两个bank各自对应的bank行，DRAM存储阵列分为至少两个刷新块block，每个block包含所述DRAM存储阵列的至少两行，
所述内存控制器用于确定待刷新的block，以及所述待刷新的block中待刷新的区域，并向所述DRAM刷新装置发送刷新指令，所述刷新指令包括待刷新的block的标识，以及用于指示待刷新的区域的刷新信息；所述DRAM刷新装置用于根据所述标识和所述刷新信息，生成所述待刷新的block中待刷新的bank行的地址，并刷新所述待刷新的block中所述bank行的地址对应的位置。
结合第六方面，在第一种可能的实现方式中，所述刷新信息包括第一指示信息和第二指示信息，所述第一指示信息用于指示所述待刷新的block中待刷新的block行，所述第二指示信息用于指示待刷新的bank。
结合第六方面或以上任一种可能的实现方式，在第二种可能的实现方式中，所述DRAM刷新装置刷新所述待刷新的block中所述bank行的地址所对应的位置包括：所述DRAM刷新装置根据所述待刷新的block中待刷新的block行的数目M，分N个刷新阶段刷新所述bank行的地址对应的位置，所述位置中位于同一block行的位置在同一个刷新阶段中并行刷新，其中，M是大于0的正整数，N是大于0并且小于等于M的正整数。
结合第六方面或以上任一种可能的实现方式，在第三种可能的实现方式中，所述刷新信息还包含行合并标识，用于指示所述DRAM刷新装置在同一个刷新阶段中刷新所述待刷新的block中的至少两个block行，所述N小于M。
结合第六方面或以上任一种可能的实现方式，在第四种可能的实现方式中，所述刷新信息还包含终止标识，所述终止标识用于指示所述DRAM刷新装 置在对指示的block行的刷新结束后，终止对所述待刷新的block的刷新；所述方法还包括：所述DRAM刷新装置根据所述终止标识，终止对所述待刷新的block的刷新。
结合第六方面或以上任一种可能的实现方式，在第五种可能的实现方式中，所述刷新信息还包含中止标识，所述中止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，中止对所述待刷新的block的刷新；所述方法还包括：所述DRAM刷新装置根据所述中止标识，中止对所述待刷新的block的刷新。
结合第六方面或以上任一种可能的实现方式，在第六种可能的实现方式中，所述DRAM刷新装置还用于恢复中止的对所述待刷新的block的刷新，并继续刷新剩余的待刷新的block行。
根据本发明实施例提供的技术方案，可以实现内存控制器对DRAM存储整列的指定位置进行刷新，从而可以实现更加合理的配置DRAM刷新操作，缩短了DRAM存储器的刷新时间，降低了刷新功耗，且使刷新操作更加灵活，保证数据完整性的前提下，节省了系统资源的消耗。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为DRAM刷新系统的框图；
图2为本发明的DRAM存储阵列结构示意图；
图3为依据本发明一实施例的DRAM刷新系统结构示意图；
图4为依据本发明一实施例的刷新信息格式示意图；
图5为依据本发明一实施例的刷新信息格式示意图；
图6为依据本发明一实施例的DRAM刷新时序图；
图7为依据本发明一实施例的刷新信息格式示意图；
图8为依据本发明一实施例的DRAM刷新时序图；
图9为依据本发明一实施例的DRAM刷新方法的示范性流程图；
图10为依据本发明一实施例的DRAM刷新方法的示范性流程图；
图11为依据本发明一实施例的DRAM刷新方法的示范性流程图；
图12为依据本发明一实施例的DRAM刷新装置的逻辑结构示意图；
图13为依据本发明一实施例的DRAM刷新装置的逻辑结构示意图；
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1是依据本发明一实施例的DRAM刷新系统100的简化框图。如图1所示，DRAM刷新系统100由存储阵列116、控制逻辑106、行地址译码器112、列地址译码器114、数据列复用器118、控制接口102、地址接口104和数据接口120组成。图1仅提供了一个相对简化的DRAM刷新系统，且DRAM刷新系统100仅仅是一个DRAM刷新系统的例子，刷新系统100可能包含相比于图1展示的更多或者更少的组件，或者有不同的组件配置方式。图2中展示的各种组件可以用硬件、软件或者硬件与软件的结合方式实施。
为了描述方便，图1所示的存储阵列116仅示出一个简单二维分布的库(bank)，但是本领域的技术人员可以理解，存储阵列116可以有多种实现方式，包括有至少两个bank，或者通过配置一个存储阵列实现与至少两个bank等同的功能。DRAM存储阵列116的每一个bank都有各自的行地址译码器112和列地址译码器114以及数据列复用器118等装置。
控制接口102、地址接口104和数据接口120共同提供了DRAM刷新系统100与刷新系统100的外设设备(未示出)之间的通信接口。刷新系统100通过耦合到控制逻辑106的控制接口102接收对DRAM存储阵列的读、写或者其他操作的操作指令。
刷新系统100通过耦合到控制逻辑106的地址接口104接收地址信息，地址信息用于指示对DRAM存储阵列的哪一个或者哪一些存储单元进行读、写或者其他操作。刷新系统100通过至少耦合到数据列复用器118的数据接口120向外部设备传输存储在存储阵列116的数据，或者从外部设备接收数据，以存储在存储阵列116中。
控制逻辑106用于结合(或不结合)通过地址接口104接收到的地址信息 和/或其他信息，控制并执行从控制接口102接收到的操作指令，存储阵列100的存储单元被被以行和列的二维方式组织在一起，所以控制逻辑通过向行地址译码器112传送行地址，向列地址译码器114传送列地址，从而对存储阵列116的部分存储单元进行读、写或者其他操作，其中行地址译码器112和列地址译码器114分别与控制逻辑106耦合。行地址译码器112对从控制逻辑106接收到的行地址进行译码，并使用译码后的行地址选择存储阵列116中的某一行存储单元进行访问。同样，列地址译码器114对从控制逻辑106接收到的列地址进行译码，并使用译码后的列地址控制数据列复用器118(数据列复用器118与列地址译码器114耦合)，以从被行地址译码器112选择出来的行中选择某一个(或者某几个)存储单元进行访问。
DRAM刷新装置108控制逻辑106的组成部分，DRAM刷新装置108在接收到刷新指令后，根据刷新指令的指示，刷新刷新指令指示的存储阵列116中的存储行。DRAM刷新装置108在一次刷新操作中，仅刷新刷新指令指示要刷新的存储行，跳过不待刷新的存储行，从此避免了刷新不待刷新的行所带来的不必要的消耗。对于一次刷新操作中待刷新的行，DRAM刷新装置108使用行地址译码器112从存储阵列116中选择待刷新的行。在一次刷新操作中，存储阵列116中的哪些行需要刷新，哪些行不需要刷新，是在刷新指令中指定的，该刷新指令是由一个与DRAM刷新系统100耦合的外部设备(未示出)发出的。
在本发明一实施例中，一次刷新操作通过以下步骤来完成，DRAM刷新系统100通过控制接口102和地址接口104接收刷新指令，控制接口传递的信息用于指示所述指令是刷新指令，地址接口传递的信息用于指示需要刷新的位置信息，该刷新指令指示刷新存储阵列116中的一行或者多行存储单元。
可选的，DRAM刷新系统100通过地址接口104接收刷新指令，DRAM刷新系统100同过刷新指令的形式，判定该指令是刷新指令，刷新指令用于指示需要刷新的位置信息，该刷新指令指示刷新存储阵列116中的一行或者多行存储单元。
可选的，DRAM刷新系统还可以通过其他通道或总线接口(图中未示出)接收该刷新指令，本发明实施例并不对此进行限定。
在另外一种工作模式中，由计数器110生成一个地址信息，并将生成的地址信息给DRAM刷新装置108，刷新控制逻辑刷新该地址信息指示的所有行，计数器110进行递增运算，在下一周期指示刷新另外一部分存储行。
图2为依据本发明实施例的存储阵列116的另外一种组织形式，如图2所示，存储阵列116包含至少两个bank，由至少两个bank逻辑上横向排列组成，为了描述方便，图2以4个bank为例进行说明，但本发明实施例不限于此，存储阵列116可以包含更多或者更少的bank，存储阵列116包含的4个bank按照二维方式进行排列，存储阵列116的第一行包含bank0的第一行、bank1的第一行、bank2的第一行和bank3的第一行，存储阵列116的第二行包含bank0的第二行、bank1的第二行、bank2的第二行和bank3的第二行，以此类推。
存储阵列116被划分为至少两个刷新块，如图2所示刷新块包含存储阵列116的多行，为了描述方便，图2中一个刷新块包含存储阵列116的4行，但本发明不限此，一个刷新块可以包含更多或者更少的存储阵列116的存储行。每一个刷新块都有自己的地址标识，刷新系统100以刷新块为单位对存储阵列116进行刷新，DRAM刷新装置108从与DRAM刷新系统100耦合的内存控制器接收的刷新指令中包含刷新块的地址标识，可选的，刷新块的地址标识可以以该刷新块中第一行中的第一个bank行的地址来指示。
图3为依据本发明一实施例的DRAM刷新系统300结构示意图，如图3所示，DRAM刷新系统300包含内存控制器302，DRAM刷新装置108，以及DRAM存储阵列116，DRAM存储阵列116由至少两个bank逻辑上横向排列组成，DRAM存储阵列的行包括所述至少两个bank各自对应的bank行，DRAM存储阵列分为至少两个刷新块block，每个block包含所述DRAM存储阵列的至少两行。
内存控制器302维护DRAM存储阵列116的刷新操作相关信息，并用于根据刷新操作相关信息确定待刷新的block，以及所述待刷新的block中待刷新的区域。具体的，待刷新的区域包含待刷新的block中待刷新的block行，以及待刷新的block行中待刷新的bank行。
内存控制器302还用于生成刷新指令，刷新指令包括待刷新的block的标识，以及用于指示待刷新的区域的刷新信息，所述刷新指令用于指示所述DRAM刷新装置刷新所述待刷新的block中的所述待刷新的区域。
可选的，刷新操作相关信息包括存储阵列116的存储单元是否有数据保存和/或存储单元的保持时间，对没有数据的DRAM可以不进行刷新，对保持时间长的DRAM单元可以以较小的刷新频率进行刷新，对保持时间短的DRAM存储单元可以以较大的刷新频率进行刷新，从而可以实现更加合理的配置DRAM刷新操作，缩短了DRAM存储器的刷新时间，降低了刷新功耗，且使刷新操作更加 灵活，保证数据完整性的前提下，节省了系统资源的消耗。
内存控制器302生成刷新指令后，将生成的刷新指令发送给DRAM刷新装置108。DRAM刷新装置108接收到来自内存控制器302的刷新指令后，根据所述标识和所述刷新信息，生成所述待刷新的block中待刷新的bank行的地址，并刷新所述待刷新的block中所述bank行的地址对应的位置。
可选的，所述刷新信息包括第一指示信息和第二指示信息，所述第一指示信息用于指示所述待刷新的block中待刷新的block行，所述第二指示信息用于指示待刷新的bank。
具体的，DRAM刷新装置108可以通过如图1所示的控制接口102和地址接口104接收所述刷新指令，通过控制接口102接收指令标识，指令标识用于表示该指令是一个刷新指令，并通过地址接口接收block的标识和所述刷新信息。
可选的，刷新信息如图4所示，刷新信息中包含block内行地址标识，以及每一个block的行中的哪些bank行需要刷新，哪些bank行不待刷新的信息，如图4所示，仍然以图2实施例为基础进行说明，该刷新信息指示该block的第一行中bank0、bank2对应的行不需要刷新，bank1、bank3对应的行需要刷新；block第二行中bank0、bank2对应的行需要刷新，bank1、bank3对应的行不需要刷新；刷新信息中不包含该block的第三行的地址标识，表示block第三行中所有的bank行都不需要刷新；block第四行中所有的bank对应的行都需要刷新。图4仅仅是示例性的说明刷新信息的格式，其目的是指示block中待刷新的bank行，但本发明实施例中刷新信息的格式并不仅限于此，可以有更多或者更少的技术特征。
图5为刷新信息的另外一种形式，为了保证每一次的刷新信息在消息格式上的一致性，刷新信息可以采用图5所示的格式。刷新信息为一个逻辑上的2维阵列，其结构与block的结构类似，如图5所示，仍然以图2实施例为基础进行说明，该刷新信息指示该block的第一行中bank0、bank2对应的行不需要刷新，bank1、bank3对应的行需要刷新；block第二行中bank0、bank2对应的行需要刷新，bank1、bank3对应的行不需要刷新；block第三行中所有的bank行都不需要刷新；block第四行中所有的bank对应的行都需要刷新。图5仅仅是示例性的说明刷新信息的格式，其目的是指示block中待刷新的bank行，但本发明实施例中刷新信息的格式并不仅限于此，可以有更多或者更少的技术 特征。
随着内存容量的增加，DRAM刷新装置的负载越来越大，根据本发明实施例公开的技术方案，通过内存控制器维护刷新信息，可以选择性的对DRAM存储阵列116进行刷新，对于没有数据的bank行，可以不进行刷新，对于保持时间高的存储单元可以增加刷新操作的间隔时间，从而极大的降低了内存刷新的功耗和性能开销。而且通过把DRAM存储阵列116划分为至少两个block，在一次刷新指令中可以一次性的指示至少两个待刷新的bank行，实现了对刷新指令的压缩，减小了地址总线的开销。
可选的，所述DRAM刷新装置刷新所述待刷新的block中所述bank行的地址所对应的位置包括：所述DRAM刷新装置根据所述待刷新的block中待刷新的block行的数目M，分N个刷新阶段刷新所述bank行的地址对应的位置，所述位置中位于同一block行的位置在同一个刷新阶段中并行刷新，其中，M是大于0的正整数，N是大于0并且小于等于M的正整数。
根据图4和图5所述的刷新信息，一次刷新信息可以携带一个block中多行的刷新信息，实现了对刷新地址的压缩，节省了地址总线的压力。且可以实现内存控制器对DRAM存储整列的指定位置进行刷新，从而可以实现更加合理的配置DRAM刷新操作，缩短了DRAM存储器的刷新时间，降低了刷新功耗，且使刷新操作更加灵活，保证数据完整性的前提下，节省了系统资源的消耗。
图6为依据本发明实施例的一种DRAM刷新时序图，为了描述方便，本实施例以图4所示的刷新信息为例进行说明，DRAM刷新装置108接收到刷新指令后，首先根据根据所述待刷新的block的标识和所述刷新信息，生成所述待刷新的block中待刷新的bank行的地址。
根据刷新指令指示，在第一个刷新阶段，DRAM刷新装置108对block的第一行进行刷新，具体的，DRAM刷新装置108将block第一行中的bank1和bank3对应的bank行的地址分别发送给bank1和bank3的行地址译码器112，在第一刷新阶段对第一block行中的bank1和bank3对应的bank行并行的进行刷新。
通常下一个刷新阶段的刷新信息可以在上一个刷新阶段真正完成之前送入，减少等待时间。如图6所示，在第一刷新阶段还没有真正结束之前，DRAM刷新装置108送入第二刷新阶段的刷新地址，即DRAM刷新装置108将block 第二行中的bank0和bank2对应的的bank行地址分别送入bank0和bank2的行地址译码器112，在第二刷新阶段对第二block行中的bank0和bank2对应的bank行并行刷新。
因为刷新信息不包含block第三行的标识，表示该block的第三block没有待刷新的bank行，DRAM刷新装置跳过不待刷新的block行，在第三刷新阶段刷新block的第四行，根据刷新信息指示，第四block行中的所有bank行都需要刷新，DRAM刷新装置将block第四行对应的所有bank行的地址分别发送给各个bank对应的行地址译码器112，在第三刷新阶段对block第四行中的所有bank行并行刷新。
由于进入刷新状态和退出刷新状态需要时间，一个block内第一个刷新阶段和最后一个刷新阶段用时可能稍长于其他刷新阶段。
在本发明实施例的另外一种实现方式中，DRAM刷新装置将该block中每一个block行中的bank行地址都送入各自对应的行地址译码器112，另外根据刷新信息，选择性的使能对bank行的刷新，对于指示待刷新的bank行就进行刷新，对于没有指示待刷新的bank行就不进行刷新。
相对于传统的一次内存刷新只有一个阶段，把内存刷新分为多个刷新阶段进行，从而保证了一个bank内在每个刷新阶段同时最多有一个行在刷新。根据本发明实施例公开的技术方案，DRAM刷新装置108可以跳过不待刷新的block，从而节省了刷新时间个刷新功耗。而且在一个刷新阶段内，由于刷新信息送入了在block行中各个bank是否刷新的信息，DRAM刷新装置108还可以跳过该block行中不待刷新的bank行，节约功耗。
可选的，所述刷新信息还包含行合并标识，用于指示所述DRAM刷新装置在同一个刷新阶段中刷新所述待刷新的block中的至少两个block行，所述N小于M。
所述DRAM刷新装置还用根据所述行合并标识指示，将所述至少两个待刷新的block行合并刷新，在一个刷新阶段，并行刷新所述至少两个待刷新的block行中待刷新的bank行。
图7为依据本发明实施例的一种刷新信息形式，在图4的基础上加入刷新阶段编号，用刷新阶段编号作为行合并标识，用于指示所述DRAM刷新装置将至少两个待刷新的block行合并刷新。如图7所示，因为第一block行的bank1和bank3对应的bank行需要刷新，而第二block的bank0和bank2对 应的bank行需要刷新，因为第一block行和第二block行中待刷新的bank行所在的bank没有重叠，则可以将两个block行合并后进行刷新，根据刷新阶段编号指示，在第一个刷新阶段内将block的第一行和第二行并行刷新。图7仅仅是示例性的说明带有行合并标识的刷新信息格式，但本发明实施例中刷新信息的格式并不仅限于此，可以有更多或者更少的技术特征，或者采用其他的方式。
图7对应的DRAM刷新时序图如图8所示，DRAM刷新装置108从内存控制器302接收到带有图7所示的刷新信息的刷新指令后，首先根据刷新指令中带有的block标识和刷新信息生成待刷新的bank行地址，根据刷新信息指示，DRAM刷新装置在第一刷新阶段将第一block第一行中bank1和bank3对应的bank行的地址分别送入bank1和bank3的行地址译码器112，将第一block第一行中bank0和bank2对应的bank行的地址分别送入bank0和bank2的行地址译码器112，在第一刷新阶段完成对第一block第一行和第二block第二行的刷新。因为刷新信息中不报包括行block第三行的标识，表明第三block第三行中所有bank行在本次刷新操作中都不需要刷新，DRAM刷新装置108跳过第三block第三行，对第四block第四行进行刷新。同样，为了节省等待时间，可以再第一刷新阶段没有真正结束之前，将第四block第四行中待刷新的bank行地址送入各自对应的行地址译码器112，在本实施例中，即将第四block第四行中的bank0、bank1、bank2和bank3对应的bank行的地址分别送入bank0、bank1、bank2和bank3的行地址译码器112，在第二刷新阶段完成对第四block行的刷新。
通过在刷新信息中增加行合并标识，可以实现将待刷新的bank行对应的bank不重合的至少两个block行合并刷新，从而节约了刷新阶段，从而减小刷新操作的功耗和时延。
可选的，所述刷新信息还包含终止标识，所述终止标识用于指示对所述待刷新的block的刷新在指示的刷新阶段结束后终止；所述DRAM刷新装置108还用于根据所述终止标识，在所述指示的刷新阶段结束后，终止对所述待刷新的block的刷新。
内存控制器302控制对DRAM存储阵列116的刷新操作和读写操作，并对DRMA存储阵列116的操作做统一的时间规划，因为读写操作的优先级一般高于刷新操作，内存控制器302可以灵活的规划对DRAM存储阵列116的操作， 可以在对block刷新过程中的某一个刷新阶段结束后，终止对DRAM存储阵列116的刷新，把时钟周期让给读写操作。
具体实现的过程中，内存控制器302可以在刷新指令的刷新信息中的某一个刷新阶段后加入终止标识，DRAM刷新装置108根据终止标识，在指示的刷新阶段结束后，终止对该block的刷新，从而给对DRAM的读写操作让出时钟周期。读写操作结束后，内存控制器302可以重新给DRAM刷新装置108发送新的刷新指令，指示刷新剩余的没有刷新的block行。
根据本发明实施例公开的技术方案，在对某一个block刷新的时候，可以在某一刷新阶段结束后，提前结束对该block的刷新，让内存可以正常访问，等读写操作结束后，在由内存控制器302向DRAM刷新装置108重新发送刷新指令，指示刷新该block没有刷新的block行。
在本发明实施例另外一种可能的实现方式中，所述刷新信息还包含中止标识，所述中止标识用于指示对所述待刷新的block的刷新在指示的刷新阶段结束后中止；所述DRAM刷新装置108还用于根据所述中止标识指示，在所述指示的刷新阶段结束后，中止对所述待刷新的block的刷新。
所述DRAM刷新装置108还用于恢复中止的对所述待刷新的block的刷新，并继续刷新剩余的待刷新的block行。
具体实现的过程中，内存控制器302可以在刷新指令的刷新信息中的某一个刷新阶段后加入中止标识，DRAM刷新装置108根据中止标识，在指示的刷新阶段结束后，中止对该block的刷新，从而给对DRAM的读写操作让出时钟周期。读写操作结束后，内存控制器302可以给DRAM刷新装置108发送恢复指令，指示恢复对该block的刷新，刷新剩余的没有刷新的block行。还可以由DRAM刷新装置108等待特定的时钟周期后，自主恢复对该block的刷新，刷新剩余的没有刷新的block行。
根据本发明实施例公开的技术方案，在对某一个block刷新的时候，可以在某一刷新阶段结束后，中止对该block的刷新，让内存可以正常访问，等读写操作结束后，DRAM刷新装置108恢复对该block的刷新，继续刷新没有刷新的block行。
可选的，刷新信息中还包含block合并标识，如果相邻的两个block中待刷新的bank行都比较少，可以在刷新时候，将两个block合并刷新。
具体实现的过程中，可以在刷新信息中加入下一个block的偏移量，依次 来定位下一个block，并加入下一个block的刷新信息，以此对相邻的两个block合并刷新。从而节省一个刷新周期的时间。
图9为依据本发明实施例的一种DRAM刷新方法的示范性流程图，DRAM存储阵列包括至少两个库bank，DRAM存储阵列的行包括所述至少两个bank各自对应的bank行，DRAM存储阵列分为至少两个刷新块block，每个block包含所述DRAM存储阵列的多行，如图9所示，所述方法包括：
S902：DRAM刷新装置接收来自内存控制器的刷新指令，所述刷新指令包括待刷新的block的标识，以及用于指示待刷新的区域的刷新信息，所述刷新指令用于指示所述DRAM刷新装置刷新所述待刷新的block中的所述待刷新的区域；
S904：所述DRAM刷新装置根据所述标识和所述刷新信息，生成所述待刷新的block中待刷新的bank行的地址；
S906：所述DRAM刷新装置刷新所述待刷新的block中所述bank行的地址对应的位置。
可选的，所述刷新信息包括第一指示信息和第二指示信息，所述第一指示信息用于指示所述待刷新的block中待刷新的block行，所述第二指示信息用于指示待刷新的bank。
具体的，DRAM刷新装置可以通过如图1所示的控制接口102和地址接口104接收所述刷新指令，通过控制接口102接收指令标识，指令标识用于表示该指令是一个刷新指令，并通过地址接口接收block的标识和所述刷新信息。
所述DRAM刷新装置刷新所述待刷新的block中所述bank行的地址所对应的位置包括：所述DRAM刷新装置根据所述待刷新的block中待刷新的block行的数目M，分N个刷新阶段刷新所述bank行的地址对应的位置，所述位置中位于同一block行的位置在同一个刷新阶段中并行刷新，其中，M是大于0的正整数，N是大于0并且小于等于M的正整数。
在一中可能的实现方式中，方法900的具体的流程图如图10所示。
1002：DRAM刷新装置接收来自内存控制器的刷新指令，刷新指令包含待刷新的block的地址和该block的刷新信息，刷新信息包含待刷新的block行的指示标识，和待刷新的block行中待刷新的bank行的指示标识。
1004：DRAM刷新装置根据刷新指令，锁存block地址和block的刷新信 息。
1006：DRAM刷新装置查找刷新信息，判断是否有待刷新的block行，如果有则执行步骤1008，如果没有，则执行步骤1012，结束本次刷新操作。
可选的，DRAM刷新装置根据block行的地址顺序，查找是否有待刷新的block行。
1008：DRAM刷新装置将block地址和该block行的标识合并，并根据该block行中待刷新的bank行的指示标识生成该block行中待刷新的bank行地址。
1010：DRAM刷新装置将生成的bank行地址分别送入各自对应的bank的行地址译码器，并行刷新该block行中待刷新的bank行，完成对该block行的刷新，并删除锁存的关于该block行的刷新信息，返回步骤1006。
可选的，所述刷新信息还包含行合并标识，用于指示所述DRAM刷新装置在同一个刷新阶段中刷新所述待刷新的block中的至少两个block行，其中，M是大于0的正整数，N是大于0，小于M的正整数。
可选的，所述刷新信息还包含终止标识，所述终止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，终止对所述待刷新的block的刷新；所述方法还包括：所述DRAM刷新装置根据所述终止标识，终止对所述待刷新的block的刷新。
可选的，所述刷新信息还包含中止标识，所述中止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，中止对所述待刷新的block的刷新；所述方法还包括：所述DRAM刷新装置根据所述中止标识，中止对所述待刷新的block的刷新。所述方法900还包括：所述DRAM刷新装置恢复中止的对所述待刷新的block的刷新，并继续刷新剩余的待刷新的block行。
图11为依据本发明实施例的一种DRAM刷新方法的示范性流程图，DRAM存储阵列包括至少两个库bank，DRAM存储阵列的行包括所述至少两个bank各自对应的bank行，DRAM存储阵列分为至少两个刷新块block，每个block包含所述DRAM存储阵列的多行，如图11所示，所述方法包括：
S1102：内存控制器确定待刷新的block，以及所述待刷新的block中待刷新的区域；
内存控制器维护DRAM存储阵列的刷新操作相关信息，并用于根据刷新操作相关信息确定待刷新的block，以及所述待刷新的block中待刷新的区域。 具体的，待刷新的区域可以包括待刷新的block中待刷新的block行，以及待刷新的block行中待刷新的bank行。
可选的，刷新操作相关信息包括存储阵列的存储单元是否有数据保存和/或存储单元的保持时间，对没有数据的bank行可以不进行刷新，对保持时间长的存储单元可以以较小的刷新频率进行刷新，对保持时间短的存储单元可以以较大的刷新频率进行刷新，从而可以实现更加合理的配置DRAM刷新操作，缩短了DRAM存储器的刷新时间，降低了刷新功耗，且使刷新操作更加灵活，保证数据完整性的前提下，节省了系统资源的消耗。
S1104：内存控制器向DRAM刷新装置发送刷新指令，所述刷新指令包括待刷新的block的标识，以及用于指示待刷新的区域的刷新信息。
可选的，所述刷新信息包括第一指示信息和第二指示信息，所述第一指示信息用于指示所述待刷新的block中待刷新的block行，所述第二指示信息用于指示待刷新的bank。
可选的，所述刷新信息还包含行合并标识，用于指示所述DRAM刷新装置在同一个刷新阶段中并行刷新所述待刷新的block中的至少两个block行。
可选的，所述刷新信息还包含终止标识，所述终止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，终止对所述待刷新的block的刷新。
可选的，所述刷新信息还包含中止标识，所述中止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，中止对所述待刷新的block的刷新。
图12是依据本发明一实施例的DRAM刷新装置1200的逻辑结构示意图，DRAM存储阵列包括至少两个库bank，DRAM存储阵列的行包括所述至少两个bank各自对应的bank行，DRAM存储阵列分为至少两个刷新块block，每个block包含所述DRAM存储阵列的多行，DRAM刷新装置，如图12所示，数据传输装置1200可以包括:接收单元1202，生成单元1204和刷新单元1206。
接收单元1202，用于接收来自内存控制器的刷新指令，所述刷新指令包括待刷新的block的标识，以及用于指示待刷新的区域的刷新信息，所述刷新指令用于指示所述DRAM刷新装置刷新所述待刷新的block中的所述待刷新的区域；
生成单元1204，用于根据所述标识和所述刷新信息，生成所述待刷新的block中待刷新的bank行的地址；
刷新单元1206，用于刷新所述待刷新的block中所述bank行的地址对应的位置。
可选的，所述刷新信息包括第一指示信息和第二指示信息，所述第一指示信息用于指示所述待刷新的block中待刷新的block行，所述第二指示信息用于指示待刷新的bank。
具体的，接收单元1202可以通过如图1所示的控制接口102和地址接口104接收所述刷新指令，通过控制接口102接收指令标识，指令标识用于表示该指令是一个刷新指令，并通过地址接口接收block的标识和所述刷新信息。
所述刷新单元1206用于刷新所述待刷新的block中所述bank行的地址所对应的位置包括：所述刷新单元1206根据所述待刷新的block中待刷新的block行的数目M，分N个刷新阶段刷新所述bank行的地址对应的位置，所述位置中位于同一block行的位置在同一个刷新阶段中并行刷新，其中，M是大于0的正整数，N是大于0并且小于等于M的正整数。
可选的，所述刷新信息还包含行合并标识，用于指示所述刷新单元在同一个刷新阶段中刷新所述待刷新的block中的至少两个block行，其中，M是大于0的正整数，N是大于0，小于M的正整数。
所述刷新单元1206用于根据所述待刷新的bank行的地址，刷新所述待刷新的block还包括：所述刷新单元1206根据所述行合并标识指示，将所述至少两个待刷新的block行合并刷新，在一个刷新阶段，并行刷新所述至少两个待刷新的block行中待刷新的bank行。
可选的，所述刷新信息还包含终止标识，所述终止标识用于指示所述刷新单元在对指示的block行的刷新结束后，终止对所述待刷新的block的刷新；所述刷新单元1206还用于根据所述终止标识，终止对所述待刷新的block的刷新。
可选的，所述刷新信息还包含中止标识，所述中止标识用于指示所述刷新单元在对指示的block行的刷新结束后，中止对所述待刷新的block的刷新；所述刷新单元1206还用于根据所述中止标识指示，中止对所述待刷新的block的刷新。所述刷新单元1206还用于恢复中止的对所述待刷新的block 的刷新，并继续刷新剩余的待刷新的block行。
图13是依据本发明一实施例的DRAM刷新装置1300的逻辑结构示意图，DRAM存储阵列包括至少两个库bank，DRAM存储阵列的行包括所述至少两个bank各自对应的bank行，DRAM存储阵列分为至少两个刷新块block，每个block包含所述DRAM存储阵列的多行，DRAM刷新装置，如图13所示，数据传输装置1300可以包括:确定单元1302、发送单元1304。
确定单元1302，用于确定待刷新的block，以及所述待刷新的block中待刷新的区域；
发送单元1304，用于向DRAM刷新装置发送刷新指令，所述刷新指令包括待刷新的block的标识，以及用于指示待刷新的区域的刷新信息。
可选的，所述刷新信息包括第一指示信息和第二指示信息，所述第一指示信息用于指示所述待刷新的block中待刷新的block行，所述第二指示信息用于指示待刷新的bank。
可选的，所述刷新信息还包含行合并标识，用于指示所述DRAM刷新装置在同一个刷新阶段中并行刷新所述待刷新的block中的至少两个block行。
可选的，所述刷新信息还包含终止标识，所述终止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，终止对所述待刷新的block的刷新。
可选的，所述刷新信息还包含中止标识，所述中止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，中止对所述待刷新的block的刷新。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，设备和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块的划分，仅仅为一种逻辑功能划分，实现时可以有另外的划分方式，例如多个模块或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或模块的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方， 或者也可以分布到多个网络模块上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用硬件加软件功能模块的形式实现。
上述以软件功能模块的形式实现的集成的模块，可以内存在一个计算机可读取内存介质中。上述软件功能模块内存在一个内存介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的部分步骤。而前述的内存介质包括：移动硬盘、只读内存器(英文：Read-Only Memory，简称ROM)、随机存取内存器(英文：Random Access Memory，简称RAM)、磁碟或者光盘等各种可以内存程序代码的介质。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的保护范围。

Claims (32)

  1. 一种刷新动态随机存取存储器DRAM的方法，其特征在于，DRAM存储阵列包括至少两个库bank，所述DRAM存储阵列的行包括所述至少两个bank各自对应的bank行，所述DRAM存储阵列分为至少两个刷新块block，每个block包含所述DRAM存储阵列的至少两行，包括：
    DRAM刷新装置接收来自内存控制器的刷新指令，所述刷新指令包括待刷新的block的标识，以及用于指示待刷新的区域的刷新信息，所述刷新指令用于指示所述DRAM刷新装置刷新所述待刷新的block中的所述待刷新的区域；
    所述DRAM刷新装置根据所述标识和所述刷新信息，生成所述待刷新的block中待刷新的bank行的地址；
    所述DRAM刷新装置刷新所述待刷新的block中所述bank行的地址对应的位置。
  2. 根据权利要求1所述的方法，其特征在于，所述刷新信息包括第一指示信息和第二指示信息，所述第一指示信息用于指示所述待刷新的block中待刷新的block行，所述第二指示信息用于指示待刷新的bank。
  3. 根据权利要求1或2所述的方法，其特征在于，所述DRAM刷新装置刷新所述待刷新的block中所述bank行的地址所对应的位置包括：所述DRAM刷新装置根据所述待刷新的block中待刷新的block行的数目M，分N个刷新阶段刷新所述bank行的地址对应的位置，所述位置中位于同一block行的位置在同一个刷新阶段中并行刷新，其中，M是大于0的正整数，N是大于0并且小于等于M的正整数。
  4. 根据权利要求3所述的方法，其特征在于，所述刷新信息还包含行合并标识，用于指示所述DRAM刷新装置在同一个刷新阶段中刷新所述待刷新的block中的至少两个block行，所述N小于M。
  5. 根据权利要求1-4任一项所述的方法，其特征在于，所述刷新信息还包含终止标识，所述终止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，终止对所述待刷新的block的刷新；所述方法还包括：所述DRAM刷新装置根据所述终止标识，终止对所述待刷新的block的刷新。
  6. 根根权利要求1-4任一项所述的方法，其特征在于，所述刷新信息还包含中止标识，所述中止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，中止对所述待刷新的block的刷新；所述方法还包括：所述DRAM刷新装置根据所述中止标识，中止对所述待刷新的block的刷新。
  7. 根据权利要求6所述的方法，其特征在于，所述方法还包括：所述DRAM刷新装置恢复中止的对所述待刷新的block的刷新，并继续刷新剩余的待刷新的block行。
  8. 一种刷新动态随机存取存储器DRAM的方法，其特征在于，DRAM存储阵列包括至少两个库bank，所述DRAM存储阵列的行包括所述至少两个bank各自对应的bank行，所述DRAM存储阵列分为至少两个刷新块block，每个block包含所述DRAM存储阵列的至少两行，包括：
    内存控制器确定待刷新的block，以及所述待刷新的block中待刷新的区域；
    内存控制器向DRAM刷新装置发送刷新指令，所述刷新指令包括所述待刷新的block的标识，以及用于指示所述待刷新的区域的刷新信息。
  9. 根据权利要求8所述的方法，其特征在于，所述刷新信息包括第一指示信息和第二指示信息，所述第一指示信息用于指示所述待刷新的block中待刷新的block行，所述第二指示信息用于指示待刷新的bank。
  10. 根据权利要求8或9所述的方法，其特征在于，所述刷新信息还包含行合并标识，用于指示所述DRAM刷新装置在同一个刷新阶段中并行刷新所述待刷新的block中的至少两个block行。
  11. 根据权利要求8-10任一项所述的方法，其特征在于，所述刷新信息还包含终止标识，所述终止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，终止对所述待刷新的block的刷新。
  12. 根根权利要求8-10任一项所述的方法，其特征在于，所述刷新信息还包含中止标识，所述中止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，中止对所述待刷新的block的刷新。
  13. 一种刷新动态随机存取存储器DRAM的装置，其特征在于，DRAM存储阵列包括至少两个库bank，所述DRAM存储阵列的行包括所述至少两个bank各自对应的bank行，所述DRAM存储阵列分为至少两个刷新块block， 每个block包含所述DRAM存储阵列的至少两行，包括：
    接收单元，用于接收来自内存控制器的刷新指令，所述刷新指令包括待刷新的block的标识，以及用于指示待刷新的区域的刷新信息，所述刷新指令用于指示所述DRAM刷新装置刷新所述待刷新的block中的所述待刷新的区域；
    生成模块，用于根据所述标识和所述刷新信息，生成所述待刷新的block中待刷新的bank行的地址；
    刷新单元，用于刷新所述待刷新的block中所述bank行的地址对应的位置。
  14. 根据权利要求13所述的装置，其特征在于，所述刷新信息包括第一指示信息和第二指示信息，所述第一指示信息用于指示所述待刷新的block中待刷新的block行，所述第二指示信息用于指示待刷新的bank。
  15. 根据权利要求13或14所述的装置，其特征在于，所述刷新单元用于刷新所述待刷新的block中所述bank行的地址所对应的位置包括：所述刷新单元根据所述待刷新的block中待刷新的block行的数目M，分N个刷新阶段刷新所述bank行的地址对应的位置，所述位置中位于同一block行的位置在同一个刷新阶段中并行刷新，其中，M是大于0的正整数，N是大于0并且小于等于M的正整数。
  16. 根据权利要求15所述的装置，其特征在于，所述刷新信息还包含行合并标识，用于指示所述刷新单元在同一个刷新阶段中刷新所述待刷新的block中的至少两个block行，所述N小于M。
  17. 根据权利要求13-16任一项所述的装置，其特征在于，所述刷新信息还包含终止标识，所述终止标识用于指示所述刷新单元在对指示的block行的刷新结束后，终止对所述待刷新的block的刷新；所述刷新单元还用于根据所述终止标识，终止对所述待刷新的block的刷新。
  18. 根根权利要求13-16任一项所述的装置，其特征在于，所述刷新信息还包含中止标识，所述中止标识用于指示所述刷新单元在对指示的block行的刷新结束后，中止对所述待刷新的block的刷新；所述刷新单元还用于根据所述中止标识指示，中止对所述待刷新的block的刷新。
  19. 根据权利要求18所述的装置，其特征在于，所述刷新单元还用于恢复中止的对所述待刷新的block的刷新，并继续刷新剩余的待刷新的 block行。
  20. 一种动态随机存取存储器DRAM芯片，其特征在于，包含DRAM存储阵列和权利要求13-19任一项所述的装置，所述装置用于对所述DRAM存储阵列进行刷新。
  21. 一种用于控制动态随机存取存储器DRAM刷新的装置，其特征在于，DRAM存储阵列包括至少两个库bank，所述DRAM存储阵列的行包括所述至少两个bank各自对应的bank行，所述DRAM存储阵列分为至少两个刷新块block，每个block包含所述DRAM存储阵列的至少两行，包括：
    确定单元，用于确定待刷新的block，以及所述待刷新的block中待刷新的区域；
    发送单元，用于向DRAM刷新装置发送刷新指令，所述刷新指令包括所述待刷新的block的标识，以及用于指示所述待刷新的区域的刷新信息。
  22. 根据权利要求21所述的装置，其特征在于，所述刷新信息包括第一指示信息和第二指示信息，所述第一指示信息用于指示所述待刷新的block中待刷新的block行，所述第二指示信息用于指示待刷新的bank。
  23. 根据权利要求21或22所述的装置，其特征在于，所述刷新信息还包含行合并标识，用于指示所述DRAM刷新装置在同一个刷新阶段中并行刷新所述待刷新的block中的至少两个block行。
  24. 根根权利要求21-23任一项所述的装置，其特征在于，所述刷新信息还包含终止标识，所述终止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，终止对所述待刷新的block的刷新。
  25. 根据权利要求21-23任一项所述的装置，其特征在于，所述刷新信息还包含中止标识，所述中止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，中止对所述待刷新的block的刷新。
  26. 一种刷新动态随机存取存储器DRAM的系统，其特征在于，包括控制动态随机存取存储器DRAM刷新的装置，DRAM刷新装置和DRAM存储阵列，DRAM存储阵列包括至少两个库bank，所述DRAM存储阵列的行包括所述至少两个bank各自对应的bank行，所述DRAM存储阵列分为至少两个刷新块block，每个block包含所述DRAM存储阵列的至少两行，
    所述控制动态随机存取存储器DRAM刷新的装置用于确定待刷新的block，以及所述待刷新的block中待刷新的区域，并向所述DRAM刷新装置 发送刷新指令，所述刷新指令包括待刷新的block的标识，以及用于指示待刷新的区域的刷新信息；
    所述DRAM刷新装置用于根据所述标识和所述刷新信息，生成所述待刷新的block中待刷新的bank行的地址，并刷新所述待刷新的block中所述bank行的地址对应的位置。
  27. 根据权利要求26所述的系统，其特征在于，所述刷新信息包括第一指示信息和第二指示信息，所述第一指示信息用于指示所述待刷新的block中待刷新的block行，所述第二指示信息用于指示待刷新的bank。
  28. 根据权利要求26或27所述的系统，其特征在于，所述DRAM刷新装置刷新所述待刷新的block中所述bank行的地址所对应的位置包括：所述DRAM刷新装置根据所述待刷新的block中待刷新的block行的数目M，分N个刷新阶段刷新所述bank行的地址对应的位置，所述位置中位于同一block行的位置在同一个刷新阶段中并行刷新，其中，M是大于0的正整数，N是大于0并且小于等于M的正整数。
  29. 根据权利要求28所述的系统，其特征在于，所述刷新信息还包含行合并标识，用于指示所述DRAM刷新装置在同一个刷新阶段中刷新所述待刷新的block中的至少两个block行，所述N小于M。
  30. 根根权利要求26-29任一项所述的系统，其特征在于，所述刷新信息还包含终止标识，所述终止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，终止对所述待刷新的block的刷新；所述方法还包括：所述DRAM刷新装置根据所述终止标识，终止对所述待刷新的block的刷新。
  31. 根据权利要求26-29任一项所述的系统，其特征在于，所述刷新信息还包含中止标识，所述中止标识用于指示所述DRAM刷新装置在对指示的block行的刷新结束后，中止对所述待刷新的block的刷新；所述方法还包括：所述DRAM刷新装置根据所述中止标识，中止对所述待刷新的block的刷新。
  32. 根据权利要求31所述的系统，其特征在于，所述DRAM刷新装置还用于恢复中止的对所述待刷新的block的刷新，并继续刷新剩余的待刷新的block行。
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