WO2021147043A1 - 一种存储器、控制器、刷新方法及存储系统 - Google Patents

一种存储器、控制器、刷新方法及存储系统 Download PDF

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Publication number
WO2021147043A1
WO2021147043A1 PCT/CN2020/073916 CN2020073916W WO2021147043A1 WO 2021147043 A1 WO2021147043 A1 WO 2021147043A1 CN 2020073916 W CN2020073916 W CN 2020073916W WO 2021147043 A1 WO2021147043 A1 WO 2021147043A1
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Prior art keywords
refresh
row
target
bank
memory
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PCT/CN2020/073916
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English (en)
French (fr)
Inventor
刘荣斌
王正波
黄天强
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202080079471.XA priority Critical patent/CN114730592A/zh
Priority to PCT/CN2020/073916 priority patent/WO2021147043A1/zh
Publication of WO2021147043A1 publication Critical patent/WO2021147043A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Definitions

  • This application relates to the technical field of memory refreshing, and in particular to a memory, a controller, a refreshing method, and a storage system.
  • Capacitive memory has low price and high storage density, and is a common basic component in electronic equipment.
  • dynamic random access memory uses the storage function of capacitors to store data to achieve data storage.
  • the storage space of the memory is generally configured as N banks arranged in parallel, and N is an integer greater than or equal to 1.
  • Each bank can be understood as a two-dimensional storage array, in which the horizontal direction is called the row, and the vertical direction is called the column.
  • a storage unit in the storage array includes a capacitor, which can store 1 bit of data. Since the charge in the capacitor will continue to drain with leakage, the data in the capacitor must be periodically read and rewritten to compensate for the lost charge. This operation is also called refresh.
  • the present application provides a memory, a controller, a refresh method, and a storage system to provide a memory refresh operation with higher flexibility.
  • an embodiment of the present application provides a memory, which mainly includes a control circuit, a refresh circuit, and a storage area.
  • the control circuit may receive refresh instruction information, which is used to indicate at least one target row to be refreshed; the control circuit may further control the refresh circuit to refresh at least one target row in the storage area according to the refresh instruction information.
  • the refresh instruction information received by the control circuit may indicate the target row to be refreshed, that is, the controller used to control the memory can flexibly control the next refresh of the memory through the refresh instruction information according to the current application scenario. Therefore, the refresh operation can be flexibly adapted to different application scenarios.
  • the storage area of the memory can be divided into at least one bank.
  • at least one target row has a corresponding row in each bank. That is, the controller can instruct the memory to refresh at least one target row of each bank in at least one bank through the refresh instruction information. For example, if the second row indicated by the refresh instruction information is the target row, the memory can refresh the second row in at least one bank respectively.
  • the memory may include at least one refresh circuit
  • the storage area may include at least one bank
  • the at least one refresh circuit is used to perform a refresh operation on the at least one bank.
  • the refresh instruction information may also indicate the target bank.
  • the control circuit may obtain the target row information according to the refresh instruction information, and send the target row information to the refresh circuit corresponding to the target bank.
  • the target row information may indicate the above-mentioned at least one target row.
  • the refresh circuit can then refresh at least one target row in the target bank according to the target row information.
  • the control circuit may also receive the first query information sent by the controller, the first query information may indicate the target bank; the control circuit may obtain the maximum number of refreshable rows of the target bank according to the first query information , And return the maximum number of refreshable rows of the target bank to the controller.
  • the controller can obtain the maximum number of refreshable rows of the target bank. The controller can thus determine at least one target row according to the maximum number of refreshable rows, so that the number of at least one target row is not greater than the maximum number of refreshable rows of the target bank, so that the memory can correctly execute the refresh instruction information of the controller.
  • control circuit may also receive first configuration information, which may indicate the number of at least one target row and the target bank; according to the number of at least one target row, the refresh corresponding to the target bank is updated.
  • first configuration information which may indicate the number of at least one target row and the target bank; according to the number of at least one target row, the refresh corresponding to the target bank is updated.
  • the number of single refresh lines of the circuit With this implementation, the number of at least one target row can be configured for the refresh circuit corresponding to the target bank, so that the refresh circuit can refresh at least one target row at the same time in the next refresh operation.
  • the target row information sent by the control circuit to the refresh circuit may include at least one row identifier of the indicated row in the target row; the refresh circuit corresponding to the target bank may be calculated based on the row identifier of the indicated row and the number of rows in a single refresh The row identifier of the at least one target row is obtained; the refresh circuit can then refresh at least one target row in the target bank according to the row identifier of the at least one target row.
  • control circuit may also return the maximum number of public refreshable rows of at least one bank to the controller after receiving the second query information sent by the controller, and the maximum number of public refreshable rows may be based on Obtained from the minimum value of the maximum number of rows that can be refreshed in at least one bank.
  • the controller can obtain the maximum number of public refreshable rows of at least one bank through the second query information, so that at least one target row can be determined according to the maximum number of public refreshable rows, so that the number of at least one target row is not greater than the maximum number of public refreshable rows .
  • the maximum number of common refreshable rows can be obtained based on the minimum value of the maximum number of refreshable rows in at least one bank, the number of at least one target row will be less than the maximum number of refreshable rows per bank in at least one bank. Therefore, at least one refresh circuit can refresh at least one target row at the same time in the next refresh operation.
  • the memory may include at least one refresh circuit, the storage area may be divided into at least one bank, and at least one refresh circuit in the memory may perform refresh operations on at least one bank respectively.
  • the control circuit may also receive second configuration information, and the second configuration information may indicate the number of at least one target row; the control circuit may respectively send the first instruction to the at least one refresh circuit according to the second configuration information Information, the first indication information can indicate the number of at least one target row; each refresh circuit can update its own single refresh number of rows according to the number of at least one target row.
  • the controller can simultaneously configure the same number of single refresh rows for at least one refresh circuit of the memory through the second configuration information.
  • the refresh instruction information may include the row identifier of the instruction row in at least one target row; the control circuit may obtain the target row information according to the refresh instruction information, and respectively send the above-mentioned target row information to at least one refresh circuit of the memory.
  • the target row information may include the row identification of the indicated row in the at least one target row; each refresh circuit can calculate the row identification of at least one target row according to the row identification of the indicated row and the number of single refresh rows; the refresh circuit may further According to the row identifier of the at least one target row, at least one target row in the corresponding bank is refreshed.
  • the embodiments of the present application provide a controller.
  • the technical effects of the corresponding solutions in the second aspect may refer to the technical effects that can be obtained by the corresponding solutions in the first aspect, and the repetitions are not described in detail.
  • the controller provided by the embodiment of the present application mainly includes a processing circuit and an interface circuit, where: the processing circuit can determine at least one target row to be refreshed in the storage area of the memory; the interface circuit can send refresh instruction information to the memory , The refresh indication information may indicate the at least one target row.
  • the storage area of the memory may be divided into at least one bank, and at least one target row indicated by the refresh instruction information sent by the controller has a corresponding row in each bank.
  • the memory includes at least one bank; the refresh indication information may also indicate a target bank in the at least one bank.
  • the interface circuit may also send first query information to the memory, and the first query information may instruct the memory to return the maximum number of refreshable rows of the target bank; the processing circuit may in turn be based on the maximum refreshable number of the target bank.
  • the number of rows is to determine at least one target row, where the number of at least one target row is not greater than the maximum number of refreshable rows of the target bank.
  • the controller may first obtain the maximum refreshable number of rows of the target bank through the first query information, and then determine at least one target row according to the maximum refreshable number of rows of the target bank. Since the number of at least one target row is not greater than the maximum number of refreshable rows of the target bank, it is beneficial to ensure that the memory can normally execute the refresh instruction information.
  • the interface circuit may also send first configuration information to the memory, and the first configuration information may instruct the memory to update the number of rows for a single refresh of the target bank according to the number of at least one target row.
  • the controller can flexibly control the refresh of the memory:
  • the processing circuit may determine at least one target row from rows in the target bank that store valid data. That is to say, the controller controls the memory to refresh rows that store valid data, and may not refresh rows that store invalid or useless data, thereby helping to reduce the overall power consumption caused by the refresh operation.
  • the processing circuit may determine at least one bank to be read where the data to be read is located; from the at least one bank, except for the at least one bank to be read, determine the target bank.
  • the controller can control the memory to refresh the data in the bank that will not be read in the next refresh, and the bank that needs to be read next may not be refreshed first, so as to reduce the impact of the refresh operation on data reading.
  • the memory includes at least one bank
  • the interface circuit may also send second query information to the memory, and the second query information may instruct the memory to return the maximum number of common refreshable rows of at least one bank; the processing circuit
  • the at least one target row may be determined according to the maximum number of common refreshable rows of at least one bank, where the number of at least one target row is not greater than the maximum number of common refreshable rows.
  • the maximum refreshable rows supported by different banks may be different.
  • the controller before sending the refresh instruction information, the controller may first obtain the maximum number of public refreshable rows of at least one bank through the second query information, and then determine at least one target row according to the maximum number of public refreshable rows. Since the number of at least one target row is not greater than the maximum number of common refreshable rows, it is beneficial to ensure that the memory can normally execute the refresh instruction information.
  • the interface circuit may also send second configuration information to the memory, and the second configuration information may instruct the memory to update the number of single refresh rows for at least one bank according to the number of at least one target row. .
  • the refresh indication information includes a row identifier of the indicated row in the at least one target row.
  • the processing circuit may determine at least one target row according to the current time point and the refresh period, where the time interval between the time point of the last refresh of each target row and the current time point, None is greater than the refresh period, and the processing circuit can also obtain the environmental parameters of the memory, and adjust the above-mentioned refresh period according to the environmental parameters.
  • the controller can flexibly adjust the refresh cycle according to environmental parameters.
  • the embodiments of the present application provide a refresh method.
  • the technical effects of the corresponding solutions in the third aspect can refer to the technical effects that can be obtained by the corresponding solutions in the first aspect, and the repetitions are not described in detail.
  • the refresh method provided in the embodiment of the present application may be applied to a memory, and the method mainly includes: the memory receives refresh instruction information, and the refresh instruction information may indicate at least one target row to be refreshed in a storage area of the memory; and the memory; Furthermore, at least one target row in the storage area can be refreshed according to the refresh instruction information.
  • the storage area of the memory may be divided into at least one bank.
  • the memory refreshes the at least one target row, the rows corresponding to the at least one target row in the at least one bank may be refreshed respectively.
  • the storage area of the memory may be divided into at least one bank, and the refresh instruction information may also indicate the target bank in the at least one bank; when the memory refreshes at least one target row according to the refresh instruction information, At least one target row in the target bank can be refreshed according to the refresh instruction information.
  • the memory may also receive first query information sent by the controller before receiving the refresh instruction information, and the first query information may indicate the target bank; the memory may obtain the information of the target bank according to the first query information. The maximum number of rows that can be refreshed, and the maximum number of rows that can be refreshed in the target bank is returned to the controller.
  • first configuration information may also be received first.
  • the first configuration information may indicate the number of at least one target row and the target bank; and update according to the number of at least one target row. The number of rows in a single refresh of the target bank.
  • the memory when the memory refreshes at least one target row in the target bank according to the refresh instruction information, it may obtain the row identifier of the instruction row in the at least one target row according to the refresh instruction information. The memory can then calculate the row ID of at least one target row according to the row ID of the indicated row and the number of rows in a single refresh; the memory can thus refresh the at least one target row in the target bank according to the row ID of the at least one target row.
  • the memory before receiving the refresh instruction information, may also return to the controller the maximum number of common refreshable rows of at least one bank after receiving the second query information sent by the controller.
  • the number of public refreshable rows is obtained based on the minimum value of the maximum refreshable rows in at least one bank.
  • the memory before receiving the refresh instruction information, may first receive second configuration information, and the second configuration information may indicate the number of at least one target row; the memory may be based on the number of at least one target row, Respectively update the number of single refresh rows for at least one bank.
  • the refresh instruction information includes the row identifier of the instruction row in the at least one target row; when the memory refreshes the row corresponding to the at least one target row in the at least one bank, it can acquire according to the refresh instruction information.
  • Target row information the target row information may include the row identifier of the indicated row in the at least one target row; the memory may further calculate the at least one target row based on the row identifier of the indicated row and the number of single refresh rows for at least one bank. The row identification of the row; the memory can thus refresh the rows corresponding to the at least one target row in the at least one bank according to the row identification of the at least one target row.
  • the embodiments of the present application provide a refresh method.
  • the technical effects of the corresponding solution in the fourth aspect may refer to the technical effects that can be obtained by the corresponding solution in the second aspect, and repetitions are not described in detail.
  • the refresh method provided in the embodiment of the present application may be applied to the controller.
  • the method provided in the embodiment of the present application mainly includes: the controller determines at least one target row to be refreshed in the storage area of the memory;
  • the memory sends refresh instruction information, and the refresh instruction information may indicate the foregoing at least one target row.
  • the storage area of the memory may be divided into at least one bank, and at least one target row indicated by the refresh indication information has a corresponding row in each bank.
  • the storage area of the memory can be divided into at least one bank; the refresh indication information can also indicate the target bank in at least one bank.
  • the memory can only refresh the target bank that needs to be refreshed. Target line.
  • the controller may first send first query information to the memory, and the first query information may instruct the memory to return the maximum number of refreshable rows of the target bank. ;
  • the controller may determine at least one target row according to the maximum number of refreshable rows of the target bank, wherein the number of at least one target row is not greater than that of the target bank The maximum number of rows that can be refreshed.
  • the controller may also send first configuration information to the memory.
  • the first configuration information may instruct the memory to update the target bank according to the number of at least one target row. The number of rows in a single refresh.
  • the controller when determining at least one target row to be refreshed in the storage area of the memory, may determine at least one target row from rows in the target bank that store valid data.
  • the storage area of the memory includes a plurality of banks
  • the controller may also determine at least where the data to be read is located before at least one target row to be refreshed in the storage area of the memory.
  • the storage area of the memory may be divided into at least one bank; before determining the at least one target row to be refreshed in the storage area of the memory, the controller may also send the second query information to the memory.
  • the second query information can instruct the memory to return the maximum number of common refreshable rows of at least one bank; when the controller determines the at least one target row to be refreshed in the storage area of the memory, it can be based on the maximum common refreshable number of the at least one bank.
  • the number of rows is used to determine at least one target row, where the number of the aforementioned at least one target row is not greater than the maximum number of public refreshable rows.
  • the controller may first send second configuration information to the memory, and the second configuration information may instruct the memory to update at least one target row according to the number of at least one target row. The number of rows in a single refresh of the bank.
  • the refresh instruction information may include the row identifier of the instruction row in the at least one target row.
  • the controller when determining at least one target row to be refreshed in the storage area of the memory, may determine at least one target row according to the current time point and the refresh period, where each row is refreshed last time. The time interval between the time point of the target row and the current time point is not greater than the refresh period, and the refresh period is adjusted by the controller according to the environmental parameters of the memory.
  • the embodiments of the present application provide a storage system.
  • the technical effects of the corresponding solutions in the fifth aspect may refer to the technical effects that can be obtained by the corresponding solutions in the first aspect, and the repetitions are not described in detail.
  • the storage system provided by the embodiment of the present application includes a controller and a memory.
  • the controller can determine at least one target row to be refreshed in the storage area of the memory, and send refresh instruction information to the memory. At least one target row can be indicated; the memory can refresh the at least one target row according to the refresh indication information.
  • FIG. 1 is a schematic structural diagram of a storage system to which an embodiment of this application is applicable;
  • FIG. 2 is a schematic flowchart of a refresh method provided by an embodiment of the application
  • FIG. 3 is a schematic diagram of the storage structure of a bank provided by an embodiment of the application.
  • Fig. 1 exemplarily shows a schematic structural diagram of a storage system to which an embodiment of the present application is applicable.
  • the storage system 100 may be an electronic device or an integrated chip with data storage function.
  • the storage system 100 may be an electronic device such as a mobile phone, a computer, a smart camera, etc., or it may be a system on chip (SOC) or a central processing unit. (central processing unit, CPU) and other chips, this embodiment of the application does not limit this.
  • SOC system on chip
  • CPU central processing unit
  • the storage system 100 includes a memory 101 and a controller 102.
  • the controller 102 may include a processing circuit 1021 and an interface circuit 1022.
  • the processing circuit 1021 may be a logic operation circuit, and the processing circuit 1021 may generate instructions.
  • the interface circuit 1022 may be a control bus interface, and the controller 102 may be connected to the memory 101 through a control bus through the interface circuit 1022.
  • the interface circuit 1022 can send instructions to the control circuit 1011 of the memory 101, so as to instruct the control circuit 1011 to complete tasks such as data reading, storage, and refresh.
  • the memory 101 may include a control circuit 1011, refresh circuits (refresh circuits 1 to N), and a storage area 1012. N is an integer greater than or equal to 1. That is to say, in the embodiment of the present application, the memory 101 may include one or more refresh circuits, which is not limited in the embodiment of the present application.
  • the storage area 1012 may be a two-dimensional storage array composed of a plurality of storage cells. Each storage unit can store 1bit data.
  • the memory 101 may be a capacitive memory, for example, the memory 101 may be a DRAM.
  • each storage unit corresponds to at least one capacitor, and each storage unit can realize data storage through the charge stored in the capacitor. For example, for any memory cell, if the capacitor of the memory cell stores charge, the data stored in the memory cell is 1. If the capacitor of the memory cell does not store charge, the data stored in the memory cell is 0 .
  • the controller 102 Since the charge in the capacitor will continue to drain along with the leakage, the controller 102 needs to refresh the memory 101 regularly. Specifically, the controller 102 may send a refresh command to the control circuit 1011.
  • the refresh command is mostly an auto-refresh command, or an active command and a pre-charge command.
  • the auto-refresh instruction may also be referred to as the refresh instruction for short.
  • the controller 102 may send a refresh instruction to the memory 101.
  • the control circuit 1011 After the control circuit 1011 receives the refresh command, it will determine the target row to be refreshed next according to the refresh logic preset in the control circuit 1011.
  • the control circuit 1011 can further refresh the target row through the refresh circuit in the memory 101.
  • the storage area 1012 can be further divided into multiple banks.
  • Each bank can be an m ⁇ n two-dimensional storage array, m is the number of rows of the two-dimensional storage array, m is greater than 1, n is the number of columns of the two-dimensional storage array, and n is greater than 1. It can be understood that different banks may have the same or different numbers of rows and columns, which is not limited in the embodiment of the present application.
  • the multiple refresh circuits in the memory 101 can perform refresh operations on one or more banks respectively.
  • the N refresh circuits in the memory 101 can respectively refresh the N banks in the storage area 1012, that is, the N refresh circuits can correspond to the N banks one-to-one, such as the refresh circuit 1 corresponds to bank1, then refresh circuit 1 can refresh the target row in bank1.
  • the N refresh circuits can correspond to the N banks one-to-one, such as the refresh circuit 1 corresponds to bank1
  • refresh circuit 1 can refresh the target row in bank1.
  • N refresh circuits and N banks take the one-to-one correspondence between N refresh circuits and N banks as an example. It should be understood that when there is a one-to-many correspondence between multiple refresh circuits and multiple banks, the same applies to this application. Examples.
  • the control circuit 1011 may send instruction information to the refresh circuits 1 to N to instruct the refresh circuits 1 to N to refresh the target rows in banks 1 to N, respectively.
  • the refresh circuit 1 can refresh the target row in bank 1 after receiving the instruction information
  • the refresh circuit 2 can refresh the target row in bank 2 after receiving the instruction information, and so on.
  • the control circuit 1011 determines the target row that needs to be refreshed next, and the controller 102 does not know the target row that needs to be refreshed next. Assuming that each bank includes 8192 rows of memory cells, the controller 102 needs to send 8192 refresh commands to refresh each memory cell in the memory 101 once.
  • the current controller 102 can instruct the memory 101 to complete the refresh through the refresh command, this control method is relatively limited and cannot flexibly adapt to different application scenarios of the memory 101.
  • the data stored in the memory 101 may be valid data or invalid data.
  • the so-called invalid data refers to useless data with no storage value.
  • the memory 101 will also refresh invalid data, which will result in waste of energy consumption.
  • embodiments of the present application provide a controller, a memory, and a refresh method.
  • the controller 102 can indicate to the memory 101 at least one target row to be refreshed through refresh instruction information. Therefore, the controller 102 can control the refresh operation of the memory 101 more flexibly. It can be understood that, compared with the control circuit 1011, the controller 102 has a stronger logic judgment ability and can deal with more complex application scenarios. Compared with the current situation where the control circuit 1011 determines the row to be refreshed next, the embodiment of the present application directly instructs at least one target row to be refreshed through the controller 102, which facilitates the refresh operation to be flexibly adapted to different application scenarios.
  • FIG. 2 exemplarily shows a schematic flowchart of a refresh method provided by an embodiment of the present application. As shown in FIG. 2, the method mainly includes the following steps:
  • the controller 102 determines at least one target row to be refreshed in the storage area of the memory. Specifically, the processing circuit 1021 in the controller 102 may determine at least one target row to be refreshed.
  • the controller 102 can flexibly determine the target row to be refreshed according to the current application scenario. For example, it can determine the target row to be refreshed according to factors such as memory access and storage conditions, so that the refresh operation of the memory can be flexibly adapted to different Application scenarios.
  • the controller 102 sends refresh instruction information to the memory 101.
  • the refresh instruction information may be sent to the memory 101 through the interface circuit 1022 in the controller 102, and the refresh instruction information may indicate the above-mentioned at least one target row.
  • the memory 101 refreshes at least one target row according to the refresh instruction information.
  • the control circuit 1011 may control the refresh circuit in the memory according to the refresh instruction information, so as to realize the refresh operation on the above-mentioned at least one target row.
  • Type 1 At least one target row indicated by the refresh indication information has a corresponding row in the N banks of the memory 101.
  • the control circuit 1011 can control the refresh circuits 1 to N to refresh the rows corresponding to the target row in bank 1 to N, respectively.
  • the control circuit 1011 can control the refresh circuits 1 to N to refresh the first row in bank 1 to N, respectively.
  • Refresh indication information can not only indicate the target row to be refreshed, but also indicate the target bank.
  • the controller 102 may also determine a target bank from the N banks of the memory 101 according to the current application scenario, and indicate the target bank through refresh instruction information.
  • the control circuit 1011 may control the refresh circuit corresponding to the target bank to refresh the target row in the target bank after receiving the refresh instruction information.
  • the refresh circuit corresponding to the target bank can be understood as a refresh circuit for performing a refresh operation on the target bank.
  • the control circuit 1011 can control the refresh circuit 1 to refresh the first row of bank1.
  • a single refresh row number is configured in the refresh circuit, and each refresh circuit needs to refresh the corresponding bank according to the current configured single refresh row number.
  • the number of single refresh rows of the refresh circuit can be understood as the number of rows that can be refreshed at the same time when the refresh circuit performs a refresh operation. Taking refresh circuit 1 as an example, if the number of single refresh rows currently configured for refresh circuit 1 is 2, then refresh circuit 1 can refresh two rows of memory cells in bank1 at the same time when refreshing bank1 next.
  • the number of single refresh lines of the refresh circuit in the memory 101 may also be configured through configuration information.
  • the process of configuring the number of rows in a single refresh will be further exemplified.
  • the controller 102 may send the first configuration information to the memory 101, and the first configuration information may indicate the number of target rows to be refreshed and the target bank.
  • the control circuit 1011 may update the number of single refresh rows of the refresh circuit corresponding to the target bank according to the number of target rows.
  • the control circuit 1011 may send first indication information to the refresh circuit corresponding to the target bank, and the first indication information may indicate the number of at least one target row to the refresh circuit.
  • the refresh circuit can update its own single refresh row number according to the number of target rows. For example, in FIG. 1, the target refresh row number indicated by the first configuration information is 2 and the target bank is 1, then the control circuit 1011 may send the first instruction information to the refresh circuit 1. After receiving the first instruction information, the refresh circuit 1 can update the number of single refresh lines to 2 according to the first instruction information.
  • the controller 102 may send second configuration information to the memory 101, and the second configuration information may indicate the number of target rows to be refreshed.
  • the bank identifier of the target bank may not be included in the second configuration information, or the bank identifiers of N banks may be included in the second configuration information. Therefore, the second configuration information may be used to refresh the N banks in the memory 101. The number of rows in a single refresh with the same circuit configuration.
  • the control circuit 1011 can send the above-mentioned first instruction information to the N refresh circuits respectively.
  • each refresh circuit receives the first instruction information, it can be based on the number of target rows. , To update the number of rows in a single refresh. For example, in FIG. 1, the number of target rows indicated by the second configuration information is 2, and the control circuit 1011 may send the first indication information to the refresh circuits 1 to N respectively.
  • each refresh circuit After receiving the first instruction information, each refresh circuit can update its single refresh line number to 2 according to the first instruction information.
  • the controller 102 can also flexibly choose to send the first configuration information and/or the second configuration information according to the current application scenario, which is not limited in the embodiment of the present application. For example, before the controller 102 sends the first configuration information or the second configuration information, it can also confirm whether the current single refresh line number of the refresh circuit is the number of at least one target line. If so, the controller 102 can save sending The first configuration information or the second configuration information, and the refresh instruction information is directly sent. This helps simplify the refresh process.
  • control circuit 1011 can refresh the target row in the storage area 1012 according to the refresh instruction information.
  • control circuit 1011 can obtain the target row information according to the refresh instruction information, and the control circuit 1011 sends the target row information to the refresh circuit, and the refresh circuit can refresh the target row in the corresponding bank according to the target row information.
  • the refresh instruction information may include the row identifier of the instruction row in at least one target row.
  • the indicator row can be a row in at least one target row that meets a preset rule.
  • the indicator row can be the row with the smallest row identifier in at least one target row, the row with the largest row identifier, or the row identifier as The row of the intermediate value is not limited in the embodiment of the present application.
  • the control circuit 1011 may obtain target row information according to the refresh instruction information, where the target row information includes the row identifier of the indicated row in the refresh instruction information.
  • the control circuit 1011 sends the target row information to the refresh circuit.
  • the refresh circuit can further calculate the row ID of at least one target row based on the row ID of the indicated row and the number of single refresh rows.
  • Figure 3 exemplarily shows the storage array of bank1, in which each small square represents a storage unit, the black small squares store valid data, and the white small squares store invalid data or unavailable data. Storing data.
  • bank1 includes a total of 8192 rows of storage units, which can be specifically divided into four storage partitions (storage partitions 1 to 4), and each storage partition includes 2048 rows of storage units.
  • the refresh circuit can refresh rows in different storage partitions at the same time during a refresh operation.
  • the refresh circuit 1 can simultaneously refresh the first row of storage units and the 2049th row of storage units shown in FIG. 3, where the first row of storage units are located in storage partition 1 and the 2049th row of storage units are located in storage partition 2.
  • the number of storage partitions in each bank may be equal to the maximum number of single refresh rows of the refresh circuit corresponding to the bank.
  • bank1 includes 4 storage partitions, and the maximum number of rows in a single refresh of the corresponding refresh circuit 1 is 4. It can also be understood that the maximum number of rows that can be refreshed is 4.
  • the refresh circuit 1 After receiving the refresh instruction information, the refresh circuit 1 can calculate the row ID of the target row to be refreshed according to the row ID of the indicated row and the number of single refresh rows. Specifically, the refresh circuit 1 may determine the instruction row and several behavior target rows adjacent to the instruction row according to the preset decoding rule and the number of rows in a single refresh.
  • the row identifier of the target row may be the storage address of the target row or the serial number of the target row, which is not limited in the embodiment of the present application.
  • the refresh circuit 1 in the embodiment of the present application may at least determine the target row to be refreshed according to any of the following decoding rules:
  • This decoding method is suitable for a bank that includes X storage partitions, where X is an integer power of 2.
  • bank1 includes 4 storage partitions, which is suitable for this decoding method.
  • the single refresh line number Y of the refresh circuit should also be an integer power of 2, and the single refresh line number Y should not be greater than X.
  • the applicable single refresh row number Y is 1, 2, and 4.
  • the refresh circuit can determine the target row to be refreshed according to the row number Y of a single refresh and the row identifier of the indicated row, and there are X/Y storage partitions between the target rows.
  • the refresh circuit 1 can determine that there is a memory partition between adjacent target rows.
  • the refresh circuit 1 The target behavior can be determined: line 1, line 2049 (the first line in the second storage partition), line 4097 (the first line in the third storage partition), and line 6145 (the fourth storage partition) The first line within).
  • the refresh circuit 1 can determine that there are two memory partitions between adjacent target rows. In the case of the instruction row in the first row, the refresh circuit 1 can Determine the target behavior: line 1 and line 4097 (the first line in the third storage partition).
  • the row identification of each row can be represented in the form of a secondary system.
  • bank1 shown in FIG. 3 includes 8192 rows of memory cells, which can be represented by a 13-bit two-level row identifier.
  • the line identifier of the first line can be expressed as 0000000000000
  • the line identifier of the second line can be expressed as 00000000001
  • the line identifier of the 2049th line can be expressed as 0100000000000
  • the line identifier of the 4097th line can be expressed as 1000000000000
  • the row identifier of line 6145 can be expressed as 1100000000000
  • the line identifier of line 8192 can be expressed as 1111111111111.
  • the four storage partitions can be represented by 2 bits.
  • the indicating row information includes the row identifier 0000000000001 of the second row
  • the number of single refresh rows is 2
  • the number of single refresh rows can be represented by 1 bit
  • the refresh circuit can directly add 1 to the highest bit of the row identifier. Get the row ID of row 4098.
  • the indication line information includes the line identifier 0000000000001 of the second line, the number of single refresh lines is 4, and the number of single refresh lines needs to be represented by two bits, and the first two bits of the line identifier of the second line can be added respectively 01, 10, and 11, so that the row identifiers of other target rows can be obtained as 0100000000001 (row 2050), 1000000000001 (row 4098), and 1100000000001 (row 6146).
  • This decoding method does not have any special requirements on the number of storage partitions in the bank.
  • the bank may include storage partitions to the power of 2 or other numbers of storage partitions.
  • the second decoding mode there is no special requirement for the single refresh line number Y of the refresh circuit, and the value can be an integer power of 2, or other values.
  • the refresh circuit can determine Y target rows according to the row identifier of the indicated row and the single refresh row number Y, and there is a storage partition between adjacent target rows.
  • the controller 102 and the memory 101 default to at least one behavior indicator row with the smallest row identifier in the target row.
  • the refresh circuit 1 can determine the target behavior: row 1, row 2049 (the first row in the second storage partition), and 4097 Row (the first row in the third storage partition).
  • the refresh circuit 1 can determine the target behavior: row 3 and row 2051 (the third row in the second storage partition).
  • the refresh circuit may also use other decoding methods, which are not listed in the embodiment of the present application.
  • the refresh circuit can refresh the target row in the corresponding bank according to the row identifier of the target row.
  • the process of refreshing any target row by the refresh circuit mainly includes an activation operation and a precharge operation.
  • the activation operation can be understood as the target refresh circuit inputting the data signal corresponding to the data in the target row into the sense amplifier.
  • the sense amplifier can amplify the input signal.
  • the precharge operation can be understood as the target refresh circuit rewrites the data signal output by the sense amplifier into the target row, thereby achieving refresh of the target row.
  • the controller 102 may also determine the maximum number of refreshable rows or the maximum number of common refreshable rows that the refresh circuit can support, so that the refresh circuit can refresh the target in the corresponding bank. Row. Specifically, it can include at least the following two possible implementations:
  • the controller 102 can query the maximum number of refreshable rows of a specific target bank through the first query information.
  • the first query information may include the bank identifier of the target bank.
  • the control circuit 1011 can obtain the maximum refreshable number of rows of the target bank according to the first query information, and return the maximum refreshable number of rows of the target bank to the controller 102.
  • the maximum number of refreshable rows of each bank can be stored in the control circuit 1011 in advance, and the control circuit 1011 can directly read the maximum number of refreshable rows of the target bank.
  • the controller 102 receives the maximum refreshable number of rows of the target bank returned by the memory 101. Before the controller 102 sends the above-mentioned type 2 refresh instruction information to the memory 101, the processing circuit 1021 may determine the target row to be refreshed according to the maximum number of refreshable rows of the target bank, where the target row to be refreshed determined by the processing circuit 1021 The number of rows is not greater than the maximum number of refreshable rows of the target bank.
  • controller 102 may also use the first query information to separately obtain and save the maximum refreshable number of rows in each bank. In the subsequent refresh operation process, the controller 102 may directly determine the target row according to the maximum number of refreshable rows of the saved target bank.
  • the refresh circuit corresponding to the target bank since the number of target rows is not greater than the maximum number of refreshable rows of the target bank, it is advantageous for the refresh circuit corresponding to the target bank to refresh the target rows in the target bank, and the memory 101 can correctly execute the refresh instruction information.
  • the controller 102 can also query the maximum number of public refreshable rows of the N banks through the second query information. After the control circuit 1011 receives the second query information sent by the controller 102, it can obtain the maximum refreshable number of rows in each of the N banks. The control circuit 1011 can then determine the maximum number of common refreshable rows of the N banks by the minimum value of the maximum number of refreshable rows in the N banks, and return the maximum number of common refreshable rows to the controller 102.
  • control circuit 1011 may also pre-store the maximum number of public refreshable rows, and after receiving the second query information, read the maximum number of public refreshable rows and send the read maximum number of public refreshable rows Give to the controller 102.
  • the controller 102 receives the maximum number of public refreshable rows returned by the memory 101. Before sending the refresh instruction information of type one, the controller 102 may determine at least one target row according to the maximum number of common refreshable rows, where the number of at least one target row is not greater than the maximum number of common refreshable rows.
  • the number of at least one target row is not greater than the maximum number of common refreshable rows, the number of at least one target row is not greater than the maximum number of refreshable rows in each bank among N banks, that is, each refresh circuit has The target row in the corresponding bank can be refreshed, so that the memory 101 can correctly execute the refresh instruction information.
  • the controller 102 can directly specify at least one target row to be refreshed through the refresh instruction information, which is beneficial to improve the flexibility of the refresh operation.
  • some application scenarios are taken as examples to illustrate the flexibility of the embodiments of the present application.
  • bank1 includes 8192 rows of storage cells, in which small black squares indicate storage cells that store valid data, and small white squares indicate storage cells that do not store valid data.
  • some rows store valid data, and some rows do not store valid data.
  • the controller 102 may obtain the configuration information of the memory 101 during the configuration phase, and the configuration information may include storage information of whether valid data is stored in each row in bank1.
  • the processing circuit 1021 can determine the target row to be refreshed from the rows in which valid data is stored, and indicate the target row through the refresh indication information. Therefore, the memory 101 can be prevented from refreshing the rows that do not store valid data, thereby helping to reduce the energy consumption of the refresh operation. .
  • the rows that store valid data in the embodiments of the present application can be rows where all storage units store valid data, or rows where some storage units store valid data. This is not much in the embodiments of the present application. Make restrictions.
  • the controller 102 may configure the number of single refresh rows of the refresh circuit 1 to 4, and refresh bank 1 by sending 4 refresh instructions.
  • the four refresh instruction information may respectively include the bank identifier of bank1 and the row identifier of row 1, the bank identifier of bank1 and the row identifier of row 2, the bank identifier of bank1 and the row identifier of row 3, bank1.
  • the refresh circuit 1 needs to refresh 8192 rows of memory cells, while using the technical solution provided by the embodiment of the present application, the refresh circuit 1 only needs to refresh 16 rows of memory cells. It can be seen that the embodiment of the present application is beneficial to reduce the number of rows that need to be refreshed by the refresh circuit 1, and thereby is beneficial to reduce the power consumption of refresh operations.
  • Scenario 2 If only bank1 and bank2 store valid data in the N banks of the memory 101, in this case, the processing circuit 1021 can determine the target bank from bank1 and bank2. Other banks (bank3 to N) may not be refreshed, which helps to save power consumption caused by refresh operations as a whole.
  • the processing circuit 1021 may also determine at least one bank to be read where the data to be read is located; from the N banks, among banks other than the at least one bank to be read, determine the above-mentioned at least one target bank.
  • the processing circuit 1021 may determine at least one bank from banks2 to N as the target bank.
  • bank1 and bank2 store valid data.
  • the processing circuit 1021 can determine that bank2 is the target bank, that is, determine that bank2 will be refreshed next. This is beneficial to improve the read and write performance of the memory 101 while saving the power consumption caused by the refresh operation as a whole.
  • the controller 102 may also adjust the number of target rows to be refreshed in different banks, so that different banks may have the same refresh period, thereby facilitating management.
  • banks 1 to N all include 8192 rows of memory cells, and each bank includes four memory partitions. Among them, the entire bank space of bank1 to bank4 stores valid data, and bank5 to bankN only use 1/4 rows to store valid data.
  • the controller 102 may obtain the configuration information of the memory 101 during the configuration phase, and the configuration information includes the above-mentioned storage information of banks 1 to N.
  • the controller 102 may configure the number of single refresh rows of the corresponding refresh circuit to 4. Generally speaking, the controller 102 should control the sending time of the refresh instruction information, so that for each bank, the controller 102 can complete the refresh of the bank within one refresh period.
  • the controller 102 may configure the number of single refresh rows of the corresponding refresh circuit to 1, that is, the number of at least one target row is 1. In this case, banks 1 to N will have the same refresh period, which can be easily managed by the controller 102.
  • N the number of N banks include 16384 rows of memory cells, and the value of N is 8.
  • the current refresh instruction it is assumed that it can refresh two rows of 8 banks at a time, that is, a total of 16 rows, so the current refresh instruction takes a long time to complete a refresh.
  • the current refresh command has a large overhead, and the refresh cycle time (refresh cycle time, tRFC) of the refresh command takes a large value.
  • the current tRFC value of the refresh command is 280ns.
  • the controller 102 needs to wait at least 280 ns before continuing to access the memory 101.
  • the refresh period is 64 ms
  • the controller 102 needs to send 16,384 refreshes within 64ms. Instruction information, that is, an average refresh instruction information is sent every 3.9 us.
  • the waiting time may only include that the read and write operations of the control circuit 1011 are switched from one bank (target bank) to another bank (bank to be read)
  • the required time that is, the controller 102 does not need to wait for the memory 101 to complete the refresh operation.
  • the use of the embodiment of the present application is also beneficial to reduce the overhead ratio of the memory 101. It can be understood that the data reading and writing to the memory 101 in the tRFC will be restricted. Therefore, the lower the proportion of overhead, the smaller the impact of the refresh process on the data reading and writing process. Therefore, the embodiments of the present application are beneficial to further improve the read and write performance of the memory 101.
  • N banks include 16384 rows of memory cells, and the value of N is 8.
  • bank1 to bank4 store 8192 rows of valid data
  • bank5 to bank8 store 4096 rows of valid data. Then, the total number of rows that actually need to be refreshed is 8192 ⁇ 4+4096 ⁇ 4.
  • the number of single refresh rows for each bank can be adjusted, that is, the number of at least one target row. For example, if the number of rows in a single refresh of refresh circuits 1 to 4 is configured to 4, and the number of rows in a single refresh of refresh circuits 5 to 8 is configured to 2, then the refresh operation performance is equivalent to the performance of scene 5, but because the total rows refreshed in scene 6 The number 8192 ⁇ 4+4096 ⁇ 4 is 62.5% less than the total number of rows refreshed in scene 5 of 16384 ⁇ 8. Therefore, scenario 6 analyzes energy consumption and saves energy compared to refreshing all rows.
  • the processing circuit 1021 may first determine the target bank by the method provided by scene two, and then determine at least one target row by the method of scene one.
  • the embodiments of the present application will not enumerate them one by one.
  • the time interval between two adjacent refreshes should not be less than the refresh period of the memory 101 to prevent data Lost.
  • the refresh period can be obtained according to the electrical properties of the capacitor, which is not limited in the embodiment of the present application.
  • the processing circuit 1021 may also determine the target row to be refreshed according to the current time point and the refresh period, where the time interval between the time point of the last refresh of each target row and the current time point is not Greater than the refresh period. That is to say, the time interval between the current point in time when any row is refreshed and the point in time when the row is last refreshed should not exceed the refresh period. From the perspective of a bank, it can also be understood that all rows in the bank need to be refreshed at least once during the refresh cycle.
  • the processing circuit 1021 can also obtain the environmental parameters of the memory 101 and adjust the refresh cycle according to the environmental parameters.
  • the controller 102 may also be connected with a temperature sensor, and the temperature sensor may be arranged near the memory 101. In this way, the processing circuit 1021 can obtain the ambient temperature of the memory 101, and then can adjust the refresh period according to the ambient temperature.
  • the refresh period can be gradually shortened as the ambient temperature rises.
  • the refresh period can be adjusted stepwise. For example, when the ambient temperature is lower than 85°C, the refresh period can be 64 ms. When the ambient temperature is between 85°C and 95°C, the refresh cycle can be modified from 64ms to 32ms.

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Abstract

本申请公开了一种存储器、控制器、刷新方法及存储系统，其中，控制器可以向存储器发送刷新指示信息，以向存储器指示待刷新的至少一个目标行。存储器进而可以根据刷新指示信息，刷新其内部的至少一个目标行。控制器可以通过刷新指示信息灵活控制存储器接下来刷新的行，从而有利于使刷新操作能够灵活适应不同的应用场景。

Description

一种存储器、控制器、刷新方法及存储系统 技术领域
本申请涉及存储器刷新技术领域，尤其涉及一种存储器、控制器、刷新方法及存储系统。
背景技术
电容式存储器的价格低廉、存储密度较高，是电子设备中常见的基础元件。例如，动态随机存取存储器(dynamic random access memory，DRAM)，便是利用电容对电荷的存储功能实现了数据存储。
具体来说，存储器的存储空间一般会被配置为N个并行排列的库(bank)，N为大于或等于1的整数。每一个bank，皆可以理解为一二维的存储阵列，其中，横向称为行，纵向称为列。存储阵列中的一个存储单元包括一个电容，可以存储1bit数据。由于电容中的电荷会随着漏电而不断流失，因此，电容里的数据必须被定期读取并重新写入，以补偿流失的电荷，这种操作也叫做刷新。
目前，对存储器进行刷新的技术方案数量有限，尚无法灵活适应不同的应用场景。因此，对存储器进行刷新的技术方案还有待进一步研究。
发明内容
本申请提供一种存储器、控制器、刷新方法及存储系统，用以提供一种具有较高灵活性的存储器刷新操作。
第一方面，本申请实施例提供一种存储器，主要包括控制电路、刷新电路和存储区域。其中：控制电路可以接收刷新指示信息，该刷新指示信息用于指示待刷新的至少一个目标行；控制电路可以进而可以根据刷新指示信息，控制刷新电路刷新存储区域中至少一个目标行。
本申请实施例中，控制电路接收的刷新指示信息可以指示待刷新的目标行，也就是说，用于控制存储器的控制器，可以根据当前的应用场景，通过刷新指示信息灵活控制存储器接下来刷新的行，从而有利于使刷新操作能够灵活适应不同的应用场景。
一般来说，存储器的存储区域可以划分为至少一个bank。在一种可能的实现方式中，本申请实施例所提供的刷新指示信息中，至少一个目标行在每个bank中均存在对应的行。也就是说，控制器可以通过刷新指示信息，指示存储器刷新至少一个bank中，每个bank的至少一个目标行。例如，若刷新指示信息所指示的第2行为目标行，则存储器可以分别刷新至少一个bank中第2行。
在另一种可能的实现方式中，存储器中可以包括至少一个刷新电路，存储区域可以包括至少一个bank，上述至少一个刷新电路分别用来执行对上述至少一个bank的刷新操作。本申请实施例中，刷新指示信息还可以指示目标bank。控制电路可以根据刷新指示信息获取目标行信息，并向目标bank对应的刷新电路发送该目标行信息。目标行信息可以指示上述至少一个目标行。刷新电路进而可以根据目标行信息，刷新目标bank中的至少一个目标行。
在一种可能的实现方式中，控制电路还可以接收控制器发送的第一查询信息，第一查 询信息可以指示目标bank；控制电路可以根据第一查询信息，获取目标bank的最大可刷新行数，并向控制器返回目标bank的最大可刷新行数。采用该实现方式，控制器可以得到目标bank的最大可刷新行数。控制器从而可以根据该最大可刷新行数确定至少一个目标行，使至少一个目标行的数量不大于目标bank的最大可刷新行数，进而可以使存储器能够正确执行控制器的刷新指示信息。
在一种可能的实现方式中，控制电路还可以接收第一配置信息，该第一配置信息可以指示至少一个目标行的数量和目标bank；根据至少一个目标行的数量，更新目标bank对应的刷新电路的单次刷新行数。采用该实现方式，可以为目标bank对应的刷新电路配置至少一目标行的数量，使得刷新电路在接下来的刷新操作中，可以同时刷新至少一个目标行。
示例性的，控制电路发送给刷新电路的目标行信息中，可以包括至少一个目标行中指示行的行标识；目标bank对应的刷新电路可以根据指示行的行标识，和单次刷新行数计算得到至少一个目标行的行标识；刷新电路进而可以根据至少一个目标行的行标识，刷新目标bank中的至少一个目标行。
在一种可能的实现方式中，控制电路还可以在接收到控制器发送的第二查询信息后，向控制器返回至少一个bank的最大公共可刷新行数，最大公共可刷新行数可以是根据至少一个bank中，最大可刷新行数的最小值得到的。控制器可以通过第二查询信息得到至少一个bank的最大公共可刷新行数，从而可以根据最大公共可刷新行数确定至少一个目标行，使至少一个目标行的数量不大于最大公共可刷新行数。又由于最大公共可刷新行数可以是根据至少一个bank中，最大可刷新行数的最小值得到的，因此至少一个目标行的数量将小于至少一个bank中每个bank的最大可刷新行数，使得至少一个刷新电路皆可以在接下来的刷新操作中，可以同时刷新至少一个目标行。
在一种可能的实现方式中，存储器中可以包括至少一个刷新电路，存储区域可以划分为至少一个bank，存储器中的至少一个刷新电路可以分别执行对至少一个bank的刷新操作。本申请实施例中，控制电路还可以接收第二配置信息，该第二配置信息可以指示至少一个目标行的数量；控制电路可以根据第二配置信息，分别向上述至少一个刷新电路发送第一指示信息，该第一指示信息可以指示至少一个目标行的数量；每个刷新电路皆可以根据至少一个目标行的数量，更新自身的单次刷新行数。也就是说，控制器可以通过第二配置信息为存储器的至少一个刷新电路同时配置相同的单次刷新行数。
示例性的，刷新指示信息中可以包括至少一个目标行中指示行的行标识；控制电路可以根据刷新指示信息，获取目标行信息，并分别向存储器的至少一个刷新电路发送上述目标行信息，该目标行信息可以包括上述至少一个目标行中指示行的行标识；每个刷新电路皆可以根据指示行的行标识，和单次刷新行数计算得到至少一个目标行的行标识；刷新电路进而可以根据至少一个目标行的行标识，刷新对应的bank中，至少一个目标行。
第二方面，本申请实施例提供一种控制器，第二方面中相应方案的技术效果可以参照第一方面中对应方案可以得到的技术效果，重复之处不予详述。示例性的，本申请实施例所提供的控制器主要包括处理电路和接口电路，其中：处理电路可以确定存储器的存储区域中，待刷新的至少一个目标行；接口电路可以向存储器发送刷新指示信息，该刷新指示信息可以指示所述至少一个目标行。
在一种可能的实现方式中，存储器的存储区域可以划分为至少一个库bank，控制器所发送的刷新指示信息所指示的至少一个目标行在每个bank中均存在对应的行。
在一种可能的实现方式中，存储器包括至少一个bank；该刷新指示信息还可以指示至少一个bank中的目标bank。
在一种可能的实现方式中，接口电路还可以向存储器发送第一查询信息，该第一查询信息可以指示存储器返回目标bank的最大可刷新行数；处理电路进而可以根据目标bank的最大可刷新行数，确定至少一个目标行，其中，至少一个目标行的数量不大于目标bank的最大可刷新行数。控制器在发送刷新指示信息之前，可以先通过第一查询信息获取目标bank的最大可刷新行数，进而根据目标bank的最大可刷新行数确定至少一个目标行。由于至少一个目标行的数量不大于目标bank的最大可刷新行数，因此有利于保证存储器能够正常执行该刷新指示信息。
在一种可能的实现方式中，接口电路还可以向存储器发送第一配置信息，该第一配置信息可以指示存储器根据至少一个目标行的数量，更新对目标bank的单次刷新行数。
在本申请实施例中，控制器可以灵活控制存储器的刷新：
例如，处理电路可以从目标bank内，存储有有效数据的行中确定至少一个目标行。也就是说，控制器控制存储器刷新存储有有效数据的行，对存储有无效或无用数据的行则可以不刷新，从而有利于从整体上降低刷新操作带来的功耗。
又例如，处理电路可以确定待读取的数据所在的至少一个待读取bank；从至少一个bank中，除上述至少一个待读取bank之外的bank中，确定目标bank。也就是说，控制器可以控制存储器在接下来刷新不会读取的bank中的数据，而接下来需要读取的bank则可以先不刷新，以降低刷新操作对数据读取的影响。
在另一种可能的实现方式中，存储器包括至少一个bank，接口电路还可以向存储器发送第二查询信息，该第二查询信息可以指示存储器返回至少一个bank的最大公共可刷新行数；处理电路可以根据至少一个bank的最大公共可刷新行数，确定至少一个目标行，其中，至少一个目标行的数量不大于最大公共可刷新行数。存储器中，不同的bank所支持的最大可刷新行数有可能不同。本申请实施例中，控制器在发送刷新指示信息之前，可以先通过第二查询信息获取至少一个bank的最大公共可刷新行数，进而根据最大公共可刷新行数确定至少一个目标行。由于至少一个目标行的数量不大于最大公共可刷新行数，因此有利于保证存储器能够正常执行该刷新指示信息。
在一种可能的实现方式中，接口电路还可以向存储器发送第二配置信息，该第二配置信息可以指示存储器中根据至少一个目标行的数量，分别更新对至少一个bank的单次刷新行数。
在一种可能的实现方式中，所述刷新指示信息包括所述至少一个目标行中指示行的行标识。
在一种可能的实现方式中，处理电路可以根据当前时间点和刷新周期，确定至少一个目标行，其中，最后一次刷新每个目标行的时间点与所述当前时间点之间的时间间隔，皆不大于刷新周期，处理电路还可以获取存储器的环境参数，根据环境参数调节上述刷新周期。也就是说，控制器可以根据环境参数灵活调节刷新周期。
第三方面，本申请实施例提供一种刷新方法，第三方面中相应方案的技术效果可以参照第一方面中对应方案可以得到的技术效果，重复之处不予详述。示例性的，本申请实施例所提供的刷新方法可以应用于存储器，该方法主要包括：存储器接收刷新指示信息，该刷新指示信息可以指示存储器的存储区域中，待刷新的至少一个目标行；存储器进而可以 根据刷新指示信息，刷新存储区域中的至少一个目标行。
在一种可能的实现方式中，存储器的存储区域可以划分为至少一个bank。存储器在刷新上述至少一个目标行时，可以分别刷新上述至少一个bank中，与至少一个目标行对应的行。
在另一种可能的实现方式中，存储器的存储区域可以划分为至少一个bank，刷新指示信息还可以指示上述至少一个bank中的目标bank；存储器在根据刷新指示信息，刷新至少一个目标行时，可以根据刷新指示信息，刷新目标bank中至少一个目标行。
在一种可能的实现方式中，存储器接收刷新指示信息之前还可以先接收控制器发送的第一查询信息，该第一查询信息可以指示目标bank；存储器可以根据第一查询信息，获取目标bank的最大可刷新行数，并向控制器返回目标bank的最大可刷新行数。
在一种可能的实现方式中，接收刷新指示信息之前，还可能先接收第一配置信息，该第一配置信息可以指示至少一个目标行的数量和目标bank；根据至少一个目标行的数量，更新对目标bank的单次刷新行数。
在一种可能的实现方式中，存储器在根据刷新指示信息，刷新目标bank中至少一个目标行时，可以根据刷新指示信息，获取至少一个目标行中指示行的行标识。存储器进而可以根据指示行的行标识，和单次刷新行数计算得到至少一个目标行的行标识；存储器从而可以根据至少一个目标行的行标识，刷新目标bank中，上述至少一个目标行。
在另一种可能的实现方式中，存储器在接收刷新指示信息之前，还可以在接收到控制器发送的第二查询信息后，向控制器返回至少一个bank的最大公共可刷新行数，该最大公共可刷新行数是根据至少一个bank中，最大可刷新行数的最小值得到的。
在一种可能的实现方式中，存储器在接收刷新指示信息之前，还可以先接收第二配置信息，该第二配置信息可以指示至少一个目标行的数量；存储器可以根据至少一个目标行的数量，分别更新对至少一个bank的单次刷新行数。
在一种可能的实现方式中，刷新指示信息包括至少一个目标行中指示行的行标识；存储器在分别刷新至少一个bank中，与至少一个目标行对应的行时，可以根据刷新指示信息，获取目标行信息，该目标行信息可以包括上述至少一个目标行中指示行的行标识；存储器进而可以根据指示行的行标识，和分别对至少一个bank的单次刷新行数，计算得到至少一个目标行的行标识；存储器从而可以根据至少一个目标行的行标识，分别刷新至少一个bank中，与至少一个目标行对应的行。
第四方面，本申请实施例提供一种刷新方法，第四方面中相应方案的技术效果可以参照第二方面中对应方案可以得到的技术效果，重复之处不予详述。示例性的，本申请实施例所提供的刷新方法可以应用于控制器，本申请实施例提供的方法主要包括：控制器确定存储器的存储区域中，待刷新的至少一个目标行；控制器进而向存储器发送刷新指示信息，该刷新指示信息可以指示上述至少一个目标行。
在一种可能的实现方式中，存储器的存储区域中可以划分为至少一个库bank，刷新指示信息所指示的至少一个目标行在每个bank中均存在对应的行。
在另一种可能的实现方式中，存储器的存储区域可以划分为至少一个bank；刷新指示信息还可以指示至少一个bank中的目标bank，在此情况下，存储器可以只刷新目标bank中需要刷新的目标行。
在一种可能的实现方式中，控制器在确定待刷新的至少一个目标行之前，还可以先向 存储器发送第一查询信息，该第一查询信息可以指示存储器返回目标bank的最大可刷新行数；控制器在确定存储器的存储区域中，待刷新的至少一个目标行时，可以根据目标bank的最大可刷新行数，确定至少一个目标行，其中，至少一个目标行的数量不大于目标bank的最大可刷新行数。
在一种可能的实现方式中，控制器在向存储器发送刷新指示信息之前，还可以先向存储器发送第一配置信息，该第一配置信息可以指示存储器根据至少一个目标行的数量更新对目标bank的单次刷新行数。
在一种可能的实现方式中，控制器在确定存储器的存储区域中，待刷新的至少一个目标行时，可以从目标bank内，存储有有效数据的行中确定至少一个目标行。
在一种可能的实现方式中，所述存储器的存储区域包括多个bank，控制器在确定存储器的存储区域中，待刷新的至少一个目标行之前，还可以确定待读取的数据所在的至少一个待读取bank；从所述多个bank中，除至少一个待读取bank之外的bank中，确定目标bank。
在另一种可能的实现方式中，存储器的存储区域可以划分为至少一个bank；控制器在确定存储器的存储区域中，待刷新的至少一个目标行之前，还可以先向存储器发送第二查询信息，该第二查询信息可以指示存储器返回至少一个bank的最大公共可刷新行数；控制器在确定存储器的存储区域中，待刷新的至少一个目标行时，可以根据至少一个bank的最大公共可刷新行数，确定至少一个目标行，其中，上述至少一个目标行的数量不大于最大公共可刷新行数。
在一种可能的实现方式中，控制器在向存储器发送刷新指示信息之前，还可以先向存储器发送第二配置信息，该第二配置信息可以指示存储器根据至少一个目标行的数量更新对至少一个bank的单次刷新行数。
在一种可能的实现方式中，刷新指示信息中可以包括上述至少一个目标行中指示行的行标识。
在一种可能的实现方式中，控制器在确定存储器的存储区域中，待刷新的至少一个目标行时，可以根据当前时间点和刷新周期，确定至少一个目标行，其中，最后一次刷新每个目标行的时间点与当前时间点之间的时间间隔，皆不大于刷新周期，上述刷新周期由控制器根据存储器的环境参数进行调节。
第五方面，本申请实施例提供一种存储系统，第五方面中相应方案的技术效果可以参照第一方面中对应方案可以得到的技术效果，重复之处不予详述。示例性的，本申请实施例所提供的存储系统包括控制器和存储器，其中，控制器可以确定存储器的存储区域中，待刷新的至少一个目标行，向存储器发送刷新指示信息，该刷新指示信息可以指示至少一个目标行；存储器从而可以根据刷新指示信息，刷新上述至少一个目标行。
本申请的这些方面或其它方面在以下实施例的描述中会更加简明易懂。
附图说明
图1为本申请实施例适用的一种存储系统结构示意图；
图2为本申请实施例提供的一种刷新方法流程示意图；
图3为本申请实施例提供的一种bank的存储结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。需要说明的是，在本申请的描述中“至少一个”是指一个或多个，其中，多个是指两个或两个以上。鉴于此，本发明实施例中也可以将“多个”理解为“至少两个”。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，字符“/”，如无特殊说明，一般表示前后关联对象是一种“或”的关系。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
图1示例性示出了本申请实施例所适用的一种存储系统结构示意图。该存储系统100可以是具备数据存储功能的电子设备或集成芯片，例如，存储系统100可以是手机、电脑、智能相机等电子设备，也可以是片上系统(system on chip，SOC)、中央处理器(central processing unit，CPU)等芯片，本申请实施例对此并不多作限制。
如图1所示，存储系统100包括存储器101和控制器102。其中，控制器102可以包括处理电路1021和接口电路1022。示例性的，处理电路1021可以是逻辑运算电路，处理电路1021可以生成指令。接口电路1022可以是控制总线接口，控制器102可以通过接口电路1022，与存储器101之间通过控制总线连接。接口电路1022可以向存储器101的控制电路1011发送指令，从而可以指示控制电路1011完成数据读取、存储及刷新等任务。
一般来说，存储器101可以包括控制电路1011、刷新电路(刷新电路1至N)和存储区域1012。N为大于等于1的整数。也就是说，本申请实施例中，存储器101可以包括一个或多个刷新电路，本申请实施例对此并不多作限制。
存储区域1012可以是由多个存储单元构成的二维存储阵列。每个存储单元可以存储1bit数据。在本申请实施例中，存储器101可以为电容式存储器，例如，存储器101可以为DRAM。在此情况下，每个存储单元对应有至少一个电容，每个存储单元可以通过电容中存储的电荷实现数据存储。例如，针对任一存储单元，若该存储单元的电容存储有电荷，则该存储单元所存储的数据为1，若该存储单元的电容未存储有电荷，则该存储单元所存储的数据为0。
由于电容中的电荷会随着漏电而不断流失，因此，控制器102需要定期刷新存储器101。具体来说，控制器102可以向控制电路1011发送刷新指令，目前，该刷新指令多为自动刷新(auto-refresh)指令，或者激活(active)指令和预充电(pre-charge)指令。其中，auto-refresh指令也可以简称为refresh指令。
以refresh指令为例，控制器102可以向存储器101发送refresh指令。控制电路1011在接收到refresh指令后，将会根据控制电路1011内部预设的刷新逻辑，确定接下来需要刷新的目标行。
控制电路1011进而可以通过存储器101中的刷新电路完成对目标行的刷新。一般来说，如图1所示，存储区域1012还可以进一步分为多个库(bank)。每个bank皆可以为m×n的二维存储阵列，m为二维存储阵列的行数，m大于1，n为二维存储阵列的列数，n大于1。可以理解，不同的bank可以具有相同或不同行数和列数，本申请实施例对此并不多作限制。
存储器101中的多个刷新电路，可以分别执行对一个或多个bank的刷新操作。示例性 的，如图1所示，存储器101中的N个刷新电路可以分别刷新存储区域1012中的N个bank，也就是说，N个刷新电路可以与N个bank一一对应，如刷新电路1与bank1对应，则刷新电路1可以刷新bank1中的目标行。接下来，以N个刷新电路可以与N个bank一一对应为例进行说明，应理解，当多个刷新电路与多个bank之间为一对多的对应关系时，同样可以适用于本申请实施例。
控制电路1011在确定了目标行之后，可以向刷新电路1至N发送指示信息，以指示刷新电路1至N分别刷新bank1至N中的目标行。具体来说，刷新电路1在接收到指示信息后，可以刷新bank1中的目标行，刷新电路2在接收到指示信息后，可以刷新bank2中的目标行，等等。
需要指出的是，在目前的刷新操作中，由控制电路1011确定接下来需要刷新的目标行，控制器102并不知晓接下来需要刷新的目标行。假设每个bank皆包括8192行存储单元，则控制器102需要发送8192个refresh指令，才可以使存储器101中的每一个存储单元皆被刷新一次。
虽然目前控制器102可以通过refresh指令指示存储器101完成刷新，但该控制方式较为局限，无法灵活适应存储器101的不同的应用场景。例如，存储器101中存储的数据即可能是有效数据，也可能是无效数据。所谓无效数据，指的是没有存储价值的、无用的数据。目前的数据刷新操作中，存储器101也会刷新无效数据，因此会造成能耗浪费。
有鉴于此，本申请实施例提供一种控制器、存储器及刷新方法。在本申请实施例中，控制器102可以通过刷新指示信息向存储器101指示待刷新的至少一个目标行，因此，控制器102可以更加灵活地控制存储器101的刷新操作。可以理解，控制器102相较于控制电路1011，具有更强的逻辑判断能力，可以应对更为复杂的应用场景。相较于目前，由控制电路1011自行确定接下来需要刷新的行，本申请实施例通过控制器102直接指示待刷新的至少一个目标行，有利于使刷新操作能够灵活适应不同的应用场景。
图2示例性示出了本申请实施例所提供的一种刷新方法流程示意图，如图2所示，该方法主要包括以下步骤：
S201：控制器102确定存储器的存储区域中，待刷新的至少一个目标行。具体来说，可以由控制器102中的处理电路1021确定待刷新的至少一个目标行。控制器102可以根据当前的应用场景灵活确定待刷新的目标行，例如，可以根据存储器的访问情况、存储器的存储情况等因素确定待刷新的目标行，使对存储器的刷新操作能够灵活适应不同的应用场景。
S202：控制器102向存储器101发送刷新指示信息。具体来说，可以通过控制器102中的接口电路1022，向存储器101发送刷新指示信息，该刷新指示信息可以指示上述至少一个目标行。
S203：存储器101根据刷新指示信息，刷新至少一个目标行。具体来说，可以由控制电路1011根据刷新指示信息，控制存储器中的刷新电路，实现对上述至少一个目标行的刷新操作。
在本申请实施例中，刷新指示信息至少存在以下两种可能的实现类型：
类型一：刷新指示信息所指示的至少一个目标行在存储器101的N个bank中皆存在对应的行。控制电路1011可以控制刷新电路1至N分别刷新bank1至N中与目标行对应的行。
举例说明，若刷新指示信息指示第1行为目标行，则意味着，bank1至N中的第1行皆为目标行。控制电路1011在接收到该刷新指示信息后，可以控制刷新电路1至N分别刷新bank1至N中第1行。
类型二：刷新指示信息不仅可以指示待刷新的目标行，还可以指示目标bank。示例性的，控制器102还可以根据当前的应用场景从存储器101的N个bank中确定目标bank，并通过刷新指示信息指示该目标bank。控制电路1011可以在接收到刷新指示信息后，控制目标bank对应的刷新电路刷新目标bank中的目标行。其中，目标bank对应的刷新电路可以理解为用于对目标bank执行刷新操作的刷新电路。
举例说明，若刷新指示信息指示第1行为目标行，bank1为目标bank。控制电路1011在接收到该刷新指示信息后，可以控制刷新电路1刷新bank1第1行。
一般来说，刷新电路中配置有单次刷新行数，每个刷新电路需要按照当前配置的单次刷新行数刷新对应的bank。其中，刷新电路的单次刷新行数可以理解为刷新电路在执行一次刷新操作时，可以同时刷新的行数。以刷新电路1为例，若刷新电路1当前配置的单次刷新行数为2，则刷新电路1在接下来对bank1进行刷新时，可以同时刷新bank1中的两行存储单元。
有鉴于此，本申请实施例中，控制器102在向存储器101发送刷新指示信息之前，还可以通过配置信息配置存储器101中刷新电路的单次刷新行数。接下来，对配置单次刷新行数的过程作进一步的示例性说明。
在一种可能的实现方式中，控制器102可以向存储器101发送第一配置信息，第一配置信息可以指示待刷新的目标行的数量和目标bank。控制电路1011在接收到第一配置信息后，可以根据目标行的数量，更新目标bank对应的刷新电路的单次刷新行数。
具体来说，控制电路1011可以向目标bank对应的刷新电路发送第一指示信息，该第一指示信息可以向刷新电路指示至少一个目标行的数量。刷新电路在接收到第一指示信息后，便可以根据目标行的数量，更新自身的单次刷新行数。例如图1中，第一配置信息指示的目标刷新行数为2，目标bank为1，则控制电路1011可以向刷新电路1发送第一指示信息。刷新电路1在接收到第一指示信息后，便可以根据第一指示信息将单次刷新行数更新为2。
在另一种可能的实现方式中，控制器102可以向存储器101发送第二配置信息，第二配置信息可以指示待刷新的目标行的数量。示例性的，第二配置信息中可以不包括目标bank的bank标识，或者，第二配置信息中可以包括N个bank的bank标识，因此第二配置信息可以用于为存储器101中的N个刷新电路配置相同的单次刷新行数。
具体来说，控制电路1011在接收到第二配置信息后，可以分别向N个刷新电路发送上述第一指示信息，每个刷新电路在接收到第一指示信息后，皆可以根据目标行的数量，更新自身的单次刷新行数。例如图1中，第二配置信息指示的目标行的数量为2，则控制电路1011可以分别向刷新电路1至N发送第一指示信息。每个刷新电路在接收到第一指示信息后，皆可以根据第一指示信息将自身的单次刷新行数更新为2。
可以理解，控制器102还可以根据当前的应用场景灵活选择发送第一配置信息和/或第二配置信息，本申请实施例对此并不多作限制。例如，控制器102在发送第一配置信息或第二配置信息之前，还可以先确认刷新电路当前的单次刷新行数是否为至少一个目标行的数量，若是，控制器102则可以省去发送第一配置信息或第二配置信息，而直接发送刷新 指示信息。从而有利于简化刷新过程。
如前所述，控制电路1011可以根据刷新指示信息刷新存储区域1012中的目标行。示例性的，控制电路1011可以根据刷新指示信息获取目标行信息，控制电路1011将目标行信息发送给刷新电路，刷新电路便可以根据目标行信息刷新对应bank中的目标行。
在一种可能的实现方式中，刷新指示信息可以包括至少一个目标行中的指示行的行标识。其中，指示行可以是至少一个目标行中符合预设规则的行，例如，该指示行可以是至少一个目标行中行标识最小的行，也可以是行标识最大的行，也可以是行标识为中间值的行，本申请实施例对此并不多作限制。
控制电路1011在接收到刷新指示信息后，可以根据刷新指示信息获取目标行信息，该目标行信息包括刷新指示信息中指示行的行标识。控制电路1011将目标行信息发送给刷新电路。刷新电路进而可以根据指示行的行标识和单次刷新行数，计算得到至少一个目标行的行标识。
举例说明，图3示例性示出了bank1的存储阵列，其中，每一个小方格代表一个存储单元，黑色的小方格中存储有有效数据，白色的小方格中存储有无效数据或未存储数据。如图3所示，bank1共包括8192行存储单元，具体可以分为四个存储分区(存储分区1至4)，每个存储分区分别包括2048行存储单元。
一般来说，刷新电路在执行一次刷新操作的过程中，可以同时刷新不同存储分区中的行。例如，刷新电路1可以同时刷新图3所示的第1行存储单元和第2049行存储单元，其中第1行存储单元位于存储分区1中，第2049行存储单元位于存储分区2中。
在一种可能的实现方式中，每个bank中存储分区的数量，可以等同于该bank所对应的刷新电路的单次刷新行数的最大值。例如图3中，bank1包括4个存储分区，对应的刷新电路1的单次刷新行数的最大值为4，也可以理解为，bank1的最大可刷新行数为4。
刷新电路1在接收到刷新指示信息后，可以根据指示行的行标识和单次刷新行数，计算得到需要刷新的目标行的行标识。具体来说，刷新电路1可以按照预设的译码规则，根据单次刷新行数，确定指示行以及与指示行相邻的若干行为目标行。本申请实施例中，目标行的行标识可以是目标行的存储地址，也可以是目标行的序列号，本申请实施例对此并不多作限制。
示例性的，本申请实施例中刷新电路1至少可以通过以下任意译码规则确定需要刷新的目标行：
译码方式一
本译码方式适用于包括X个存储分区的bank，X为2的整数次幂。如图3所示，bank1包括4个存储分区，便适用于本译码方式。
在译码方式一中，刷新电路的单次刷新行数Y也应为2的整数次幂，且单次刷新行数Y不大于X。例如，与图3所示的bank1对应的刷新电路1，可以适用的单次刷新行数Y为1、2和4。
在译码方式一中，刷新电路可以根据单次刷新行数Y和指示行的行标识确定待刷新的目标行，且目标行之间间隔X/Y个存储分区。
以图3所示的bank1为例，假设控制器102与存储器101之间默认待刷新的目标行中 行标识最小的行为指示行。例如，当指示行为第1行，单次刷新行数Y为4时，刷新电路1可以确定相邻的目标行之间间隔1个存储分区，在指示行为第1行的情况下，刷新电路1可以确定目标行为：第1行、第2049行(第二个存储分区内的第一行)、第4097行(第三个存储分区内的第一行)和第6145行(第四个存储分区内的第一行)。
又例如，指示行为第1行，单次刷新行数为2，则刷新电路1可以确定相邻的目标行之间间隔2个存储分区，在指示行为第1行的情况下，刷新电路1可以确定目标行为：第1行和第4097行(第三个存储分区内的第一行)。
采用该译码规则，可以简化刷新电路的计算过程。具体来说，每一行的行标识皆可以采用二级制形式进行表示。例如，图3所示的bank1中共包括8192行存储单元，可以通过13位二级制的行标识表示。其中，第1行的行标识可以表示为0000000000000，第2行的行标识可以表示为00000000001，……，第2049行的行标识可以表示为0100000000000，……,第4097行的行标识可以表示为1000000000000，……，第6145行的行标识可以表示为1100000000000，第8192行的行标识可以表示为1111111111111。
在此情况下，四个存储分区可以通过2个比特位表示。也就是说，直接在指示行的前两位加上单次刷新行数，既可以得到除指示行之外的其它目标行。例如，指示行信息包括第2行的行标识0000000000001，单次刷新行数为2，单次刷新行数采用1个比特位即可表示，则刷新电路可以直接在行标识的最高位加1，得到第4098行的行标识。
又例如，指示行信息包括第2行的行标识0000000000001，单次刷新行数为4，单次刷新行数需要采用两个比特位表示，则可以在第2行行标识的前两位分别加01、10和11，从而可以得到其它目标行的行标识为0100000000001(第2050行)、1000000000001(第4098行)和1100000000001(第6146行)。
由此可见，采用上述译码规则，有利于简化刷新电路的译码过程。
译码方式二：
本译码方式对bank中存储分区的数量并没有特别要求，bank中既可以包括2的整数次幂个存储分区，也可以包括其它数量的存储分区。在译码方式二中，刷新电路的单次刷新行数Y也没有特别要求，取值既可以是2的整数次幂，也可以是其它取值。
在译码方式二中，刷新电路可以根据指示行的行标识和单次刷新行数Y确定Y个目标行，相邻的目标行之间间隔一个存储分区。
以图3所示的bank1为例，假设控制器102与存储器101之间默认至少一个目标行中行标识最小的行为指示行。例如，当指示行为第1行，单次刷新行数Y为3时，刷新电路1可以确定目标行为：第1行、第2049行(第二个存储分区内的第一行)、和第4097行(第三个存储分区内的第一行)。又例如，当指示行为第3行，单次刷新行数Y为2时，刷新电路1可以确定目标行为：第3行和第2051行(第二个存储分区内的第三行)。
应理解，除上述译码方式一和译码方式二之外，刷新电路还可以使用其他译码方式，本申请实施例对此不再一一列举。
刷新电路在确定待刷新的目标行的行标识之后，便可以根据目标行的行标识刷新对应的bank中目标行。
刷新电路对任一目标行进行刷新的过程，主要包括激活操作和预充电操作。其中，激活操作可以理解为目标刷新电路将目标行中的数据对应的数据信号输入感应放大器中。感 应放大器可以对输入信号进行放大。预充电操作可以理解为，目标刷新电路将感应放大器输出的数据信号重新写入目标行，从而实现了目标行的刷新。
需要指出的是，不同的bank中存储分区的数量有可能相同，也有可能不同，因此不同bank的最大可刷新行数有可能相同，也有可能不同。有鉴于此，控制器102在确定待刷新的目标行之前，还可以先确定刷新电路可以支持的最大可刷新行数或最大公共可刷新行数，以使刷新电路可以刷新对应的bank中的目标行。具体来说，至少可以包括以下两种可能的实现方式：
第一查询信息
控制器102可以通过第一查询信息查询特定的目标bank的最大可刷新行数。示例性的，该第一查询信息可以包括目标bank的bank标识。控制电路1011接收第一查询信息后，可以根据第一查询信息，获取目标bank的最大可刷新行数，并向控制器102返回目标bank的最大可刷新行数。在一种可能的实现方式中，每个bank的最大可刷新行数可以预先存储于控制电路1011，控制电路1011可以直接读取目标bank的最大可刷新行数。
控制器102接收存储器101返回的目标bank的最大可刷新行数。控制器102在向存储器101发送上述类型二的刷新指示信息之前，处理电路1021可以根据目标bank的最大可刷新行数，确定待刷新的目标行，其中，处理电路1021所确定的待刷新的目标行的数量不大于目标bank的最大可刷新行数。
可以理解，控制器102也可以采用第一查询信息分别获取并保存每个bank的最大可刷新行数。在后续的刷新操作过程中，控制器102可以直接根据保存的目标bank的最大可刷新行数，确定目标行。
采用该实现方式，由于目标行的数量不大于目标bank的最大可刷新行数，因此，有利于目标bank对应的刷新电路可以刷新目标bank中的目标行，存储器101可以正确执行刷新指示信息。
第二查询信息
控制器102还可以通过第二查询信息查询N个bank的最大公共可刷新行数。控制电路1011接收控制器102发送的第二查询信息后，可以获取N个bank中每个bank的最大可刷新行数。控制电路1011进而可以N个bank中最大可刷新行数的最小值，确定该N个bank的最大公共可刷新行数，并向控制器102返回该最大公共可刷新行数。
可以理解，控制电路1011也可以预先存储有该最大公共可刷新行数，在接收到第二查询信息后，读取该最大公共可刷新行数并将读取到的最大公共可刷新行数发送给控制器102。
控制器102接收存储器101返回的最大公共可刷新行数。在发送上述类型一的刷新指示信息之前，控制器102可以根据最大公共可刷新行数，确定至少一个目标行，其中，至少一个目标行的数量不大于该最大公共可刷新行数。
由于至少一个目标行的数量不大于最大公共可刷新行数，因此，至少一目标行的数量不大于N个bank中，每个bank的最大可刷新行数，也就是说，每个刷新电路皆可以刷新对应的bank中的目标行，进而使得存储器101可以正确执行刷新指示信息。
在本申请实施例中，控制器102通过刷新指示信息，可以直接指定待刷新的至少一个目标行，有利于提高刷新操作的灵活性。接下来，以部分应用场景为例，对本申请实施例的灵活性进行示例性说明。
场景一
如图3所示的bank1中包括8192行存储单元，其中，黑色小方格表示存储有有效数据的存储单元，白色小方格表示未存储有有效数据的存储单元。图3中，一部分行存储有有效数据，另一部分行未存储有效数据。控制器102可以在配置阶段获取存储器101的配置信息，该配置信息中便可以包括bank1中每行是否存储有有效数据的存储信息。
处理电路1021可以从存储有有效数据的行中确定待刷新的目标行，并通过刷新指示信息指示目标行，因此可以避免存储器101刷新未存储有效数据的行，从而有利于降低刷新操作的能耗。
一般来说，刷新电路多以行为单位进行刷新。因此，本申请实施例中存储有有效数据的行，既可以是所有存储单元都存储有有效数据的行，也可以是部分存储单元存储有有效数据的行，本申请实施例对此并不多作限制。
例如，控制器102可以将刷新电路1的单次刷新行数配置为4，通过发送4个刷新指示信息便可以完成对bank1的刷新。示例性的，该4个刷新指示信息分别可以包括bank1的bank标识和第1行的行标识，bank1的bank标识和第2行的行标识，bank1的bank标识和第3行的行标识，bank1的bank标识和第4行的行标识。
如图3所示，bank1中共存在16个存储有有效数据的行。若采用目前的刷新方案，刷新电路1需要刷新8192行存储单元，而采用本申请实施例所提供的技术方案，刷新电路1只需要刷新16行存储单元。可见，本申请实施例有利于降低刷新电路1所需要刷新的行数，进而有利于降低刷新操作的功耗。
场景二：若存储器101的N个bank中，只有bank1和bank2存储有有效数据，在此情况下，处理电路1021可以从bank1和bank2中确定目标bank。其它bank(bank3至N)可以不刷新，从而有利于从整体上节省刷新操作带来的功耗。
场景三：处理电路1021还可以确定待读取的数据所在的至少一个待读取bank；从N个bank中，除该至少一个待读取bank之外的bank中，确定上述至少一个目标bank。示例性的，当控制器102轮询到bank1时，也就是说，bank1为待读取的bank，则处理电路1021可以从bank2至N中确定至少一个bank为目标bank。采用该实现方式，可以在保证正常的数据读写的情况下，完成刷新操作，有利于提高存储器101的读写性能。
更进一步的，如上例中，只有bank1和bank2存储有有效数据，在bank1为待读取的bank时，处理电路1021可以确定bank2为目标bank，也就是确定接下来对bank2进行刷新操作。从而有利于在提高存储器101的读写性能的同时，从整体上节省刷新操作带来的功耗。
场景四：
本申请实施例中，控制器102还可以调节不同bank的待刷新的目标行的数量，使不同bank之间可以具有相同的刷新周期，从而便于管理。
假设bank1至N皆包括8192行存储单元，且每个bank皆包括四个存储分区。其中，bank1～bank4的全bank空间皆存储有有效数据，bank5～bankN只用了1/4行存储有效数据。控制器102可以在配置阶段获取存储器101的配置信息，该配置信息中便包括了bank1至N的上述存储信息。
进而在对bank1～bank4中的任一bank进行刷新时，控制器102可以将对应的刷新电路的单次刷新行数配置为4。一般来说，控制器102应控制刷新指示信息的发送时间，使得针对每一个bank，控制器102都可以在一个刷新周期内完成对该bank的刷新。
而对bank5～bankN中的任一bank进行刷新时，控制器102可以将对应的刷新电路的单次刷新行数配置为1，也就是说，至少一个目标行的数量为1。在此情况下，bank1至N将具有相同的刷新周期，可以便于控制器102管理。
场景五
假设N个bank皆包括16384行存储单元，N的取值为8。以前述refresh指令为例，假设其能够一次刷新8个bank中的两行，也就是总共16行，因此目前的refresh指令完成一次刷新用时较大。也就是说，目前的refresh指令具有较大的开销，refresh指令的刷新循环时间(refresh cycle time，tRFC)取值较大。
一般来说，目前的refresh指令的tRFC取值为280ns。也就是说，控制器102在发送了一个refresh指令之后，需要等待至少280ns，才可以继续访问存储器101。假设刷新周期为64ms，控制器102需要在64ms内发送8192个refresh指令，即平均每7.8us发送一个refresh指令。则，可以计算目前通过refresh指令刷新存储器101的方案中，开销占比至少为280ns/7.8us＝3.59％。
而采用本申请实施例所提供的技术方案，在通过刷新指示信息指定目标bank，且将目标刷新电路的单次刷新行数配置为8的情况下，控制器102需要在64ms内发送16384个刷新指示信息，即平均每3.9us发送一个刷新指示信息。
在本申请实施例中，控制器102在发送刷新指示信息之后，所需要等待的时间可以仅包括控制电路1011的读写操作从一个bank(目标bank)切换至另一个bank(待读取bank)所需的时间，也就是说，控制器102无需等待存储器101完成刷新操作，在控制电路1011的读写操作切换至待读取bank之后，控制器102便可以继续访问存储器101。因此本申请实施例中tRFC远远小于目前的refresh指令。一般来说，在此情况下tRFC的取值为8ns。进而，可以计算本申请实施例中开销占比为8ns/3.9us＝0.21％。
由此可见，采用本申请实施例还有利于降低存储器101的开销占比。可以理解，tRFC内对存储器101的数据读写将会受到限制。因此，开销占比越低，则刷新过程对数据读写过程的影响便越小。因此，本申请实施例有利于进一步提高存储器101的读写性能。
场景六
假设N个bank皆包括16384行存储单元，N的取值为8。其中，bank1～bank4存储有8192行有效数据，bank5～bank8存储有4096行有效数据。则，实际需要进行刷新的行总量为8192×4+4096×4。
若在64ms的刷新周期内，保持平均每3.9us发送一个刷新指示信息，则可以调整对每个bank的单次刷新行数，也就是至少一个目标行的数量。比如刷新电路1至4的单次刷新 行数配置为4，刷新电路5至8的单次刷新行数配置为2，那么刷新操作性能和场景五的性能相当，但因为场景六中刷新的总行数8192×4+4096×4比场景五中刷新的总行数16384×8减少了62.5％。因此，场景六从能耗上分析，比对所有行进行刷新操作节省能耗。
需要指出的是，以上场景仅为示例，且不同场景可以同时存在。例如，当场景一和场景二同时存在时，处理电路1021可以先通过场景二所提供的方法确定目标bank，再通过场景一通过的方法确定至少一个目标行。本申请实施例对此不再一一列举。
应理解，由于电容中的电荷会随着时间逐渐流失，因此对于存储器101中的任意行来说，相邻的两次刷新之间的时间间隔，应不小于存储器101的刷新周期，以防止数据丢失。其中，刷新周期可以是根据电容的电学性质得到的，本申请实施例对此并不多作限制。
本申请实施例中，处理电路1021还可以根据当前时间点和刷新周期，确定待刷新的目标行，其中，最后一次刷新每个目标行的时间点与当前时间点之间的时间间隔，皆不大于刷新周期。也就是说，对任一行进行刷新的当前时间点，与最后一次刷新该行的时间点之间的时间间隔，不应超过刷新周期。从一个bank的角度，也可以理解为在刷新周期内需要对bank中所有行完成至少一次刷新。
由于电容的性能容易受环境因素的影响，本申请实施例中，处理电路1021还可以获取存储器101的环境参数，并根据环境参数调节刷新周期。例如，控制器102还可以连接有温度传感器，该温度传感器可以设置于存储器101附近。使得处理电路1021可以获取存储器101的环境温度，进而可以根据环境温度调节刷新周期。
示例性的，由于电容的漏电情况会随着环境温度的升高而越发严重，因此刷新周期可以随着环境温度的升高而逐渐缩短。在一种可能实现方式中，可以阶梯式调节刷新周期。例如，当环境温度低于85℃时，刷新周期可以为64ms。当环境温度为85℃～95℃之间时，刷新周期可以从64ms修改为32ms。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (41)

  1. 一种存储器，其特征在于，包括控制电路、刷新电路和存储区域，其中：
    所述控制电路，用于：
    接收刷新指示信息，所述刷新指示信息用于指示所述存储区域中待刷新的至少一个目标行；
    根据所述刷新指示信息，控制所述刷新电路刷新所述至少一个目标行。
  2. 根据权利要求1所述的存储器，其特征在于，所述存储区域包括至少一个库bank，所述刷新指示信息指示的至少一个目标行在每个bank中均存在对应的行。
  3. 根据权利要求1所述的存储器，其特征在于，包括至少一个所述刷新电路，所述存储区域包括至少一个库bank，所述至少一个刷新电路分别用来执行对所述至少一个bank的刷新操作，所述刷新指示信息还用于指示目标bank；
    所述控制电路，具体用于：
    根据所述刷新指示信息获取目标行信息，并向所述目标bank对应的刷新电路发送所述目标行信息，所述目标行信息用于指示所述至少一个目标行；
    所述刷新电路，用于：
    根据所述目标行信息，刷新所述目标bank中所述至少一个目标行。
  4. 根据权利要求3所述的存储器，其特征在于，所述控制电路，还用于：
    接收控制器发送的第一查询信息，所述第一查询信息用于指示所述目标bank；
    根据所述第一查询信息，获取所述目标bank的最大可刷新行数，并向所述控制器返回所述目标bank的最大可刷新行数。
  5. 根据权利要求3或4所述的存储器，其特征在于，所述控制电路还用于：
    接收第一配置信息，所述第一配置信息用于指示所述至少一个目标行的数量和所述目标bank；
    根据所述至少一个目标行的数量，更新所述目标bank对应的刷新电路单次刷新行数。
  6. 根据权利要求5所述的存储器，其特征在于，所述目标行信息包括所述至少一个目标行中指示行的行标识；
    所述目标bank对应的刷新电路，具体用于：
    根据所述指示行的行标识，和所述单次刷新行数计算得到所述至少一个目标行的行标识；
    根据所述至少一个目标行的行标识，刷新所述目标bank中，所述至少一个目标行。
  7. 根据权利要求2所述的存储器，其特征在于，所述控制电路，还用于：
    在接收到控制器发送的第二查询信息后，向所述控制器返回所述至少一个bank的最大公共可刷新行数，所述最大公共可刷新行数是根据所述至少一个bank中，最大可刷新行数的最小值得到的。
  8. 根据权利要求2或7所述的存储器，其特征在于，包括至少一个所述刷新电路，所述存储区域包括至少一个库bank，所述至少一个刷新电路分别用来执行对所述至少一个bank的刷新操作；
    所述控制电路还用于：
    接收第二配置信息，所述第二配置信息用于指示所述至少一个目标行的数量；
    根据至少一个目标行的数量，分别更新所述至少一个刷新电路的单次刷新行数。
  9. 根据权利要求8所述的存储器，其特征在于，所述控制电路，具体用于：根据所述刷新指示信息，获取目标行信息，并分别向所述至少一个刷新电路发送所述目标行信息，所述目标行信息包括所述至少一个目标行中指示行的行标识；
    所述刷新电路，具体用于：
    根据所述指示行的行标识，和所述单次刷新行数计算得到所述至少一个目标行的行标识；
    根据所述至少一个目标行的行标识，刷新与所述刷新电路对应的bank中，所述至少一个目标行。
  10. 一种控制器，其特征在于，包括处理电路和接口电路，其中：
    所述处理电路，用于确定存储器的存储区域中，待刷新的至少一个目标行；
    所述接口电路，用于向所述存储器发送刷新指示信息，所述刷新指示信息指示所述至少一个目标行。
  11. 根据权利要求10所述的控制器，其特征在于，所述存储区域包括至少一个库bank，所述刷新指示信息指示的至少一个目标行在每个bank中均存在对应的行。
  12. 根据权利要求10所述的控制器，其特征在于，所述存储器的存储区域包括至少一个bank；
    所述刷新指示信息还用于指示所述至少一个bank中的目标bank。
  13. 根据权利要求12所述的控制器，其特征在于，所述接口电路，还用于：
    向所述存储器发送第一查询信息，所述第一查询信息用于指示所述存储器返回所述目标bank的最大可刷新行数；
    所述处理电路，具体用于：
    根据所述目标bank的最大可刷新行数，确定所述至少一个目标行，其中，所述至少一个目标行的数量不大于所述目标bank的最大可刷新行数。
  14. 根据权利要求13所述的控制器，其特征在于，所述接口电路，还用于：
    向所述存储器发送第一配置信息，所述第一配置信息用于指示所述存储器根据所述至少一个目标行的数量更新对所述目标bank的单次刷新行数。
  15. 根据权利要求12至14中任一项所述的控制器，其特征在于，所述处理电路，具体用于：
    从所述目标bank内，存储有有效数据的行中确定所述至少一个目标行。
  16. 根据权利要求12至15中任一项所述的控制器，其特征在于，所述存储器的存储区域包括多个bank，所述处理电路，还用于：
    确定待读取的数据所在的至少一个待读取bank；
    从所述多个bank中，除所述至少一个待读取bank之外的bank中，确定所述目标bank。
  17. 根据权利要求11所述的控制器，其特征在于，所述存储器的存储区域包括至少一个bank；
    所述接口电路，还用于：
    向所述存储器发送第二查询信息，所述第二查询信息用于指示所述存储器返回所述至少一个bank的最大公共可刷新行数；
    所述处理电路，具体用于：
    根据所述至少一个bank的最大公共可刷新行数，确定所述至少一个目标行，其中，所述至少一个目标行的数量不大于所述最大公共可刷新行数。
  18. 根据权利要求17所述的控制器，其特征在于，所述接口电路还用于：
    向所述存储器发送第二配置信息，所述第二配置信息用于指示所述存储器根据所述至少一个目标行的数量，分别更新对所述至少一个bank的单次刷新行数。
  19. 根据权利要求10至18所述的控制器，其特征在于，所述刷新指示信息包括所述至少一个目标行中指示行的行标识。
  20. 根据权利要求10至19中任一项所述的控制器，其特征在于，所述处理电路，具体用于：
    根据当前时间点和刷新周期，确定所述至少一个目标行，其中，最后一次刷新每个目标行的时间点与所述当前时间点之间的时间间隔，皆不大于所述刷新周期；
    所述处理电路，还用于：
    获取所述存储器的环境参数，根据所述环境参数调节所述刷新周期。
  21. 一种刷新方法，其特征在于，应用于存储器，所述方法包括：
    接收刷新指示信息，所述刷新指示信息用于指示所述存储器的存储区域中，待刷新的至少一个目标行；
    根据所述刷新指示信息，刷新所述至少一个目标行。
  22. 根据权利要求21所述的方法，其特征在于，所述存储区域包括至少一个库bank；
    刷新所述至少一个目标行，包括：
    分别刷新所述至少一个bank中，与所述至少一个目标行对应的行。
  23. 根据权利要求21所述的方法，其特征在于，所述存储区域包括至少一个库bank，所述刷新指示信息还用于指示所述至少一个bank中的目标bank；
    根据所述刷新指示信息，刷新所述至少一个目标行，包括：
    根据所述刷新指示信息，刷新所述目标bank中所述至少一个目标行。
  24. 根据权利要求23所述的方法，其特征在于，接收刷新指示信息之前，还包括：
    接收控制器发送的第一查询信息，所述第一查询信息用于指示所述目标bank；
    根据所述第一查询信息，获取所述目标bank的最大可刷新行数，并向所述控制器返回所述目标bank的最大可刷新行数。
  25. 根据权利要求23或24所述的方法，其特征在于，接收刷新指示信息之前，还包括：
    接收第一配置信息，所述第一配置信息用于指示所述至少一个目标行的数量和所述目标bank；
    根据所述至少一个目标行的数量，更新对所述目标bank的单次刷新行数。
  26. 根据权利要求25所述的方法，其特征在于，根据所述刷新指示信息，刷新所述目标bank中所述至少一个目标行，包括：
    根据所述刷新指示信息，获取所述至少一个目标行中指示行的行标识；
    根据所述指示行的行标识，和所述单次刷新行数计算得到所述至少一个目标行的行标识；
    根据所述至少一个目标行的行标识，刷新所述目标bank中，所述至少一个目标行。
  27. 根据权利要求22所述的方法，其特征在于，接收刷新指示信息之前，还包括：
    在接收到控制器发送的第二查询信息后，向所述控制器返回所述至少一个bank的最大公共可刷新行数，所述最大公共可刷新行数是根据所述至少一个bank中，最大可刷新行数的最小值得到的。
  28. 根据权利要求22或27所述的方法，其特征在于，接收刷新指示信息之前，还包括：
    接收第二配置信息，所述第二配置信息用于指示所述至少一个目标行的数量；
    根据所述至少一个目标行的数量，分别更新对所述至少一个bank的单次刷新行数。
  29. 根据权利要求28所述的方法，其特征在于，所述刷新指示信息包括所述至少一个目标行中指示行的行标识；
    分别刷新所述至少一个bank中，与所述至少一个目标行对应的行，包括：
    根据所述指示行的行标识，和分别对所述至少一个bank的单次刷新行数，计算得到所述至少一个目标行的行标识；
    根据所述至少一个目标行的行标识，分别刷新所述至少一个bank中，与所述至少一个目标行对应的行。
  30. 一种刷新方法，其特征在于，应用于控制器，所述方法包括：
    确定存储器的存储区域中，待刷新的至少一个目标行；
    向所述存储器发送刷新指示信息，所述刷新指示信息用于指示所述至少一个目标行。
  31. 根据权利要求30所述的方法，其特征在于，所述存储区域包括至少一个库bank，所述刷新指示信息指示的至少一个目标行在每个bank中均存在对应的行。
  32. 根据权利要求30所述的方法，其特征在于，所述存储器的存储区域包括至少一个bank；
    所述刷新指示信息还用于指示所述至少一个bank中的目标bank。
  33. 根据权利要求32所述的方法，其特征在于，确定存储器的存储区域中，待刷新的至少一个目标行之前，还包括：
    向所述存储器发送第一查询信息，所述第一查询信息用于指示所述存储器返回所述目标bank的最大可刷新行数；
    确定存储器的存储区域中，待刷新的至少一个目标行，包括：
    根据所述目标bank的最大可刷新行数，确定所述至少一个目标行，其中，所述至少一个目标行的数量不大于所述目标bank的最大可刷新行数。
  34. 根据权利要求33所述的方法，其特征在于，向所述存储器发送刷新指示信息之前，还包括：
    向所述存储器发送第一配置信息，所述第一配置信息用于指示所述存储器根据所述至少一个目标行的数量更新对所述目标bank的单次刷新行数。
  35. 根据权利要求32至34中任一项所述的方法，其特征在于，确定所述存储器的存储区域中，待刷新的至少一个目标行，包括：
    从所述目标bank内，存储有有效数据的行中确定所述至少一个目标行。
  36. 根据权利要求32至35中任一项所述的方法，其特征在于，所述存储器的存储区域包括多个bank，确定所述存储器的存储区域中，待刷新的至少一个目标行之前，还包括：
    确定待读取的数据所在的至少一个待读取bank；
    从所述多个bank中，除所述至少一个待读取bank之外的bank中，确定所述目标bank。
  37. 根据权利要求31所述的方法，其特征在于，所述存储器的存储区域包括至少一个bank；
    确定存储器的存储区域中，待刷新的至少一个目标行之前，还包括：
    向所述存储器发送第二查询信息，所述第二查询信息用于指示所述存储器返回所述至少一个bank的最大公共可刷新行数；
    确定存储器的存储区域中，待刷新的至少一个目标行，包括：
    根据所述至少一个bank的最大公共可刷新行数，确定所述至少一个目标行，其中，所述至少一个目标行的数量不大于所述最大公共可刷新行数。
  38. 根据权利要求37所述的方法，其特征在于，向所述存储器发送刷新指示信息之前，还包括：
    向所述存储器发送第二配置信息，所述第二配置信息用于指示所述存储器根据所述至少一个目标行的数量更新对所述至少一个bank的单次刷新行数。
  39. 根据权利要求30至38所述的方法，其特征在于，所述刷新指示信息包括所述至少一个目标行中指示行的行标识。
  40. 根据权利要求30至39中任一项所述的方法，其特征在于，确定存储器的存储区域中，待刷新的至少一个目标行，包括：
    根据当前时间点和刷新周期，确定所述至少一个目标行，其中，最后一次刷新每个目标行的时间点与所述当前时间点之间的时间间隔，皆不大于所述刷新周期，所述刷新周期由所述控制器根据所述存储器的环境参数进行调节。
  41. 一种存储系统，其特征在于，包括控制器和存储器，其中，所述控制器，用于确定所述存储器的存储区域中，待刷新的至少一个目标行，向所述存储器发送刷新指示信息，所述刷新指示信息用于指示所述至少一个目标行；
    所述存储器，用于根据所述刷新指示信息，刷新所述至少一个目标行。
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