WO2016173027A1 - 薄膜晶体管阵列基板及其制作方法 - Google Patents

薄膜晶体管阵列基板及其制作方法 Download PDF

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WO2016173027A1
WO2016173027A1 PCT/CN2015/079668 CN2015079668W WO2016173027A1 WO 2016173027 A1 WO2016173027 A1 WO 2016173027A1 CN 2015079668 W CN2015079668 W CN 2015079668W WO 2016173027 A1 WO2016173027 A1 WO 2016173027A1
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layer
gate
gate insulating
plate
insulating layer
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French (fr)
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吕晓文
苏智昱
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
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    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
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    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
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    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
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    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials

Definitions

  • the present invention relates to the field of flat panel displays, and in particular to a thin film transistor array substrate and a method of fabricating the same.
  • the active matrix flat panel display has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the flat panel display devices on the existing market include a liquid crystal display (LCD) and an organic light-emitting diode (OLED).
  • LCD liquid crystal display
  • OLED organic light-emitting diode
  • the LCD includes a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates, and control the liquid crystal molecules to change direction by energizing or not the glass substrate, and refract the light of the backlight module to produce a picture.
  • OLED has many characteristics such as self-illumination, high brightness, wide viewing angle, high contrast, flexibility, low energy consumption, etc., and has been widely concerned as a new generation of display mode, has gradually replaced the traditional liquid crystal display, is widely used in mobile phones. Screen, computer monitor, full color TV, etc.
  • OLED display technology is different from traditional liquid crystal display technology. It does not require a backlight. It uses a very thin coating of organic materials and a glass substrate. When there is current, these organic materials will emit light.
  • Thin Film Transistor Array substrates are widely used in LCDs and OLEDs, and generally include a glass substrate and a thin film transistor and a storage capacitor formed on the glass substrate.
  • the storage capacitor plays a important role in maintaining the potential of the coupling capacitor in the thin film transistor array substrate. In general, we hope that the capacitor is better.
  • the storage capacitor is generally made of a metal-interposed insulating layer, the metal electrode is opaque, and the larger the storage capacitance, the lower the aperture ratio.
  • Reducing the thickness of the insulating layer can increase the size of the storage capacitor, and on the basis of this, the relative area of the metal plate can be appropriately reduced, which is a method for increasing the storage capacitance and increasing the aperture ratio.
  • FIG. 1 is a cross-sectional structural diagram of a conventional thin film transistor array substrate, including a substrate 100, a thin film transistor and a storage capacitor provided on the substrate 100, and a gate insulating layer 300 and an etch barrier 500 interposed between the first plate 310 and the second plate 320 of the storage capacitor because of the gate
  • Both the insulating layer 300 and the etch stop layer 500 have a certain thickness, so that the insulating layer is relatively thick, and a large relative area is required to obtain a set capacitance value, resulting in a decrease in device aperture ratio.
  • the present invention provides a thin film transistor array substrate including a substrate, and a thin film transistor and a storage capacitor formed on the substrate;
  • the storage capacitor is disposed on the first plate and the second plate above the first plate, and is disposed between the first plate and the second plate.
  • the thickness of the portion of the gate insulating layer corresponding to the first plate is smaller than the thickness of other portions of the gate insulating layer.
  • the thin film transistor array substrate includes a substrate, a first gate and a second gate disposed on the substrate, and a first plate disposed on a side of the second gate away from the first gate.
  • a gate insulating layer on the first gate, the second gate, the first plate, and the substrate respectively disposed on the gate insulating layer above the first gate and the second gate a first oxide semiconductor layer and a second oxide semiconductor layer, an etch barrier layer provided on the first oxide semiconductor layer, the second oxide semiconductor layer, and the gate insulating layer, respectively located at the first a first source, a first drain, a second source, and a second drain disposed on the etch barrier layer above the gate and the second gate, and disposed on the etch barrier layer above the first plate a second plate, a passivation layer covering the etch stop layer disposed on the first source, the first drain, the second source, the second drain, and the second plate a planarization layer on the passivation layer, a pixel electrode layer disposed on the planarization layer, and
  • the gate insulating layer is provided with a first via hole corresponding to a side of the second gate adjacent to the first gate, and the passivation layer and the flat layer are corresponding to the second source.
  • a hole, a third via hole is disposed on the pixel defining layer corresponding to the pixel electrode layer; the first source and the first drain are in contact with the first oxide semiconductor layer, and the second source Pole, and second drain and Contacting the second oxide semiconductor layer, the first source is in contact with the second gate via the first via, and the pixel electrode layer is via the second via and the second The source contacts, and the third via exposes a portion of the pixel electrode layer;
  • the first gate, the second gate, the gate insulating layer, the first oxide semiconductor layer, the second oxide semiconductor layer, the etch barrier layer, the first source, the first drain, the second source, And the second drain constitutes a thin film transistor
  • the first electrode plate, the second electrode plate, and the gate insulating layer and the etch barrier layer between the first electrode plate and the second electrode plate constitute a storage capacitor.
  • the material of the gate insulating layer is one of aluminum oxide, silicon nitride, and silicon oxide, or a combination thereof.
  • the invention also provides a method for fabricating a thin film transistor array substrate, comprising the following steps:
  • Step 1 Providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer to obtain a first gate, a second gate, and the second gate a first plate away from a side of the first gate;
  • Step 2 depositing a gate insulating layer on the first metal layer
  • Step 3 applying a photoresist layer on the gate insulating layer, exposing and developing the photoresist layer by using a halftone mask, corresponding to the first gate and the second gate, and a second exposed gate is adjacent to a side of the first gate to obtain a full exposed area, and a half exposed area is obtained corresponding to the upper side of the first plate;
  • Step 4 using the photoresist layer as a shielding layer, performing a first etching on the gate insulating layer under the fully exposed region to obtain a first via hole, and removing the photoresist layer at the half exposed region ;
  • Step 5 using the photoresist layer as a shielding layer, performing a second etching on the gate insulating layer above the first plate, so that the gate insulating layer corresponds to a portion on the first plate
  • the thickness is less than the thickness of other portions of the gate insulating layer
  • Step 6 stripping the photoresist layer, sequentially forming a first oxide semiconductor layer, a second oxide semiconductor layer, an etch barrier layer, a first source, a first drain, and a second on the gate insulating layer a source, a second drain, a second plate, a passivation layer, a flat layer, a pixel electrode layer, a pixel defining layer, and a photoresist spacer.
  • the gate insulating layer is deposited by chemical vapor deposition.
  • the first etching uses a dry etching process, and the photoresist layer at the half exposed region is removed by an oxygen ashing process.
  • the second etching uses a dry etching process.
  • the thickness of the portion corresponding to the first plate on the gate insulating layer is controlled according to the rate of the second etching.
  • the material of the gate insulating layer is one of aluminum oxide, silicon nitride, and silicon oxide, or a combination thereof.
  • the first source and the first drain are in contact with both side regions of the first oxide semiconductor layer, and the second source, the second drain, and the second oxide semiconductor layer
  • the two sides are in contact with each other, the first source is in contact with the second gate via the first via;
  • the passivation layer and the flat layer are formed with a second pass over the second source a third via hole formed on the pixel defining layer corresponding to the pixel electrode layer;
  • the pixel electrode layer is in contact with the second source via the second via hole, the third via hole A portion of the pixel electrode layer is exposed.
  • the invention also provides a method for fabricating a thin film transistor array substrate, comprising the following steps:
  • Step 1 Providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer to obtain a first gate, a second gate, and the second gate a first plate away from a side of the first gate;
  • Step 2 depositing a gate insulating layer on the first metal layer
  • Step 3 applying a photoresist layer on the gate insulating layer, exposing and developing the photoresist layer by using a halftone mask, corresponding to the first gate and the second gate, and a second exposed gate is adjacent to a side of the first gate to obtain a full exposed area, and a half exposed area is obtained corresponding to the upper side of the first plate;
  • Step 4 using the photoresist layer as a shielding layer, performing a first etching on the gate insulating layer under the fully exposed region to obtain a first via hole, and removing the photoresist layer at the half exposed region ;
  • Step 5 using the photoresist layer as a shielding layer, performing a second etching on the gate insulating layer above the first plate, so that the gate insulating layer corresponds to a portion on the first plate
  • the thickness is less than the thickness of other portions of the gate insulating layer
  • Step 6 stripping the photoresist layer, sequentially forming a first oxide semiconductor layer, a second oxide semiconductor layer, an etch barrier layer, a first source, a first drain, and a second on the gate insulating layer a source, a second drain, a second plate, a passivation layer, a flat layer, a pixel electrode layer, a pixel defining layer, and a photoresist spacer;
  • step 2 depositing the gate insulating layer by chemical vapor deposition
  • the first etching adopts a dry etching process, and the photoresist layer at the half exposure region is removed by an oxygen ashing process;
  • the second etching uses a dry etching process.
  • the thickness of the gate insulating layer between the two electrode plates of the storage capacitor is smaller than the thickness of the gate insulating layer of other portions, and the thickness of the insulating layer between the storage capacitors is smaller.
  • the capacitor has a relatively small relative area and a high aperture ratio.
  • the method for fabricating the thin film transistor array substrate of the present invention utilizes a halftone mask process through two The secondary etching partially etches off the gate insulating layer above the first plate of the storage capacitor to reduce the thickness thereof, thereby reducing the thickness of the insulating layer between the storage capacitors, and can reduce the size of the same capacitor.
  • the relative area of the required capacitive electrode plates increases the aperture ratio.
  • FIG. 1 is a schematic cross-sectional structural view of a conventional thin film transistor array substrate
  • FIG. 2 is a schematic cross-sectional structural view of a thin film transistor array substrate of the present invention
  • FIG. 3 is a flow chart of a method for fabricating a thin film transistor array substrate of the present invention.
  • step 1 is a schematic diagram of step 1 of a method for fabricating a thin film transistor array substrate of the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating a thin film transistor array substrate according to the present invention
  • FIG. 6 is a schematic diagram of step 3 of a method for fabricating a thin film transistor array substrate according to the present invention.
  • step 4 is a schematic diagram of step 4 of a method for fabricating a thin film transistor array substrate according to the present invention.
  • step 5 is a schematic diagram of step 5 of a method for fabricating a thin film transistor array substrate according to the present invention.
  • FIG. 9 is a schematic diagram of step 6 of the method for fabricating a thin film transistor array substrate of the present invention.
  • the present invention provides a thin film transistor array substrate including a substrate 1, and a thin film transistor and a storage capacitor formed on the substrate 1.
  • the storage capacitor is provided by the first plate 31 disposed on the substrate 1 , the second plate 32 above the first plate 31 , and the first plate 31 and the second plate 32 . a gate insulating layer 3 disposed on the first plate 31, and an etch barrier layer 5 disposed on the gate insulating layer 3 between the first plate 31 and the second plate 32 Composition.
  • the thickness of the portion 3' of the gate insulating layer 3 corresponding to the first plate 31 is smaller than the thickness of the other portion 3" of the gate insulating layer 3.
  • the substrate 1 includes a first gate 21, a second gate 22, and a first plate 31 on the side of the second gate 22 away from the first gate 21, and is disposed on the substrate
  • the first gate electrode 21, the second gate electrode 22, the first electrode plate 31, and the gate insulating layer 3 on the substrate 1 are respectively disposed above the first gate electrode 21 and the second gate electrode 22.
  • the passivation layer 71 covering the etch stop layer 5, the flat layer 72 disposed on the passivation layer 71, and the flat layer 72 are disposed on the second drain 64 and the second plate 32.
  • a first via 51 is disposed on the gate insulating layer 3 corresponding to a side of the second gate 22 adjacent to the first gate 21, and the passivation layer 71 and the flat layer 72 correspond to the second source
  • a second via hole 52 is disposed on the pixel defining layer 9
  • a third via hole 53 is disposed above the pixel electrode layer 81; the first source 61 , the first drain 62 and the first
  • the oxide semiconductor layer 41 is in contact with the second source 63 and the second drain 64 in contact with the second oxide semiconductor layer 42 via the first via 51 is in contact with the second gate 22, the pixel electrode layer 81 is in contact with the second source 63 via the second via 52, and the third via 53 exposes a portion of the pixel electrode layer 81.
  • the first gate 21, the second gate 22, the gate insulating layer 3, the first oxide semiconductor layer 41, the second oxide semiconductor layer 42, the etch barrier layer 5, the first source 61, and the first A drain electrode 62, a second source electrode 63, and a second drain electrode 64 constitute a thin film transistor.
  • the first plate 31, the second plate 32, and the gate insulating layer 3 and the etch stop layer 5 between the first plate 31 and the second plate 32 constitute a storage capacitor due to the gate
  • the thickness of the portion 3' of the pole insulating layer 3 corresponding to the first electrode plate 31 is smaller than the thickness of the other portion 3" of the gate insulating layer 3, the thickness of the insulating layer between the storage capacitors is thin, and the relative area of the capacitor is small. Has a higher aperture ratio.
  • the material of the gate insulating layer 3 may be one of or a combination of aluminum oxide (Al 2 O 3 ), silicon nitride (SiNx), and silicon oxide (SiOx).
  • the thin film transistor array substrate of the present invention is also applicable to the Back Channel Etched (BCE) and the channel in addition to the above-described Etch Stopper (ES) structure.
  • BCE Back Channel Etched
  • ES Etch Stopper
  • the thickness of the gate insulating layer between the two electrode plates of the storage capacitor is smaller than the thickness of the gate insulating layer of other portions, the thickness of the insulating layer between the storage capacitors is thin, and the relative area of the capacitor is small, which is high.
  • the aperture ratio is smaller than the thickness of the gate insulating layer of other portions, the thickness of the insulating layer between the storage capacitors is thin, and the relative area of the capacitor is small, which is high.
  • the present invention provides a method for fabricating a thin film transistor array substrate, including the following steps:
  • Step 1 as shown in FIG. 4, a substrate 1 is provided, a first metal layer is deposited on the substrate 1, and the first metal layer is patterned to obtain a first gate 21 and a second gate. 22.
  • the first electrode plate 31 located on a side of the second gate 22 away from the first gate 21 .
  • Step 2 As shown in FIG. 5, a gate insulating layer 3 is deposited on the first metal layer.
  • the gate insulating layer 3 is deposited by chemical vapor deposition (CVD); the material of the gate insulating layer 3 may be one of or a combination of aluminum oxide, silicon nitride, and silicon oxide.
  • CVD chemical vapor deposition
  • Step 3 coating the photoresist layer 30 on the gate insulating layer 3, and exposing and developing the photoresist layer 30 by using a halftone mask (Half Tone), corresponding to the A full exposure region 301 is obtained between the first gate 21 and the second gate 22 and the second gate 22 is adjacent to the first gate 21 side, and a half exposure region is obtained corresponding to the upper portion of the first plate 31. 302.
  • a halftone mask Half Tone
  • Step 4 as shown in FIG. 7, the photoresist layer 30 is used as a shielding layer, and the gate insulating layer 3 under the fully exposed region 301 is first etched to obtain a first via 51, and is removed.
  • the first etching uses a dry etching process, and the photoresist layer 30 at the half exposed region 302 is removed by an O 2 Ashing process.
  • Step 5 as shown in FIG. 8, the photoresist layer 30 is used as a shielding layer, and the gate insulating layer 3 above the first electrode plate 31 is etched a second time to make the gate insulating layer 3
  • the thickness of the portion 3' corresponding to the first plate 31 is smaller than the thickness of the other portion 3" of the gate insulating layer 3.
  • the second etching adopts a dry etching process, and the portion of the gate insulating layer 3 corresponding to the first plate 31 may be controlled according to the rate of the second etching. thickness of.
  • Step 6 as shown in FIG. 9, the photoresist layer 30 is peeled off, and the first oxide semiconductor layer 41, the second oxide semiconductor layer 42, and the etching barrier layer 5 are sequentially formed on the gate insulating layer 3.
  • the step 6 can be implemented by using a prior art; the first source 61 and the first drain 62 are in contact with two side regions of the first oxide semiconductor layer 41, and the second source The pole 63 and the second drain 64 are in contact with both side regions of the second oxide semiconductor layer 42
  • the first source 61 is in contact with the second gate 22 via the first via 51; the passivation layer 71 and the flat layer 72 are formed with a second pass above the second source 63.
  • a second via hole 53 is formed on the pixel defining layer 9 corresponding to the pixel electrode layer 81; the pixel electrode layer 81 is in contact with the second source 63 via the second via hole 52.
  • the third via hole 53 exposes a portion of the pixel electrode layer 81.
  • the first gate 21, the second gate 22, the gate insulating layer 3, the first oxide semiconductor layer 41, the second oxide semiconductor layer 42, the etch barrier layer 5, the first source 61, and the first A drain electrode 62, a second source electrode 63, and a second drain electrode 64 constitute a thin film transistor.
  • the first plate 31, the second plate 32, and the gate insulating layer 3 and the etch barrier layer 5 between the first plate 31 and the second plate 32 constitute a storage capacitor, and the gate
  • the thickness of the portion 3' of the insulating layer 3 corresponding to the first plate 31 is smaller than the thickness of the other portion 3" of the gate insulating layer 3.
  • the thickness of the insulating layer between the storage capacitors is thin, and the relative area of the capacitor is small. Higher aperture ratio.
  • a portion of the gate insulating layer above the first plate of the storage capacitor is etched away by two etchings by a halftone mask process to reduce the thickness thereof, thereby reducing the storage.
  • the thickness of the insulating layer between the capacitors can reduce the relative area of the required capacitor electrode plates and increase the aperture ratio under the condition that the same capacitance is required.
  • the present invention provides a thin film transistor array substrate in which the thickness of the gate insulating layer between the two electrode plates of the storage capacitor is smaller than the thickness of the gate insulating layer of other portions, and the thickness of the insulating layer between the storage capacitors is thin.
  • the capacitance has a relatively small relative area and a high aperture ratio.
  • a portion of the gate insulating layer above the first plate of the storage capacitor is etched away by two etchings by using a halftone mask process to reduce the thickness thereof, thereby reducing
  • the thickness of the insulating layer between the storage capacitors can reduce the relative area of the required capacitor electrode plates and increase the aperture ratio under the condition that the same capacitance is required.

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Abstract

一种薄膜晶体管阵列基板及其制作方法，薄膜晶体管阵列基板的存储电容的两电极板（31, 32）之间的栅极绝缘层（3'）的厚度小于其他部分的栅极绝缘层的厚度，存储电容间绝缘层厚度较薄，电容相对面积较小，具有较高的开口率。薄膜晶体管阵列基板的制作方法包括：采用半色调掩膜工艺，通过两次蚀刻，将存储电容处的栅极绝缘层打薄，减小存储电容间绝缘层的厚度，在需要同样电容大小的条件下，可以减小存储电容两电极板的金属相对面积，从而提高开口率。

Description

薄膜晶体管阵列基板及其制作方法 技术领域
本发明涉及平面显示器领域，尤其涉及一种薄膜晶体管阵列基板及其制作方法。
背景技术
主动矩阵平面显示器具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有市场上的平面显示器装置包括液晶显示装置(Liquid Crystal Display，LCD)和有机发光二极管(Organic Light-Emitting Diode，OLED)。
LCD包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，通过玻璃基板通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
OLED具备自发光、高亮度、宽视角、高对比度、可挠曲、低能耗等特性，因此受到广泛的关注，并作为新一代的显示方式，已开始逐渐取代传统液晶显示器，被广泛应用在手机屏幕、电脑显示器、全彩电视等。OLED显示技术与传统的液晶显示技术不同，无需背光灯，采用非常薄的有机材料涂层和玻璃基板，当有电流通过时，这些有机材料就会发光。
薄膜晶体管阵列基板(Thin Film Transistor Array substrate)在LCD和OLED中被广泛应用，一般包括玻璃基板及形成于玻璃基板上的薄膜晶体管及存储电容。
存储电容在薄膜晶体管阵列基板中扮演着保持电位，降低耦合电容分压等重要作用，一般而言，我们希望电容大点比较好。电容大小的计算公式为C＝εS/D其中S代表面积，D代表绝缘层厚度，改变存储电容的大小，一般有以下几种方法，1.选用介电常数较大的绝缘材料。2.增大面积。3.降低绝缘层厚度。
一般来说，增大两金属板的相对面积会增大电容，但是由于存储电容一般以金属夹置绝缘层制成，金属电极是不透光的，存储电容越大，开口率就越低。而降低绝缘层厚度，既能增大存储电容大小，同时在此基础上，可以适当减小金属板相对面积，是较好的增加存储电容，提高开口率的方法。
请参阅图1，为一种现有薄膜晶体管阵列基板的剖面结构示意图，包括 基板100、及设于所述基板100上的薄膜晶体管和存储电容，存储电容的第一极板310与第二极板320中间夹置有栅极绝缘层300和蚀刻阻挡层500，因为栅极绝缘层300和蚀刻阻挡层500都有一定的厚度，就使得绝缘层比较厚，需要较大的相对面积才能得到设定的电容值，造成器件开口率降低。
发明内容
本发明的目的在于提供一种薄膜晶体管阵列基板，具有较大存储电容的同时，具有较高开口率。
本发明的目的在于提供一种薄膜晶体管阵列基板的制作方法，可以增大存储电容的同时，提高开口率。
为实现上述目的，本发明提供一种薄膜晶体管阵列基板，包括基板、及形成于所述基板上的薄膜晶体管和存储电容；
所述存储电容由设于所述基板上的第一极板、位于所述第一极板上方的第二极板、位于所述第一极板与第二极板之间设于所述第一极板上的栅极绝缘层、及位于所述第一极板与第二极板之间设于所述栅极绝缘层上的蚀刻阻挡层构成；
所述栅极绝缘层对应所述第一极板上的部分的厚度小于所述栅极绝缘层的其他部分的厚度。
所述的薄膜晶体管阵列基板，包括基板、设于所述基板上的第一栅极、第二栅极、及位于所述第二栅极远离第一栅极一侧的第一极板、设于所述第一栅极、第二栅极、第一极板、及基板上的栅极绝缘层、分别位于所述第一栅极与第二栅极上方设于所述栅极绝缘层上的第一氧化物半导体层与第二氧化物半导体层、设于所述第一氧化物半导体层、第二氧化物半导体层、及栅极绝缘层上的蚀刻阻挡层、分别位于所述第一栅极、第二栅极上方设于蚀刻阻挡层上的第一源极、第一漏极、第二源极、第二漏极、位于所述第一极板上方设于所述蚀刻阻挡层上的第二极板、设于所述第一源极、第一漏极、第二源极、第二漏极、及第二极板上方覆盖所述蚀刻阻挡层的钝化层、设于所述钝化层上的平坦层、设于所述平坦层上的像素电极层、设于所述平坦层与像素电极层上的像素定义层、及设于所述像素定义层上的光阻间隙物；
所述栅极绝缘层对应所述第二栅极靠近第一栅极一侧的上方设有第一过孔，所述钝化层与平坦层对应所述第二源极上方设有第二过孔，所述像素定义层上对应所述像素电极层上方设有第三过孔；所述第一源极、第一漏极与所述第一氧化物半导体层相接触，所述第二源极、及第二漏极与所 述第二氧化物半导体层相接触，所述第一源极经由所述第一过孔与所述第二栅极相接触，所述像素电极层经由所述第二过孔与所述第二源极相接触，所述第三过孔暴露出部分像素电极层；
所述第一栅极、第二栅极、栅极绝缘层、第一氧化物半导体层、第二氧化物半导体层、蚀刻阻挡层、第一源极、第一漏极、第二源极、及第二漏极构成薄膜晶体管；
所述第一极板、第二极板、及位于所述第一极板与第二极板之间的栅极绝缘层和蚀刻阻挡层构成存储电容。
所述栅极绝缘层的材料为氧化铝、氮化硅、及氧化硅中的一种或其组合。
本发明还提供一种薄膜晶体管阵列基板的制作方法，包括以下步骤：
步骤1、提供一基板，在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，得到第一栅极、第二栅极、及位于所述第二栅极远离第一栅极一侧的第一极板；
步骤2、在所述第一金属层上沉积栅极绝缘层；
步骤3、在所述栅极绝缘层上涂布光阻层，利用半色调掩膜板对所述光阻层进行曝光、显影，对应所述第一栅极与第二栅极之间、及第二栅极靠近第一栅极一侧的上方得到全曝光区域，对应所述第一极板的上方得到半曝光区域；
步骤4、以所述光阻层为遮蔽层，对所述全曝光区域下方的栅极绝缘层进行第一次刻蚀，得到第一过孔，并除去所述半曝光区域处的光阻层；
步骤5、以所述光阻层为遮蔽层，对所述第一极板上方的栅极绝缘层进行第二次刻蚀，使所述栅极绝缘层对应所述第一极板上的部分的厚度小于所述栅极绝缘层其他部分的厚度；
步骤6、剥离所述光阻层，依次在所述栅极绝缘层上形成第一氧化物半导体层、第二氧化物半导体层、蚀刻阻挡层、第一源极、第一漏极、第二源极、第二漏极、第二极板、钝化层、平坦层、像素电极层、像素定义层、及光阻间隙物。
所述步骤2中，通过化学气相沉积法沉积所述栅极绝缘层。
所述步骤4中，所述第一次刻蚀采用干法刻蚀工艺，并通过氧气灰化制程除去所述半曝光区域处的光阻层。
所述步骤5中，所述第二次刻蚀采用干法刻蚀工艺。
所述步骤5中，根据所述第二次刻蚀的速率控制所述栅极绝缘层上对应所述第一极板上的部分的厚度。
所述栅极绝缘层的材料为氧化铝、氮化硅、及氧化硅中的一种或其组合。
所述第一源极、及第一漏极与所述第一氧化物半导体层的两侧区域相接触，所述第二源极、及第二漏极与所述第二氧化物半导体层的两侧区域相接触，所述第一源极经由所述第一过孔与所述第二栅极相接触；所述钝化层与平坦层对应所述第二源极上方形成有第二过孔，所述像素定义层上对应所述像素电极层上方形成有第三过孔；所述像素电极层经由所述第二过孔与所述第二源极相接触，所述第三过孔暴露出部分像素电极层。
本发明还提供一种薄膜晶体管阵列基板的制作方法，包括以下步骤：
步骤1、提供一基板，在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，得到第一栅极、第二栅极、及位于所述第二栅极远离第一栅极一侧的第一极板；
步骤2、在所述第一金属层上沉积栅极绝缘层；
步骤3、在所述栅极绝缘层上涂布光阻层，利用半色调掩膜板对所述光阻层进行曝光、显影，对应所述第一栅极与第二栅极之间、及第二栅极靠近第一栅极一侧的上方得到全曝光区域，对应所述第一极板的上方得到半曝光区域；
步骤4、以所述光阻层为遮蔽层，对所述全曝光区域下方的栅极绝缘层进行第一次刻蚀，得到第一过孔，并除去所述半曝光区域处的光阻层；
步骤5、以所述光阻层为遮蔽层，对所述第一极板上方的栅极绝缘层进行第二次刻蚀，使所述栅极绝缘层对应所述第一极板上的部分的厚度小于所述栅极绝缘层其他部分的厚度；
步骤6、剥离所述光阻层，依次在所述栅极绝缘层上形成第一氧化物半导体层、第二氧化物半导体层、蚀刻阻挡层、第一源极、第一漏极、第二源极、第二漏极、第二极板、钝化层、平坦层、像素电极层、像素定义层、及光阻间隙物；
其中，所述步骤2中，通过化学气相沉积法沉积所述栅极绝缘层；
其中，所述步骤4中，所述第一次刻蚀采用干法刻蚀工艺，并通过氧气灰化制程除去所述半曝光区域处的光阻层；
其中，所述步骤5中，所述第二次刻蚀采用干法刻蚀工艺。
本发明的有益效果：本发明提供的一种薄膜晶体管阵列基板，存储电容的两电极板之间的栅极绝缘层的厚度小于其他部分的栅极绝缘层的厚度，存储电容间绝缘层厚度较薄，电容相对面积较小，具有较高的开口率。本发明的薄膜晶体管阵列基板的制作方法，利用半色调掩膜工艺，通过两 次刻蚀，将位于存储电容的第一极板上方的栅极绝缘层部分蚀刻掉，减小其厚度，从而降低了存储电容间绝缘层厚度，在需要同样电容大小的条件下，可以减小需要的电容电极板的相对面积，提高了开口率。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为一种现有薄膜晶体管阵列基板的剖面结构示意图；
图2为本发明薄膜晶体管阵列基板的剖面结构示意图；
图3为本发明薄膜晶体管阵列基板制作方法的流程图；
图4为本发明薄膜晶体管阵列基板制作方法的步骤1的示意图；
图5为本发明薄膜晶体管阵列基板制作方法的步骤2的示意图；
图6为本发明薄膜晶体管阵列基板制作方法的步骤3的示意图；
图7为本发明薄膜晶体管阵列基板制作方法的步骤4的示意图；
图8为本发明薄膜晶体管阵列基板制作方法的步骤5的示意图；
图9为本发明薄膜晶体管阵列基板制作方法的步骤6的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明提供一种薄膜晶体管阵列基板，包括基板1、及形成于所述基板1上的薄膜晶体管和存储电容。
所述存储电容由设于所述基板1上的第一极板31、位于所述第一极板31上方的第二极板32、位于所述第一极板31与第二极板32之间设于所述第一极板31上的栅极绝缘层3、及位于所述第一极板31与第二极板32之间设于所述栅极绝缘层3上的蚀刻阻挡层5构成。
所述栅极绝缘层3对应所述第一极板31上的部分3’的厚度小于所述栅极绝缘层3的其他部分3”的厚度。
具体地，如图2所示，为本发明的薄膜晶体管阵列基板的一具体实施例，即刻蚀阻挡型(Etch Stopper，ES)结构的薄膜晶体管阵列基板的剖面 结构示意图。包括基板1、设于所述基板1上的第一栅极21、第二栅极22、及位于所述第二栅极22远离第一栅极21一侧的第一极板31、设于所述第一栅极21、第二栅极22、第一极板31、及基板1上的栅极绝缘层3、分别位于所述第一栅极21与第二栅极22上方设于所述栅极绝缘层3上的第一氧化物半导体层41与第二氧化物半导体层42、设于所述第一氧化物半导体层41、第二氧化物半导体层42、及栅极绝缘层3上的蚀刻阻挡层5、分别位于所述第一栅极21、第二栅极22上方设于蚀刻阻挡层5上的第一源极61、第一漏极62、第二源极63、第二漏极64、位于所述第一极板31上方设于所述蚀刻阻挡层5上的第二极板32、设于所述第一源极61、第一漏极62、第二源极63、第二漏极64、及第二极板32上方覆盖所述蚀刻阻挡层5的钝化层71、设于所述钝化层71上的平坦层72、设于所述平坦层72上的像素电极层81、设于所述平坦层72与像素电极层81上的像素定义层9、及设于所述像素定义层9上的光阻间隙物91。
所述栅极绝缘层3对应所述第二栅极22靠近第一栅极21一侧的上方设有第一过孔51，所述钝化层71与平坦层72对应所述第二源极63上方设有第二过孔52，所述像素定义层9上对应所述像素电极层81上方设有第三过孔53；所述第一源极61、第一漏极62与所述第一氧化物半导体层41相接触，所述第二源极63、及第二漏极64与所述第二氧化物半导体层42相接触，所述第一源极61经由所述第一过孔51与所述第二栅极22相接触，所述像素电极层81经由所述第二过孔52与所述第二源极63相接触，所述第三过孔53暴露出部分像素电极层81。
其中，所述第一栅极21、第二栅极22、栅极绝缘层3、第一氧化物半导体层41、第二氧化物半导体层42、蚀刻阻挡层5、第一源极61、第一漏极62、第二源极63、及第二漏极64构成薄膜晶体管。
所述第一极板31、第二极板32、及位于所述第一极板31与第二极板32之间的栅极绝缘层3和蚀刻阻挡层5构成存储电容，由于所述栅极绝缘层3对应所述第一极板31上的部分3’的厚度小于所述栅极绝缘层3的其他部分3”的厚度，存储电容间绝缘层厚度较薄，电容相对面积较小，具有较高的开口率。
具体地，所述栅极绝缘层3的材料可以是氧化铝(Al2O3)、氮化硅(SiNx)、及氧化硅(SiOx)中的一种或其组合。
值得一提的是，除上述刻蚀阻挡型(Etch Stopper，ES)结构之外，本发明的薄膜晶体管阵列基板也同样适用于背沟道刻蚀型(Back Channel Etched，BCE)、及沟道保护型(Channel Protected，CP) 的结构。
上述薄膜晶体管阵列基板，存储电容的两电极板之间的栅极绝缘层的厚度小于其他部分的栅极绝缘层的厚度，存储电容间绝缘层厚度较薄，电容相对面积较小，具有较高的开口率。
请参阅图3，本发明提供一种薄膜晶体管阵列基板的制作方法，包括以下步骤：
步骤1、如图4所示，提供一基板1，在所述基板1上沉积第一金属层，并对所述第一金属层进行图案化处理，得到第一栅极21、第二栅极22、及位于所述第二栅极22远离第一栅极21一侧的第一极板31。
步骤2、如图5所示，在所述第一金属层上沉积栅极绝缘层3。
具体地，通过化学气相沉积法(CVD)沉积所述栅极绝缘层3；所述栅极绝缘层3的材料可以是氧化铝、氮化硅、及氧化硅中的一种或其组合。
步骤3、如图6所示，在所述栅极绝缘层3上涂布光阻层30，利用半色调掩膜板(Half Tone)对所述光阻层30进行曝光、显影，对应所述第一栅极21与第二栅极22之间、及第二栅极22靠近第一栅极21一侧的上方得到全曝光区域301，对应所述第一极板31的上方得到半曝光区域302。
步骤4、如图7所示，以所述光阻层30为遮蔽层，对所述全曝光区域301下方的栅极绝缘层3进行第一次刻蚀，得到第一过孔51，并除去所述半曝光区域302处的光阻层30。
具体地，所述第一次刻蚀采用干法刻蚀工艺，并通过氧气灰化(O2Ashing)制程除去所述半曝光区域302处的光阻层30。
步骤5、如图8所示，以所述光阻层30为遮蔽层，对所述第一极板31上方的栅极绝缘层3进行第二次刻蚀，使所述栅极绝缘层3对应所述第一极板31上的部分3’的厚度小于所述栅极绝缘层3其他部分3”的厚度。
具体地，所述第二次刻蚀采用干法刻蚀工艺，可以根据所述第二次刻蚀的速率控制所述栅极绝缘层3上对应所述第一极板31上的部分3’的厚度。
步骤6、如图9所示，剥离所述光阻层30，依次在所述栅极绝缘层3上形成第一氧化物半导体层41、第二氧化物半导体层42、蚀刻阻挡层5、第一源极61、第一漏极62、第二源极63、第二漏极64、第二极板32、钝化层71、平坦层72、像素电极层81、像素定义层9、及光阻间隙物91。
具体地，所述步骤6可以采用现有技术实现；所述第一源极61、及第一漏极62与所述第一氧化物半导体层41的两侧区域相接触，所述第二源极63、及第二漏极64与所述第二氧化物半导体层42的两侧区域相接触， 所述第一源极61经由所述第一过孔51与所述第二栅极22相接触；所述钝化层71与平坦层72对应所述第二源极63上方形成有第二过孔52，所述像素定义层9上对应所述像素电极层81上方形成有第三过孔53；所述像素电极层81经由所述第二过孔52与所述第二源极63相接触，所述第三过孔53暴露出部分像素电极层81。
其中，所述第一栅极21、第二栅极22、栅极绝缘层3、第一氧化物半导体层41、第二氧化物半导体层42、蚀刻阻挡层5、第一源极61、第一漏极62、第二源极63、及第二漏极64构成薄膜晶体管。
所述第一极板31、第二极板32、及位于所述第一极板31与第二极板32之间的栅极绝缘层3和蚀刻阻挡层5构成存储电容，所述栅极绝缘层3对应所述第一极板31上的部分3’的厚度小于所述栅极绝缘层3的其他部分3”的厚度，存储电容间绝缘层厚度较薄，电容相对面积较小，具有较高的开口率。
上述薄膜晶体管阵列基板的制作方法，利用半色调掩膜工艺，通过两次刻蚀，将位于存储电容的第一极板上方的栅极绝缘层部分蚀刻掉，减小其厚度，从而降低了存储电容间绝缘层厚度，在需要同样电容大小的条件下，可以减小需要的电容电极板的相对面积，提高了开口率。
综上所述，本发明提供的一种薄膜晶体管阵列基板，存储电容的两电极板之间的栅极绝缘层的厚度小于其他部分的栅极绝缘层的厚度，存储电容间绝缘层厚度较薄，电容相对面积较小，具有较高的开口率。本发明的薄膜晶体管阵列基板的制作方法，利用半色调掩膜工艺，通过两次刻蚀，将位于存储电容的第一极板上方的栅极绝缘层部分蚀刻掉，减小其厚度，从而降低了存储电容间绝缘层厚度，在需要同样电容大小的条件下，可以减小需要的电容电极板的相对面积，提高了开口率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (14)

  1. 一种薄膜晶体管阵列基板，包括基板、及形成于所述基板上的薄膜晶体管和存储电容；
    所述存储电容由设于所述基板上的第一极板、位于所述第一极板上方的第二极板、位于所述第一极板与第二极板之间设于所述第一极板上的栅极绝缘层、及位于所述第一极板与第二极板之间设于所述栅极绝缘层上的蚀刻阻挡层构成；
    所述栅极绝缘层对应所述第一极板上的部分的厚度小于所述栅极绝缘层的其他部分的厚度。
  2. 如权利要求1所述的薄膜晶体管阵列基板，其中，包括基板、设于所述基板上的第一栅极、第二栅极、及位于所述第二栅极远离第一栅极一侧的第一极板、设于所述第一栅极、第二栅极、第一极板、及基板上的栅极绝缘层、分别位于所述第一栅极与第二栅极上方设于所述栅极绝缘层上的第一氧化物半导体层与第二氧化物半导体层、设于所述第一氧化物半导体层、第二氧化物半导体层、及栅极绝缘层上的蚀刻阻挡层、分别位于所述第一栅极、第二栅极上方设于蚀刻阻挡层上的第一源极、第一漏极、第二源极、第二漏极、位于所述第一极板上方设于所述蚀刻阻挡层上的第二极板；
    设于所述第一源极、第一漏极、第二源极、第二漏极、及第二极板上方覆盖所述蚀刻阻挡层的钝化层、设于所述钝化层上的平坦层、设于所述平坦层上的像素电极层、设于所述平坦层与像素电极层上的像素定义层、及设于所述像素定义层上的光阻间隙物；
    所述栅极绝缘层对应所述第二栅极靠近第一栅极一侧的上方设有第一过孔，所述钝化层与平坦层对应所述第二源极上方设有第二过孔，所述像素定义层上对应所述像素电极层上方设有第三过孔；所述第一源极、第一漏极与所述第一氧化物半导体层相接触，所述第二源极、及第二漏极与所述第二氧化物半导体层相接触，所述第一源极经由所述第一过孔与所述第二栅极相接触，所述像素电极层经由所述第二过孔与所述第二源极相接触，所述第三过孔暴露出部分像素电极层；
    所述第一栅极、第二栅极、栅极绝缘层、第一氧化物半导体层、第二氧化物半导体层、蚀刻阻挡层、第一源极、第一漏极、第二源极、及第二漏极构成薄膜晶体管；
    所述第一极板、第二极板、及位于所述第一极板与第二极板之间的栅极绝缘层和蚀刻阻挡层构成存储电容。
  3. 如权利要求1所述的薄膜晶体管阵列基板，其中，所述栅极绝缘层的材料为氧化铝、氮化硅、及氧化硅中的一种或其组合。
  4. 一种薄膜晶体管阵列基板的制作方法，包括以下步骤：
    步骤1、提供一基板，在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，得到第一栅极、第二栅极、及位于所述第二栅极远离第一栅极一侧的第一极板；
    步骤2、在所述第一金属层上沉积栅极绝缘层；
    步骤3、在所述栅极绝缘层上涂布光阻层，利用半色调掩膜板对所述光阻层进行曝光、显影，对应所述第一栅极与第二栅极之间、及第二栅极靠近第一栅极一侧的上方得到全曝光区域，对应所述第一极板的上方得到半曝光区域；
    步骤4、以所述光阻层为遮蔽层，对所述全曝光区域下方的栅极绝缘层进行第一次刻蚀，得到第一过孔，并除去所述半曝光区域处的光阻层；
    步骤5、以所述光阻层为遮蔽层，对所述第一极板上方的栅极绝缘层进行第二次刻蚀，使所述栅极绝缘层对应所述第一极板上的部分的厚度小于所述栅极绝缘层其他部分的厚度；
    步骤6、剥离所述光阻层，依次在所述栅极绝缘层上形成第一氧化物半导体层、第二氧化物半导体层、蚀刻阻挡层、第一源极、第一漏极、第二源极、第二漏极、第二极板、钝化层、平坦层、像素电极层、像素定义层、及光阻间隙物。
  5. 如权利要求4所述的薄膜晶体管阵列基板的制作方法，其中，所述步骤2中，通过化学气相沉积法沉积所述栅极绝缘层。
  6. 如权利要求4所述的薄膜晶体管阵列基板的制作方法，其中，所述步骤4中，所述第一次刻蚀采用干法刻蚀工艺，并通过氧气灰化制程除去所述半曝光区域处的光阻层。
  7. 如权利要求4所述的薄膜晶体管阵列基板的制作方法，其中，所述步骤5中，所述第二次刻蚀采用干法刻蚀工艺。
  8. 如权利要求7所述的薄膜晶体管阵列基板的制作方法，其中，所述步骤5中，根据所述第二次刻蚀的速率控制所述栅极绝缘层上对应所述第一极板上的部分的厚度。
  9. 如权利要求4所述的薄膜晶体管阵列基板的制作方法，其中，所述栅极绝缘层的材料为氧化铝、氮化硅、及氧化硅中的一种或其组合。
  10. 如权利要求4所述的薄膜晶体管阵列基板的制作方法，其中，所述第一源极、及第一漏极与所述第一氧化物半导体层的两侧区域相接触，所述第二源极、及第二漏极与所述第二氧化物半导体层的两侧区域相接触，所述第一源极经由所述第一过孔与所述第二栅极相接触；所述钝化层与平坦层对应所述第二源极上方形成有第二过孔，所述像素定义层上对应所述像素电极层上方形成有第三过孔；所述像素电极层经由所述第二过孔与所述第二源极相接触，所述第三过孔暴露出部分像素电极层。
  11. 一种薄膜晶体管阵列基板的制作方法，包括以下步骤：
    步骤1、提供一基板，在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，得到第一栅极、第二栅极、及位于所述第二栅极远离第一栅极一侧的第一极板；
    步骤2、在所述第一金属层上沉积栅极绝缘层；
    步骤3、在所述栅极绝缘层上涂布光阻层，利用半色调掩膜板对所述光阻层进行曝光、显影，对应所述第一栅极与第二栅极之间、及第二栅极靠近第一栅极一侧的上方得到全曝光区域，对应所述第一极板的上方得到半曝光区域；
    步骤4、以所述光阻层为遮蔽层，对所述全曝光区域下方的栅极绝缘层进行第一次刻蚀，得到第一过孔，并除去所述半曝光区域处的光阻层；
    步骤5、以所述光阻层为遮蔽层，对所述第一极板上方的栅极绝缘层进行第二次刻蚀，使所述栅极绝缘层对应所述第一极板上的部分的厚度小于所述栅极绝缘层其他部分的厚度；
    步骤6、剥离所述光阻层，依次在所述栅极绝缘层上形成第一氧化物半导体层、第二氧化物半导体层、蚀刻阻挡层、第一源极、第一漏极、第二源极、第二漏极、第二极板、钝化层、平坦层、像素电极层、像素定义层、及光阻间隙物；
    其中，所述步骤2中，通过化学气相沉积法沉积所述栅极绝缘层；
    其中，所述步骤4中，所述第一次刻蚀采用干法刻蚀工艺，并通过氧气灰化制程除去所述半曝光区域处的光阻层；
    其中，所述步骤5中，所述第二次刻蚀采用干法刻蚀工艺。
  12. 如权利要求11所述的薄膜晶体管阵列基板的制作方法，其中，所述步骤5中，根据所述第二次刻蚀的速率控制所述栅极绝缘层上对应所述第一极板上的部分的厚度。
  13. 如权利要求11所述的薄膜晶体管阵列基板的制作方法，其中，所述栅极绝缘层的材料为氧化铝、氮化硅、及氧化硅中的一种或其组合。
  14. 如权利要求11所述的薄膜晶体管阵列基板的制作方法，其中，所述第一源极、及第一漏极与所述第一氧化物半导体层的两侧区域相接触，所述第二源极、及第二漏极与所述第二氧化物半导体层的两侧区域相接触，所述第一源极经由所述第一过孔与所述第二栅极相接触；所述钝化层与平坦层对应所述第二源极上方形成有第二过孔，所述像素定义层上对应所述像素电极层上方形成有第三过孔；所述像素电极层经由所述第二过孔与所述第二源极相接触，所述第三过孔暴露出部分像素电极层。
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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105931995B (zh) 2016-04-29 2018-11-23 京东方科技集团股份有限公司 阵列基板及其制作方法
CN106094366B (zh) * 2016-08-23 2019-02-01 深圳市华星光电技术有限公司 Ips型阵列基板的制作方法及ips型阵列基板
CN106229297B (zh) * 2016-09-18 2019-04-02 深圳市华星光电技术有限公司 Amoled像素驱动电路的制作方法
CN108064414A (zh) * 2016-11-23 2018-05-22 深圳市柔宇科技有限公司 阵列基板的制造方法
CN108806572A (zh) * 2017-05-05 2018-11-13 元太科技工业股份有限公司 像素结构
CN107680993B (zh) 2017-10-23 2019-12-24 深圳市华星光电半导体显示技术有限公司 Oled面板及其制作方法
US10475825B2 (en) 2018-03-05 2019-11-12 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. TFT backplane and manufacturing method thereof
CN108538851A (zh) * 2018-03-05 2018-09-14 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管背板及其制作方法
CN113192980B (zh) * 2018-03-21 2023-06-16 福建华佳彩有限公司 一种阵列基板结构、显示装置及阵列基板结构的制备方法
CN108807471B (zh) 2018-05-30 2019-11-26 武汉华星光电半导体显示技术有限公司 一种有源矩阵有机发光二极管显示器
WO2020006716A1 (zh) * 2018-07-04 2020-01-09 深圳市柔宇科技有限公司 阵列基板及其制造方法、显示装置
CN112534566A (zh) * 2018-07-04 2021-03-19 深圳市柔宇科技股份有限公司 阵列基板及其制造方法、显示装置
CN111640703B (zh) * 2019-07-02 2025-08-01 福建省晋华集成电路有限公司 半导体结构及其形成方法
CN110600507B (zh) * 2019-08-21 2024-04-16 福建华佳彩有限公司 一种oled面板及制作方法
KR102946440B1 (ko) 2022-05-25 2026-04-01 엘지디스플레이 주식회사 표시 장치 및 그 제조 방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030122981A1 (en) * 2001-12-29 2003-07-03 Seung-Kyu Choi Liquid crystal display device and fabricating method thereof
CN101562154A (zh) * 2009-03-24 2009-10-21 福州华映视讯有限公司 薄膜晶体管的制造方法
CN103928470A (zh) * 2013-06-24 2014-07-16 上海天马微电子有限公司 一种氧化物半导体tft阵列基板及其制造方法
CN104392991A (zh) * 2014-12-04 2015-03-04 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1020920B1 (en) * 1999-01-11 2010-06-02 Sel Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a driver TFT and a pixel TFT on a common substrate
KR100886241B1 (ko) * 2002-09-10 2009-02-27 엘지디스플레이 주식회사 액정표시소자의 제조방법
KR101086477B1 (ko) * 2004-05-27 2011-11-25 엘지디스플레이 주식회사 표시 소자용 박막 트랜지스터 기판 제조 방법
KR101121620B1 (ko) * 2004-06-05 2012-02-28 엘지디스플레이 주식회사 표시 소자용 박막 트랜지스터 기판 및 그 제조 방법
KR100600878B1 (ko) * 2004-06-29 2006-07-14 삼성에스디아이 주식회사 박막트랜지스터 및 그 제조방법
KR101108369B1 (ko) * 2004-12-31 2012-01-30 엘지디스플레이 주식회사 폴리 실리콘형 액정 표시 장치용 어레이 기판 및 그 제조방법
KR20070014715A (ko) * 2005-07-29 2007-02-01 삼성전자주식회사 개구율이 향상된 어레이 기판 및 이의 제조방법
KR20070115235A (ko) * 2006-06-01 2007-12-05 삼성전자주식회사 개구율이 향상된 표시 장치 및 그 제조 방법
KR20100081772A (ko) * 2009-01-07 2010-07-15 삼성모바일디스플레이주식회사 유기 발광 표시 장치
CN102270604B (zh) * 2010-06-03 2013-11-20 北京京东方光电科技有限公司 阵列基板的结构及其制造方法
CN103022080B (zh) * 2012-12-12 2015-09-16 京东方科技集团股份有限公司 阵列基板及其制作方法、有机发光二极管显示装置
CN103943628B (zh) * 2013-10-14 2017-01-11 上海天马微电子有限公司 Tft阵列基板、制造方法及其显示面板
CN104037129A (zh) * 2014-06-20 2014-09-10 深圳市华星光电技术有限公司 Tft背板的制造方法及tft背板结构
CN104091785A (zh) * 2014-07-22 2014-10-08 深圳市华星光电技术有限公司 Tft背板的制作方法及tft背板结构

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030122981A1 (en) * 2001-12-29 2003-07-03 Seung-Kyu Choi Liquid crystal display device and fabricating method thereof
CN101562154A (zh) * 2009-03-24 2009-10-21 福州华映视讯有限公司 薄膜晶体管的制造方法
CN103928470A (zh) * 2013-06-24 2014-07-16 上海天马微电子有限公司 一种氧化物半导体tft阵列基板及其制造方法
CN104392991A (zh) * 2014-12-04 2015-03-04 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置

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