WO2016169169A1 - 阵列基板及其制备方法、显示面板、显示装置 - Google Patents

阵列基板及其制备方法、显示面板、显示装置 Download PDF

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WO2016169169A1
WO2016169169A1 PCT/CN2015/087592 CN2015087592W WO2016169169A1 WO 2016169169 A1 WO2016169169 A1 WO 2016169169A1 CN 2015087592 W CN2015087592 W CN 2015087592W WO 2016169169 A1 WO2016169169 A1 WO 2016169169A1
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Prior art keywords
pattern
substrate
gate
data line
trace
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PCT/CN2015/087592
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English (en)
French (fr)
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邹志翔
黄寅虎
杨成绍
宋博韬
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to EP15839121.9A priority Critical patent/EP3288079B1/en
Priority to US15/022,036 priority patent/US20170062487A1/en
Publication of WO2016169169A1 publication Critical patent/WO2016169169A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals

Definitions

  • the present invention relates to the field of display design, and in particular, to an array substrate, a preparation method thereof, a display panel, and a display device.
  • the outer surface of the protective layer in the peripheral trace area ie, the surface away from the base substrate
  • the thickness of the protective layer corresponding to the position of the trace around the data line (200) ⁇ 400 nm) is smaller than the thickness of the insulating layer plus the protective layer corresponding to the position of the trace around the gate line (600 nm to 800 nm in total) (ie, the trace around the gate line is only protected by the protective layer from the periphery of the data line)
  • the wire is protected by the insulating layer. Therefore, the wire around the data line is more fragile than the wire around the gate line, and is easily scratched or crushed by foreign objects, thereby causing the line. Bad problems, which in turn affect product performance stability.
  • an embodiment of the present invention provides an array substrate, a method for fabricating the same, a display panel, and a display device, which can reduce the probability of the wire around the data line being crushed or scratched by foreign objects, thereby improving product performance stability.
  • An embodiment of the present invention provides an array substrate including a substrate substrate and a gate line peripheral trace, a gate insulating layer, a data line peripheral trace, and a protective layer sequentially formed on the base substrate, wherein A surface height of the protective layer at a position of a trace at a periphery of the gate line is higher than a surface height of the protective layer at a position corresponding to a trace at a periphery of the data line.
  • a portion of the gate insulating layer corresponding to a trace of the periphery of the data line is disposed a groove, and the data line peripheral trace is formed in the groove such that at least a portion of the data line peripheral trace in the height direction falls into the groove.
  • the groove has a depth of 100 to 400 nm in a direction perpendicular to the substrate.
  • the array substrate further includes a semiconductor layer between the gate insulating layer and the protective layer and overlapping the peripheral line of the gate line in a direction perpendicular to the substrate substrate.
  • the semiconductor layer has a thickness of 100 to 300 nm in a direction perpendicular to the substrate.
  • the embodiment of the invention further provides a display panel comprising any of the above array substrates.
  • the embodiment of the invention further provides a display device comprising the above display panel.
  • the embodiment of the invention further provides a method for preparing an array substrate, comprising:
  • a gate line peripheral trace pattern, a gate insulating layer, a data line peripheral trace pattern, and a protective layer on the base substrate wherein a surface height of the protective layer corresponding to a position of the trace pattern around the gate line is formed Higher than the surface height of the protective layer corresponding to the position of the trace pattern at the periphery of the data line.
  • the above preparation method specifically includes:
  • the gate insulating layer pattern includes a recess formed in a design region of the trace pattern around the data line;
  • a protective layer is formed on the base substrate on which the data line peripheral trace pattern and the gate insulating layer pattern are formed.
  • the groove has a depth of 100 to 400 nm in a direction perpendicular to the substrate.
  • the above preparation method specifically includes:
  • a protective layer is formed on the underlying substrate on which the data line peripheral trace pattern, the gate insulating layer, and the semiconductor layer pattern are formed.
  • the semiconductor layer pattern has a thickness in a direction perpendicular to the substrate substrate of 100 to 300 nm.
  • the above preparation method specifically includes:
  • the gate insulating layer pattern includes a recess formed in a design region of the trace pattern around the data line;
  • a protective layer is formed on the base substrate on which the data line peripheral trace pattern, the gate insulating layer pattern, and the semiconductor layer pattern are formed.
  • the semiconductor layer pattern has a thickness in a direction perpendicular to the substrate substrate of 100 to 300 nm.
  • the groove has a depth of 100 to 400 nm in a direction perpendicular to the substrate.
  • the surface height therefore, when the foreign matter is in contact with the peripheral routing area of the array substrate, first contact with the protective layer corresponding to the position of the wiring at the periphery of the gate line, thereby reducing the external foreign matter and the position corresponding to the peripheral line of the data line.
  • the probability of contact with the protective layer thereby reducing the probability that the traces around the data line are crushed or scratched by foreign objects, and improving product performance stability.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is another schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 3 is still another schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • Embodiments of the present invention provide an array substrate, a display panel including the array substrate, and a display device including the display panel.
  • the array substrate includes a base substrate 1 and a gate line peripheral trace 2, a gate insulating layer 3, a data line peripheral trace 5, and a protective layer 6 which are sequentially formed on the base substrate 1.
  • the surface height of the protective layer 6 corresponding to the position of the trace 2 at the periphery of the gate line is higher than the surface height of the protective layer 6 corresponding to the position of the trace 5 around the periphery of the data line.
  • the surface height of the protective layer 6 corresponding to the position of the trace 2 at the periphery of the gate line is higher than the surface height of the protective layer 6 corresponding to the position of the trace 5 at the periphery of the data line, foreign matter in the outside When contacting the peripheral routing area of the array substrate, the foreign matter first contacts the protective layer 6 corresponding to the position of the peripheral line 2 of the gate line, thereby reducing the foreign matter and the protective layer corresponding to the position of the peripheral line 5 of the data line. 6
  • the probability of contact which in turn can reduce the probability that the traces 5 around the data line are crushed or scratched by foreign objects, and improve the performance stability of the array substrate.
  • the product performance stability of the display panel including the above array substrate and the display device including the above display panel is improved.
  • the embodiment of the present invention further provides a method for fabricating the above array substrate, which comprises: sequentially forming a gate line peripheral trace pattern, a gate insulating layer, a data line peripheral trace pattern, and a protective layer on the base substrate, wherein The surface height of the protective layer corresponding to the position of the trace pattern around the gate line is higher than the surface height of the protective layer corresponding to the position of the trace pattern at the periphery of the data line.
  • the array substrate may have a surface height corresponding to a position of the protective layer at a position of the peripheral trace pattern of the gate line higher than a surface height of the protective layer at a position corresponding to the trace pattern at the periphery of the data line by the following specific structure:
  • an array substrate provided by an embodiment of the present invention includes a base substrate 1 and a gate line peripheral trace 2 formed on the base substrate 1 in sequence, a gate insulating layer 3, and a data line peripheral trace 5 , protective layer 6.
  • a groove is formed in a portion of the gate insulating layer 3 corresponding to the peripheral trace 5 of the data line, and a data line peripheral trace 5 is formed in the recess, so that at least a portion of the data line peripheral trace 5 in the height direction falls. Into the groove.
  • the traces 5 in the height direction of the data line peripherals fall into the recesses.
  • the protective layer 6 is formed, the position of the traces 5 corresponding to the periphery of the data lines can be reduced as compared with the prior art.
  • the surface height of the protective layer 6 at the location, and the surface height of the protective layer 6 corresponding to the position of the trace 2 at the periphery of the gate line is constant, so that the surface height of the protective layer 6 corresponding to the position of the trace 2 around the gate line is high.
  • the surface height of the protective layer 6 at the position corresponding to the periphery 5 of the data line is constant, so that the surface height of the protective layer 6 corresponding to the position of the trace 2 around the gate line is high.
  • the groove has a depth of 100 to 400 nm in a direction perpendicular to the substrate 1 , Such as 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm.
  • the array substrate provided in the above manner can be prepared by the following preparation method, and the preparation method specifically includes:
  • a pattern of the gate insulating layer 3 is formed on the base substrate 1 on which the pattern of the gate line peripheral traces 2 is formed by a halftone mask process, wherein the pattern of the gate insulating layer 3 is included in the design region of the traces 5 around the data line a groove formed;
  • a protective layer 6 is formed on the base substrate 1 on which the pattern of the wiring 5 around the data line and the pattern of the gate insulating layer 3 are formed.
  • the array substrate provided by the embodiment of the present invention includes a base substrate 1, a gate line peripheral trace 2 formed on the base substrate 1, a gate insulating layer 3, a semiconductor layer 4, and a data line periphery. Trace 5, protective layer 6.
  • the semiconductor layer 4 is located between the gate insulating layer 3 and the protective layer 6 and overlaps the gate line 2 in a direction perpendicular to the substrate substrate 1.
  • the semiconductor layer 4 located between the gate insulating layer 3 and the protective layer 6 overlaps the gate line 2 in a direction perpendicular to the substrate substrate 1, it can be raised corresponding to the periphery of the gate line as compared with the prior art.
  • the surface height of the protective layer 6 at the position of the trace 2 is constant, and the surface height of the protective layer 6 corresponding to the position of the trace 5 at the periphery of the data line is constant, so that the protective layer 6 corresponding to the position of the trace 2 around the gate line is made.
  • the surface height is higher than the surface height of the protective layer 6 corresponding to the position of the trace 5 around the data line.
  • the semiconductor layer 4 has a thickness in a direction perpendicular to the substrate 1 of 100 to 300 nm, such as 100 nm, 130 nm, 150 nm, 200 nm, 230 nm, 250 nm, 300 nm.
  • the array substrate provided in the above manner 2 can be prepared by the following preparation method.
  • the preparation method comprises:
  • a pattern of the semiconductor layer 4 is formed on the gate insulating layer 3, wherein the pattern of the semiconductor layer 4 is disposed at a portion overlapping the pattern of the traces 2 around the gate line in a direction perpendicular to the substrate substrate 1;
  • a protective layer 6 is formed on the base substrate 1 on which the pattern of the wiring 5 around the data line, the gate insulating layer 3, and the pattern of the semiconductor layer 4 are formed.
  • the array substrate provided by the embodiment of the present invention includes a base substrate 1, a gate line peripheral trace 2 formed on the base substrate 1, a gate insulating layer 3, a semiconductor layer 4, and a data line periphery. Trace 5, protective layer 6.
  • a groove is formed in a portion of the gate insulating layer 3 corresponding to the peripheral trace 5 of the data line, and a data line peripheral trace 5 is formed in the recess, so that at least a portion of the data line peripheral trace 5 in the height direction falls.
  • the semiconductor layer 4 is located between the gate insulating layer 3 and the protective layer 6, and overlaps the gate line 2 in a direction perpendicular to the substrate substrate 1.
  • the protective layer 6 In the array substrate, at least a portion of the traces 5 in the height direction of the data line peripherals fall into the recesses.
  • the position of the traces 5 corresponding to the periphery of the data lines can be reduced as compared with the prior art.
  • the surface height of the protective layer 6 corresponding to the position of the trace 2 at the periphery of the gate line can be raised. Therefore, the surface height of the protective layer 6 corresponding to the position of the peripheral line 2 of the gate line is higher than the surface height of the protective layer 6 corresponding to the position of the peripheral line 5 of the data line.
  • the groove has a depth in a direction perpendicular to the base substrate 1 of 100 to 400 nm, such as 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm.
  • the semiconductor layer 4 has a thickness in a direction perpendicular to the substrate 1 of 100 to 300 nm, such as 100 nm, 130 nm, 150 nm, 200 nm, 230 nm, 250 nm, 300 nm.
  • the array substrate provided in the above manner 3 can be prepared by the following preparation method, and the preparation method comprises:
  • a pattern of the gate insulating layer 3 is formed on the base substrate 1 on which the pattern of the gate line peripheral traces 2 is formed, wherein the pattern of the gate insulating layer 3 includes grooves formed in the design region of the pattern of the traces 5 around the data line ;
  • a pattern of the semiconductor layer 4 is formed on the pattern of the gate insulating layer 3, wherein the pattern of the semiconductor layer 4 is disposed at a portion overlapping the pattern of the traces 2 around the gate line in a direction perpendicular to the substrate substrate 1;
  • a source/drain metal layer is formed on the pattern of the gate insulating layer 3 by one patterning process, and a pattern of the data line peripheral traces 5 is formed in the recess included in the pattern of the gate insulating layer 3, so that the data line is surrounded by the trace 5 At least a portion of the pattern in the height direction falls into the groove;
  • a protective layer 6 is formed on the base substrate 1 on which the pattern of the peripheral line 5 of the data line, the pattern of the gate insulating layer 3, and the pattern of the semiconductor layer 4 are formed.
  • the above array substrate can also be realized by other structures, as long as the surface height of the protective layer corresponding to the position of the trace at the periphery of the gate line is higher than the surface height of the protective layer corresponding to the position of the trace at the periphery of the data line, thereby reducing the data.

Abstract

提供一种阵列基板及其制备方法、显示面板、显示装置。该阵列基板包括衬底基板（1）和依次形成于所述衬底基板（1）上的栅线周边走线（2）、栅绝缘层（3）、数据线周边走线（5）、保护层（6），其中，对应于所述栅线周边走线（2）位置处的所述保护层（6）的表面高度高于对应于所述数据线周边走线（5）位置处的所述保护层（6）的表面高度。上述阵列基板中，当外界异物在与阵列基板的周边走线区域接触时首先与对应于栅线周边走线（2）位置处的保护层接触，从而减少数据线周边走线（5）被外界异物压伤或划伤的概率，提高产品性能稳定性。

Description

阵列基板及其制备方法、显示面板、显示装置 技术领域
本发明涉及显示器设计领域，特别涉及一种阵列基板及其制备方法、显示面板、显示装置。
背景技术
在阵列基板周边走线的设计中，周边走线区域内的栅线周边走线与数据线周边走线之间需要交替布线以解决空间不足问题。在现有技术中，周边走线区域内的保护层的外表面(即，其远离衬底基板的表面)是平坦的，由于与数据线周边走线位置处相对应的保护层的厚度(200～400nm)小于与栅线周边走线位置处相对应的绝缘层加保护层的厚度(共600nm～800nm)(即，与数据线周边走线仅由保护层进行保护相比，栅线周边走线除了所述保护层之外，还受到绝缘层的保护)，因此，与栅线周边走线相比，数据线周边走线更加脆弱，容易被外界异物的划伤或压伤，从而导致线不良问题，进而影响产品性能稳定性。
发明内容
针对上述问题，本发明实施例提供了一种阵列基板及其制备方法、显示面板、显示装置，能够减少数据线周边走线被外界异物压伤或划伤的概率，从而提高产品性能稳定性。
本发明实施例提供一种阵列基板，包括衬底基板和依次形成于所述衬底基板上的栅线周边走线、栅绝缘层、数据线周边走线、保护层，其中，对应于所述栅线周边走线位置处的所述保护层的表面高度高于对应于所述数据线周边走线位置处的所述保护层的表面高度。
优选地，在所述栅绝缘层中对应于所述数据线周边走线的部位设置 凹槽，并在凹槽中形成所述数据线周边走线，使得所述数据线周边走线在高度方向上的至少一部分落入所述凹槽内。
优选地，所述凹槽在垂直于衬底基板的方向上的深度为100～400nm。
优选地，上述阵列基板还包括位于所述栅绝缘层与所述保护层之间、且沿垂直于所述衬底基板方向与所述栅线周边走线重叠的半导体层。
优选地，所述半导体层在垂直于衬底基板的方向上的厚度为100～300nm。
本发明实施例还提供一种显示面板，包括上述任一阵列基板。
本发明实施例还提供一种显示装置，包括上述显示面板。
本发明实施例还提供了一种阵列基板制备方法，包括：
在衬底基板上依次形成栅线周边走线图形、栅绝缘层、数据线周边走线图形、保护层，其中，对应于所述栅线周边走线图形位置处的所述保护层的表面高度高于对应于所述数据线周边走线图形位置处的所述保护层的表面高度。
优选地，上述制备方法，具体包括：
在衬底基板上形成栅金属层，并形成栅线周边走线图形；
在形成有所述栅线周边走线图形的所述衬底基板上形成栅绝缘层图形，所述栅绝缘层图形中包括在数据线周边走线图形的设计区域形成的凹槽；
在所述栅绝缘层图形上形成源漏金属层，并在所述栅绝缘层图形中所包括的凹槽中形成数据线周边走线图形，使得所述数据线周边走线图形在高度方向上的至少一部分落入所述凹槽内；
在形成了所述数据线周边走线图形和所述栅绝缘层图形的衬底基板上形成保护层。
优选地，所述凹槽在垂直于衬底基板的方向上的深度为100～400nm。
优选地，上述制备方法，具体包括：
在衬底基板上形成栅金属层，并形成栅线周边走线图形；
在形成了所述栅线周边走线图形的所述衬底基板上形成栅绝缘层；
在所述栅绝缘层上形成半导体层图形，其中，所述半导体层图形被布置在沿垂直于所述衬底基板方向与所述栅线周边走线图形重叠的部位；
在所述栅绝缘层上形成源漏金属层，并形成数据线周边走线图形；
在形成有所述数据线周边走线图形、所述栅绝缘层和所述半导体层图形的衬底基板上形成保护层。
优选地，所述半导体层图形在垂直于衬底基板的方向上的厚度为100～300nm。
优选地，上述制备方法，具体包括：
在衬底基板上形成栅金属层，并形成栅线周边走线图形；
在形成有所述栅线周边走线图形的所述衬底基板上形成栅绝缘层图形，所述栅绝缘层图形中包括在数据线周边走线图形的设计区域形成的凹槽；
在所述栅绝缘层图形上形成半导体层图形，其中，所述半导体层图形被布置在沿垂直于所述衬底基板方向与所述栅线周边走线图形重叠的部位；
在所述栅绝缘层图形上形成源漏金属层，并在所述栅绝缘层图形所包括的凹槽中形成数据线周边走线图形，使得所述数据线周边走线图形在高度方向上的至少一部分落入所述凹槽内；
在形成了所述数据线周边走线图形、所述栅绝缘层图形和所述半导体层图形的衬底基板上形成保护层。
优选地，所述半导体层图形在垂直于衬底基板的方向上的厚度为100～300nm。
优选地，所述凹槽在垂直于衬底基板的方向上的深度为100～400nm。
根据本发明实施例提供的阵列基板及其制备方法，显示面板和显示装置，由于对应于栅线周边走线位置处的保护层的表面高度高于对应于数据线周边走线位置处的保护层的表面高度，因此，当外界异物在与阵列基板的周边走线区域接触时首先与对应于栅线周边走线位置处的保护层接触，从而减少了外界异物与对应于数据线周边走线位置处的保护层接触的几率，进而减少数据线周边走线被外界异物压伤或划伤的概率，提高产品性能稳定性。
附图说明
图1是本发明实施例提供的阵列基板的结构示意图；
图2是本发明实施例提供的阵列基板的另一结构示意图；
图3是本发明实施例提供的阵列基板的又一结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供了一种阵列基板、包括该阵列基板的显示面板及包括该显示面板的显示装置。如图1-图3所示，所述阵列基板包括衬底基板1和依次形成于衬底基板1上的栅线周边走线2、栅绝缘层3、数据线周边走线5、保护层6，其中，对应于栅线周边走线2位置处的保护层6的表面高度高于对应于数据线周边走线5位置处的保护层6的表面高度。由于对应于栅线周边走线2位置处的保护层6的表面高度高于对应于数据线周边走线5位置处的保护层6的表面高度，所以，在外界异物 与阵列基板的周边走线区域接触时，外界异物首先与对应于栅线周边走线2位置处的保护层6接触，从而减少了外界异物与对应于数据线周边走线5位置处的保护层6接触的几率，进而能够减小数据线周边走线5被外界异物压伤或划伤的概率，提高了阵列基板的产品性能稳定性。且提高了包括上述阵列基板的显示面板、以及包括上述显示面板的显示装置的产品性能稳定性。
本发明实施例还提供了一种上述阵列基板的制备方法，该制备方法包括：在衬底基板上依次形成栅线周边走线图形、栅绝缘层、数据线周边走线图形、保护层，其中，对应于栅线周边走线图形位置处的保护层的表面高度高于对应于数据线周边走线图形位置处的保护层的表面高度。
具体地，上述阵列基板可以通过下述具体结构实现对应于栅线周边走线图形位置处的保护层的表面高度高于对应于数据线周边走线图形位置处的保护层的表面高度：
方式一：如图1所示，本发明实施例提供的阵列基板包括衬底基板1和依次形成于衬底基板1上的栅线周边走线2、栅绝缘层3、数据线周边走线5、保护层6。其中，在栅绝缘层3中对应于数据线周边走线5的部位设置凹槽，并在凹槽中形成数据线周边走线5，使得数据线周边走线5在高度方向上的至少一部分落入凹槽内。
上述阵列基板中，因数据线周边走线5在高度方向上的至少一部分落入凹槽内，在形成保护层6时，与现有技术相比，可以降低对应于数据线周边走线5位置处的保护层6的表面高度，而对应于栅线周边走线2位置处的保护层6的表面高度不变，从而使对应于栅线周边走线2位置处的保护层6的表面高度高于对应于数据线周边走线5位置处的保护层6的表面高度。
优选地，该凹槽在垂直于衬底基板1的方向上的深度为100～400nm， 如100nm、150nm、200nm、250nm、300nm、350nm、400nm。
相应地，上述方式一中提供的阵列基板可以通过下述制备方法制备，该制备方法具体包括：
在衬底基板1上通过一次构图工艺形成栅金属层，并形成栅线周边走线2的图形；
通过半色调掩膜工艺在形成有栅线周边走线2的图形的衬底基板1上形成栅绝缘层3的图形，其中栅绝缘层3的图形中包括在数据线周边走线5的设计区域形成的凹槽；
通过一次构图工艺在栅绝缘层3的图形上形成源漏金属层，并在栅绝缘层3的图形中所包括的凹槽中形成数据线周边走线5的图形，使得数据线周边走线5的图形在高度方向上的至少一部分落入凹槽内；
在形成了上述数据线周边走线5的图形和栅绝缘层3的图形的衬底基板1上形成保护层6。
方式二：如图2所示，本发明实施例提供的阵列基板包括衬底基板1、形成于衬底基板1上的栅线周边走线2、栅绝缘层3、半导体层4、数据线周边走线5、保护层6。其中，半导体层4位于栅绝缘层3与保护层6之间、且沿垂直于衬底基板1方向与栅线周边走线2重叠。
因位于栅绝缘层3与保护层6之间的半导体层4沿垂直于衬底基板1的方向与栅线周边走线2重叠，使得与现有技术相比，可以升高对应于栅线周边走线2位置处的保护层6的表面高度，而对应于数据线周边走线5位置处的保护层6的表面高度不变，从而使对应于栅线周边走线2位置处的保护层6的表面高度高于对应于数据线周边走线5位置处的保护层6的表面高度。
优选地，半导体层4在垂直于衬底基板1的方向上的厚度为100～300nm，如100nm、130nm、150nm、200nm、230nm，250nm、300nm。
相应地，上述方式二中提供的阵列基板可以通过下述制备方法制备， 该制备方法包括：
在衬底基板1上通过一次构图工艺形成栅金属层，并形成栅线周边走线2的图形；
在形成有栅线周边走线2的图形的衬底基板1上形成栅绝缘层3；
在栅绝缘层3上形成半导体层4的图形，其中，半导体层4的图形被布置在沿垂直于衬底基板1方向与栅线周边走线2的图形重叠的部位；
在栅绝缘层3上形成源漏金属层，并形成数据线周边走线5的图形；
在形成有上述数据线周边走线5的图形、栅绝缘层3和半导体层4的图形的衬底基板1上形成保护层6。
方式三：如图3所示，本发明实施例提供的阵列基板包括衬底基板1、形成于衬底基板1上的栅线周边走线2、栅绝缘层3、半导体层4、数据线周边走线5、保护层6。其中，在栅绝缘层3中对应于数据线周边走线5的部位设置凹槽，并在凹槽中形成数据线周边走线5，使得数据线周边走线5在高度方向上的至少一部分落入凹槽内；半导体层4位于栅绝缘层3与保护层6之间、且沿垂直于衬底基板1方向与栅线周边走线2重叠。
上述阵列基板中，因数据线周边走线5在高度方向上的至少一部分落入凹槽内，在形成保护层6时，与现有技术相比，可以降低对应于数据线周边走线5位置处的保护层6的表面高度；同时位于栅绝缘层3与保护层6之间的半导体层4沿垂直于衬底基板1的方向与栅线周边走线2重叠，使得与现有技术相比，可以升高对应于栅线周边走线2位置处的保护层6的表面高度。因此，对应于栅线周边走线2位置处的保护层6的表面高度高于对应于数据线周边走线5位置处的保护层6的表面高度。
优选地，该凹槽在垂直于衬底基板1的方向上的深度为100～400nm，如100nm、150nm、200nm、250nm、300nm、350nm、400nm。
优选地，半导体层4在垂直于衬底基板1的方向上的厚度为100～300nm，如100nm、130nm、150nm、200nm、230nm，250nm、300nm。
相应地，上述方式三中提供的阵列基板可以通过下述制备方法制备，该制备方法包括：：
在衬底基板1上通过一次构图工艺形成栅金属层，并形成栅线周边走线2的图形；
在形成有栅线周边走线2的图形的衬底基板1上形成栅绝缘层3的图形，其中栅绝缘层3的图形中包括在数据线周边走线5的图形的设计区域形成的凹槽；
在栅绝缘层3的图形上形成半导体层4的图形，其中，半导体层4的图形被布置在沿垂直于衬底基板1方向与栅线周边走线2的图形重叠的部位；
在栅绝缘层3的图形上通过一次构图工艺形成源漏金属层，并在栅绝缘层3的图形所包括的凹槽中形成数据线周边走线5的图形，使得数据线周边走线5的图形在高度方向上的至少一部分落入上述凹槽内；
在形成了上述数据线周边走线5的图形、栅绝缘层3的图形和半导体层4的图形的衬底基板1上形成保护层6。
当然，上述阵列基板还可以通过其他结构实现，只要对应于栅线周边走线位置处的保护层的表面高度高于对应于数据线周边走线位置处的保护层的表面高度，即可减少数据线周边走线被外界异物压伤或划伤的概率，从而提高产品性能稳定性。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (15)

  1. 一种阵列基板，包括衬底基板和依次形成于所述衬底基板上的栅线周边走线、栅绝缘层、数据线周边走线、保护层，其中，对应于所述栅线周边走线位置处的所述保护层的表面高度高于对应于所述数据线周边走线位置处的所述保护层的表面高度。
  2. 根据权利要求1所述的阵列基板，其中，在所述栅绝缘层中对应于所述数据线周边走线的部位设置凹槽，并在凹槽中形成所述数据线周边走线，使得所述数据线周边走线在高度方向上的至少一部分落入所述凹槽内。
  3. 根据权利要求2所述的阵列基板，其中，所述凹槽在垂直于衬底基板的方向上的深度为100～400nm。
  4. 根据权利要求1或2所述的阵列基板，其中，所述阵列基板还包括位于所述栅绝缘层与所述保护层之间、且沿垂直于所述衬底基板方向与所述栅线周边走线重叠的半导体层。
  5. 根据权利要求4所述的阵列基板，其中，所述半导体层在垂直于衬底基板的方向上的厚度为100～300nm。
  6. 一种显示面板，包括权利要求1-5任一项所述的阵列基板。
  7. 一种显示装置，包括权利要求6所述的显示面板。
  8. 一种阵列基板制备方法，包括：
    在衬底基板上依次形成栅线周边走线图形、栅绝缘层、数据线周边走线图形、保护层，其中，对应于所述栅线周边走线图形位置处的所述保护层的表面高度高于对应于所述数据线周边走线图形位置处的所述保护层的表面高度。
  9. 如权利要求8中所述的制备方法，其中，所述在衬底基板上依次形成栅线周边走线图形、栅绝缘层、数据线周边走线图形、保护层， 包括：
    在衬底基板上形成栅金属层，并形成栅线周边走线图形；
    在形成有所述栅线周边走线图形的所述衬底基板上形成栅绝缘层图形，所述栅绝缘层图形中包括在数据线周边走线图形的设计区域形成的凹槽；
    在所述栅绝缘层图形上形成源漏金属层，并在所述栅绝缘层图形中所包括的凹槽中形成数据线周边走线图形，使得所述数据线周边走线图形在高度方向上的至少一部分落入所述凹槽内；
    在形成了所述数据线周边走线图形和所述栅绝缘层图形的衬底基板上形成保护层。
  10. 如权利要求9中所述的制备方法，其中，所述凹槽在垂直于衬底基板的方向上的深度为100～400nm。
  11. 如权利要求8中所述的制备方法，其中，所述在衬底基板上依次形成栅线周边走线图形、栅绝缘层、数据线周边走线图形、保护层，包括：
    在衬底基板上形成栅金属层，并形成栅线周边走线图形；
    在形成了所述栅线周边走线图形的所述衬底基板上形成栅绝缘层；
    在所述栅绝缘层上形成半导体层图形，其中，所述半导体层图形被布置在沿垂直于所述衬底基板方向与所述栅线周边走线图形重叠的部位；
    在所述栅绝缘层上形成源漏金属层，并形成数据线周边走线图形；
    在形成有所述数据线周边走线图形、所述栅绝缘层和所述半导体层图形的衬底基板上形成保护层。
  12. 如权利要求11中所述的制备方法，其中，所述半导体层图形在垂直于衬底基板的方向上的厚度为100～300nm。
  13. 如权利要求8中所述的制备方法，其中，所述在衬底基板上依 次形成栅线周边走线图形、栅绝缘层、数据线周边走线图形、保护层，包括：
    在衬底基板上形成栅金属层，并形成栅线周边走线图形；
    在形成有所述栅线周边走线图形的所述衬底基板上形成栅绝缘层图形，所述栅绝缘层图形中包括在数据线周边走线图形的设计区域形成的凹槽；
    在所述栅绝缘层图形上形成半导体层图形，其中，所述半导体层图形被布置在沿垂直于所述衬底基板方向与所述栅线周边走线图形重叠的部位；
    在所述栅绝缘层图形上形成源漏金属层，并在所述栅绝缘层图形所包括的凹槽中形成数据线周边走线图形，使得所述数据线周边走线图形在高度方向上的至少一部分落入所述凹槽内；
    在形成了所述数据线周边走线图形、所述栅绝缘层图形和所述半导体层图形的衬底基板上形成保护层。
  14. 如权利要求13中所述的制备方法，其中，所述半导体层图形在垂直于衬底基板的方向上的厚度为100～300nm。
  15. 如权利要求13或14中所述的制备方法，其中，所述凹槽在垂直于衬底基板的方向上的深度为100～400nm。
PCT/CN2015/087592 2015-04-22 2015-08-20 阵列基板及其制备方法、显示面板、显示装置 WO2016169169A1 (zh)

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Publication number Priority date Publication date Assignee Title
CN101241911A (zh) * 2008-03-21 2008-08-13 友达光电股份有限公司 整合于显示面板的栅极驱动电路及其制作方法
CN101697053A (zh) * 2009-09-23 2010-04-21 深超光电（深圳）有限公司 有源组件阵列基板
CN203324619U (zh) * 2013-07-15 2013-12-04 合肥京东方光电科技有限公司 一种阵列基板及显示装置

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JP2011221098A (ja) * 2010-04-05 2011-11-04 Seiko Epson Corp 電気光学装置用基板、電気光学装置、及び電子機器
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TWI442152B (zh) * 2011-10-06 2014-06-21 Hannstar Display Corp 顯示裝置及其製造方法
KR102023737B1 (ko) * 2012-11-20 2019-09-23 삼성디스플레이 주식회사 액정 표시 장치 및 이의 제조 방법
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101241911A (zh) * 2008-03-21 2008-08-13 友达光电股份有限公司 整合于显示面板的栅极驱动电路及其制作方法
CN101697053A (zh) * 2009-09-23 2010-04-21 深超光电（深圳）有限公司 有源组件阵列基板
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