WO2016165517A1 - 阵列基板及其制作方法和显示面板 - Google Patents

阵列基板及其制作方法和显示面板 Download PDF

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WO2016165517A1
WO2016165517A1 PCT/CN2016/076470 CN2016076470W WO2016165517A1 WO 2016165517 A1 WO2016165517 A1 WO 2016165517A1 CN 2016076470 W CN2016076470 W CN 2016076470W WO 2016165517 A1 WO2016165517 A1 WO 2016165517A1
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layer
electrode layer
array substrate
data line
barrier layer
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English (en)
French (fr)
Inventor
王骁
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US15/514,366 priority Critical patent/US10209595B2/en
Publication of WO2016165517A1 publication Critical patent/WO2016165517A1/zh
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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    • H10D86/021—Manufacture or treatment of multiple TFTs
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display panel.
  • the multi-dimensional electric field display mode is a commonly used display mode in a liquid crystal display panel. Based on its inherent structure definition, the process flow of an exemplary multi-dimensional electric field display mode display panel is mainly: gate line ⁇ active layer ⁇ data line ⁇ first layer of indium tin oxide (ITO) ⁇ passivation Layer ⁇ second layer ITO, wherein the first layer of ITO is a pixel electrode layer, the second layer of ITO is a common electrode layer; and the common electrode layer covers the data lines.
  • ITO indium tin oxide
  • Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display panel, which solve the problem that the parasitic capacitance between the data line and the common electrode layer is too large and the image is greenish in the structure of the array substrate, thereby avoiding signal delay and improving The display quality of the screen of the display device.
  • an array substrate in a first aspect, includes: a substrate; a data line and a passivation layer formed on the substrate; a common electrode layer formed on the passivation layer; An electrode layer and a barrier layer are formed on the base substrate, wherein the shield electrode layer is disposed between the data line and the passivation layer, and the barrier layer is disposed on the data line and the shield Between the electrode layers, the shield electrode layer is grounded, and the material of the barrier layer is a material having an insulating effect.
  • a method of fabricating an array substrate comprising: forming a data line and a passivation layer on a base substrate; forming a common electrode layer on the passivation layer; Forming a shield electrode layer between the passivation layers; forming a first barrier layer between the data line and the first barrier layer; wherein the shield electrode is grounded; the material of the first barrier layer is insulated The material of action.
  • a display panel comprising any of the array substrates of the first aspect.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of another array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic flow chart of another method for fabricating an array substrate according to an embodiment of the present invention.
  • an embodiment of the present invention provides an array substrate, as shown in FIG. 1, the substrate substrate includes a substrate substrate 1, a data line 2 formed on the substrate substrate 1, a passivation layer 3, and a passivation layer 3 On the common electrode layer 4, the array substrate further includes a shielding electrode layer 5 and a barrier layer 6, wherein:
  • the shield electrode layer 5 is disposed between the data line 2 and the passivation layer 3.
  • the barrier layer 6 is disposed between the data line 2 and the shield electrode layer 5.
  • the shield electrode layer 5 is grounded; the material of the barrier layer 6 is a material having an insulating effect.
  • the thickness of the barrier layer 6 can be any thickness of the barrier layer 6
  • the array substrate further includes a gate insulating layer 7.
  • the gate insulating layer 7 may be formed by chemical vapor deposition, the material of the gate insulating layer may be silicon nitride, etc., and the thickness of the gate insulating layer may be
  • the material of the passivation layer 3 may be silicon nitride or a transparent organic resin material, and the thickness of the passivation layer may be
  • the material of the common electrode layer 4 may be Indium Tin Oxide (ITO) or Indium-doped zinc oxide (IZO), and the common electrode layer may be formed by magnetron sputtering. The thickness of the layer can be
  • a barrier layer is formed on the data line, and a shielding electrode layer is formed between the barrier layer and the passivation layer, such that the data line of the finally formed array substrate and the shielding electrode layer are formed.
  • the barrier layer has a passivation layer between the shield electrode layer and the common electrode layer; since the shield electrode layer is grounded, the shield electrode layer is equivalent to a shield electrode, and the excessive parasitic capacitance generated can be grounded through the shield electrode layer.
  • Line derivation compared with only the passivation layer between the data line and the common electrode layer, can greatly reduce the parasitic capacitance generated between the data line and the common electrode layer, and avoid the problem of greening of the display image.
  • an array substrate is provided by providing a barrier layer on a data line of the array substrate, and a shielding electrode layer is disposed between the barrier layer and the common electrode layer, so that there is a barrier between the shielding electrode layer and the data line.
  • a layer, a passivation layer is formed between the shield electrode layer and the common electrode layer, and the shield electrode layer is grounded, and excessive parasitic capacitance generated between the common electrode layer and the data line can be derived through the ground line of the shield electrode layer, The effect of parasitic capacitance is greatly reduced, and the problem of excessive parasitic capacitance between the data line and the common electrode layer and green of the image in the structure of the array substrate is solved, the signal delay is avoided, and the display of the display device is improved. quality.
  • the array substrate further includes a pixel electrode layer 8 formed under the passivation layer 3, wherein the shield electrode layer 5 is formed in the same layer as the pixel electrode layer 8.
  • the material of the shield electrode layer 5 is the same as that of the pixel electrode layer 8.
  • the array substrate further includes a thin film transistor including a gate electrode 9, a gate insulating layer 7, a source electrode 10, a drain electrode 11 and an active layer 12, wherein:
  • the barrier layer 6 is also disposed on the thin film transistor to cover the active layer 12 in the thin film transistor.
  • the source and the drain may be formed by magnetron sputtering, and the materials of the source and the drain may be metal materials such as molybdenum (Mo), aluminum (Al) or copper (Cu), or may be used. a combination of material films; the thickness of the source and drain can be The source and the drain may be formed by magnetron sputtering; the material of the active layer may be amorphous silicon, and the thickness of the active layer may be The material of the pixel electrode layer may be ITO or IZO, and the pixel electrode layer may be formed by magnetron sputtering, and the thickness of the pixel electrode layer may be
  • the material of the barrier layer 6 may include silicon nitride, silicon oxynitride, silicon oxide or an organic film or the like.
  • a barrier layer is disposed between the data metal layer and the pixel electrode layer, such that the barrier layer is formed before the pixel electrode layer, and when the pixel electrode layer is patterned, whether dry or not
  • Both the etching method and the wet etching barrier layer can block the influence of the etching liquid or the etching gas on the channel of the formed thin film transistor, and the performance of the thin film transistor is ensured.
  • the thickness of the shield electrode layer 5 may be The material of the shield electrode layer may be the same material as that of the pixel electrode layer, for example, ITO or IZO. It should be noted that the shielding electrode layer in this embodiment may be formed by using the same material as the pixel electrode layer and using the same patterning process, thereby reducing the manufacturing process and reducing the production cost.
  • the thickness of the barrier layer can be In this way, while the barrier layer of the barrier layer is patterned to affect the channel of the thin film transistor, the thickness of the formed display panel can be prevented from being too thick, the production cost can be reduced, and the display device can be lightened and thinned.
  • the array substrate provided in the embodiment of the present invention can be applied to an advanced super-dimension field switching (ADS) and HADS mode display device with high aperture ratio.
  • ADS advanced super-dimension field switching
  • an array substrate is provided by providing a barrier layer on a data line of the array substrate, and a shielding electrode layer is disposed between the barrier layer and the common electrode layer, so that there is a barrier between the shielding electrode layer and the data line.
  • a layer, a passivation layer is formed between the shield electrode layer and the common electrode layer, and the shield electrode layer is grounded, and excessive parasitic capacitance generated between the common electrode layer and the data line can be derived through the ground line of the shield electrode layer, The effect of parasitic capacitance is greatly reduced, and the problem of excessive parasitic capacitance between the data line and the common electrode layer and green of the image in the structure of the array substrate is solved, the signal delay is avoided, and the display of the display device is improved. quality.
  • An embodiment of the present invention provides a method for fabricating an array substrate. Referring to FIG. 3, the method includes the following steps:
  • a thickness can be deposited on a substrate such as a glass substrate or a quartz substrate by magnetron sputtering.
  • a substrate such as a glass substrate or a quartz substrate by magnetron sputtering.
  • the data lines are formed in a certain area by a patterning process.
  • the thickness can be deposited on the data line by chemical vapor deposition or magnetron sputtering.
  • the first barrier film may be made of a material having an insulating effect, such as silicon nitride, or silicon oxide or silicon oxynitride.
  • a transparent conductive material such as ITO or IZO or the like is deposited on the first barrier layer by magnetron sputtering, and then a shield electrode layer is formed by exposure, development, and etching.
  • a layer of thickness is applied over the entire substrate in a manner similar to that of the gate insulating layer and the active layer.
  • the passivation layer is made of, for example, silicon nitride or a transparent organic resin material.
  • a method of magnetron sputtering is used to deposit a layer of thickness at A transparent conductive material, such as ITO or IZO, is then exposed, developed, and etched to form a common electrode layer.
  • a transparent conductive material such as ITO or IZO
  • the method for fabricating an array substrate comprises: forming a barrier layer on a data line of the array substrate, and forming a shield electrode layer between the barrier layer and the common electrode layer, such that between the shield electrode layer and the data line There is a barrier layer, a passivation layer is formed between the shield electrode layer and the common electrode layer, and the shield electrode layer is grounded, and excessive parasitic capacitance generated between the common electrode layer and the data line can pass through the ground line of the shield electrode layer.
  • the derivation can greatly reduce the influence of parasitic capacitance, solve the problem of excessive parasitic capacitance between the data line and the common electrode layer in the structure of the array substrate and the green of the image, avoid signal delay, and improve the display device.
  • the display quality of the picture comprises: forming a barrier layer on a data line of the array substrate, and forming a shield electrode layer between the barrier layer and the common electrode layer, such that between the shield electrode layer and the data line There is a barrier layer, a passivation layer is formed between the shield electrode layer
  • An embodiment of the present invention provides a method for fabricating an array substrate. Referring to FIG. 4, the method includes the following steps:
  • a gate metal layer including a gate electrode, a gate line, and a gate line lead on the base substrate.
  • a thickness can be deposited on a substrate such as a glass substrate or a quartz substrate by magnetron sputtering.
  • a metal such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper may be used, or a combination of the above-mentioned materials may be used.
  • the gate metal layer is formed on a certain area of the substrate by a patterning process such as exposure, development, etching, and peeling using a mask.
  • a thickness can be deposited on a glass substrate on which a gate metal layer is formed by chemical vapor deposition or magnetron sputtering.
  • the gate electrode insulating layer film is made of, for example, silicon nitride, and silicon oxide, silicon oxynitride or the like.
  • a metal oxide semiconductor thin film may be deposited on the gate insulating layer by chemical vapor deposition, and then the metal oxide semiconductor thin film is subjected to a patterning process to form an active layer, that is, after the photoresist is coated,
  • the mask may expose, develop, and etch the substrate to form an active layer.
  • the materials of the first barrier layer and the second barrier layer may each comprise: silicon nitride, silicon oxynitride, silicon oxide or an organic film; etc.; for example, the thickness of the first barrier layer and the second barrier layer may be
  • a thickness can be deposited on the first barrier layer and the second barrier layer by magnetron sputtering.
  • a transparent conductive material such as ITO or IZO, is then formed on the first barrier layer by exposure, development, and etching to form a pixel electrode layer on the second barrier layer.
  • the method for fabricating an array substrate comprises: forming a barrier layer on a data line of the array substrate, and forming a shield electrode layer between the barrier layer and the common electrode layer, such that between the shield electrode layer and the data line There is a barrier layer, a passivation layer is formed between the shield electrode layer and the common electrode layer, and the shield electrode layer is grounded, and excessive parasitic capacitance generated between the common electrode layer and the data line can pass through the ground line of the shield electrode layer.
  • the derivation can greatly reduce the influence of parasitic capacitance, solve the problem of excessive parasitic capacitance between the data line and the common electrode layer in the structure of the array substrate and the green of the image, avoid signal delay, and improve the display device.
  • the display quality of the picture Further, the performance of the thin film transistor can be improved.
  • Embodiments of the present invention provide a display panel including an embodiment of the present invention.
  • Array substrate provided.
  • the display panel provided by the embodiment of the present invention forms a barrier layer on a data line of the array substrate of the display panel, and forms a shield electrode layer between the barrier layer and the common electrode layer, such that between the shield electrode layer and the data line
  • a barrier layer a passivation layer is formed between the shield electrode layer and the common electrode layer, and the shield electrode layer is grounded, and excessive parasitic capacitance generated between the common electrode layer and the data line can pass through the ground line of the shield electrode layer.
  • the derivation can greatly reduce the influence of parasitic capacitance, solve the problem of excessive parasitic capacitance between the data line and the common electrode layer in the structure of the array substrate and the green of the image, avoid signal delay, and improve the display device.
  • the display quality of the picture Further, the performance of the thin film transistor can be improved, and the display performance of the display panel can be improved.

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Abstract

提供一种阵列基板及其制作方法和显示面板，该阵列基板包括：衬底基板（1）；数据线（2）和钝化层（3），形成在所述衬底基板（1）上；公共电极层（4），形成在所述钝化层（3）上；屏蔽电极层（5）和阻挡层（6），形成在所述衬底基板（1）上，其中所述屏蔽电极层（5）设置在所述数据线（2）与所述钝化层（3）之间，所述阻挡层（6）设置在所述数据线（2）与所述屏蔽电极层（5）之间，所述屏蔽电极层（5）接地，所述阻挡层（6）的材料为具有绝缘作用的材料。这样，解决了阵列基板的结构中数据线与公共电极层之间的寄生电容过大和图像泛绿的问题，避免出现信号延迟，提高了显示器件的画面的显示质量。

Description

阵列基板及其制作方法和显示面板 技术领域
本发明的实施例涉及一种阵列基板及其制作方法和显示面板。
背景技术
多维电场显示模式是液晶显示面板中的一种常用的显示模式。基于其固有结构限定，一种示例性多维电场显示模式显示面板的工艺流程主要是制作：栅线→有源层→数据线→第一层氧化铟锡(Indium tin oxide，简称ITO)→钝化层→第二层ITO，其中第一层ITO是像素电极层，第二层ITO是公共电极层；而且，公共电极层是覆盖数据线的。
这样，由于公共电极层与数据线之间还会有其它非导电的膜层存在，因此公共电极层与数据线之间会产生较大的寄生电容，产生信号延迟；甚至，会使得显示在屏幕上的画面会出现图像泛绿的问题，严重影响画面的显示质量。
发明内容
本发明的实施例提供一种阵列基板及其制作方法和显示面板，解决了阵列基板的结构中数据线与公共电极层之间的寄生电容过大和图像泛绿的问题，避免出现信号延迟，提高了显示器件的画面的显示质量。
第一方面，提供一种阵列基板，所述阵列基板包括：衬底基板；数据线和钝化层，形成在所述衬底基板上；公共电极层，形成在所述钝化层上；屏蔽电极层和阻挡层，形成在所述衬底基板上，其中所述屏蔽电极层设置在所述数据线与所述钝化层之间，所述阻挡层设置在所述数据线与所述屏蔽电极层之间，所述屏蔽电极层接地，所述阻挡层的材料为具有绝缘作用的材料。
第二方面，提供一种阵列基板的制作方法，所述方法包括：在衬底基板上形成数据线和钝化层；在所述钝化层上形成公共电极层；在所述数据线与所述钝化层之间形成屏蔽电极层；在所述数据线与所述第一阻挡层之间形成第一阻挡层；其中，所述屏蔽电极接地；所述第一阻挡层的材料为具有绝缘 作用的材料。
第三方面，提供一种显示面板，所述显示面板包括第一方面所述的任一阵列基板。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明的实施例提供的一种阵列基板的结构示意图；
图2为本发明的实施例提供的另一种阵列基板的结构示意图；
图3为本发明的实施例提供的一种阵列基板的制作方法的流程示意图；
图4为本发明的实施例提供的另一种阵列基板的制作方法的流程示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的实施例提供一种阵列基板，如图1中所示，该阵列基板包括衬底基板1、形成在衬底基板1上的数据线2、钝化层3和形成在钝化层3上的公共电极层4，该阵列基板还包括屏蔽电极层5和阻挡层6，其中：
屏蔽电极层5设置在数据线2与钝化层3之间。
阻挡层6设置在数据线2与屏蔽电极层5之间。
屏蔽电极层5接地；阻挡层6的材料为具有绝缘作用的材料。
阻挡层6的厚度可以为
Figure PCTCN2016076470-appb-000001
如图1中所示，该阵列基板上还包括栅绝缘层7。栅绝缘层7可以采用化学气相沉积的方法形成，栅绝缘层的材料可以为氮化硅等，栅绝缘层的厚度可以为
Figure PCTCN2016076470-appb-000002
钝化层3的材料可以为氮化硅或透明的有机树脂材 料，钝化层的厚度可以为
Figure PCTCN2016076470-appb-000003
公共电极层4的材料可以为氧化铟锡(Indium Tin Oxide，简称ITO)或者掺铟氧化锌(indium-doped zinc oxide，简称IZO)，公共电极层可以采用磁控溅射的方法形成，公共电极层的厚度可以为
Figure PCTCN2016076470-appb-000004
示例性地，本实施例中在数据线上形成一层阻挡层，同时在阻挡层与钝化层之间形成一层屏蔽电极层，这样最终形成的阵列基板的数据线与屏蔽电极层之间具有阻挡层，屏蔽电极层与公共电极层之间具有钝化层；由于屏蔽电极层接地，此时屏蔽电极层相当于一个屏蔽电极，可以将产生的过多的寄生电容通过屏蔽电极层的接地线导出，相比于数据线与公共电极层之间只有钝化层，可以极大的降低数据线与公共电极层之间产生的寄生电容，避免出现显示画面图像泛绿的问题。
本发明的实施例提供的阵列基板，通过在阵列基板的数据线上设置阻挡层，并在阻挡层与公共电极层之间设置屏蔽电极层，这样在屏蔽电极层与数据线之间会有阻挡层，在屏蔽电极层与公共电极层之间会有钝化层，而且屏蔽电极层接地，公共电极层与数据线之间产生的过多的寄生电容可以通过屏蔽电极层的接地线导出，可以极大的减小寄生电容的影响，解决解决了阵列基板的结构中数据线与公共电极层之间的寄生电容过大和图像泛绿的问题，避免出现信号延迟，提高了显示器件的画面的显示质量。
示例性地，参照图2所示，阵列基板还包括形成在钝化层3下方的像素电极层8，其中：屏蔽电极层5与像素电极层8同层形成。
屏蔽电极层5的材料与像素电极层8的材料相同。
进一步，如图2中所示，阵列基板上还包括薄膜晶体管，薄膜晶体管包括栅极9、栅绝缘层7、源极10，漏极11和有源层12，其中：
阻挡层6还设置在薄膜晶体管上，覆盖薄膜晶体管中的有源层12。
源极和漏极可以采用磁控溅射的方法形成，源极和漏极的材料均可以为：钼(Mo)、铝(Al)或者铜(Cu)等金属材料，也可以是用上述几种材料薄膜的组合结构；源极和漏极的厚度可以为
Figure PCTCN2016076470-appb-000005
源极和漏极可以采用磁控溅射的方法形成；有源层的材料可以为非晶硅，有源层的厚度可以为
Figure PCTCN2016076470-appb-000006
像素电极层的材料可以为ITO或者IZO，像素电极层可以采用磁控溅射的方法形成，像素电极层的厚度可以为
Figure PCTCN2016076470-appb-000007
阻挡层6的材料可以包括：氮化硅、氮氧化硅、氧化硅或者有机膜等。
示例性地，本实施例中在数据金属层和像素电极层之间设置一层阻挡层，这样阻挡层是在像素电极层之前形成的，在进行像素电极层的图案化时，无论是采用干法刻蚀还是湿法刻蚀阻挡层均可以阻挡刻蚀液或者刻蚀气体对已经形成的薄膜晶体管的沟道的影响，保证了薄膜晶体管的性能。
屏蔽电极层5的厚度可以为
Figure PCTCN2016076470-appb-000008
屏蔽电极层的材料可以采用与像素电极层的材料相同的材料，例如：ITO或者IZO。需要说明的是，本实施例中的屏蔽电极层可以是与像素电极层采用相同的材料，使用同一构图工艺形成的，从而可以减少制作工艺，降低生产成本。
示例性地，阻挡层的厚度可以为
Figure PCTCN2016076470-appb-000009
这样在实现阻挡层的阻挡像素电极层图案化对薄膜晶体管沟道的影响的同时，可以避免形成的显示面板的厚度过厚，降低生产成本，实现显示装置的轻薄化趋势。
需要说明的是本发明实施例中提供的阵列基板可以适用于高开口率的高级超维场转换技术(Advanced Super Dimension Switch，简称ADS)，HADS模式的显示器件中。
本发明的实施例提供的阵列基板，通过在阵列基板的数据线上设置阻挡层，并在阻挡层与公共电极层之间设置屏蔽电极层，这样在屏蔽电极层与数据线之间会有阻挡层，在屏蔽电极层与公共电极层之间会有钝化层，而且屏蔽电极层接地，公共电极层与数据线之间产生的过多的寄生电容可以通过屏蔽电极层的接地线导出，可以极大的减小寄生电容的影响，解决解决了阵列基板的结构中数据线与公共电极层之间的寄生电容过大和图像泛绿的问题，避免出现信号延迟，提高了显示器件的画面的显示质量。
本发明的实施例提供一种阵列基板的制作方法，参照图3所示，该方法包括以下步骤：
101、在衬底基板上形成数据线。
示例性地，可以采用磁控溅射的方法在基板例如玻璃基板或石英基板上沉积一层厚度在
Figure PCTCN2016076470-appb-000010
到
Figure PCTCN2016076470-appb-000011
金属薄膜。通过构图工艺处理在一定区域形成数据线。
102、在数据线上形成第一阻挡层。
示例性地，可以利用化学汽相沉积法或者磁控溅射的方法在数据线上沉 积厚度为
Figure PCTCN2016076470-appb-000012
至
Figure PCTCN2016076470-appb-000013
的第一阻挡层薄膜，该第一阻挡层薄膜的材料可以是具有绝缘作用的材料，例如氮化硅，也可以使用氧化硅或氮氧化硅等。
103、在第一阻挡层上形成屏蔽电极层。
示例性地，采用磁控溅射的方法在第一阻挡层上沉积透明导电材料，例如ITO或者IZO等，然后经过曝光、显影、刻蚀形成屏蔽电极层。
104、在屏蔽电极层上形成钝化层。
示例性地，采用与栅绝缘层以及有源层相类似的方法，在整个基板上涂覆一层厚度在
Figure PCTCN2016076470-appb-000014
到
Figure PCTCN2016076470-appb-000015
的钝化层，其材料例如是氮化硅或透明的有机树脂材料。
105、在钝化层上形成公共电极层。
示例性地，采用磁控溅射的方法沉积一层厚度在
Figure PCTCN2016076470-appb-000016
之间的透明导电材料，例如ITO或者IZO等，之后经过曝光、显影、刻蚀形成公共电极层。
本发明的实施例提供的阵列基板的制作方法，通过在阵列基板的数据线上形成阻挡层，并在阻挡层与公共电极层之间形成屏蔽电极层，这样在屏蔽电极层与数据线之间会有阻挡层，在屏蔽电极层与公共电极层之间会有钝化层，而且屏蔽电极层接地，公共电极层与数据线之间产生的过多的寄生电容可以通过屏蔽电极层的接地线导出，可以极大的减小寄生电容的影响，解决解决了阵列基板的结构中数据线与公共电极层之间的寄生电容过大和图像泛绿的问题，避免出现信号延迟，提高了显示器件的画面的显示质量。
本发明的实施例提供一种阵列基板的制作方法，参照图4所示，该方法包括以下步骤：
201、在衬底基板上形成包括栅极、栅线和栅线引线的栅金属层。
示例性地，可以采用磁控溅射的方法在基板例如玻璃基板或石英基板上沉积一层厚度在
Figure PCTCN2016076470-appb-000017
至
Figure PCTCN2016076470-appb-000018
的金属薄膜，该金属薄膜通常可以采用钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以使用上述几种材料薄膜的组合结构。然后，用掩模板通过曝光、显影、刻蚀、剥离等构图工艺处理，在基板的一定区域上形成栅金属层。
202、在栅金属层上形成栅绝缘层。
示例性地，可以利用化学气相沉积法或者磁控溅射的方法在形成有栅金 属层的玻璃基板上沉积厚度为
Figure PCTCN2016076470-appb-000019
至
Figure PCTCN2016076470-appb-000020
的栅电极绝缘层薄膜，该栅绝缘层薄膜的材料例如是氮化硅，也可以使用氧化硅和氮氧化硅等。
203、在栅绝缘层上形成有源层、源极、漏极和数据线。
示例性地，可以利用化学汽相沉积法在栅绝缘层上沉积金属氧化物半导体薄膜，然后对金属氧化物半导体薄膜进行一次构图工艺形成有源层，即在光刻胶涂覆后，用普通的掩模板对基板进行曝光、显影、刻蚀形成有源层即可。
204、采用具有绝缘作用的材料在数据线形成第一阻挡层，同时采用和第一阻挡层相同的材料在源极和漏极上形成第二阻挡层。
其中，第一阻挡层和第二阻挡层的材料均可以包括：氮化硅、氮氧化硅、氧化硅或者有机膜等；例如，第一阻挡层和第二阻挡层的厚度可以为
Figure PCTCN2016076470-appb-000021
205、在第二阻挡层上形成像素电极层，同时在第一阻挡层上形成屏蔽电极层。
示例性地，可以采用磁控溅射的方法在第一阻挡层和第二阻挡层上沉积一层厚度在
Figure PCTCN2016076470-appb-000022
之间的透明导电材料，例如ITO或者IZO等，之后经过曝光、显影、刻蚀在第一阻挡层上形成屏蔽电极层，在第二阻挡层上形成像素电极层。
206、在像素电极层上形成覆盖像素电极层和屏蔽电极层的钝化层。
207、在钝化层上形成公共电极层。
需要说明的是，本实施例中的流程与上述实施例中的步骤相同的描述与上述实施例中的说明类似，此处不再赘述。
本发明的实施例提供的阵列基板的制作方法，通过在阵列基板的数据线上形成阻挡层，并在阻挡层与公共电极层之间形成屏蔽电极层，这样在屏蔽电极层与数据线之间会有阻挡层，在屏蔽电极层与公共电极层之间会有钝化层，而且屏蔽电极层接地，公共电极层与数据线之间产生的过多的寄生电容可以通过屏蔽电极层的接地线导出，可以极大的减小寄生电容的影响，解决解决了阵列基板的结构中数据线与公共电极层之间的寄生电容过大和图像泛绿的问题，避免出现信号延迟，提高了显示器件的画面的显示质量。进而，可以提高薄膜晶体管的性能。
本发明的实施例提供一种显示面板，该显示面板包括本发明的实施例中 提供的阵列基板。
本发明的实施例提供的显示面板，通过在显示面板的阵列基板的数据线上形成阻挡层，并在阻挡层与公共电极层之间形成屏蔽电极层，这样在屏蔽电极层与数据线之间会有阻挡层，在屏蔽电极层与公共电极层之间会有钝化层，而且屏蔽电极层接地，公共电极层与数据线之间产生的过多的寄生电容可以通过屏蔽电极层的接地线导出，可以极大的减小寄生电容的影响，解决解决了阵列基板的结构中数据线与公共电极层之间的寄生电容过大和图像泛绿的问题，避免出现信号延迟，提高了显示器件的画面的显示质量。进而，可以提高薄膜晶体管的性能，可以提高显示面板的显示性能。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
本申请要求于2015年4月14日递交的中国专利申请第201510176672.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (13)

  1. 一种阵列基板，包括:
    衬底基板；
    数据线和钝化层，形成在所述衬底基板上的；
    公共电极层，形成在所述钝化层上；
    屏蔽电极层和阻挡层，形成在所述衬底基板上，
    其中所述屏蔽电极层设置在所述数据线与所述钝化层之间，
    所述阻挡层设置在所述数据线与所述屏蔽电极层之间，
    所述屏蔽电极层接地，所述阻挡层的材料为具有绝缘作用的材料。
  2. 根据权利要求1所述的阵列基板，其中所述阵列基板还包括形成在所述钝化层下方的像素电极层，所述屏蔽电极层与所述像素电极层同层形成。
  3. 根据权利要求2所述的阵列基板，其中所述屏蔽电极层与所述像素电极层的材料相同。
  4. 根据权利要求1所述的阵列基板，其中所述阵列基板还包括形成在所述衬底基板上的薄膜晶体管，所述阻挡层还设置在所述薄膜晶体管上，覆盖所述薄膜晶体管中的有源层。
  5. 根据权利要求1所述的阵列基板，其中所述阻挡层的材料包括：氮化硅、氮氧化硅、氧化硅或者有机膜。
  6. 根据权利要求1所述的阵列基板，其中所述阻挡层的厚度为
    Figure PCTCN2016076470-appb-100001
  7. 根据权利要求6所述的阵列基板，其中所述阻挡层的厚度为
    Figure PCTCN2016076470-appb-100002
  8. 根据权利要求1所述的阵列基板，其中所述屏蔽电极层的厚度为
    Figure PCTCN2016076470-appb-100003
  9. 一种阵列基板的制作方法，所述方法包括：
    在衬底基板上形成数据线和钝化层；
    在所述钝化层上形成公共电极层；
    在所述数据线与所述钝化层之间形成屏蔽电极层；
    在所述数据线与所述屏蔽电极层之间形成第一阻挡层；
    其中，所述屏蔽电极接地，所述第一阻挡层的材料为具有绝缘作用的材 料。
  10. 根据权利要求9所述的方法，所述方法还包括：
    在所述钝化层下方形成像素电极层；
    所述在所述数据线上形成屏蔽电极层包括：
    采用与所述像素电极层相同的材料，与所述像素电极层同层在所述数据线上形成所述屏蔽电极层。
  11. 根据权利要求9所述的方法，所述方法还包括：
    在所述衬底基板上形成薄膜晶体管；
    在所述薄膜晶体管上形成覆盖所述薄膜晶体管的有源层的第二阻挡层；
    其中，所述第一阻挡层与所述第二阻挡层同层同材料形成。
  12. 根据权利要求9所述的方法，其中所述阻挡层的材料包括：氮化硅、氮氧化硅、氧化硅或者有机膜。
  13. 一种显示面板，其中所述显示面板包括权利要求1-8中任一所述的阵列基板。
PCT/CN2016/076470 2015-04-14 2016-03-16 阵列基板及其制作方法和显示面板 Ceased WO2016165517A1 (zh)

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