WO2016165264A1 - 像素单元及其制备方法、阵列基板和显示装置 - Google Patents

像素单元及其制备方法、阵列基板和显示装置 Download PDF

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WO2016165264A1
WO2016165264A1 PCT/CN2015/088509 CN2015088509W WO2016165264A1 WO 2016165264 A1 WO2016165264 A1 WO 2016165264A1 CN 2015088509 W CN2015088509 W CN 2015088509W WO 2016165264 A1 WO2016165264 A1 WO 2016165264A1
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Prior art keywords
layer
gate
pad
drain
film transistor
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PCT/CN2015/088509
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English (en)
French (fr)
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尹小斌
陈传宝
孙东领
王立森
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/105,032 priority Critical patent/US10332917B2/en
Priority to EP15866400.3A priority patent/EP3270416A4/en
Publication of WO2016165264A1 publication Critical patent/WO2016165264A1/zh

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    • H10K59/88—Dummy elements, i.e. elements having non-functional features

Definitions

  • Embodiments of the present invention generally relate to the field of liquid crystal display, and in particular, to a pixel unit, a method of fabricating the same, an array substrate, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the basic structure of a Thin Film Transistor Liquid Crystal Display includes an array substrate and an opposite substrate.
  • the liquid crystal layer is filled between the array substrate and the opposite substrate, and a cell structure is formed by a process of a cell.
  • each of the pixel units includes a thin film transistor (TFT) 20, a pixel electrode 41, and a common electrode 43.
  • TFT thin film transistor
  • the thin film transistor 20 includes a gate electrode 21, a gate insulating layer 22 formed on the gate electrode 21, an active layer 23 formed on the gate insulating layer 22, and a source electrode 24 and a drain electrode formed on the active layer 23. 25.
  • the gate insulating layer 22 made from a material SiOx, SiN x and the like.
  • the pixel electrode 41 and the common electrode 43 are typically made of an ITO material separated by a passivation layer 42.
  • an organic layer 30 is used as an insulating layer.
  • the use of an organic insulating layer has the advantage that its insulating properties are better than inorganic insulating layers (generally prepared from SiN x materials), and it tends to form thicker film layers.
  • the thickness of the SiN x insulating layer is generally 0.2 to 0.6 ⁇ m, and the thickness of the organic insulating layer can be 2 ⁇ m. The greater the thickness of the insulating layer between the drain electrode 25 and the pixel electrode 41, the larger the distance between the source/drain electrodes (24, 25) and the pixel electrode 41, the smaller the coupling capacitance is formed, and the quality of the displayed picture will be better.
  • the organic insulating layer In order to electrically connect the pixel electrode 41 to the drain electrode 25 of the thin film transistor, it is necessary to form a via hole 50 in the organic insulating layer.
  • the depth of the via hole 50 is deep (up to 2 ⁇ m), and the slope is large, and the conductive material overlapped on the side of the via hole is liable to be broken. Further, the depth of the via hole 50 is deep and the flatness is poor, and Rubbing Mura (that is, a fine stripe-like defect formed on the panel by the alignment film rubbing alignment process) is also generated.
  • Rubbing Mura that is, a fine stripe-like defect formed on the panel by the alignment film rubbing alignment process
  • FIG. 2 is a schematic structural view of a pixel unit after reducing a via slope on a prior art array substrate.
  • the above conditions can be alleviated by controlling the slope of the via by process conditions.
  • the via depth is constant
  • to reduce the via slope it is necessary to increase the via size, which requires the space size of the via to be large enough.
  • the method of reducing the slope of the via is difficult to implement.
  • the present invention provides a pixel unit, a method of fabricating the same, an array substrate, and a display device, which achieve a reduction in via slope at low cost and high feasibility.
  • a pixel unit includes: a thin film transistor; an insulating layer formed on at least a drain of the thin film transistor, wherein a via hole is formed in the insulating layer, the via hole penetrating through the insulating layer to expose a drain of the thin film transistor below a pixel electrode formed on the insulating layer and electrically connected to the drain of the thin film transistor at the via; and at least one pad upper layer formed under the via and located in the drain The pole is below the exposed portion of the via such that the height of the exposed portion is greater than the height of the portion of the drain adjacent the exposed portion.
  • a method of fabricating a pixel unit includes: forming at least one pad upper layer in a region below a predetermined via position of the pixel unit; forming a drain of the thin film transistor, a portion of the drain being formed over the at least one pad upper layer, such that a portion having a height greater than a height of a portion of the drain adjacent to the portion; forming the insulating layer at least over a drain of the thin film transistor, and corresponding to the predetermined via location in the insulating layer Forming a via hole penetrating the insulating layer to expose a drain of the underlying thin film transistor; and fabricating a pixel electrode on the insulating layer such that a drain of the pixel electrode and the thin film transistor is electrically conductive at the via hole connection.
  • an array substrate includes: a base substrate; a gate line formed on the base substrate; and a data line formed on the base substrate substantially perpendicular to the gate line; wherein, the gate line and A plurality of pixel areas are defined between the data lines.
  • Each pixel area includes at least the above pixel unit.
  • a display device is also provided.
  • the display device includes the above array substrate.
  • the pixel unit of the present invention the preparation method thereof, the array substrate and the display device have at least the following beneficial effects:
  • the upper layer of the pad is composed of a gate metal layer and/or an active layer which are not etched during the process, and does not increase any production cost and process difficulty.
  • FIG. 1 is a schematic cross-sectional view of a pixel unit on a prior art array substrate
  • FIG. 2 is a schematic cross-sectional view showing the structure of a pixel unit after reducing a via slope on a prior art array substrate;
  • FIG. 3 is a schematic cross-sectional view showing the structure of a pixel unit according to a first embodiment of the present invention
  • FIG. 4 is a flow chart of a method of fabricating a pixel unit in accordance with a second embodiment of the present invention.
  • Figure 5 is a plan view of an array substrate in accordance with a third embodiment of the present invention.
  • the depth and slope of the via are reduced by adding a pad to the bottom or under the via, thereby reducing the breakage of the conductive material on the side or wall of the via when the pixel electrode and the drain are overlapped.
  • the risk that the pad high layer can be formed by the gate metal layer and/or the active layer that are not etched during the process does not increase any production cost and process difficulty.
  • the structure of the pixel unit of the first embodiment of the present invention will be described in detail below with reference to FIG. It should be clarified that the pixel unit defined in this embodiment does not include the gate line and the data line.
  • the pixel unit of this embodiment mainly includes a thin film transistor 20, a pixel electrode 41, and a common electrode 43.
  • the thin film transistor 20 is a bottom gate type field effect transistor including a gate electrode 21, a gate insulating layer 22 formed on the gate electrode 21, and an active layer formed on the gate insulating layer 22.
  • the drain extends below the predetermined via location as described below.
  • the gate insulating layer may also extend below the predetermined via location.
  • the thin film transistor in the pixel unit may also be a top gate type thin film transistor, and the specific structure thereof is known to those skilled in the art, and a description thereof will be omitted herein.
  • the pixel unit in this embodiment includes an insulating layer formed on at least a drain of the thin film transistor, and a via hole is formed in the insulating layer, the via hole penetrating through the insulating layer to expose the thin film transistor underlying The drain.
  • the insulating layer 30 is covered.
  • the insulating layer 30 may be an organic insulating layer.
  • the pixel electrode 41 and the common electrode 43 are formed over the organic insulating layer 30 with a passivation layer 42 therebetween.
  • the pixel electrode 41 and/or the common electrode 43 are transparent electrodes, and may be transparent conductive materials such as ITO or IZO.
  • a via hole 50 is formed in the insulating layer 30.
  • the via 50 extends through the insulating layer 30 to expose the drain 25 of the thin film transistor.
  • the via 50 is in the shape of a truncated cone whose radial dimension R gradually decreases in its depth direction.
  • the pixel electrode 41 is electrically connected to the drain electrode 25 of the thin film transistor through a conductive material formed on the sidewall of the via hole, or a portion of the pixel electrode 41 is formed on the sidewall of the via hole to be electrically connected to the drain.
  • At least one pad upper layer may be disposed under the via hole, and the material layer subsequently formed on the pad upper layer is raised relative to the prior art arrangement, resulting in via hole
  • the bottom or lower opening is raised relative to the existing via, as shown, such that the depth of the via is relative to the existing via depth (typically equal to the thickness of the insulating layer, as shown in Figures 1 and 2)
  • the display is reduced so that the slope of the via can be reduced.
  • the at least one pad high layer is formed of one or more material layers forming a thin film transistor, such as a material layer forming at least one of a gate electrode and an active layer of a thin film transistor; alternatively, The at least one mat high layer may be formed separately from different materials.
  • a first pad layer 51 and a second pad layer 52 are disposed below the connection region of the drain 25 and the pixel electrode 41, and the second pad layer 52 is located above the first pad layer 51.
  • the exposed portion of the drain 25 in the via 50 is formed above the pad level, and therefore, the height of the exposed portion is greater than the height of the portion of the drain 25 adjacent to the exposed portion such that the via 50 is
  • the bottom or lower opening portion at the exposed portion of the drain electrode 25 is raised with respect to the existing via hole, so that the slope of the via hole can be reduced.
  • the first pad high layer is formed of a gate material that remains below the via location during the gate fabrication process.
  • the first pad layer 51 functions only as a pad, and is electrically connected to the gate 21 or electrically insulated from the gate 21.
  • the second pad layer 52 is formed of an active layer material that remains under the via location during the preparation of the active layer.
  • the second pad upper layer only functions as a pad, and is electrically connected to the active layer 23 or electrically insulated from the active layer 23.
  • the cross-sectional shape of the first pad layer 51 and the second pad layer 52 that is, the shape of the section taken along a plane perpendicular to the thickness direction thereof, or the shape of the projection area in a plane perpendicular to the thickness direction thereof, may Design according to needs, which may be square, circular, elliptical, etc., as long as the corresponding shape of the pattern is designed on the corresponding mask. Further, the shapes of the first pad upper layer 51 and the second pad upper layer 52 may be the same or different.
  • a step is formed between the gate insulating layer 22 and the second pad layer 52, which is due to
  • the first pad high layer 51 and the second pad high layer 52 have the same cross-sectional shape, that is, the first pad high layer 51 and the second pad upper layer 52 have the same shape in the plane perpendicular to the thickness direction thereof, and the first pad layer 51
  • the radial dimension is greater than the corresponding radial dimension of the second pad upper layer 52, that is, the area of the projection area of the second pad layer 52 is smaller than the area of the projection area of the first pad layer 51.
  • the total thickness of the film layer under the via is increased relative to the prior art, the via depth is reduced, and the actual depth is reduced by the size of the gate material layer.
  • the total thickness of the source layer of material is equivalent.
  • the thickness of the gate material layer is about 0.35 ⁇ m
  • the thickness of the active layer material layer is about 0.2 ⁇ m, so the depth of the via hole can be reduced from 2 ⁇ m to 1.45 ⁇ m. Since the depth of the via 50 is reduced, the slope of the via crossing is correspondingly reduced, which can effectively reduce the risk of breakage when the pixel electrode and the drain overlap, and can also improve the flatness of the array substrate and reduce the Rubbing Mura.
  • the present embodiment simultaneously adds the first pad upper layer and the second pad upper layer below the via hole 50.
  • the present invention only the first high layer or the second high layer may be added, and the depth of the via hole may be reduced, but the present invention can also be implemented.
  • the pad high layer in addition to the first pad high layer formed simultaneously with the gate electrode and the second pad high layer formed simultaneously with the active layer, the pad high layer can be separately prepared under the via hole, The purpose of raising the via hole and reducing the risk of breakage when the pixel electrode and the drain are overlapped can be achieved, and it is within the scope of the present invention.
  • the embodiment of the invention further provides a method for preparing a pixel unit.
  • the method includes:
  • a drain of the thin film transistor Forming a drain of the thin film transistor, a portion of the drain being formed over the at least one pad upper layer such that a height of the portion is greater than a height of a portion of the drain adjacent to the portion;
  • a pixel electrode is formed on the insulating layer such that the pixel electrode and the drain of the thin film transistor are electrically connected at the via.
  • At least one of the upper layers of the pad is formed while forming a material layer of at least one of a gate electrode and an active layer of the thin film transistor.
  • FIG. 4 is a flow chart of a method of fabricating a pixel unit in accordance with a second embodiment of the present invention. Please refer to 3 and 4, the method of this embodiment mainly includes the following steps A-F.
  • step A a gate electrode 21 is formed on the base substrate 10, and a first pad layer 51 is formed in a region below the predetermined via position of the pixel unit.
  • the step A can include:
  • Sub-step A1 forming a gate material layer on the base substrate 10;
  • Sub-step A2 A patterning process is performed on the gate material layer to form a gate electrode 21 at a predetermined gate position, and a first pad layer 51 is formed in a region below the predetermined via hole position.
  • the patterning process may include:
  • the photoresist is exposed and developed by a gate mask, so that the photoresist in the region below the preset gate position and the predetermined via location is retained; wherein the gate mask is used
  • the stencil is different from the conventional gate reticle; after exposure and development of the photoresist using a conventional gate reticle, only the photoresist at the gate position is retained, and in the present embodiment, the gate mask is used. After the template is exposed and exposed to the photoresist, the photoresist in the region below the gate position and the predetermined via position is retained;
  • the gate material layer is etched by using the retained photoresist as a mask. Due to the photoresist protection, the gate material in the region below the gate position and the predetermined via position is retained, and the gate position is retained. The remaining gate material constitutes the gate electrode 21, and the gate material remaining in the region below the predetermined via location constitutes the first pad layer 51. Moreover, there is no electrical connection between the first pad high layer 51 and the gate 21;
  • the remaining photoresist is removed.
  • step B a gate insulating layer 22 is formed on the gate electrode 21.
  • the step of forming the gate insulating layer is consistent with the corresponding steps in the prior art and will not be described in detail herein.
  • step C an active layer 23 and a second pad layer 52 are formed on the gate insulating layer 22, and the second pad layer 52 is located in a region below the predetermined via location.
  • step C specifically includes:
  • Sub-step C1 depositing a layer of active layer material on the gate insulating layer 22;
  • Sub-step C2 performing a patterning process on the active layer material layer to form the active layer 23 at a predetermined active layer position, and forming a second pad high layer 52 in a region below the predetermined via position;
  • the patterning process may include:
  • the photoresist is exposed and developed by using an active layer mask, so that the photoresist in the region below the predetermined active layer position and under the predetermined via position is retained;
  • Floor The mask is different from the conventional active layer mask; after the photoresist is exposed and developed by the conventional active layer mask, only the photoresist at the position of the active layer is reserved, and this embodiment is After exposing and developing the photoresist by using the active layer mask, the photoresist in the active layer position and the region below the predetermined via position are retained;
  • the active layer material layer is etched by using the retained photoresist as a mask. Due to the photoresist protection, the active layer material in the active layer position and the region below the predetermined via position is retained. The active layer material remaining at the position of the active layer constitutes the active layer 23, and the active layer material in the region below the predetermined via position constitutes the second pad layer 52, and the second pad layer 52 and the active layer There is no electrical connection between 23;
  • the remaining photoresist is removed.
  • step D a source electrode 24 and a drain electrode 25 are formed on the active layer 23, and a portion of the drain electrode 25 is formed on the second pad high layer 52.
  • step E an organic insulating layer 30 is formed at least over the drain of the thin film transistor, and a via 50 is formed in the organic insulating layer at a predetermined via position, the via penetrating through the insulating layer 30 to expose the underlying film The drain 25 of the transistor.
  • step F a pixel electrode 41 is formed on the insulating layer 30, wherein the pixel electrode 41 and the drain electrode 25 are electrically connected at the via 50;
  • the step F can include:
  • Sub-step F1 depositing a layer of pixel electrode material
  • the pixel electrode 41 may be a single layer film of a transparent conductive material such as ITO or IZO, or a composite film composed of a transparent conductive material such as ITO or IZO, and the method of depositing the pixel electrode layer is generally magnetron sputtering. law;
  • Sub-step F2 the pixel electrode material at the position of the via hole, the preset pixel electrode position, and the overlapped position are retained by the patterning process to form the pixel electrode and realize electrical connection with the drain of the thin film transistor 20.
  • the thickness of the gate material layer is about 0.35 ⁇ m
  • the thickness of the active layer material layer is about 0.2 ⁇ m, so the via depth can be reduced from 2 ⁇ m to 1.45 ⁇ m. Therefore, the bonding force between the conductive material between the pixel electrode and the via position and the organic insulating layer is better, thereby reducing the risk of the conductive material breaking when the pixel electrode and the drain overlap.
  • Step F may further include sub-step F3: sequentially forming a passivation layer 42 and a common electrode on the pixel electrode 41. Common electrode 43.
  • the bottom or lower opening portion of the via hole is raised by the first pad high layer 51 and the second pad high layer 52 to reduce the depth and the slope of the via hole, and the conductive material connecting the pixel electrode and the drain electrode can be effectively broken.
  • the risk can also improve the flatness of the array substrate and reduce the Rubbing Mura.
  • only two masks, a gate mask and an active mask need to be replaced, without changing other processes, and will not increase. Any production cost and process difficulty are more acceptable to the industry.
  • Figure 5 is a plan view of an array substrate in accordance with a third embodiment of the present invention.
  • the passivation layer and the common electrode above the pixel electrode are omitted.
  • the array substrate includes: a substrate substrate, such as a glass substrate; a gate line 1; formed on the base substrate; and a data line 2 formed on the base substrate substantially perpendicular to the gate line 1.
  • a plurality of pixel regions are defined by the gate line 1 and the data line 2.
  • Each of the pixel regions includes the pixel unit as shown in FIG. 3 described in the first embodiment.
  • a gate of the thin film transistor is connected to the gate line, and a source of the thin film transistor is connected to the data line.
  • gate lines are disposed above and below each of the plurality of pixel units of each row, and data lines are disposed on the left and right sides of each pixel unit, and each adjacent Only one gate line is disposed between the pixel units of the two rows, and one data line is disposed between each adjacent two columns of pixel units.
  • the array substrate of the present embodiment is different from the conventional array substrate in the prior art in that the pixel unit is the pixel unit according to the first embodiment of the present invention.
  • gate lines are disposed above and below a plurality of pixel units of each row, and two gate lines are disposed between each adjacent two rows of the pixel units;
  • a data line is disposed on the left or right side of each column of pixel units, and two columns of the pixel units are included between each adjacent two data lines.
  • a display device in a fourth embodiment, includes: an array substrate; an opposite substrate disposed opposite to the array substrate; and a liquid crystal layer filled between the array substrate and the opposite substrate.
  • the array substrate is the array substrate described in the third embodiment, wherein the array substrate and the opposite substrate are One has a color film.
  • an array substrate is provided.
  • the array substrate differs from the array substrate of the third embodiment in that it is an array substrate using OLED technology.
  • the common electrode and the pixel electrode are not separated by a passivation layer, but have an organic light-emitting layer.
  • the organic light emitting layer can emit light of a preset color and gradation.
  • a display device in a sixth embodiment, includes: an array substrate, which is the array substrate of the fifth embodiment; and a cover plate fixed above the array substrate.
  • the pad high layer may be separately prepared under the via hole
  • This document may provide an example of parameters containing specific values, but these parameters need not be exactly equal to the corresponding values, but may approximate the corresponding values within acceptable error tolerances or design constraints;
  • the present invention adds a pad upper layer below the via, such as a pad high layer formed of a material forming at least one of a gate electrode and an active layer (independent structure, not with the gate and active layer of the thin film transistor) Connection), the height of the bottom of the hole is increased, thereby reducing the depth and slope of the via hole, which can effectively reduce the risk of breakage when the pixel electrode and the drain are overlapped, improve the flatness of the array substrate, and reduce the Rubbing Mura.
  • the invention not only increases any production cost and process difficulty while effectively improving the product quality, and has good promotion and application value.

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Abstract

提供了一种像素单元及其制备方法、阵列基板和显示装置。像素单元包括：薄膜晶体管（20）；绝缘层（30），至少形成于薄膜晶体管（20）的漏极（25）上，绝缘层（30）中形成有过孔（50），过孔（50）贯穿绝缘层（30）以露出下方的薄膜晶体管（20）的漏极（25）；像素电极（41），形成于绝缘层（30）上，并与薄膜晶体管（20）的漏极（25）在过孔（50）处电性连接；以及至少一个垫高层（51,52），形成于过孔（50）的下方并位于漏极（25）在过孔（50）中的露出部分的下方，使得露出部分的高度大于漏极（25）的与露出部分相邻的部分的高度。通过在过孔下方增加垫高层来降低过孔的深度和坡度，同时，垫高层可以由工艺过程中未被刻蚀的栅极金属层和/或有源层构成，不会增加生产成本和工艺难度。

Description

像素单元及其制备方法、阵列基板和显示装置 技术领域
本发明的实施例一般地涉及液晶显示领域，尤其涉及一种像素单元及其制备方法、阵列基板和显示装置。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，简称TFT-LCD)的基本结构包括：阵列基板和对向基板。其中，阵列基板和对向基板之间充满液晶层，通过对盒工艺形成液晶盒(Cell)结构。
图1为现有技术阵列基板上的像素单元的剖面示意图。在阵列基板的衬底基板10上分布着若干个像素单元。请参照图1，每一个像素单元包括：薄膜晶体管(TFT)20、像素电极41和公共电极43。
该薄膜晶体管20包括：栅极21、形成于栅极21上的栅绝缘层22、形成于栅绝缘层22上的有源层23，以及形成于有源层23上的源极24和漏极25。一般情况下，栅极绝缘层22由SiOx、SiNx等材料制备。像素电极41和公共电极43一般由ITO材料制备，两者之间由钝化层42隔开。
像素电极41和漏极25之间，采用有机膜(Organic layer)30做绝缘层。采用有机绝缘层，好处在于其绝缘性能较无机绝缘层(一般由SiNx材料制备)更好，且其容易形成较厚的膜层。一般情况下，SiNx绝缘层的厚度一般在0.2～0.6μm，而有机绝缘层的厚度可以达到2μm。漏极25和像素电极41之间的绝缘层的厚度越大，源极/漏极(24、25)和像素电极41之间的距离越大，形成的耦合电容更小，显示的画面品质会更好。
为了使像素电极41与薄膜晶体管的漏极25电性连接，需要在有机绝缘层中形成过孔(Via Hole)50。但是，由于有机绝缘层厚度较大，导致过孔50的深度深(可达2μm)，坡度大，容易出现过孔侧面搭接的导电材料断裂的情况。此外，过孔50的深度深、平坦度差，也会产生Rubbing Mura(即因取向膜摩擦取向工艺在面板上形成的细条纹状不良)的情况。此外，当采用较大厚度的无机绝缘层时，同样会出现上述情况。
为了避免上述情况，现有技术采用直接降低过孔坡度的办法。图2为现有技术阵列基板上降低过孔坡度后的像素单元的结构示意图。请参照图2，通过工艺条件控制过孔坡度，可以缓解上述情况。但是，在过孔深度一定的前提下，要减小过孔坡度，就需要增加过孔尺寸，这需要过孔处空间尺寸足够大才行。实际上由于像素单元排列紧密，过孔空间尺寸有限，该降低过孔坡度的方法很难实现。
发明内容
(一)要解决的技术问题
鉴于上述问题，本发明提供了一种像素单元及其制备方法、阵列基板和显示装置，以低成本、高可行性地实现过孔坡度的降低。
(二)技术方案
根据本发明的一个方面，提供了一种像素单元。该像素单元包括：薄膜晶体管；绝缘层，至少形成于所述薄膜晶体管的漏极上，该绝缘层中形成有过孔，该过孔贯穿该绝缘层以露出下方的所述薄膜晶体管的漏极；像素电极，形成于所述绝缘层上，并与所述薄膜晶体管的漏极在所述过孔处电性连接；以及至少一个垫高层，形成于所述过孔的下方并位于所述漏极从所述过孔的露出部分的下方，使得所述露出部分的高度大于所述漏极的与该露出部分相邻的部分的高度。
根据本发明的另一个方面，还提供了一种像素单元的制备方法。该制备方法包括：在所述像素单元的预设过孔位置下方的区域内形成至少一个垫高层；制作薄膜晶体管的漏极，该漏极的一部分形成在所述至少一个垫高层上方，使得该部分的高度大于所述漏极的与该部分相邻的部分的高度；至少在所述薄膜晶体管的漏极上方形成所述绝缘层，并在该绝缘层中对应所述预设过孔位置处形成过孔，该过孔贯穿该绝缘层以露出下方的薄膜晶体管的漏极；以及在所述绝缘层上制作像素电极，使得该像素电极与薄膜晶体管的漏极在所述过孔处电性连接。
根据本发明的再一个方面，还提供了一种阵列基板。该阵列基板包括：衬底基板；栅线，形成于所述衬底基板上；以及数据线，形成于所述衬底基板上，与所述栅线大体垂直；其中，由所述栅线和数据线之间限定出若干个像素区域， 每个像素区域至少包含上述的像素单元。
根据本发明的又一个方面，还提供了一种显示装置。该显示装置包括上述的阵列基板。
(三)有益效果
从上述技术方案可以看出，本发明像素单元及其制备方法、阵列基板和显示装置至少具有以下有益效果：
(1)通过在过孔底部增加垫高层来降低过孔的坡度，降低像素电极与漏极搭接时导电材料断裂的风险；
(2)垫高层由工艺过程中未被刻蚀的栅极金属层和/或有源层构成，不会增加任何生产成本和工艺难度。
附图说明
通过参考附图能够更加清楚地理解本发明的特征和优点，附图是示意性的而不应理解为对本发明进行任何限制，在附图中：
图1为现有技术阵列基板上像素单元的剖面示意图；
图2为示出现有技术阵列基板上降低过孔坡度后的像素单元的结构的剖面示意图；
图3为示出根据本发明的第一实施例的像素单元的结构的剖面示意图；
图4为根据本发明的第二实施例的制备像素单元的方法的流程图；以及
图5为根据本发明的第三实施例的阵列基板的俯视图。
【附图标记说明】
1-栅线；          2-数据线；
10-基板；
20-薄膜晶体管；
21-栅极；         22-栅绝缘层；
23-有源层；       24-源极；
25-漏极；
30-有机绝缘层；
41-像素电极；     43-公共电极
42-钝化层；
50-过孔；
51-第一垫高层；    52-第二垫高层。
具体实施方式
根据本发明的一个总的构思，通过在过孔底部或下方增加垫高层来降低过孔的深度和坡度，进而降低像素电极与漏极搭接时位于过孔的侧面或壁上的导电材料断裂的风险，该垫高层可以由工艺过程中未被刻蚀的栅极金属层和/或有源层构成，不会增加任何生产成本和工艺难度。
以下结合具体实施例，并参照附图，对本发明进一步详细说明。另外，在下面的详细描述中，为便于说明，阐述了许多具体的细节以提供对本发明的实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。在其它情况下，公知的结构和装置以图示的方式体现以简化附图。
下面参照图3来详细说明本发明的第一实施例的像素单元的结构。需要明确的是，本实施例中定义的像素单元，并不包括栅线和数据线。
图3为示出根据本发明第一实施例的像素单元的结构的剖面示意图。请参照图3，本实施例的像素单元主要包括：薄膜晶体管20、像素电极41和公共电极43。
在图3示出的实施例中，该薄膜晶体管20为底栅型场效应晶体管，包括：栅极21、形成于栅极21上的栅绝缘层22、形成于栅绝缘层22上的有源层23、以及形成于有源层23上的源极24和漏极25。其中，漏极延伸至如下文所述的预设过孔位置的下方。栅绝缘层也可以延伸至预设过孔位置的下方。可以理解，像素单元中的薄膜晶体管也可以是顶栅型薄膜晶体管，其具体结构对本领域技术人员来说是已知的，在此省略对其的描述。
本实施例中的像素单元包含绝缘层，该绝缘层至少形成于所述薄膜晶体管的漏极上，该绝缘层中形成有过孔，该过孔贯穿该绝缘层以露出下方的所述薄膜晶体管的漏极。具体的，如图3所示，至少在薄膜晶体管的漏极上，覆盖有绝缘层30。在一个示例中，绝缘层30可以是有机绝缘层。像素电极41和公共电极43制备于有机绝缘层30上方，两者之间由钝化层42隔开。其中，像素电极41和/或公共电极43为透明电极，可以是ITO或IZO等透明导电材料的 单层膜，或者为ITO或IZO等透明导电材料组成的复合膜。
如图3所示，在绝缘层30中形成有过孔50。该过孔50贯穿该绝缘层30以露出薄膜晶体管的漏极25。在一个示例中，该过孔50呈倒圆台形状，其径向尺寸R沿其深度方向逐渐减小。像素电极41通过形成于过孔的侧壁上的导电材料电连接至薄膜晶体管的漏极25，或者像素电极41的一部分形成于过孔的侧壁上以与所述漏极电连接。
根据本发明的实施例，为了降低过孔的深度，在过孔的下方可以设置有至少一个垫高层，后续形成在垫高层上的材料层相对于现有技术中的布置升高，导致过孔的底部或下开口部相对于现有的过孔升高，如图所示，即，使得过孔的深度相对于现有的过孔深度(通常等于绝缘层的厚度，如图1和2所示)减小，从而能够降低过孔的坡度。在一个示例中，所述至少一个垫高层由形成薄膜晶体管的一个或多个材料层形成，例如由形成薄膜晶体管的栅极和有源层中的至少一个的材料层形成；可替换地，所述至少一个垫高层可以由不同的材料单独地形成。
在图3中示出的示例中，在漏极25和像素电极41的连接区域的下方设置有第一垫高层51和第二垫高层52，第二垫高层52位于第一垫高层51的上方。如图所示，漏极25在过孔50中的露出部分形成在垫高层上方，因此，该露出部分的高度大于漏极25的与该露出部分相邻的部分的高度，使得过孔50在漏极25的露出部分处的底部或下开口部相对于现有的过孔升高，从而能够降低过孔的坡度。
在一个示例中，该第一垫高层为在制备栅极过程中，在过孔位置的下方保留下来的栅极材料形成。并且，该第一垫高层51仅起到垫高的作用，与栅极21不电性连接或与栅极21电绝缘。示例性地，该第二垫高层52为在制备有源层过程中，在过孔位置的下方保留下来的有源层材料形成。同样，该第二垫高层仅起到垫高的作用，与有源层23不电性连接或与有源层23电绝缘。
其中，第一垫高层51和第二垫高层52的截面形状，即沿垂直于其厚度方向的平面截取的截面的形状，或者说在垂直于其厚度方向的平面内的投影区域的形状，可以根据需要进行设计，其可以为方形、圆形、椭圆形等等，只要在相应掩模板上设计上对应形状的图案即可。并且，第一垫高层51和第二垫高层52的形状可以相同，也可以不同。
请参照图3，在栅绝缘层22和第二垫高层52之间形成有台阶，这是由于 第一垫高层51和第二垫高层52的截面形状相同，即第一垫高层51和第二垫高层52在垂直于其厚度方向的平面内的投影区域的形状相同，且第一垫高层51的径向尺寸大于第二垫高层52的对应的径向尺寸，即第二垫高层52的该投影区域的面积小于第一垫高层51的该投影区域的面积。如此设计，可以缓解漏极的陡峭程度，避免其断线。
通过增加第一垫高层51和第二垫高层52，过孔下方的膜层的总厚度相对于现有技术增加，过孔深度减小了，实际深度减小的大小与栅极材料层和有源层材料层的总厚度相当。一般情况下，栅极材料层的厚度约0.35μm，有源层材料层的厚度约0.2μm，故过孔的深度可由2μm减小到1.45μm。由于过孔50的深度减小，过孔跨接处坡度相应减小，能有效降低像素电极与漏极搭接时断裂风险，也可以改善阵列基板的平坦度，减轻Rubbing Mura。
需要说明的是，本实施例中，为了尽可能减小过孔深度，本实施例在过孔50的下方同时增加了第一垫高层和第二垫高层。而在本发明其他实施例中，可以仅增加第一垫高层或第二垫高层，同样能够减小过孔的深度，但同样能够实现本发明。
此外，本领域技术人员应当了解，除了通过增加与栅极同时形成的第一垫高层和与有源层同时形成的第二垫高层之外，还可以在过孔的下方单独制备垫高层，同样能够实现将过孔垫高，降低像素电极和漏极搭接时断裂风险的目的，其一并在本发明的保护范围之内。
本发明实施例还提供了一种像素单元的制备方法。该方法包括：
在所述像素单元的预设过孔位置下方的区域内形成至少一个垫高层；
制作薄膜晶体管的漏极，该漏极的一部分形成在所述至少一个垫高层上方，使得该部分的高度大于所述漏极的与该部分相邻的部分的高度；
至少在所述薄膜晶体管的漏极上方形成所述绝缘层，并在该绝缘层中对应所述预设过孔位置处形成过孔，该过孔贯穿该绝缘层以露出下方的薄膜晶体管的漏极；以及
在所述绝缘层上制作像素电极，使得该像素电极与薄膜晶体管的漏极在所述过孔处电性连接。
其中，在形成上述薄膜晶体管的栅极和有源层中的至少一个的材料层的同时形成上述至少一个垫高层。
图4为根据本发明的第二实施例的制备像素单元的方法的流程图。请参照 图3和图4，本实施例的方法主要包括下述步骤A-F。
在步骤A中，在衬底基板10上形成栅极21，以及在所述像素单元的预设过孔位置下方的区域内形成第一垫高层51。
在一个示例中，该步骤A可以包括：
子步骤A1：在衬底基板10上形成栅极材料层；以及
子步骤A2：对栅极材料层进行构图工艺，以在预设栅极位置处形成栅极21，并在预设过孔位置下方的区域内形成第一垫高层51。
在本子步骤A2中，构图工艺可以包括：
在栅极材料层上形成光刻胶；
采用栅极掩模板(Gate Mask)对光刻胶进行曝光、显影，使预设栅极位置处和预设过孔位置下方的区域内的光刻胶被保留；其中，所使用的栅极掩模板与常规的栅极掩模板不一样；在利用常规的栅极掩模板对光刻胶曝光显影后，仅是栅极位置的光刻胶被保留，而在本实施例中，采用栅极掩模板对光刻胶曝光显影后，栅极位置处和预设过孔位置下方的区域内的光刻胶均被保留；
以保留的光刻胶为掩模，对栅极材料层进行刻蚀，由于具有光刻胶保护，栅极位置处和预设过孔位置下方的区域内的栅极材料被保留，栅极位置处保留的栅极材料构成栅极21，而预设过孔位置下方的区域内保留的栅极材料构成第一垫高层51。并且，第一垫高层51与栅极21之间没有电性连接；以及
去除剩余的光刻胶。
在步骤B中，在栅极21上形成栅极绝缘层22。
形成栅极绝缘层的步骤与现有技术中相应的步骤一致，此处不再详细说明。
在步骤C中，在栅极绝缘层22上形成有源层23和第二垫高层52，第二垫高层52位于预设过孔位置下方的区域内。
在一个示例中，该步骤C具体包括：
子步骤C1：在栅极绝缘层22上沉积有源层材料层；
子步骤C2：对有源层材料层进行构图工艺，以在预设有源层位置处形成有源层23，并在预设过孔位置下方的区域内形成第二垫高层52；
在本子步骤C2中，构图工艺可以包括：
在有源层材料层上形成光刻胶；
采用有源层掩模板(Active Mask)对光刻胶进行曝光、显影，使预设有源层位置处和预设过孔位置下方的区域内的光刻胶被保留；其中，使用的有源层 掩模板与常规的有源层掩模板不一样；在利用常规的有源层掩模板对光刻胶曝光显影后，仅是预设有源层位置处的光刻胶被保留，而本实施例中在采用有源层掩模板对光刻胶曝光显影后，有源层位置处和预设过孔位置下方的区域内的光刻胶均被保留；
以保留的光刻胶为掩模，对有源层材料层进行刻蚀，由于具有光刻胶保护，有源层位置处和预设过孔位置下方的区域内的有源层材料被保留，有源层位置处保留的有源层材料构成有源层23，而预设过孔位置下方的区域内的有源层材料构成第二垫高层52，并且，第二垫高层52与有源层23之间没有电性连接；以及
去除剩余的光刻胶。
在步骤D中，在有源层23上形成源极24和漏极25，漏极25的一部分形成在第二垫高层52上。
在步骤E中，至少在薄膜晶体管的漏极上方形成有机绝缘层30，以及在预设过孔位置处在该有机绝缘层中形成过孔50，该过孔贯穿绝缘层30以露出下方的薄膜晶体管的漏极25。
在步骤F中，在绝缘层30上形成像素电极41，其中，像素电极41与漏极25在过孔50处电性连接；
在一个示例中，该步骤F可以包括：
子步骤F1：沉积一层像素电极材料；
如前所述，像素电极41可以是ITO或IZO等透明导电材料的单层膜，或者为ITO或IZO等透明导电材料组成的复合膜，而该沉积像素电极层的方法一般为磁控溅射法；
子步骤F2：通过构图工艺保留过孔位置、预设像素电极位置和两者搭接位置处的像素电极材料，形成像素电极并实现其与薄膜晶体管20的漏极的电性连接。
由于在过孔50的下方增加了第一垫高层51和第二垫高层52，过孔的底部或下开口部被垫高，过孔的深度和坡度减小。一般情况下，栅极材料层的厚度约0.35μm，有源层材料层的厚度约0.2μm，故过孔深度可由2μm减小到1.45μm。因此，像素电极和过孔位置之间的导电材料与有机绝缘层的结合力较好，从而降低像素电极与漏极搭接时导电材料断裂的风险。
步骤F还可以包括子步骤F3：在像素电极41上依次形成钝化层42和公 共电极43。
本实施例中，通过第一垫高层51和第二垫高层52垫高过孔的底部或下开口部，减小过孔的深度和坡度，能有效降低连接像素电极与漏极的导电材料断裂的风险，也可以改善阵列基板平坦度，减轻Rubbing Mura。同时，在现有工艺流程的基础上，仅需更换两块掩模板-栅极掩模板(Gate Mask)和有源层掩模板(Active Mask)即可，不用更改其他的工艺流程，不会增加任何生产成本和工艺难度，更易于产业界所接受。
需要特别说明的是，本实施例中，除非特别描述或必须依序发生的步骤，步骤的顺序并无限制于以上所列且可根据需要变化或重新安排。
图5为根据本发明的第三实施例阵列基板的俯视图。为清楚表述本实施例起见，省略了像素电极上方的钝化层和公共电极。
请参照图5，该阵列基板包括：衬底基板，如玻璃基板；栅线1；形成于衬底基板上；以及数据线2，形成于衬底基板上，与栅线1大体垂直。其中，由栅线1和数据线2限定出若干个像素区域。每个像素区域包括第一实施例所述的、如图3所示的像素单元。
在该像素单元中，薄膜晶体管的栅极与所述栅线连接，所述薄膜晶体管的源极与所述数据线连接。
示例性地，在本实施例的阵列基板上，每行的多个像素单元的上方和下方均设置有栅线，每个像素单元的左侧和右侧均设置有数据线，且每相邻两行的像素单元之间仅设置有一条栅线，每相邻两列像素单元之间设置有一条数据线。与现有技术中普通的阵列基板相比，本实施例的阵列基板的不同之处在于，其像素单元为本发明第一实施例所述的像素单元。
可替换地，在本实施例的阵列基板上，每行的多个像素单元的上方和下方均设置有栅线，且每相邻两行所述像素单元之间设置有两条栅线；在每列像素单元的左侧或右侧设置有数据线，且每相邻两条数据线之间包括两列所述像素单元。此为在ADS显示模式基础上实现双栅结构的阵列基板，与现有技术中普通的阵列基板相比，其不同之处在于，其像素单元为本发明第一实施例所述的像素单元。
在第四实施例中，提供了一种显示装置。该显示装置包括：阵列基板；对向基板，与阵列基板对向设置；以及液晶层，填充于阵列基板和对向基板之间。其中，该阵列基板为第三实施例所述的阵列基板，该阵列基板和对向基板其中 之一上具有彩膜。
在第五实施例中，提供了一种阵列基板。该阵列基板与第三实施例阵列基板的区别在于，其是采用OLED技术的阵列基板。具体而言，在像素单元中，公共电极和像素电极之间不是由钝化层隔开，而是具有有机发光层。在公共电极和像素电极提供电压的情况下，该有机发光层可以发出预设色彩和灰度的光。
在第六实施例中，提供了一种显示装置。该显示装置包括：阵列基板，为第五实施例的阵列基板；以及盖板，固定于所述阵列基板的上方。
此外，上述对各元件和步骤的描述并不仅限于实施例中提到的各种具体结构、形状或方式，本领域普通技术人员可对其进行简单地更改或替换，例如：
(1)对于由SiNx材料制备的绝缘层同样应用于本发明；
(2)在阵列基板中，还可以采用玻璃基板之外的其他透明衬底基板；
(3)除了通过增加与栅极同时形成和第一垫高层和与有源层同时形成的第二垫高层之外，还可以在过孔的下方单独制备垫高层；
(4)本文可提供包含特定值的参数的示范，但这些参数无需确切等于相应的值，而是可在可接受的误差容限或设计约束内近似于相应值；
(5)实施例中提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向，并非用来限制本发明的保护范围。
综上所述，本发明在过孔的下方增加垫高层，例如由形成栅极和有源层中的至少一个的材料形成的垫高层(独立结构，不与薄膜晶体管的栅极和有源层连接)，垫高过孔底部高度，从而减小过孔的深度和坡度，能够有效降低像素电极与漏极搭接时断裂风险，改善阵列基板平坦度，减轻Rubbing Mura。本发明在有效提高产品品质的同时不会增加任何生产成本和工艺难度，具有较好的推广应用价值。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (19)

  1. 一种像素单元，其特征在于，包括：
    薄膜晶体管；
    绝缘层，至少形成于所述薄膜晶体管的漏极上，该绝缘层中形成有过孔，该过孔贯穿该绝缘层以露出下方的所述薄膜晶体管的漏极；
    像素电极，形成于所述绝缘层上，并与所述薄膜晶体管的漏极在所述过孔处电性连接；以及
    至少一个垫高层，形成于所述过孔的下方并位于所述漏极从所述过孔的露出部分的下方，使得所述露出部分的高度大于所述漏极的与该露出部分相邻的部分的高度。
  2. 根据权利要求1所述的像素单元，其特征在于，所述至少一个垫高层的材料与所述薄膜晶体管的栅极和有源层中的至少一个的材料相同。
  3. 根据权利要求1或2所述的像素单元，其特征在于，所述薄膜晶体管为底栅型场效应晶体管，包括：
    栅极；
    形成于所述栅极上的栅绝缘层；
    形成于所述栅绝缘层上的有源层；以及
    形成于所述有源层上的源极和漏极；并且
    所述至少一个垫高层包括：
    第一垫高层，所述第一垫高层由制备所述栅极的栅极材料形成且与所述栅极电绝缘设置；和/或
    第二垫高层，所述第二垫高层由制备所述有源层的有源层材料形成且与所述有源层电绝缘设置。
  4. 根据权利要求1所述的像素单元，其特征在于，所述至少一个垫高层在垂直于其厚度方向的平面内的投影区域的形状为以下形状中的一种：方形、圆形和椭圆形。
  5. 根据权利要求3所述的像素单元，其特征在于，所述至少一个垫高层包括所述第一垫高层和位于所述第一垫高层上方的所述第二垫高层，所述第一垫高层和第二垫高层的在垂直于其厚度方向的平面内的投影区域的形状相同，且所述第二垫高层的该投影区域的面积小于所述第一垫高层的该投影区域的 面积。
  6. 根据权利要求1所述的像素单元，其特征在于，所述过孔呈倒圆台形状，其径向尺寸沿过孔的深度方向逐渐减小；并且
    所述像素电极通过形成于过孔的侧壁上的导电材料电连接至薄膜晶体管的漏极，或者像素电极的一部分形成于过孔的侧壁上以与所述漏极的所述露出部分电连接。
  7. 根据权利要求1所述的像素单元，其特征在于，所述绝缘层为有机绝缘层或无机绝缘层。
  8. 一种像素单元的制备方法，其特征在于，该方法包括：
    在所述像素单元的预设过孔位置下方的区域内形成至少一个垫高层；
    制作薄膜晶体管的漏极，该漏极的一部分形成在所述至少一个垫高层上方，使得该部分的高度大于所述漏极的与该部分相邻的部分的高度；
    至少在所述薄膜晶体管的漏极上方形成所述绝缘层，并在该绝缘层中对应所述预设过孔位置处形成过孔，该过孔贯穿该绝缘层以露出下方的薄膜晶体管的漏极；以及
    在所述绝缘层上制作像素电极，使得该像素电极与薄膜晶体管的漏极在所述过孔处电性连接。
  9. 根据权利要求8所述的制备方法，其特征在于，由制备薄膜晶体管的栅极和有源层中的至少一个的材料层形成所述至少一个垫高层。
  10. 根据权利要求8或9所述的制备方法，其特征在于，形成至少一个垫高层的步骤包括：
    由制备薄膜晶体管的栅极的栅极材料与所述栅极同时地形成第一垫高层，该第一垫高层与所述栅极电绝缘；和/或
    由制备薄膜晶体管的有源层的有源层材料与所述有源层同时地形成第二垫高层，该第二垫高层与所述有源层电绝缘。
  11. 根据权利要求8-10中任一项所述的制备方法，其特征在于，该方法包括制作薄膜晶体管的步骤，并且制作薄膜晶体管的步骤和形成所述至少一个垫高层的步骤包括：
    步骤A：在衬底基板上形成栅极和第一垫高层；
    步骤B：在所述栅极和第一垫高层上形成栅极绝缘层；
    步骤C：在所述栅极绝缘层上形成有源层和第二垫高层，第二垫高层位于 第一垫高层的上方；以及
    步骤D：在所述有源层上形成薄膜晶体管的源极和漏极，漏极的一部分形成在第二垫高层上。
  12. 根据权利要求11所述的制备方法，所述步骤A包括：
    子步骤A1：在衬底基板上形成栅极材料层；以及
    子步骤A2：对所述栅极材料层进行构图工艺，以在预设栅极位置形成栅极，并在预设过孔位置下方的区域内形成第一垫高层。
  13. 根据权利要求12所述的制备方法，其特征在于，所述子步骤A2包括：
    在栅极材料层上形成光刻胶；
    对所述光刻胶进行曝光、显影，使预设栅极位置处和预设过孔位置正下方的区域内的光刻胶被保留；
    以保留的光刻胶为掩模，对栅极材料层进行刻蚀，使得预设栅极位置处和预设过孔位置下方的区域内的栅极材料被保留，其中，预设栅极位置处保留的栅极材料构成栅极，预设过孔位置下方的区域内保留的栅极材料构成第一垫高层；以及
    去除剩余的光刻胶。
  14. 根据权利要求11所述的制备方法，所述步骤C包括：
    子步骤C1：在栅极绝缘层上沉积有源层材料层；以及
    子步骤C2：对有源层材料层进行构图工艺，以在预设有源层位置形成有源层，并在预设过孔位置下方的区域内形成第二垫高层。
  15. 根据权利要求14所述的制备方法，其特征在于，所述子步骤C2包括：
    在有源层材料层上形成光刻胶；
    对所述光刻胶进行曝光、显影，使预设有源层位置处和预设过孔位置下方的区域内的光刻胶被保留；
    以保留的光刻胶为掩模，对有源层材料层进行刻蚀，使得预设有源层位置处和预设过孔位置下方的区域内的有源层材料被保留，预设有源层位置处保留的有源层材料构成有源层，而预设过孔位置下方的区域内保留的有源层材料构成第二垫高层；以及
    去除剩余的光刻胶。
  16. 一种阵列基板，其特征在于，包括：
    衬底基板；
    栅线，形成于所述衬底基板上；以及
    数据线，形成于所述衬底基板上，与所述栅线大体垂直；
    其中，由所述栅线和数据线之间限定出若干个像素区域，每个像素区域至少包含权利要求1至7中任一项所述的像素单元。
  17. 一种显示装置，其特征在于，包括权利要求16所述的阵列基板。
  18. 根据权利要求17所述的显示装置，其特征在于，该显示装置还包括：
    对向基板，与所述阵列基板对向设置；以及
    液晶层，填充于所述阵列基板和对向基板之间；并且
    所述像素单元还包括设置在所述像素电极上方的公共电极，所述公共电极和像素电极之间由钝化层隔开。
  19. 根据权利要求17所述的显示装置，其特征在于，该显示装置还包括盖设于所述阵列基板的上方的盖板；并且
    所述像素单元还包括：
    公共电极，形成在所述像素电极的上且位于所述盖板和所述像素电极之间；和
    位于像素电极和公共电极之间的有机发光层。
PCT/CN2015/088509 2015-04-13 2015-08-31 像素单元及其制备方法、阵列基板和显示装置 WO2016165264A1 (zh)

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