WO2016165256A1 - 阵列基板及其制造方法和显示装置 - Google Patents

阵列基板及其制造方法和显示装置 Download PDF

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Publication number
WO2016165256A1
WO2016165256A1 PCT/CN2015/087633 CN2015087633W WO2016165256A1 WO 2016165256 A1 WO2016165256 A1 WO 2016165256A1 CN 2015087633 W CN2015087633 W CN 2015087633W WO 2016165256 A1 WO2016165256 A1 WO 2016165256A1
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Prior art keywords
layer
transparent electrode
active layer
conductive transition
pattern including
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PCT/CN2015/087633
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English (en)
French (fr)
Inventor
刘正
白金超
张治超
张小祥
刘明悬
郭总杰
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US14/913,123 priority Critical patent/US20160307930A1/en
Publication of WO2016165256A1 publication Critical patent/WO2016165256A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned

Definitions

  • the present invention relates to the field of manufacturing a display device, and in particular to an array substrate, a method of fabricating the array substrate, and a display device including the array substrate.
  • Shown in Figure 1 is a partial cross-sectional view of an array substrate of the prior art.
  • the array substrate includes a thin film transistor, a first transparent electrode 200 and a second transparent electrode 300.
  • the first transparent electrode 200 is a pixel electrode that overlaps the drain 520 of the thin film transistor.
  • the first transparent electrode 200 In order to ensure the transparency of the array substrate, the first transparent electrode 200 generally has a small thickness (generally ). Due to the large thickness of the drain 520 of the thin film transistor The height of the step formed on the first transparent electrode 200 lapped thereon (i.e., the difference in height of the lower surface of the first transparent electrode 200 at different horizontal planes) is large. In this case, in the process of depositing the thin first transparent electrode 200 on the drain 520, the first transparent electrode 200 is liable to be broken, resulting in an open circuit, thereby reducing product yield.
  • An object of the present invention is to provide an array substrate and a manufacturer of the array substrate And a display device including the array substrate.
  • the first transparent electrode is less likely to be broken.
  • an array substrate is provided, the array substrate being divided into a plurality of pixel units, each of which is provided with a first transparent electrode and a thin film And a thin film transistor including a drain, wherein a drain of the thin film transistor is disposed on the first transparent electrode and electrically connected to the first transparent electrode.
  • the thin film transistor further includes an active layer disposed under the first transparent electrode.
  • the thin film transistor further includes a conductive transition layer disposed between the active layer and the first transparent electrode, the conductive transition layer being on the active layer a surface is conformally formed, and a position of the conductive transition layer corresponds to a position of a drain of the thin film transistor, and one end of the first transparent electrode overlaps over the conductive transition layer such that the first An ohmic contact is formed between the transparent electrode and the conductive transition layer and between the active layer and the conductive transition layer.
  • the thin film transistor further includes a source and an additional conductive filter layer disposed between the active layer and the source, the additional conductive transition layer being conformally formed on a surface of the active layer And the position of the additional conductive filter layer corresponds to the position of the source of the thin film transistor.
  • each of the pixel units further includes an additional transparent electrode disposed between the additional conductive transition layer and the source, the additional transparent electrode being conformally formed on a lower surface of the source.
  • the conductive transition layer has a thickness smaller than a thickness of the drain.
  • the material of the conductive transition layer is the same as the material of the drain.
  • a method of fabricating an array substrate the array substrate is divided into a plurality of pixel units, and each of the plurality of pixel units is provided with a first transparent electrode and a thin film transistor
  • the thin film transistor includes a drain, wherein the manufacturing method includes the steps of: forming a pattern including the first transparent electrode; and forming a pattern including the drain on the pattern including the first transparent electrode.
  • the thin film transistor further includes an active layer
  • the manufacturing method further comprising: before the step of forming a pattern including the first transparent electrode, A pattern including an active layer is formed, and the pattern including the first transparent electrode is over the pattern including the active layer.
  • the manufacturing method further includes: after the step of forming a pattern including an active layer, and in the Before the step of forming a pattern including the first transparent electrode, a pattern including a conductive transition layer formed conformally on the surface of the active layer is formed.
  • one end of the first transparent electrode is overlapped on the conductive transition layer such that the first transparent electrode and the conductive transition layer An ohmic contact is formed between the active layer and the conductive transition layer.
  • the thickness of the conductive transition layer is smaller than the thickness of the drain.
  • the material of the conductive transition layer is the same as the material of the drain.
  • the thin film transistor further includes a source, and the step of forming a pattern including the active layer, the forming the pattern including the conductive transition layer
  • the step of forming the pattern including the first transparent electrode and the step of forming the pattern including the drain specifically include:
  • the pattern includes a channel hole corresponding to a spacing region between a source and a drain of the thin film transistor, and each of the pixel units is formed with one of the first mask patterns, and the first mask pattern is covered
  • the shape of the region coincides with the shape of the source of the thin film transistor and the upper surface of the first transparent electrode;
  • the second mask pattern layer including a plurality of second mask patterns respectively corresponding to the respective pixel units, each of the Forming, in the pixel unit, a second mask pattern, wherein a shape of a region covered by the second mask pattern is consistent with a shape of a source and a drain upper surface;
  • a pattern including a source and a drain is formed by etching, and an initial conductive transition layer material on the active layer in the channel hole is removed by etching.
  • the step of sequentially forming the pattern including the initial active layer and the pattern including the initial conductive transition layer specifically includes:
  • the semiconductor material layer and the first metal material layer are patterned to obtain a pattern including an initial active layer and a pattern including an initial conductive transition layer.
  • the manufacturing method further includes the steps of: etching a portion of the active layer corresponding to the channel hole after forming a pattern including a drain, so as to correspond to the active layer
  • the thickness of the portion of the channel hole is smaller than the thickness of other portions of the active layer.
  • a display device comprising an array substrate, wherein the array substrate is the above array substrate provided by the present invention.
  • the step height formed on the first transparent electrode is smaller than in the prior art, thereby In the process of forming the first transparent electrode by deposition, the first transparent electrode is less likely to be broken, and the product yield is improved.
  • FIG. 1 is a partial cross-sectional view of an array substrate in the prior art
  • FIG. 2 is a partial cross-sectional view of an array substrate in accordance with an embodiment of the present invention.
  • FIG. 3 illustrates a structure after a gate electrode, an initial active layer, and an initial conductive transition layer are formed on a transparent substrate in accordance with an embodiment of the present invention
  • FIG. 4 illustrates a structure after a method of manufacturing a transparent electrode material layer and a metal material layer on the structure shown in FIG. 3 according to an embodiment of the present invention
  • FIG. 5 illustrates a structure after a manufacturing method according to an embodiment of the present invention forms a first mask pattern on the structure illustrated in FIG. 4;
  • FIG. 6 illustrates a manufacturing method in which a transparent electrode material layer and a second metal material layer are removed by etching in addition to a region covered by a first mask pattern, in accordance with an embodiment of the present invention. Structure after the material;
  • FIG. 7 illustrates a structure in which a manufacturing method according to an embodiment of the present invention forms a second mask pattern on the structure illustrated in FIG. 6;
  • FIG. 8 shows a structure after a manufacturing method according to an embodiment of the present invention forms a pattern including a drain on the structure shown in FIG.
  • the term “upper” refers to the “upper” side as indicated in FIGS. 2 through 8.
  • the term “conformal” is used to describe a positional relationship in which a first layer is formed on the surface of the second layer, and The shape of the first layer is the same as the shape of the portion of the surface of the second layer in contact therewith, regardless of the tolerances of the manufacturing process.
  • an array substrate is provided, the array substrate is divided into a plurality of pixel units, and each of the plurality of pixel units is provided with a first transparent electrode 200.
  • a thin film transistor including a drain 520 disposed on the first transparent electrode 200 and electrically connected to the first transparent electrode 200.
  • the thin film transistor includes a structure such as a gate 600, a source 520a, a drain 520, and an active layer 400.
  • the arrangement of these structures is well known to those skilled in the art, and thus the present invention is not It is described in detail.
  • the drain electrode 520 of the thin film transistor is generally made of an opaque metal material, it cannot be disposed in the open area of the array substrate so as not to affect the aperture ratio.
  • the step height formed on the first transparent electrode 200 is smaller than that of the prior art, thereby forming a During the process of a transparent electrode 200, the first transparent electrode 200 does not break, thereby improving product yield.
  • a second transparent electrode 300 is further disposed in each of the plurality of pixel units. It is easily understood that the first transparent electrode 200, the second transparent electrode 300, and the thin film transistor are all disposed on the transparent substrate 100.
  • one end of the first transparent electrode 200 is overlapped over the active layer 400.
  • the active layer 400 starts to conduct, and a gray scale signal input from the source 520a of the thin film transistor can be transmitted to the first transparent electrode through the active layer 400. 200 and a drain 520 electrically connected to the first transparent electrode 200.
  • the specific material of the active layer is not limited.
  • the active layer 400 may be made of an oxide or a polysilicon.
  • the active layer 400 is made of an oxide, in order to prevent the active layer from being destroyed when the first transparent electrode is formed, it is necessary to form an etch stop layer on the active layer 400 before the first transparent electrode 200 is formed.
  • the active layer 400 is made of polysilicon, since the active layer is not destroyed when the first transparent electrode is formed, it is not necessary to form an etch on the active layer. Barrier layer.
  • the active layer 400 is made of polysilicon as an example for detailed description.
  • the transparent electrode is made of ITO (i.e., indium tin oxide), and when the polycrystalline silicon is in direct contact with the ITO, a Schottky contact is formed therebetween, and the contact resistance is large.
  • the conductive transition layer 510 may be optionally disposed between the active layer 400 made of polysilicon and the first transparent electrode 200 made of ITO.
  • the material of the conductive transition layer 510 may be any material capable of satisfying the following conditions, that is, forming an ohm between the active layer and the conductive transition layer and between the first transparent electrode and the conductive transition layer. contact.
  • the thin film transistor further includes a conductive transition layer 510 disposed between the active layer 400 and the first transparent electrode 200, and the conductive transition layer 510 is at the active layer 400
  • the surface is conformally formed and its position corresponds to the position of the drain 520 of the thin film transistor, and one end of the first transparent electrode 200 is overlapped over the conductive transition layer 510.
  • a metal layer is first formed on the active layer 400, and then a metal layer corresponding to the spacer region between the source and the drain is removed by etching, thereby Forming two separate metal layers that are independent of one another.
  • the portion of the metal layer corresponding to the position of the drain 520 of the thin film transistor is the conductive transition layer 510, and the portion of the metal layer corresponding to the position of the source 520a of the thin film transistor is the additional conductive transition layer 510a.
  • the additional transparent electrode 510a is conformally formed on the lower surface of the source 520a.
  • An advantage of forming the additional conductive transition layer 510a is that a material layer for forming the active layer 400 and a material layer for forming the conductive transition layer 510 may be continuously formed in the fabrication of the array substrate, and then formed using the same mask process.
  • the initial active layer B and the initial conductive transition layer A (as shown in FIG. 3), and then the transparent electrode material layer C and the metal material layer are sequentially formed on the transparent substrate 100 on which the initial active layer B and the initial conductive transition layer A are formed.
  • D (as shown in FIG. 4), the initial conductive transition layer A is further formed into an additional conductive transition layer 510a and a conductive transition layer 510 by forming the channel hole E1.
  • the additional conductive may not be retained.
  • the layer 510a is crossed (i.e., only the portion of the metal layer corresponding to the position of the drain 520 of the thin film transistor is left, and the other portions of the metal layer are completely etched away).
  • a masking and etching process is further performed, and the metal layer corresponding to the position except the drain 520 of the thin film transistor is removed by etching.
  • the conductive transition layer 510 can be formed.
  • a masking and etching process is added as compared to the solution of retaining the additional conductive transition layer 510a described above. It can be seen that retaining the additional conductive transition layer 510a can simplify the steps of fabricating the array substrate.
  • the transparent electrode material layer corresponding to the position other than the first transparent electrode 200 may be removed by etching, so that only the first transparent electrode 200 located under the drain 520 is formed;
  • a transparent electrode material layer corresponding to a position below the source 520a may also be left, thereby simultaneously forming a first transparent electrode 200 under the drain 520 and an additional transparent electrode 200a under the source 520a to save a mask and etch. Process.
  • the additional transparent electrode 200a is left, it is necessary to simultaneously retain the additional conductive transition layer 510a to ensure that the signal input through the source 520a can be transferred to the active layer 400.
  • both the additional conductive transition layer 510a and the additional transparent electrode 200a remain in the thin film transistor, so that the step of manufacturing the array substrate can be simplified.
  • the thickness of the optional conductive transition layer 510 is smaller than the thickness of the drain 520. Since the thickness of the conductive transition layer 510 is small, the step height (ie, the step height) of the first transparent electrode 200 when the first transparent electrode 200 is formed can be reduced.
  • the optional material of the conductive transition layer 510 is the same as the material of the drain 520.
  • the conductive transition layer 510 is also made of metallic aluminum.
  • the material of the conductive transition layer 510 may also be different from the material of the drain 520.
  • the drain may include a three-layer metal structure of MoAlMo (molybdenum aluminum molybdenum).
  • the array substrate according to the embodiment of the present invention may further include a second transparent electrode 300 located at the gate layer (including the gate line, the common electrode line, the gate, etc.) and A gate insulating layer 700 between the source layers, and a passivation layer 800 over the active layer.
  • the second transparent electrode 300 is formed on the passivation layer 800, and the second transparent electrode 300 may be a comb electrode electrically connected through a common electrode line in the via hole and the gate layer.
  • the first transparent electrode 200 is a bulk electrode.
  • a method for manufacturing the above array substrate is provided, wherein the array substrate is divided into a plurality of pixel units, and each of the plurality of pixel units is provided with a first A transparent electrode and a thin film transistor, wherein the manufacturing method includes the steps of: forming a pattern including a first transparent electrode; and forming a pattern including a drain on the pattern including the first transparent electrode.
  • the first transparent electrode since the first transparent electrode is located below the drain, the first transparent electrode has a smaller step height when forming the first transparent electrode than the prior art, so the first transparent electrode It is not easy to break.
  • a second transparent electrode is further disposed in each of the plurality of pixel units, and the thin film transistor includes an active layer, a gate, a source, and a drain.
  • the manufacturing method according to an embodiment of the present invention further includes the step of forming a pattern including an active layer before the patterning including the first transparent electrode is formed.
  • a pattern including the first transparent electrode is formed over the pattern including the active layer, that is, the pattern including the first transparent electrode is over the pattern including the active layer.
  • the pattern including the active layer includes a plurality of active layers respectively corresponding to the thin film transistors of the respective pixel units.
  • the pattern including the drain includes a drain of each thin film transistor, and further includes a source of each thin film transistor, a plurality of data lines, and the like.
  • the material for forming the active layer is not limited.
  • the active layer may be made of an oxide or may be made of polysilicon.
  • the active layer when the active layer is made of an oxide, before the formation of the first transparent electrode, in order to prevent the active layer from being destroyed when the first transparent electrode is formed, it is required to be on the active layer.
  • Forming an etch barrier layer when the active layer is made of polysilicon, since the active layer is not destroyed when the first transparent electrode is formed, it is not necessary
  • An etch stop layer is formed on the active layer.
  • the manufacturing method when the active layer is made of polysilicon, since the transparent electrode is usually made of ITO, if the polysilicon is in direct contact with the ITO, a Schottky contact is formed between the two.
  • the resistance is large, and in order to reduce the contact resistance between the polysilicon and the ITO, the manufacturing method further includes the following steps: after forming the pattern including the active layer, and before forming the pattern including the first transparent electrode Forming a pattern including a conductive transition layer conformally formed on a surface of the active layer and having a position corresponding to a position of the drain. In this case, one end of the first transparent electrode is overlapped on the conductive transition layer such that the first transparent electrode and the conductive transition layer and the active layer and the conductive transition An ohmic contact is formed between the layers.
  • the material of the conductive transition layer may be any material capable of satisfying the following requirements, that is, between the first transparent electrode and the conductive transition layer and between the active layer and the conductive transition layer An ohmic contact is formed.
  • the thickness of the conductive transition layer is smaller than the thickness of the drain to reduce the step height of the first transparent electrode.
  • the material of the conductive transition layer is the same as the material of the source and the drain to simplify the manufacturing method of the array substrate.
  • the specific manner of forming the respective graphic layers is not limited. Generally, it can be formed by a photolithographic patterning process.
  • the step of forming a pattern including an active layer, the step of forming a pattern including a conductive transition layer, and the forming the pattern including the first transparent electrode may be selected
  • the step of forming the pattern including the drain specifically includes:
  • the edge contour of the initial active layer B corresponding to the outline of the active layer, the edge of the initial conductive transition layer A
  • the edges of the initial active layer B are aligned, and the initial conductive transition layer A is stacked on the initial active layer B (as shown in FIG. 3), wherein the pattern including the initial active layer B includes Corresponding to a plurality of initial active layers B of thin film transistors of respective pixel units, respectively, including initial conduction
  • the pattern of the transition layer A includes a plurality of initial conductive transition layers A respectively corresponding to the thin film transistors of the respective pixel units;
  • the first mask pattern layer including a plurality of first mask patterns E respectively corresponding to the respective pixel units, in other words, each pixel unit A first mask pattern E (shown in FIG. 5) is formed therein, and the first mask pattern E includes a channel hole E1 corresponding to a spacing region between a source and a drain of the thin film transistor, And the shape of the region covered by the first mask pattern E is consistent with the shape of the source of the thin film transistor and the upper surface of the first transparent electrode;
  • the second mask pattern layer including a plurality of second mask patterns F respectively corresponding to the respective pixel units, in other words, each A second mask pattern F (shown in FIG. 7) is formed in the pixel unit, and a shape of a region covered by the second mask pattern F and a source and a drain of the thin film transistor are formed.
  • the shape of the upper surface is the same;
  • a pattern including a drain is formed by etching, and an initial conductive transition layer A (shown in FIG. 8) on the active layer 400 in the channel hole E1 is removed by etching.
  • the etching can prevent the conductive material from remaining on the surface of the active layer 400, thereby ensuring the normal conduction and normal shutdown performance of the thin film transistor, and is advantageous for improving the yield of the display panel.
  • the second mask pattern F can protect the material of the region covered by the second mask pattern F from being etched, and the unetched metal material layer is formed as the source and drain of the thin film transistor. pole.
  • the “the source of the thin film transistor and the shape of the upper surface of the first transparent electrode” as used herein means the combined shape of the upper surface of the source of the thin film transistor and the upper surface of the first transparent electrode.
  • the shape of the source and drain upper surfaces means a combined shape of the upper surface of the source and the upper surface of the drain.
  • the initial conductive transition layer A at the position on the active layer and corresponding to the source is not removed by etching before the source and the drain are formed by the etching process, thereby reducing one mask.
  • the film and the etching process simplify the manufacturing method of the array substrate and reduce the production cost.
  • the manufacturing method further includes the steps of: etching a portion of the active layer corresponding to the channel hole E1 after forming a pattern including a drain, such that the active layer The thickness corresponding to the channel hole portion is smaller than the thickness of other portions of the active layer.
  • the above steps may all be completed by dry etching.
  • the second metal material layer D may include a plurality of sub-metal layers stacked in a stack, and the composition of the adjacent two-layer sub-metal layers may be different.
  • the second metal layer may be a three-layer metal structure of AlMoAl (aluminum molybdenum aluminum).
  • the step of sequentially forming the pattern including the initial active layer B and the pattern including the initial conductive transition layer A may specifically include:
  • the semiconductor material layer and the first metal material layer are patterned to obtain a pattern including the initial active layer B and a pattern including the initial conductive transition layer A (as shown in FIG. 3).
  • the composition of the first metal material layer and the composition of the second metal material layer D may be the same to simplify the manufacturing method of the array substrate.
  • the composition of the first metal material layer and the composition of the second metal material layer may also be different.
  • the manufacturing method according to an embodiment of the present invention may further include the steps of sequentially forming a pattern including a gate electrode 600 and a gate insulating layer, and a gate insulating layer before forming a pattern including the active layer.
  • a pattern including the gate includes a gate of each thin film transistor, and further includes a gate line and a common electrode line.
  • the manufacturing method according to an embodiment of the present invention may further include the steps of sequentially forming a passivation layer and a pattern including the second transparent electrode after forming the pattern including the drain, and including the second The pattern of transparent electrodes is on the passivation layer.
  • the passivation layer covers the pattern including the drain
  • the second transparent electrode is a comb electrode connected to the common electrode line through the via hole.
  • a display device comprising an array substrate, wherein the array substrate is the above array substrate provided by the present invention.
  • the display device may be a liquid crystal display device, and the display device further includes a pair of cassette substrates disposed on the array substrate.
  • the color film layer can be disposed on the counter substrate to achieve color display.
  • the display device may be a display, a notebook computer, a navigator, a mobile phone, a tablet computer, or the like.

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Abstract

一种阵列基板及其制造方法，以及一种显示装置，所述阵列基板被划分为多个像素单元，所述多个像素单元中的每一个内均设置有第一透明电极（200）和薄膜晶体管，所述薄膜晶体管包括漏极（520），所述薄膜晶体管的漏极（520）设置在所述第一透明电极（200）上，并与所述第一透明电极（200）电连接。由于第一透明电极（200）设置在漏极（520）的下方，因此，相比于现有技术，第一透明电极（200）上形成的台阶高度较小，从而在形成第一透明电极（200）的过程中，第一透明电极（200）不会产生断裂。

Description

阵列基板及其制造方法和显示装置
相关申请的交叉引用
本申请要求在2015年4月16日向中国国家知识产权局提交的申请号为201510181256.1的优先权，该申请全部内容以引用方式并入本文中。
技术领域
本发明涉及显示装置的制造领域，具体地，涉及一种阵列基板、该阵列基板的制造方法和一种包括所述阵列基板的显示装置。
背景技术
图1中所示的是现有技术的一种阵列基板的局部剖视图。如图1所示，所述阵列基板包括薄膜晶体管、第一透明电极200和第二透明电极300，第一透明电极200为像素电极，其搭接在薄膜晶体管的漏极520上。
为了保证阵列基板的透明度，第一透明电极200通常具有较小的厚度(一般为
Figure PCTCN2015087633-appb-000001
)。由于薄膜晶体管的漏极520的厚度较大
Figure PCTCN2015087633-appb-000002
导致搭接在其上的第一透明电极200上形成的台阶高度(即，第一透明电极200的处于不同水平面的下表面的高度差)较大。这种情况下，在漏极520上沉积形成较薄的第一透明电极200的过程中，第一透明电极200上容易产生断裂、导致断路，从而降低产品良率。
因此，如何避免第一透明电极产生断裂成为本领域亟待解决的技术问题。
发明内容
本发明的目的在于提供一种阵列基板、该阵列基板的制造方 法和一种包括所述阵列基板的显示装置。在所述阵列基板中，第一透明电极不容易产生断裂。
为了实现上述目的，作为本发明的一个方面，提供一种阵列基板，所述阵列基板被划分为多个像素单元，所述多个像素单元中的每一个内均设置有第一透明电极和薄膜晶体管，所述薄膜晶体管包括漏极，其中，所述薄膜晶体管的漏极设置在所述第一透明电极上，并与所述第一透明电极电连接。
可选地，所述薄膜晶体管还包括设置在所述第一透明电极下方的有源层。当所述有源层由多晶硅制成时，所述薄膜晶体管还包括设置在所述有源层与所述第一透明电极之间的导电过渡层，所述导电过渡层在所述有源层表面共形地形成，且所述导电过渡层的位置对应于所述薄膜晶体管的漏极的位置，所述第一透明电极的一端搭接在所述导电过渡层上方，以使得所述第一透明电极与所述导电过渡层之间以及所述有源层和所述导电过渡层之间均形成欧姆接触。
可选地，所述薄膜晶体管还包括源极和设置在所述有源层与所述源极之间的附加导电过滤层，所述附加导电过渡层在所述有源层表面共形地形成，且所述附加导电过滤层的位置对应于所述薄膜晶体管的源极的位置。
可选地，每个像素单元还包括设置在所述附加导电过渡层与所述源极之间的附加透明电极，所述附加透明电极在所述源极的下表面共形地形成。
可选地，所述导电过渡层的厚度小于所述漏极的厚度。
可选地，所述导电过渡层的材料与所述漏极的材料相同。
作为本发明的另一个方面，提供一种阵列基板的制造方法，所述阵列基板被划分为多个像素单元，所述多个像素单元中的每一个内均设置有第一透明电极和薄膜晶体管，所述薄膜晶体管包括漏极，其中，所述制造方法包括步骤：形成包括第一透明电极的图形；以及在所述包括第一透明电极的图形上形成包括漏极的图形。
可选地，在根据本发明实施例的阵列基板的制造方法中，所述薄膜晶体管还包括有源层，所述制造方法还包括：在所述形成包括第一透明电极的图形的步骤之前，形成包括有源层的图形，并且所述包括第一透明电极的图形位于所述包括有源层的图形上方。
在根据本发明实施例的阵列基板的制造方法中，当所述有源层由多晶硅制成时，所述制造方法还包括：在所述形成包括有源层的图形的步骤之后，并且在所述形成包括第一透明电极的图形的步骤之前，形成包括导电过渡层的图形，所述导电过渡层在有源层表面共形地形成。
其中，在所述形成包括第一透明电极的图形的步骤中，所述第一透明电极的一端搭接在所述导电过渡层上，以使得所述第一透明电极与所述导电过渡层之间以及所述有源层和所述导电过渡层之间均形成欧姆接触。
可选地，在根据本发明实施例的阵列基板的制造方法中，所述导电过渡层的厚度小于所述漏极的厚度。
可选地，在根据本发明实施例的阵列基板的制造方法中，所述导电过渡层的材料与所述漏极的材料相同。
可选地，在根据本发明实施例的阵列基板的制造方法中，所述薄膜晶体管还包括源极，并且所述形成包括有源层的图形的步骤、所述形成包括导电过渡层的图形的步骤、所述形成包括第一透明电极的图形的步骤和所述形成包括漏极的图形的步骤具体包括：
依次形成包括初始有源层的图形和包括初始导电过渡层的图形，所述初始有源层的边缘轮廓对应于所述有源层的轮廓，所述初始导电过渡层的边缘与所述初始有源层的边缘对齐，且所述初始导电过渡层层叠在所述初始有源层上；
依次形成透明电极材料层和第二金属材料层，且所述第二金属材料层位于所述透明电极材料层上；
在所述第二金属材料层上方形成光刻胶层；
对所述光刻胶层进行曝光显影，以形成第一掩膜图形层，所述第一掩膜图形层包括分别对应于各个像素单元的多个第一掩膜图形，所述第一掩膜图形包括对应于所述薄膜晶体管的源极和漏极之间的间隔区域的沟道孔，每个像素单元内均形成有一个所述第一掩膜图形，所述第一掩膜图形所覆盖的区域的形状与所述薄膜晶体管的源极和第一透明电极的上表面的形状一致；
通过刻蚀去除所述透明电极材料层和所述第二金属材料层上除所述第一掩膜图形所覆盖的区域之外的材料；
对所述第一掩膜图形层进行灰化处理，以获得第二掩膜图形层，所述第二掩膜图形层包括分别对应于各个像素单元的多个第二掩膜图形，每个所述像素单元内均形成有一个所述第二掩膜图形，所述第二掩膜图形所覆盖的区域的形状与源极和漏极上表面的形状一致；
通过刻蚀形成包括源极和漏极的图形，并通过刻蚀去除所述沟道孔中的位于有源层上的初始导电过渡层材料。
可选地，依次形成包括初始有源层的图形和包括初始导电过渡层的图形的步骤具体包括：
依次形成半导体材料层和第一金属材料层，且所述第一金属材料层位于所述半导体材料层上；
对所述半导体材料层和所述第一金属材料层进行构图，以获得包括初始有源层的图形和包括初始导电过渡层的图形。
可选地，所述制造方法还包括步骤：在形成包括漏极的图形之后，对所述有源层上对应于所述沟道孔的部分进行刻蚀，以使得所述有源层上对应于所述沟道孔的部分的厚度小于所述有源层上其他部分的厚度。
作为本发明的另一个方面，提供一种显示装置，所述显示装置包括阵列基板，其中，所述阵列基板为本发明所提供的上述阵列基板。
在本发明中，由于第一透明电极设置在漏极的下方，因此，相比于现有技术，第一透明电极上形成的台阶高度较小，从而在 通过沉积形成第一透明电极的过程中，第一透明电极不易产生断裂，提高了产品良率。
附图说明
附图用于提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并非旨在限定本发明。在附图中：
图1是现有技术中的阵列基板的局部剖视图；
图2是根据本发明实施例的阵列基板的局部剖视图；
图3示出了根据本发明实施例的制造方法，在透明基板上形成栅极、初始有源层和初始导电过渡层之后的结构；
图4示出了根据本发明实施例的制造方法在图3中所示的结构上形成透明电极材料层和金属材料层之后的结构；
图5示出了根据本发明实施例的制造方法在图4中所示的结构上形成第一掩膜图形之后的结构；
图6示出了根据本发明实施例的制造方法，在图5中所示的结构上通过刻蚀去除透明电极材料层和第二金属材料层上除第一掩膜图形所覆盖的区域之外的材料后的结构；
图7示出了根据本发明实施例的制造方法在图6中所示的结构上形成第二掩膜图形至后的结构；以及
图8示出了根据本发明实施例的制造方法在图7中所示的结构上形成包括了漏极的图形之后的结构。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
应当理解的是，在本发明实施例中，术语“上”是指图2至图8中所指向的“上”方。在本发明实施例中，术语“共形”用于描述这样一种位置关系：第一层形成在第二层的表面上，并且 在不考虑制造工艺的公差的情况下，第一层的形状和与其接触的第二层的表面的那部分的形状相同。
如图2所示，作为本发明的一个方面，提供一种阵列基板，所述阵列基板被划分为多个像素单元，所述多个像素单元中的每一个内均设置有第一透明电极200和薄膜晶体管，所述薄膜晶体管包括漏极520，其设置在第一透明电极200上，并与第一透明电极200电连接。
本领域技术人员应当理解的是，薄膜晶体管包括栅极600、源极520a、漏极520和有源层400等结构，这些结构的设置是本领域人员所公知的，故本发明中并未对其进行详细描述。应当注意的是，由于薄膜晶体管的漏极520一般采用不透明的金属材料制成，因此不能够设置在阵列基板的开口区中，以免影响开口率。
在本发明的实施例中，由于第一透明电极200设置在漏极520的下方，因此，相比于现有技术，第一透明电极200上形成的台阶高度较小，从而在通过沉积形成第一透明电极200的过程中，第一透明电极200不会产生断裂，由此提高了产品良率。
在本发明实施例中，所述多个像素单元中的每一个内还设置有第二透明电极300。容易理解的是，第一透明电极200、第二透明电极300和薄膜晶体管均设置在透明基板100上。
根据本发明的实施例，第一透明电极200的一端搭接在有源层400上方。当向所述薄膜晶体管的栅极600提供开启电压时，有源层400开始导电，并且，从所述薄膜晶体管的源极520a输入的灰阶信号能够通过有源层400传递给第一透明电极200以及和第一透明电极200电连接的漏极520。
在本发明实施例中，对有源层的具体材料并不做限定，例如，有源层400可以由氧化物制成，也可以由多晶硅制成。
当有源层400由氧化物制成时，在形成第一透明电极200之前，为防止在形成第一透明电极时破坏有源层，需要在有源层400上形成刻蚀阻挡层。当有源层400由多晶硅制成时，由于在形成第一透明电极时不会破坏有源层，因此无需在有源层上形成刻蚀 阻挡层。
本发明实施例中，以有源层400由多晶硅制成为例进行详细描述。通常，透明电极由ITO(即，氧化铟锡)制成，当多晶硅与ITO直接接触时，在二者之间形成肖基特接触，其接触电阻较大。可选地，为了减小多晶硅与ITO之间的接触电阻，可选可以在采用多晶硅制成的有源层400和采用ITO制成的第一透明电极200之间设置导电过渡层510。在本发明实施例中，导电过渡层510的材料可以是能够满足以下条件的任何材料，即，在有源层和导电过渡层之间以及在第一透明电极和导电过渡层之间均形成欧姆接触。
具体地，当有源层400由多晶硅制成时，所述薄膜晶体管还包括设置在有源层400与第一透明电极200之间的导电过渡层510，导电过渡层510在有源层400的表面共形地形成，且其位置对应于所述薄膜晶体管的漏极520的位置，第一透明电极200的一端搭接在导电过渡层510上方。
在本发明实施例中，为了形成导电过渡层510，需要先在有源层400上形成一层金属层，然后通过刻蚀去除对应于源极和漏极之间的间隔区域的金属层，从而形成彼此独立的两部分金属层。其中，对应于薄膜晶体管的漏极520的位置的那部分金属层为导电过渡层510，对应于薄膜晶体管的源极520a的位置的那部分金属层为附加导电过渡层510a。换言之，附加透明电极510a在所述源极520a的下表面共形地形成。形成附加导电过渡层510a的优点在于，在制造阵列基板时，可以连续地形成用于形成有源层400的材料层和用于形成导电过渡层510的材料层，然后利用同一道掩膜工艺形成初始有源层B和初始导电过渡层A(如图3所示)，然后在形成有初始有源层B和初始导电过渡层A的透明基板100上依次形成透明电极材料层C和金属材料层D(如图4所示)，再通过形成沟道孔E1的方式使初始导电过渡层A形成附加导电过渡层510a和导电过渡层510。
当然，在形成导电过渡层510时，也可以不保留附加导电过 渡层510a(即，仅保留对应于所述薄膜晶体管的漏极520的位置的那部分金属层，而将其他部分的金属层全部刻蚀掉)。这种情况下，在形成了初始导电过渡层A之后，还要再进行一道掩膜、刻蚀工艺，通过刻蚀去除对应于除所述薄膜晶体管的漏极520的位置之外的金属层，才能形成导电过渡层510。与上文中所述的保留附加导电过渡层510a的方案相比，多了一道掩膜、刻蚀工艺。由此可知，保留附加导电过渡层510a可以简化制造阵列基板的步骤。
相应地，在形成第一透明电极200时，可以通过刻蚀去除对应于除第一透明电极200的位置之外的透明电极材料层，从而只形成位于漏极520下方的第一透明电极200；也可以保留对应于源极520a下方位置的透明电极材料层，从而同时形成位于漏极520下方的第一透明电极200和位于源极520a下方的附加透明电极200a，以节省一道掩膜、刻蚀工艺。需要指出的是，如果保留了附加透明电极200a，则需要同时保留附加导电过渡层510a，以确保通过源极520a输入的信号能够传递至有源层400。可选地，所述薄膜晶体管中保留有附加导电过渡层510a和附加透明电极200a这两者，从而可以简化制造阵列基板的步骤。
可选地，为了进一步地确保第一透明电极200不会产生断裂，可选导电过渡层510的厚度小于漏极520的厚度。由于导电过渡层510厚度较小，因此，可以减小形成第一透明电极200时第一透明电极200的阶跃高度(即，台阶高度)。
可选地，为了简化阵列基板的制造方法，导电过渡层510的可选材料与所漏极520的材料相同。例如，当漏极520由金属铝制成时，导电过渡层510也由金属铝制成。
当然，导电过渡层510的材料也可以不同于漏极520的材料。例如，当导电过渡层510由金属铝制成时，漏极可以包括MoAlMo(钼铝钼)的三层金属结构。
如图2所示，根据本发明实施例的阵列基板还可以包括第二透明电极300、位于栅极层(包括栅线、公共电极线、栅极等)与有 源层之间的栅绝缘层700，以及位于有源层上方的钝化层800。第二透明电极300形成在钝化层800上，并且，第二透明电极300可以为通过过孔和栅极层中的公共电极线进行电连接的梳状电极。这种情况下，相应地，第一透明电极200为块状电极。
参照图3至图8，作为本发明的另一个方面，提供上述阵列基板的制造方法，所述阵列基板被划分为多个像素单元，所述多个像素单元中的每一个内均设置有第一透明电极和薄膜晶体管，其中，所述制造方法包括步骤：形成包括第一透明电极的图形；以及在所述包括第一透明电极的图形上形成包括漏极的图形。
在本发明实施例中，由于第一透明电极位于漏极的下方，因此，相比于现有技术，在形成第一透明电极时，第一透明电极的台阶高度较小，所以第一透明电极不容易产生断裂。
在本发明实施例中，所述多个像素单元中的每一个内还设置有第二透明电极，所述薄膜晶体管包括有源层、栅极、源极和漏极等结构。
根据本发明实施例的制造方法还包括步骤：在所述形成包括第一透明电极的图形之前，形成包括有源层的图形。这种情况下，在所述包括有源层的图形上方形成包括第一透明电极的图形，即，包括第一透明电极的图形位于包括有源层的图形上方。
在上述步骤中，所述包括有源层的图形包括分别对应于各个像素单元的薄膜晶体管的多个有源层。所述包括漏极的图形包括各个薄膜晶体管的漏极，还包括各个薄膜晶体管的源极、多条数据线等。
如上文所述，在本发明实施例中，对形成有源层的材料并不做限定，例如，有源层可以由氧化物制成，也可以由多晶硅制成。
在根据本发明实施例的制造方法中，当有源层由氧化物制成时，在形成第一透明电极之前，为防止在形成第一透明电极时破坏有源层，需要在有源层上形成刻蚀阻挡层；当有源层由多晶硅制成时，由于在形成第一透明电极时不会破坏有源层，因此无需 在有源层上形成刻蚀阻挡层。
在根据本发明实施例的制造方法中，当所述有源层由多晶硅制成时，由于透明电极通常由ITO制成，若多晶硅与ITO直接接触，二者之间形成肖特基接触，接触电阻较大，为了减小多晶硅与ITO之间的接触电阻，可选地，所述制造方法还包括以下步骤：在形成包括有源层的图形之后，并且在形成包括第一透明电极的图形之前，形成包括导电过渡层的图形，所述导电过渡层在有源层的表面共形地形成，且其位置对应于所述漏极的位置。这种情况下，所述第一透明电极的一端搭接在所述导电过渡层上，以使得所述第一透明电极与所述导电过渡层之间以及所述有源层和所述导电过渡层之间均形成欧姆接触。
在根据本发明实施例的制造方法中，导电过渡层的材料可以是能够满足以下要求的任何材料，即，在第一透明电极与导电过渡层之间以及有源层和导电过渡层之间均形成欧姆接触。
可选地，在根据本发明实施例的制造方法中，所述导电过渡层的厚度小于所述漏极的厚度，以减小第一透明电极的台阶高度。
可选地，所述导电过渡层的材料与所述源极和漏极的材料相同，以简化所述阵列基板的制造方法。
在本发明中，对形成各个图形层的具体方式并不做限定。通常，可以通过光刻构图工艺形成。
可选地，为了简化所述阵列基板的制造方法，可选所述形成包括有源层的图形的步骤、所述形成包括导电过渡层的图形的步骤、所述形成包括第一透明电极的图形的步骤和所述形成包括漏极的图形的步骤具体包括：
依次形成包括初始有源层B的图形和包括初始导电过渡层A的图形，所述初始有源层B的边缘轮廓对应于所述有源层的轮廓，所述初始导电过渡层A的边缘与所述初始有源层B的边缘对齐，且所述初始导电过渡层A堆叠在所述初始有源层B上(如图3所示)，其中，所述包括初始有源层B的图形包括分别对应于各个像素单元的薄膜晶体管的多个初始有源层B，所述包括初始导电 过渡层A的图形包括分别对应于各个像素单元的薄膜晶体管的多个初始导电过渡层A；
依次形成透明电极材料层C和第二金属材料层D(如图4所示)，且第二金属材料层D位于透明电极材料层C上；
在第二金属材料层D上形成光刻胶层；
对所述光刻胶层进行曝光显影，以形成第一掩膜图形层，该第一掩膜图形层包括分别对应于各个像素单元的多个第一掩膜图形E，换言之，每个像素单元内均形成有一个第一掩膜图形E(如图5所示)，该第一掩膜图形E包括对应于所述薄膜晶体管的源极和漏极之间的间隔区域的沟道孔E1，且所述第一掩膜图形E所覆盖的区域的形状与所述薄膜晶体管的源极和第一透明电极的上表面的形状一致；
通过刻蚀去除透明电极材料层C和第二金属材料层D上除第一掩膜图形E所覆盖的区域之外的材料(如图6所示)；
对第一掩膜图形层进行灰化处理，以获得第二掩膜图形层，所述第二掩膜图形层包括分别对应于各个像素单元的多个第二掩膜图形F，换言之，每个所述像素单元内均形成有一个第二掩膜图形F(如图7所示)，所述第二掩膜图形F所覆盖的区域的形状与所述薄膜晶体管中的源极和漏极的上表面的形状一致；
通过刻蚀形成包括漏极的图形，并通过刻蚀去除沟道孔E1中的位于有源层400上的初始导电过渡层A(如图8所示)。经过此次刻蚀可以防止有源层400的表面上残留导电材料，从而可以确保薄膜晶体管的正常导通和正常关断的性能，有利于提高显示面板的良率。在刻蚀时，第二掩膜图形F可以保护该第二掩膜图形F所覆盖的区域的材料不被刻蚀，未被刻蚀的金属材料层形成为所述薄膜晶体管的源极和漏极。
应当理解的是，本文中所述的“薄膜晶体管的源极和第一透明电极的上表面的形状”是指薄膜晶体管的源极的上表面与第一透明电极的上表面形成的组合的形状，以及“源极和漏极上表面的形状”是指源极的上表面与漏极的上表面形成的组合的形状。
如上文所述，在通过刻蚀工艺形成源极和漏极之前，并未通过刻蚀去除位于有源层上且与源极相对应的位置处的初始导电过渡层A，这样可以减少一道掩膜、刻蚀工艺，从而简化了所述阵列基板的制造方法，降低了生产成本。
可选地，在根据本发明实施例的制造方法中，对应于沟道孔E1位置处的有源层400的厚度小于其他位置处的有源层400的厚度，从而可以确保有源层上没有导电材料残留。因此，所述制造方法还包括以下步骤：在形成了包括漏极的图形之后，对所述有源层上对应于所述沟道孔E1的部分进行刻蚀，以使得所述有源层的对应于所述沟道孔部分的厚度小于所述有源层的其他部分的厚度。
在根据本发明实施例的制造方法中，上述步骤均可以通过干法刻蚀完成。
在根据本发明实施例的制造方法中，第二金属材料层D可以包括堆叠设置的多个子金属层，且相邻两层子金属层的成分可以不同。例如，第二金属层可以是AlMoAl(铝钼铝)三层金属结构。
在根据本发明实施例的制造方法中，依次形成包括初始有源层B的图形和包括初始导电过渡层A的图形的步骤具体可以包括：
依次形成半导体材料层和第一金属材料层，且第一金属材料层位于半导体材料层上；
对所述半导体材料层和所述第一金属材料层进行构图，以获得包括初始有源层B的图形和包括初始导电过渡层A的图形(如图3所示)。
可选地，在根据本发明实施例的制造方法中，第一金属材料层的成分与第二金属材料层D的成分可以相同，以简化所述阵列基板的制造方法。当然，第一金属材料层的成分与第二金属材料层的成分也可以不同。
本领域技术人员容易理解的是，根据本发明实施例的制造方法还可包括以下步骤：在形成包括有源层的图形之前，依次形成包括栅极600的图形和栅绝缘层，且栅绝缘层位于包括栅极的图 形上。其中，有源层形成在栅极上方的栅绝缘层上。所述包括栅极的图形包括各薄膜晶体管的栅极，还包括栅线和公共电极线。
本领域技术人员容易理解的是，根据本发明实施例的制造方法还可包括以下步骤：在形成包括漏极的图形之后，依次形成钝化层和包括第二透明电极的图形，且包括第二透明电极的图形位于钝化层上。其中，钝化层覆盖包括漏极的图形，而第二透明电极为梳状电极，通过过孔与公共电极线相连。
作为本发明的又一个方面，提供一种显示装置，所述显示装置包括阵列基板，其中，所述阵列基板为本发明所提供的上述阵列基板。
容易理解的是，所述显示装置可以为液晶显示装置，该显示装置还包括与所述阵列基板对盒设置的对盒基板。可以将彩膜层设置在对盒基板上，以实现彩色显示。
所述显示装置可以是显示器、笔记本电脑、导航仪、手机、平板电脑等。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (18)

  1. 一种阵列基板，所述阵列基板被划分为多个像素单元，所述多个像素单元中的每一个内均设置有第一透明电极和薄膜晶体管，所述薄膜晶体管包括漏极，其中，所述薄膜晶体管的漏极设置在所述第一透明电极上，并与所述第一透明电极电连接。
  2. 根据权利要求1所述的阵列基板，其中，所述薄膜晶体管还包括有源层，所述有源层设置在所述第一透明电极下方。
  3. 根据权利要求2所述的阵列基板，其中所述有源层由多晶硅制成，并且所述薄膜晶体管还包括设置在所述有源层与所述第一透明电极之间的导电过渡层，所述导电过渡层在所述有源层表面共形地形成，且所述导电过渡层的位置对应于所述薄膜晶体管的漏极的位置，所述第一透明电极的一端搭接在所述导电过渡层上方，以使得所述第一透明电极与所述导电过渡层之间以及所述有源层与所述导电过渡层之间均形成欧姆接触。
  4. 根据权利要求3所述的阵列基板，其中所述薄膜晶体管还包括源极和设置在所述有源层与所述源极之间的附加导电过渡层，所述附加导电过渡层在所述有源层表面共形地形成，且所述附加导电过渡层的位置对应于所述薄膜晶体管的源极的位置。
  5. 根据权利要求4所述的阵列基板，其中所述多个像素单元中的每一个内还包括设置在所述附加导电过渡层与所述源极之间的附加透明电极，所述附加透明电极在所述源极的下表面共形地形成。
  6. 根据权利要求3所述的阵列基板，其中所述导电过渡层的厚度小于所述漏极的厚度。
  7. 根据权利要求3所述的阵列基板，其中所述导电过渡层的材料与所述漏极的材料相同。
  8. 一种阵列基板的制造方法，其中所述阵列基板被划分为多个像素单元，所述多个像素单元中的每一个内均设置有第一透明电极和薄膜晶体管，所述薄膜晶体管包括漏极，所述制造方法包括步骤：
    形成包括第一透明电极的图形；以及
    在所述包括第一透明电极的图形上形成包括漏极的图形。
  9. 根据权利要求8所述的制造方法，其中所述薄膜晶体管还包括有源层，并且所述制造方法还包括步骤：
    在所述形成包括第一透明电极的图形的步骤之前，形成包括有源层的图形，并且所述包括第一透明电极的图形位于所述包括有源层的图形上方。
  10. 根据权利要求9所述的制造方法，其中所述有源层由多晶硅制成，并且所述制造方法还包括步骤：
    在所述形成包括有源层的图形的步骤之后，并且在所述形成包括第一透明电极的图形的步骤之前，形成包括导电过渡层的图形，所述导电过渡层在有源层表面共形地形成，其中，
    在形成包括第一透明电极的图形的步骤中，所述第一透明电极的一端搭接在所述导电过渡层上，以使得所述第一透明电极与所述导电过渡层之间以及所述有源层和所述导电过渡层之间均形成欧姆接触。
  11. 根据权利要求10所述的制造方法，其中所述导电过渡层的厚度小于所述漏极的厚度。
  12. 根据权利要求10所述的制造方法，其特征在于，所述导电过渡层的材料与所述漏极的材料相同。
  13. 根据权利要求10所述的制造方法，其中所述薄膜晶体管还包括源极，并且所述形成包括有源层的图形的步骤、所述形成包括导电过渡层的图形的步骤、所述形成包括第一透明电极的图形的步骤和所述形成包括漏极的图形的步骤具体包括：
    依次形成包括初始有源层的图形和包括初始导电过渡层的图形，所述初始有源层的边缘轮廓对应于所述有源层的轮廓，所述初始导电过渡层的边缘与所述初始有源层的边缘对齐，且所述初始导电过渡层堆叠在所述初始有源层上；
    依次形成透明电极材料层和第二金属材料层，且所述第二金属材料层位于所述透明电极材料层上；
    在所述第二金属材料层上方形成光刻胶层；
    对所述光刻胶层进行曝光显影，以形成第一掩膜图形层，所述第一掩膜图形层包括分别对应于各个像素单元的多个第一掩膜图形，所述第一掩膜图形包括对应于所述薄膜晶体管的源极和漏极之间的间隔区域的沟道孔，每个像素单元内均形成有一个所述第一掩膜图形，所述第一掩膜图形所覆盖的区域的形状与所述薄膜晶体管的源极和第一透明电极的上表面的形状一致；
    通过刻蚀去除所述透明电极材料层和所述第二金属材料层上除所述第一掩膜图形所覆盖的区域之外的材料；
    对所述第一掩膜图形层进行灰化处理，以获得第二掩膜图形层，所述第二掩膜图形层包括分别对应于各个像素单元的多个第二掩膜图形，每个所述像素单元内均形成有一个所述第二掩膜图形，所述第二掩膜图形所覆盖的区域的形状与源极和漏极上表面的形状一致；以及
    通过刻蚀形成包括漏极的图形，并通过刻蚀去除所述沟道孔中的位于有源层上的初始导电过渡层材料。
  14. 根据权利要求13所述的制造方法，其中所述依次形成包括初始有源层的图形和包括初始导电过渡层的图形的步骤具体包括：
    依次形成半导体材料层和第一金属材料层，且所述第一金属材料层位于所述半导体材料层上；以及
    对所述半导体材料层和所述第一金属材料层进行构图，以获得包括初始有源层的图形和包括初始导电过渡层的图形。
  15. 根据权利要求13所述的制造方法，其中所述制造方法还包括：
    在所述形成包括漏极的图形之后，对所述有源层上对应于所述沟道孔的部分进行刻蚀，以使得所述有源层上对应于所述沟道孔的部分的厚度小于所述有源层上其他部分的厚度。
  16. 根据权利要求15所述的制造方法，其中利用干法刻蚀对对所述有源层上对应于所述沟道孔的部分进行刻蚀。
  17. 根据权利要求13所述的方法，其中第二金属层由多层金属材料堆叠而成。
  18. 一种显示装置，所述显示装置包括阵列基板，其中所述阵列基板为权利要求1-7中任意一项所述的阵列基板。
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