WO2016165224A1 - 金属氧化物薄膜晶体管及制备方法、显示基板和显示装置 - Google Patents

金属氧化物薄膜晶体管及制备方法、显示基板和显示装置 Download PDF

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WO2016165224A1
WO2016165224A1 PCT/CN2015/084343 CN2015084343W WO2016165224A1 WO 2016165224 A1 WO2016165224 A1 WO 2016165224A1 CN 2015084343 W CN2015084343 W CN 2015084343W WO 2016165224 A1 WO2016165224 A1 WO 2016165224A1
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metal oxide
oxygen
layer
thin film
film transistor
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PCT/CN2015/084343
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English (en)
French (fr)
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王美丽
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京东方科技集团股份有限公司
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Priority to US15/122,902 priority Critical patent/US10199395B2/en
Publication of WO2016165224A1 publication Critical patent/WO2016165224A1/zh

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    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a metal oxide thin film transistor and a corresponding fabrication method, display substrate, and display device.
  • TFT-LCDs thin film transistor liquid crystal displays
  • CRT cathode ray tube
  • the performance of thin film transistors (TFTs) directly affects the quality of the display.
  • PPI pixels per inch
  • the development of high mobility materials has become a hot spot.
  • the conventional polysilicon thin film transistor has a high mobility, the preparation process is complicated, the preparation cost is high, and the requirements for large-area production cannot be satisfied.
  • the oxide thin film transistor is suitable for large-area production, but the mobility is low, and currently only 10-30 cm 2 /Vs, which needs to be further improved.
  • m* is the effective mass of the electron and ⁇ is the carrier release time.
  • a particular material has the ability to absorb strong oxygen defects by removing an excess of oxygen dangling bonds from the active layer by forming an oxygen-depleted gettering layer between the active layer and the source and drain electrodes.
  • the oxygen-deficient state increases the carrier release time, thereby increasing the mobility of the metal oxide thin film transistor.
  • the oxide as the material of the oxygen-depleted gettering layer should be more stable than the metal oxide in the active layer.
  • the Gibbs free energy is generated by an oxide unit volume standard to judge the stability of various oxides.
  • the standard Gibbs free energy of a compound is a measure of whether the compound is easily decomposed into the corresponding elemental substance, that is, the larger the standard Gibbs free energy, the more stable the compound, and the more easily the compound is easily decomposed into the corresponding elemental substance.
  • Figure 1 is a graph showing the change in Gibbs free energy per unit volume standard of a common oxide, in which, at a certain temperature, when ⁇ r G m ⁇ 0, the reaction of generating oxides from the corresponding elemental substance in the standard state can Spontaneously, and the smaller the value of ⁇ r G m (i.e., the larger the absolute value), the stronger the stability of the oxide, and the more difficult it is to decompose into a simple substance.
  • materials such as Hf, Ti, Be, Al, and Ca have strong oxide stability.
  • a material that is more stable to oxides can absorb weaker oxygen dangling bonds and oxygen-deficient states from less stable oxides.
  • a metal oxide thin film transistor is provided in a first aspect of the present disclosure, wherein an oxygen deficiency may be present between the active layer and the source, and/or between the active layer and the drain
  • the oxygen-depleted gettering layer of the gettering material the unit volume standard of the oxide of the oxygen-depleted gettering material generates Gibbs free energy greater than the metal oxide in the active layer.
  • the metal oxide thin film transistor In the metal oxide thin film transistor, it has strong oxygen absorption ability (ie, corresponding oxide)
  • the oxygen-depleted gettering layer of the unit volume standard generates a large Gibbs free energy can absorb the weak oxygen dangling bonds and the oxygen-deficient state in the active layer of the metal oxide, thereby effectively improving the metal oxide thin film transistor Mobility.
  • the oxygen-depleted gettering layer may be disposed between the source and the active layer, or between the drain and the active layer, or in particular, disposed on the active layer and the source and drain electrodes To further improve the mobility of the metal oxide thin film transistor.
  • the thickness of the oxygen-depleted gettering layer may be 100 to In the scope of.
  • the thickness of the oxygen-depleted gettering layer is related to the thickness of the active layer, the material and the oxygen dangling bonds and the concentration of the oxygen-deficient state.
  • the thickness of the active layer is thick, the metal oxide in the active layer is relatively stable, or the concentration of the oxygen dangling bond and the oxygen-deficient state is large, the thickness of the oxygen-depleted gettering layer may be correspondingly increased. It is pointed out that those skilled in the art can design and implement an oxygen-deficient gettering layer having different thicknesses according to actual needs.
  • the oxygen-deficient gettering material may be selected from the group consisting of Hf, Ti, Be, Al, Si, and Ca.
  • the oxides of the above materials are excellent in stability and are very suitable for use as an oxygen-deficient gettering layer in metal oxide thin film transistors.
  • the oxygen-depleted gettering material may be the same as the source and drain materials.
  • the oxygen-depleted gettering layer and the source and the drain can be simultaneously formed, so that no additional process steps are added, the preparation is simple, and the cost is lowered.
  • the metal oxide in the active layer may be selected from oxides of Zn, In, Sn, and Ga.
  • the stability of the above oxide is low, and accordingly there are several materials suitable for use as an oxygen-deficient gettering layer in a metal oxide thin film transistor.
  • the metal oxide in the active layer may include metal oxynitride.
  • a method of fabricating a metal oxide thin film transistor may include sequentially forming a gate layer, a gate insulating layer, and an active layer on a substrate, and patterning each layer Processing; forming an oxygen-deficient gettering layer containing an oxygen-deficient gettering material on the active layer; making a source-drain electrode layer; performing a patterning process on the source-drain electrode layer and the oxygen-depleting gettering layer, wherein the oxygen defect is removed a layer between the active layer and the source, and/or between the active layer and the drain, the unit volume standard of the oxide of the oxygen-deficient gettering material generates Gibbs free energy greater than that in the active layer Metal oxide.
  • the oxygen gettering ability having a strong oxygen gettering ability (that is, the Gibbs free energy per unit volume standard corresponding to the oxide is generated) is large.
  • the removing layer can absorb the weak oxygen dangling bonds and the oxygen-deficient state in the active layer of the metal oxide, thereby effectively increasing the mobility of the metal oxide thin film transistor.
  • oxygen defect absorption may be made between the source and the active layer, or between the drain and the active layer, or in particular between the active layer and the source and drain. Layer to further increase the mobility of the metal oxide thin film transistor.
  • the above method may further include an annealing step after the source and drain electrode layers are formed.
  • the annealing step can accelerate the absorption speed of the oxygen defect state and the oxygen dangling bond in the active layer by the oxygen defect gettering layer, thereby facilitating carrier transport, thereby increasing the mobility of the metal oxide thin film transistor.
  • the annealing step may have an annealing temperature of 100 ° C to 350 ° C and an annealing time of 30 to 90 minutes.
  • a suitable annealing process can improve device mobility, improve threshold voltage, current switching ratio and other important parameters to improve device performance.
  • the annealing temperature should not be too high. When the annealing temperature is too high, the mobility of the metal oxide thin film transistor will decrease as the temperature increases.
  • the above method may further include the step of forming a passivation layer over the resultant metal oxide thin film transistor.
  • the present disclosure also provides a display substrate including the metal oxide thin film transistor according to the first aspect of the present disclosure and a display device including the display substrate, which has similarities to those described above with respect to the metal oxide thin film transistor Features and advantages are not described here.
  • Figure 1 is a graph showing the generation of Gibbs free energy change for a common oxide unit volume standard
  • FIG. 2 illustrates a cross-sectional view of a metal oxide thin film transistor employing a bottom gate BCE structure in accordance with an embodiment of the present disclosure
  • FIG. 3 illustrates a cross-sectional view of a metal oxide thin film transistor employing a bottom gate ESL structure in accordance with an embodiment of the present disclosure
  • FIG. 4 illustrates a cross-sectional view of a metal oxide thin film transistor employing a top gate structure in accordance with an embodiment of the present disclosure
  • FIG. 5 illustrates a flow chart of a method of fabricating a metal oxide thin film transistor of a bottom gate BCE structure in accordance with an embodiment of the present disclosure
  • FIGS 6(a)-(c) illustrate schematic diagrams of some of the steps in the method illustrated in Figure 5, respectively.
  • the thin film transistor includes a gate electrode 1, a gate insulating layer 2, an active layer 3, a source 4 and a drain 5 on a substrate, and a passivation layer 7 over the device.
  • the gate insulating layer 2 is disposed between the gate electrode 1 and the active layer 3
  • the source electrode 4 and the drain electrode 5 are disposed above the active layer 3
  • the active layer 3 may be composed of a metal oxide or, in particular, a metal Nitrogen oxides form.
  • the thin film transistor further includes an oxygen defect gettering layer 6 including an oxygen defect gettering material disposed between the active layer 3 and the source 4 and the drain 5, wherein the unit volume standard of the oxide of the oxygen defective gettering material is generated
  • the Booth free energy is greater than the metal oxide in the active layer 3. Therefore, the oxygen-depleted gettering layer 6 having a strong oxygen gettering ability can absorb the weak oxygen dangling bonds and the oxygen-deficient state in the metal oxide active layer 3, thereby effectively increasing the mobility of the thin film transistor.
  • oxygen-depleted gettering layer 6 is shown in FIG. 2 between the active layer 3 and the source 4 and the drain 5, as will be appreciated and appreciated by those skilled in the art, The oxygen-depletion gettering layer 6 may also be disposed only between the source 4 and the active layer 3 or only between the drain 5 and the active layer 3.
  • the thickness of the oxygen-depleted gettering layer 6 can be from 100 to And the oxygen-depleted gettering material may be selected from the group consisting of Hf, Ti, Be, Al, Si, and Ca. In practice, those skilled in the art can design and implement oxygen defects having different thicknesses and materials according to the thickness of the oxygen-depleted gettering layer 6 and the thickness of the active layer 3, the concentration of materials and oxygen dangling bonds and oxygen-deficient states, and the like. Aspirate layer 6.
  • the metal oxide in the active layer 3 may be selected from oxides or oxynitrides including Zn, In, Sn, and Ga.
  • the source 4 and the drain 5 may be made of metal Mo.
  • FIG. 3 illustrates a cross-sectional view of a metal oxide thin film transistor employing a bottom gate ESL structure in accordance with an embodiment of the present disclosure.
  • the structure in FIG. 3 is substantially similar to the structure in FIG. 2 except that the thin film transistor further includes an etch stop layer (ESL) 8, and the etch stop layer 8 is disposed between the source 4 and the drain 5.
  • ESL etch stop layer
  • Both Fig. 2 and Fig. 3 employ a bottom gate type structure. Since the metal gate and the gate insulating layer of the thin film transistor of the bottom gate type structure can serve as an optical protective layer as a semiconductor layer, the light emitted from the backlight is prevented from being irradiated to the photogenerated carriers generated by the semiconductor layer to destroy the semiconductor layer. Electrical special Therefore, the performance of the thin film transistor of the bottom gate type structure is relatively stable.
  • FIG. 4 illustrates a cross-sectional view of a metal oxide thin film transistor employing a top gate structure in accordance with an embodiment of the present disclosure.
  • the structure in FIG. 4 is different from the structure in FIG. 2 in that in FIG. 4, the active layer 3 is disposed on a substrate on which a source 4 and a drain 5 are disposed, and a gate insulating layer 2 is located at the source 4 Above the drain 5, and the gate 1 is disposed on a side of the gate insulating layer 2 facing away from the source 4 and the drain 5.
  • an oxygen-depleted gettering layer 6 is disposed between the active layer 3 and the source 4 and the drain 5, and the oxygen-depleted gettering layer 6 may be disposed only between the active layer 3 and the source 4 as needed. Or it is only arranged between the active layer 3 and the drain 5.
  • the thin film transistor of the top gate type structure used in FIG. 4 has the advantages of simple manufacturing process, small number of required lithography plates, and low cost.
  • FIG. 5 illustrates a flow chart of a method of fabricating a metal oxide thin film transistor of a bottom gate BCE structure
  • FIGS. 6(a)-(c) illustrate the method illustrated in FIG. 5, respectively, according to an embodiment of the present disclosure.
  • step 502 Various film forming processes known in the art, such as sputtering, chemical vapor deposition, and the like, may be employed in step 502, and patterning processes known in the art, including photolithography processes, etching processes, and the like, may be employed.
  • an oxygen-depleted gettering layer 6 is formed on the active layer 3.
  • a source/drain electrode layer is formed on the oxygen-depleted gettering layer 6.
  • the oxygen-depleted gettering layer 6 and the source-drain electrode layer are formed of the same material. In this case, step 504 and step 506 can be performed simultaneously. Further, the oxygen-depleted gettering layer 6 may exist only between the active layer 3 and the source or between the active layer 3 and the drain.
  • an annealing process is performed, as shown in Figure 6(b), where the arrows indicate the annealing direction.
  • the annealing temperature is from 100 ° C to 350 ° C and the annealing time is from 30 to 90 minutes. In some cases, step 508 can be omitted.
  • the source drain electrode layer and the oxygen defect gettering layer 6 are subjected to a patterning process, as shown in FIG. 6(c), wherein a patterning process known in the art, including photolithography, may be employed. Process, etching process, etc.
  • step 512 a passivation layer 7 is formed over the device, resulting in a structure as shown in FIG. In some cases, step 512 can be omitted.

Abstract

提供一种金属氧化物薄膜晶体管，其中在有源层（3）与源极（4）之间、和/或在有源层（3）与漏极（5）之间存在包含氧缺陷吸除材料的氧缺陷吸除层（6），氧缺陷吸除材料的氧化物的单位体积标准生成吉布斯自由能大于有源层（3）中的金属氧化物。还提供包括金属氧化物薄膜晶体管的显示基板和包括显示基板的显示装置。

Description

金属氧化物薄膜晶体管及制备方法、显示基板和显示装置 技术领域
本公开涉及显示技术领域，并且特别地涉及一种金属氧化物薄膜晶体管及相应的制备方法、显示基板和显示装置。
背景技术
伴随信息技术的不断发展，显示技术作为获取信息的窗口也得到了飞速发展。目前，薄膜晶体管液晶显示器(TFT-LCD)已经超过阴极射线管(CRT)显示器，成为全球第一大显示器市场。作为当前最为流行的平板显示器的核心元件，薄膜晶体管(TFT)的性能直接影响到显示器的质量。随着显示领域中对高PPI(每英寸像素)、高刷新率的日益增加的需求，对高迁移率材料的开发成为热点。常规的多晶硅薄膜晶体管虽然具有较高的迁移率，但是其制备工艺复杂、制备成本高，无法满足大面积生产的要求。另一方面，氧化物薄膜晶体管适于大面积生产，但是迁移率较低，目前仅为10-30cm2/Vs，有待进一步提高。
已知氧化物薄膜晶体管的迁移率μ计算公式可以表述为：
Figure PCTCN2015084343-appb-000001
其中m*为电子有效质量，τ为载流子释放时间。
因此，存在提高氧化物薄膜晶体管迁移率的两种方式：
(1)增加分子有效质量m*的数值小的金属离子的含量：例如在IGZO(铟镓锌氧化物)中，参见表1，电子在In2O3中的m*最小，因此In对薄膜晶体管迁移率的提升起到的作用也最突出，增加氧化物中In3+的离子含量可以显著提高氧化物薄膜晶体管的迁移率。但是，In3+离子的轨道半径最大，且In3+离子与O的键能最小，所形成的In-O键易断开，从而形成一些氧悬挂键或多余的氧缺陷态，进而影响薄膜晶体管的稳定性。
Figure PCTCN2015084343-appb-000002
表1
(2)减少氧化物中影响载流子传输缺陷态的数量：载流子释放时间受缺陷态影响最大，具体地，减少氧化物中缺陷态数量，可以增加载流子释放时间，从而提升薄膜晶体管的迁移率。
发明内容
申请人已经发现，特定材料具有强氧缺陷吸除的能力，通过在有源层和源漏电极之间制作一层氧缺陷吸除层，可以吸除掉有源层中多余的氧悬挂键和氧缺陷态，增加载流子释放时间，从而起到提高金属氧化物薄膜晶体管迁移率的目的。为此目的，作为氧缺陷吸除层的材料的氧化物应当比有源层中的金属氧化物更加稳定。
为探究适合作为用于氧化物薄膜晶体管的氧缺陷吸除层的材料，将通过氧化物单位体积标准生成吉布斯自由能来判断多种氧化物的稳定性。化合物的标准生成吉布斯自由能是该化合物是否容易分解成相应单质的量度，即标准生成吉布斯自由能越大，该化合物越稳定，反之则该化合物越容易分解成相应单质。
图1图示了常见氧化物单位体积标准生成吉布斯自由能的变化图，其中，在一定温度下，当ΔrGm＜0时，在标准态下由相应单质生成氧化物的反应能够自发地进行，并且ΔrGm的值越小(即绝对值越大)，氧化物的稳定性就越强，也就越不易分解成单质。可以看到，在一定温度下，Hf、Ti、Be、Al、Ca等材料的氧化物稳定性都很强。对应氧化物的稳定性较强的材料能够从稳定性较弱的氧化物中吸除较弱的氧悬挂键及氧缺陷态。
鉴于上文，在本公开的第一方面中提供了一种金属氧化物薄膜晶体管，其中在有源层与源极之间、和/或在有源层与漏极之间可以存在包含氧缺陷吸除材料的氧缺陷吸除层，所述氧缺陷吸除材料的氧化物的单位体积标准生成吉布斯自由能大于有源层中的金属氧化物。
在该金属氧化物薄膜晶体管中，具有较强氧吸除能力(即对应氧化物 的单位体积标准生成吉布斯自由能较大)的氧缺陷吸除层能够将金属氧化物有源层中较弱的氧悬挂键及氧缺陷态吸除，从而有效提高金属氧化物薄膜晶体管的迁移率。在实施例中，氧缺陷吸除层可以布置在源极与有源层之间，或者布置在漏极与有源层之间，或者特别地，布置在有源层与源极和漏极二者之间以进一步提高金属氧化物薄膜晶体管的迁移率。
根据本公开的实施例，氧缺陷吸除层的厚度可以在100至
Figure PCTCN2015084343-appb-000003
的范围中。氧缺陷吸除层的厚度与有源层的厚度、材料和氧悬挂键及氧缺陷态的浓度有关。当有源层的厚度较厚、有源层中的金属氧化物的较稳定或者氧悬挂键及氧缺陷态的浓度较大时，氧缺陷吸除层的厚度可以相应增加。要指出，本领域技术人员可以根据实际需要，设计和实现具有不同厚度的氧缺陷吸除层。
根据本公开的另一实施例，氧缺陷吸除材料可以选自Hf、Ti、Be、Al、Si和Ca。从图1可以看到，以上几种材料的氧化物的稳定性优异，非常适合于用作金属氧化物薄膜晶体管中的氧缺陷吸除层。
根据本公开的又一实施例，氧缺陷吸除材料可以与源极、漏极材料相同。在这种情况下，可以同时形成氧缺陷吸除层和源极以及漏极，因此不增加额外的工艺步骤，制备简单且成本降低。
根据本公开的再一实施例，有源层中的金属氧化物可以选自Zn、In、Sn和Ga的氧化物。同样从图1可以看到，以上氧化物的稳定性较低，因此相应地存在若干适合于用作金属氧化物薄膜晶体管中的氧缺陷吸除层的材料。
另外，根据本公开的实施例，有源层中的金属氧化物可以包括金属氮氧化物。
在本公开的第二方面中提供了一种制备金属氧化物薄膜晶体管的方法，可以包括在基板上依次制作栅极层、栅极绝缘层和有源层，并且对每一层进行图案化工艺处理；在有源层上制作包含氧缺陷吸除材料的氧缺陷吸除层；制作源漏电极层；对源漏电极层和氧缺陷吸除层进行图案化工艺处理，其中，氧缺陷吸除层在有源层与源极之间、和/或在有源层与漏极之间，所述氧缺陷吸除材料的氧化物的单位体积标准生成吉布斯自由能大于有源层中的金属氧化物。
在通过该方法制备得到的金属氧化物薄膜晶体管中，具有较强氧吸除能力(即对应氧化物的单位体积标准生成吉布斯自由能较大)的氧缺陷吸 除层能够将金属氧化物有源层中较弱的氧悬挂键及氧缺陷态吸除，从而有效提高金属氧化物薄膜晶体管的迁移率。在实施例中，可以在源极与有源层之间、或者在漏极与有源层之间，或者特别地，在有源层与源极和漏极二者之间制作氧缺陷吸除层，以进一步提高金属氧化物薄膜晶体管的迁移率。
根据本公开的实施例，上述方法还可以包括在制作源漏电极层之后的退火步骤。退火步骤可以加快氧缺陷吸除层对有源层中氧缺陷态和氧悬挂键的吸除速度，因此更有利于载流子的传输，从而提高金属氧化物薄膜晶体管的迁移率。
根据本公开的另一实施例，退火步骤的退火温度可以为100℃-350℃，退火时间可以为30-90分钟。合适的退火工艺可以提高器件的迁移率，改善阈值电压、电流开关比等重要参数，从而改善器件的性能。但是，退火温度不宜过高，当退火温度过高时，金属氧化物薄膜晶体管的迁移率将随温度的增加而减小。
根据本公开的实施例，上述方法还可以包括在结果得到的金属氧化物薄膜晶体管上方制作钝化层的步骤。
本公开还提供了一种包括根据本公开的第一方面的金属氧化物薄膜晶体管的显示基板和包括所述显示基板的显示装置，其具有与上文关于金属氧化物薄膜晶体管所描述的类似的特征和优点，在此不再赘述。
附图说明
本公开的其它目的和特征将从以下结合附图考虑的详细描述变得显而易见。然而，要理解，仅出于说明性而非限制性的目的示出各图，并且各图未必按照比例绘制。在图中，
图1图示了常见氧化物单位体积标准生成吉布斯自由能变化图；
图2图示了根据本公开的实施例的采用底栅BCE结构的金属氧化物薄膜晶体管的横截面视图；
图3图示了根据本公开的实施例的采用底栅ESL结构的金属氧化物薄膜晶体管的横截面视图；
图4图示了根据本公开的实施例的采用顶栅结构的金属氧化物薄膜晶体管的横截面视图；
图5图示了根据本公开的实施例的制备底栅BCE结构的金属氧化物薄膜晶体管的方法的流程图；以及
图6(a)-(c)分别图示了图5中所示的方法中的一些步骤的示意图。
其中，贯穿各图，相同的附图标记表示相同的部分，具体为1：栅极；2：栅极绝缘层；3：有源层；4：源极；5：漏极；6：氧缺陷吸除层；7：钝化层；8：蚀刻阻挡层(ESL)。
具体实施方式
图2图示了根据本公开的实施例的采用底栅BCE结构的金属氧化物薄膜晶体管的横截面视图。如图2所示，薄膜晶体管包括在基板上的栅极1、栅极绝缘层2、有源层3、源极4和漏极5，以及器件上方的钝化层7。其中栅极绝缘层2布置在栅极1和有源层3之间，源极4和漏极5布置在有源层3上方，并且有源层3可以由金属氧化物，或者特别地，金属氮氧化物形成。薄膜晶体管还包括布置在有源层3和源极4、漏极5之间的包括氧缺陷吸除材料的氧缺陷吸除层6，其中氧缺陷吸除材料的氧化物的单位体积标准生成吉布斯自由能大于有源层3中的金属氧化物。因此，具有较强氧吸除能力的氧缺陷吸除层6能够将金属氧化物有源层3中较弱的氧悬挂键及氧缺陷态吸除，从而有效提高薄膜晶体管的迁移率。
需要指出的是，尽管在图2中示出氧缺陷吸除层6布置在有源层3与源极4和漏极5二者之间，但是如本领域技术人员将设想和领会到的，氧缺陷吸除层6也可以仅布置在源极4与有源层3之间，或者仅布置在漏极5与有源层3之间。
氧缺陷吸除层6的厚度可以在100至
Figure PCTCN2015084343-appb-000004
的范围中，并且氧缺陷吸除材料可以选自Hf、Ti、Be、Al、Si和Ca。在实践中，本领域技术人员可以根据氧缺陷吸除层6的厚度和有源层3的厚度、材料和氧悬挂键及氧缺陷态的浓度等来设计和实现具有不同厚度和材料的氧缺陷吸除层6。
有源层3中的金属氧化物可以选自包括Zn、In、Sn和Ga的氧化物或者氮氧化物。另外，源极4和漏极5可以采用金属Mo。
图3图示了根据本公开的实施例的采用底栅ESL结构的金属氧化物薄膜晶体管的横截面视图。图3中的结构与图2中的结构基本上类似，不同之处仅在于薄膜晶体管还包括蚀刻阻挡层(ESL)8，蚀刻阻挡层8布置在源极4和漏极5之间的有源层3上。
图2和图3都采用了底栅型结构。由于底栅型结构的薄膜晶体管的金属栅极和栅极绝缘层可以充当作为半导体层的光学保护层，以防止背光源发射的光照射到半导体层所产生的光生载流子而破坏半导体层的电学特 性，因此，底栅型结构的薄膜晶体管性能较为稳定。
图4图示了根据本公开的实施例的采用顶栅结构的金属氧化物薄膜晶体管的横截面视图。图4中的结构与图2中的结构的不同之处在于在图4中，有源层3布置在基板上，其上布置源极4和漏极5，栅极绝缘层2位于源极4和漏极5上方，并且栅极1布置在栅极绝缘层2的背离源极4和漏极5的一侧上。同样地，在有源层3与源极4和漏极5之间布置氧缺陷吸除层6，并且氧缺陷吸除层6可以按照需要而仅布置在有源层3与源极4之间或者仅布置在有源层3与漏极5之间。
图4中所采用的顶栅型结构的薄膜晶体管具有制造工艺简单、所需光刻板数量少、成本低等优点。
图5图示了根据本公开的实施例的制备底栅BCE结构的金属氧化物薄膜晶体管的方法的流程图，并且图6(a)-(c)分别图示了图5中所示的方法中的一些步骤的示意图。该方法包括在步骤502处，在基板上依次制作栅极层1、栅极绝缘层2和有源层3，并且对每一层进行相应的图案化工艺处理，如图6(a)中所示。在步骤502中可以采用本领域中已知的各种成膜工艺，例如溅射、化学气相沉积等，并且可以采用本领域中已知的图案化工艺过程，包括光刻工艺、蚀刻工艺等。
在步骤504处，在有源层3上制作氧缺陷吸除层6。在步骤506处，在氧缺陷吸除层6上制作源漏电极层。特别地，氧缺陷吸除层6和源漏电极层由相同材料形成。在这种情况下，步骤504和步骤506可以同时执行。另外，氧缺陷吸除层6也可以仅存在于有源层3与源极之间或者有源层3与漏极之间。
在步骤508处，执行退火过程，如图6(b)所示，其中箭头表示退火方向。退火温度为100℃-350℃，并且退火时间为30-90分钟。在一些情况中，可以省略步骤508。
在步骤510处，对源漏电极层和氧缺陷吸除层6进行图案化工艺处理，如图6(c)中所示，其中可以采用本领域中已知的图案化工艺过程，包括光刻工艺、蚀刻工艺等。
最后，在步骤512处，在器件上方制作钝化层7，从而得到如图2中所示的结构。在一些情况中，可以省略步骤512。
应当指出的是，本公开中所公开的方法不受限于方法被陈述的顺序，一些步骤可以与其它步骤同时执行，并且可以省略一些步骤。
虽然在附图和前述描述中已经详细图示和描述了本公开，但是这样的图示和描述要被视为是说明性或示例性而非限制性的；本公开不限于所公开的实施例。
本领域技术人员在实践所要求保护的本公开中，通过研究附图、公开内容和随附的权利要求，能够理解和实现所公开的实施例的变型。在相互不同的从属权利要求中陈述某些措施这一仅有事实不指示这些措施的组合不能被有利地使用。

Claims (12)

  1. 一种金属氧化物薄膜晶体管，其中在有源层与源极之间、和/或在有源层与漏极之间存在包含氧缺陷吸除材料的氧缺陷吸除层，所述氧缺陷吸除材料的氧化物的单位体积标准生成吉布斯自由能大于有源层中的金属氧化物。
  2. 根据权利要求1的金属氧化物薄膜晶体管，其中所述氧缺陷吸除层的厚度在100至
    Figure PCTCN2015084343-appb-100001
    的范围中。
  3. 根据权利要求1的金属氧化物薄膜晶体管，其中所述氧缺陷吸除材料选自Hf、Ti、Be、Al、Si和Ca。
  4. 根据权利要求1的金属氧化物薄膜晶体管，其中所述氧缺陷吸除材料与源极、漏极材料相同。
  5. 根据权利要求1的金属氧化物薄膜晶体管，其中所述有源层中的金属氧化物选自Zn、In、Sn和Ga的氧化物。
  6. 根据权利要求1的金属氧化物薄膜晶体管，其中所述有源层中的金属氧化物包括金属氮氧化物。
  7. 一种显示基板，包括如权利要求1-6中任一项所述的金属氧化物薄膜晶体管。
  8. 一种显示装置，包括如权利要求7中所述的显示基板。
  9. 一种制备金属氧化物薄膜晶体管的方法，包括以下步骤：
    在基板上依次制作栅极层、栅极绝缘层和有源层，并且对每一层进行图案化工艺处理；
    在有源层上制作包含氧缺陷吸除材料的氧缺陷吸除层；
    制作源漏电极层；
    对源漏电极层和氧缺陷吸除层进行图案化工艺处理，
    其中，氧缺陷吸除层在有源层与源极之间、和/或在有源层与漏极之间，所述氧缺陷吸除材料的氧化物的单位体积标准生成吉布斯自由能大于有源层中的金属氧化物。
  10. 根据权利要求9的方法，还包括在制作源漏电极层之后的退火步骤。
  11. 根据权利要求10的方法，其中所述退火步骤的退火温度为100℃-350℃，退火时间为30-90分钟。
  12. 根据权利要求9的方法，还包括在结果得到的金属氧化物薄膜晶体管上方制作钝化层的步骤。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412623B2 (en) * 2011-06-08 2016-08-09 Cbrite Inc. Metal oxide TFT with improved source/drain contacts and reliability
CN104779299A (zh) 2015-04-16 2015-07-15 京东方科技集团股份有限公司 金属氧化物薄膜晶体管及制备方法、显示基板和显示装置
CN107315033B (zh) * 2016-04-26 2021-08-06 新唐科技日本株式会社 气体检测装置以及氢检测方法
CN110729358B (zh) * 2019-10-24 2022-11-04 Tcl华星光电技术有限公司 薄膜晶体管及其制造方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101257048A (zh) * 2007-02-28 2008-09-03 三星电子株式会社 薄膜晶体管及其制造方法
CN101673770A (zh) * 2008-09-09 2010-03-17 富士胶片株式会社 薄膜场效应晶体管和使用该薄膜场效应晶体管的显示器
CN102194692A (zh) * 2010-03-04 2011-09-21 中国科学院微电子研究所 一种半导体器件的制造方法
US20130134412A1 (en) * 2011-11-25 2013-05-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN103904125A (zh) * 2012-12-26 2014-07-02 鸿富锦精密工业（深圳）有限公司 薄膜晶体管
CN104167446A (zh) * 2014-07-14 2014-11-26 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板和显示装置
CN104779299A (zh) * 2015-04-16 2015-07-15 京东方科技集团股份有限公司 金属氧化物薄膜晶体管及制备方法、显示基板和显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105428424A (zh) * 2009-09-16 2016-03-23 株式会社半导体能源研究所 晶体管及显示设备
US9660092B2 (en) * 2011-08-31 2017-05-23 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor thin film transistor including oxygen release layer
CN102709326B (zh) * 2012-04-28 2018-04-17 北京京东方光电科技有限公司 薄膜晶体管及其制造方法、阵列基板和显示装置
CN104685635B (zh) * 2012-10-01 2017-05-17 夏普株式会社 半导体装置
US9887291B2 (en) * 2014-03-19 2018-02-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display device including the semiconductor device, display module including the display device, and electronic device including the semiconductor device, the display device, or the display module

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101257048A (zh) * 2007-02-28 2008-09-03 三星电子株式会社 薄膜晶体管及其制造方法
CN101673770A (zh) * 2008-09-09 2010-03-17 富士胶片株式会社 薄膜场效应晶体管和使用该薄膜场效应晶体管的显示器
CN102194692A (zh) * 2010-03-04 2011-09-21 中国科学院微电子研究所 一种半导体器件的制造方法
US20130134412A1 (en) * 2011-11-25 2013-05-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN103904125A (zh) * 2012-12-26 2014-07-02 鸿富锦精密工业（深圳）有限公司 薄膜晶体管
CN104167446A (zh) * 2014-07-14 2014-11-26 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板和显示装置
CN104779299A (zh) * 2015-04-16 2015-07-15 京东方科技集团股份有限公司 金属氧化物薄膜晶体管及制备方法、显示基板和显示装置

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