WO2016161744A1 - 显示驱动电路及显示装置 - Google Patents

显示驱动电路及显示装置 Download PDF

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Publication number
WO2016161744A1
WO2016161744A1 PCT/CN2015/087695 CN2015087695W WO2016161744A1 WO 2016161744 A1 WO2016161744 A1 WO 2016161744A1 CN 2015087695 W CN2015087695 W CN 2015087695W WO 2016161744 A1 WO2016161744 A1 WO 2016161744A1
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Prior art keywords
timing
module
timing module
display
chip
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PCT/CN2015/087695
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English (en)
French (fr)
Inventor
上官星辰
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京东方科技集团股份有限公司
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Priority to US14/913,320 priority Critical patent/US9922606B2/en
Publication of WO2016161744A1 publication Critical patent/WO2016161744A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the invention belongs to the technical field of liquid crystal display, and in particular relates to a display driving circuit and a display device.
  • the Gate-driver On Array (GOA) technology is a widely used technology in the field of liquid crystal display.
  • a gate driving chip is mounted on the array substrate to save the cost of the gate driving chip and reduce the distance from the display pixel region to the bezel on the gate side.
  • the GOA requires that the voltage difference of the voltage change is much larger than the drive signal of the general digital voltage range to drive.
  • a level shifting chip Level Shift IC
  • Tcon Timing Controller
  • the driving signal of the driving GOA generated by the time controller is converted into a required signal by means of the level converting chip.
  • the use of the above display driving circuit with a level shifting chip has found that the following problems still exist in practical applications. Since the number of display pixels (set pixels or v-total) set by the system is larger than the number of actually displayed pixels (effective pixels) during the image display of each frame. Set the pixel display duration to one frame period, and the effective pixel display duration to less than one frame period. Therefore, there is a certain amount of time idle after the completion of the effective pixel display of one frame of image and before the start of the next frame (ie, the frame period minus the effective pixel display duration). This time idle is called the non-effective pixel display duration (or Blanking duration). Since the display driver does not need to charge the pixel unit during the blanking time, the level shifting chip is still turned on. That is to say, the level conversion chip still generates a certain power consumption, thereby failing to meet the current energy saving requirements of the display device, resulting in poor quality of the display device.
  • the present invention is directed to at least one of the technical problems existing in the prior art, and provides a display driving circuit and a display device, which can prevent the idle driving chip from being turned on to generate power consumption, thereby satisfying the current display device.
  • the requirements for energy saving improve the quality of the display device.
  • the present invention provides a display driving circuit including a time controller and a driving chip, the time controller including a first generating module and a first timing module; wherein the first generating module Connected to the first timing module and the driving chip respectively, configured to generate a line start signal to trigger the driving of the first timing module to start timing and idle; the first timing module is connected to the driving chip, The driving chip is configured to be turned off that is idle during the non-effective pixel display duration when its current timing duration is equal to the effective pixel display duration.
  • the time controller further includes a second generating module and a second timing module, wherein the second generating module is connected to the second timing module, configured to receive a data enable start hopping signal to trigger the The second timing module starts timing, and receiving the data enables the closing of the hopping signal to trigger the second timing module to stop timing; the second timing module is coupled to the first timing module and configured to be recorded in the The current timing duration under the triggering of the second generation module is the current effective pixel display duration of the first timing module.
  • the time controller further includes a clock module configured to output a clock signal of a preset period; the clock module is respectively connected to the first timing module and the second timing module, the first timing module and the The second timing module is configured to accumulate the number of cycles of the clock signal as the timing duration when it is timed.
  • the idle driving chip includes a gate driving chip, a source driving chip, a level conversion chip or a power management chip.
  • the present invention also provides a display driving circuit including a time controller and a driving chip, the time controller including a third generating module and a third timing module, wherein the third generating module and the third timing module respectively
  • the driving chips are connected, configured to generate the row start hopping signal, trigger the driving of the third timing module to start timing and idle, and generate a line end hopping signal to trigger idle during the non-effective pixel display duration.
  • the third timing module is connected to the third generating module, and is configured to trigger the third generating module to generate the end-of-line transition when the current timing duration is equal to the effective pixel display duration signal.
  • the time controller further includes a fourth generating module and a fourth timing module, wherein the fourth generating module is connected to the fourth timing module, configured to receive a data enable start hopping signal to trigger the The fourth timing module starts timing, and receiving the data enables the closing of the hopping signal to trigger the fourth timing module to stop timing; the fourth timing module is coupled to the third timing module, configured to be recorded in the fourth generation Module triggered The current timing is the current effective pixel display duration of the third timing module.
  • the time controller further includes a clock module for outputting a clock signal of a preset period; the clock module is respectively connected to the third timing module and the fourth timing module, and the third timing module and the fourth The timing modules are each configured to accumulate the number of cycles of the clock signal as the timing duration when it is clocked.
  • the idle driving chip includes a gate driving chip, a source driving chip, a level conversion chip or a power management chip.
  • the present invention also provides a display device including a display driving circuit using the first display driving circuit described above.
  • the present invention also provides a display device comprising a display driving circuit, wherein the display driving circuit adopts the second display driving circuit described above.
  • the first display driving circuit provided by the present invention is respectively connected to the first timing module and the driving chip by using the first generating module, and the first generating module generates a line start signal to trigger the first timing module to start timing and trigger the idle driving chip.
  • the so-called line start signal refers to a trigger signal indicating the start of one frame of image
  • the so-called idle drive chip refers to a drive chip that does not need to work during the display period of the non-effective pixel
  • the first timing module is connected to the drive chip.
  • the first timing module triggers the driving chip off that is idle during the non-effective pixel display duration when its current timing duration is equal to the effective pixel display duration.
  • the display driving circuit can not only turn on the idle driving chip in the effective pixel display time period, but also ensure the effective output of the effective pixel; and can also turn off the idle driving chip in the non-effective pixel display time to avoid idle.
  • the driving chip is turned on to generate power consumption, thereby meeting the current energy saving requirements of the display device and improving the quality of the display device.
  • the second display driving circuit provided by the present invention is respectively connected to the third timing module and the driving chip by the third generating module, and the third generating module generates a driving start chip that triggers the third timing module to start timing and idle. Turning on, and generating a line end hopping signal triggers the driving chip to be idle during the non-effective pixel display duration.
  • the so-called line start hopping signal refers to a hopping signal indicating the start of one frame of image
  • the so-called end-of-line hopping signal means A hopping signal indicating the end of the effective pixel display of one frame of image
  • the so-called idle driving chip refers to a driving chip that does not need to work during the display period of the non-effective pixel
  • the third timing module is connected to the driving chip, and the third timing is The module is at its current timing When the effective pixel display duration is equal to trigger the third generation module to generate a line end transition signal.
  • the display driving circuit can not only turn on the driving chip during the effective pixel display time to ensure the normal output of the effective pixel; but also can turn off the idle driving chip in the non-effective pixel display time to avoid the idle driving chip.
  • the power is turned on, power consumption is generated, so that the current energy saving requirements of the display device can be satisfied, and the quality of the display device can be improved.
  • the present invention provides a first display device, which adopts the first display driving circuit provided by the present invention, which can prevent the idle driving chip from being turned on and generate power consumption, thereby meeting the current energy saving requirements of the display device and improving The quality of the display device.
  • the present invention provides a second display device, which adopts the second display driving circuit provided by the present invention, which can prevent the idle driving chip from being turned on and generate power consumption, thereby meeting the current energy saving requirements of the display device and improving The quality of the display device.
  • FIG. 1 is a schematic block diagram of a display driving circuit according to a first embodiment of the present invention
  • FIG. 2 is a schematic view showing the application of the display driving circuit shown in FIG. 1;
  • FIG. 3 is a timing diagram of signals of the display driving circuit of FIG. 2;
  • FIG. 4 is a schematic block diagram of a display driving circuit according to a second embodiment of the present invention.
  • FIG. 5 is a schematic diagram of applying the display driving circuit shown in FIG. 4;
  • FIG. 6 is a timing diagram of signals of the display driving circuit of FIG. 5.
  • FIG. 1 is a schematic block diagram of a display driving circuit according to a first embodiment of the present invention
  • FIG. 2 is a schematic diagram of a display driving circuit shown in FIG. 1
  • FIG. 3 is a timing chart of signals of the display driving circuit of FIG.
  • the display driving circuit provided in this embodiment is configured to output a scan voltage signal and a data voltage signal to the gate line 101 and the data line 102 on the array substrate 10 , for example, in FIG. 3 .
  • Data (Data) output signal is included in the display driving circuit.
  • the display driving circuit includes a time controller (Tcon) and a driving chip.
  • the driving chip includes a gate driving chip (GOA chip) disposed on the array substrate 10, a source driving chip (Source COF) disposed on the flexible wiring board, and is connected to the time controller and the source a level shifting IC and a power management chip (PMIC) between the driving chips; the level converting chip is connected to the gate driving chip by the source driving chip, and drives the driving signal of the GOA generated by the time controller. Converted to a desired GOA signal with a large voltage difference.
  • GOA chip gate driving chip
  • Source COF source driving chip
  • PMIC power management chip
  • the time controller includes a first generation module and a first timing module.
  • the first generation module is respectively connected to the first timing module and the driving chip, and is configured to generate a line start signal to trigger the first timing module to start timing and the idle driving chip to be turned on.
  • the line start signal refers to a trigger signal indicating the start of one frame of image, which is also referred to as a "frame start signal”.
  • the idle driver chip refers to a driver chip that does not need to work in the length T2 of the non-effective pixel display.
  • the idle driving chip may include a gate driving chip, a source driving chip, a level conversion chip, and a power management chip.
  • the first timing module triggers the gate drive chip, the source driver chip, the level shifting chip, and/or the power management chip to be turned on or off. It can be understood that the first timing module can implement all or part of the idle driving chips according to the connection relationship of the power supply lines of the respective idle driving chips in the actual driving circuit. For example, if the power management chip is configured to supply power to all other idle driver chips, only the first timing module is required to turn the power management chip on or off to enable or disable all idle driver chips.
  • the signal that the first timing module triggers the idle driver chip to be turned off is referred to as the non-effective pixel display start signal S BlankingStart , as shown in FIG.
  • the invention does not limit the manner in which the first timing module triggers the idle driving chip to be turned on or off, and not only the direct triggering mode but also the indirect triggering mode, and the so-called indirect triggering mode refers to triggering by other devices.
  • the display driving circuit can not only turn on the idle driving chip in the effective pixel display time length T1 to ensure the effective output of the effective pixel; but also can turn off the idle driving chip in the non-effective pixel display time length T2 to avoid The idle driving chip is in an on state to generate power consumption, thereby meeting the current energy saving requirements of the display device and improving the quality of the display device.
  • the display driving circuit further includes a second generating module and a second timing module.
  • the second generating module is connected to the second timing module and configured to receive data
  • the hopping signal can be activated to trigger the second timing module to start timing, and the receiving data enables the hopping signal to be turned off to trigger the second timing module to stop timing.
  • the data enable start transition signal refers to a start signal indicating an effective pixel display of one frame image, specifically a signal whose low level jumps to a high level.
  • the data enable off transition signal is a signal indicating that the effective pixel display of one frame of image is turned off, specifically a signal whose high level jumps to a low level.
  • the data enable start transition signal can also be a high level transition to a low level signal.
  • the data enables the signal to turn off the transition signal to a low level.
  • the second timing module is connected to the first timing module, and is configured to record that the current timing duration triggered by the second generation module is the current effective pixel display duration of the first timing module. Since the second timing module starts timing when the data is enabled to enable the hopping signal, and stops counting until the data is enabled to turn off the hopping signal, the current effective pixel display duration gradually accumulates from the initial value in one frame period.
  • the effective pixel display time is T1.
  • the row start signal generated by the first generation module is delayed relative to the data generated by the second generation module to enable the off-jump signal to be delayed for a certain time (the time may be at least one clock cycle or one frame period), so as to know the current The effective pixel display duration, and then the first timing module starts timing and determines whether the current timing duration and the effective pixel display duration T1 are equal.
  • the effective pixel display duration T1 can be automatically obtained by the second generation module and the second timing module. Therefore, the display driving circuit provided in this embodiment can be applied to a display device in which the effective pixel display duration T1 is unknown, so that the applicability and practicability of the display driving circuit can be improved.
  • the effective pixel display duration T1 can be automatically obtained without using the second generation module and the second timing module, and the known effective pixel display duration T1 is directly set in the first timing module.
  • the embodiment provides that the display driving circuit further includes a clock module configured to output a clock signal of a preset period.
  • the clock module is respectively connected to the first timing module and the second timing module, and the first timing module and the second timing module are respectively configured to accumulate the number of cycles of the clock signal as the timing duration when counting.
  • the first timing module is configured to trigger the idle driver chip off within the non-effective pixel display time length T2 in the present embodiment, the present invention is not limited thereto. In practical applications, the first timing module can also turn off other non-working devices such as the light source that triggers the backlight module in the non-effective pixel display duration T2.
  • FIG. 4 is a schematic block diagram of a display driving circuit according to a second embodiment of the present invention
  • FIG. 5 is a schematic diagram of a display driving circuit shown in FIG. 4
  • FIG. 6 is a timing chart of signals of the display driving circuit of FIG.
  • the display driving circuit provided in this embodiment is configured to output a scan voltage signal and a data voltage signal to the gate line 101 and the data line 102 on the array substrate 10, for example, in FIG. Data (Data) output signal.
  • the display driving circuit includes a time controller (Tcon) and a driving chip.
  • the driving chip includes a GOA disposed on the array substrate 10, a source driving chip disposed on the flexible wiring board, a level conversion chip and a power management chip connected between the time controller and the source driving chip, and the like.
  • the level conversion chip is connected to the gate driving chip by the source driving chip, and converts the driving signal of the driving GOA generated by the time controller into a GOA signal with a large voltage variation difference.
  • the time controller includes a third generation module and a third timing module.
  • the third generating module is respectively connected to the third timing module and the driving chip, configured to generate a line start hopping signal to trigger the third timing module to start timing and idle driving chip turn-on, and generate a line end hopping signal to trigger the non-active
  • the pixel display shows that the idle driver chip in the T2 is off.
  • the line start hopping signal refers to a hopping signal indicating the start of one frame of image
  • the line ending hopping signal refers to a hopping signal indicating the end of effective pixel display of one frame of image.
  • the signal that the third generation module triggers the driving chip to be turned on or off is referred to as a “line start end transition signal”. As shown in FIG.
  • the line start hopping signal is specifically a signal whose low level jumps to a high level
  • the line end hopping signal is a signal whose high level jumps to a low level.
  • the line start transition signal can also be a signal that transitions from a high level to a low level.
  • the end-of-line transition signal is a signal that goes low to a high level.
  • the idle driving chip refers to a chip that does not need to work in the length T2 of the non-effective pixel display, and may include a gate driving chip, a source driving chip, a level conversion chip, and a power management chip.
  • the third generation module triggers the gate drive chip, the source driver chip, the level shifting chip, and/or the power management chip to be turned on or off.
  • the first timing module can implement all or part of the idle driving chips according to the connection relationship of the power supply lines of the respective idle driving chips in the actual driving circuit. For example, if the power management chip is configured to supply power to all other idle driver chips, only the first timing module is required to turn the power management chip on or off to enable or disable all idle driver chips.
  • the third timing module is connected to the third generation module, configured to be in its current timing, etc.
  • the invention does not limit the manner in which the third generation module triggers the idle driver chip to be turned on or off, and not only the direct trigger mode but also the indirect trigger mode, and the so-called indirect trigger mode refers to triggering by other devices.
  • the display driving circuit can not only turn on the idle driving chip in the effective pixel display time T 1 to ensure the effective output of the effective pixel; but also can turn off the idle driving chip in the non-effective pixel display time length T2, The idle driving chip is prevented from being turned on to generate power consumption, thereby meeting the current energy saving requirements of the display device and improving the quality of the display device.
  • the display driving circuit further includes a fourth generating module and a fourth timing module.
  • the fourth generating module is connected to the fourth timing module, configured to receive the data enable trigger signal to trigger the fourth timing module to start timing, and receive the data enable to turn off the jump signal to trigger the fourth timing module to stop timing.
  • the data enable start transition signal refers to a start signal indicating an effective pixel display of one frame image, specifically a signal whose low level jumps to a high level.
  • the data enable off transition signal is a signal indicating that the effective pixel display of one frame of image is turned off, specifically a signal whose high level jumps to a low level.
  • the data enable start transition signal can also be a high level transition to a low level signal.
  • the data enables the signal to turn off the transition signal to a low level.
  • the fourth timing module is connected to the third timing module, and is configured to record that the current timing duration triggered by the fourth generation module is the current effective pixel display duration of the third timing module. Since the fourth timing module starts timing when the data is enabled to enable the hopping signal, and stops counting until the receiving data enables the hopping signal to be turned off, the current effective pixel display duration gradually increases from the initial value to one frame period.
  • the effective pixel display time is T1.
  • the line start end hopping signal generated by the third generating module is delayed relative to the data generated by the fourth generating module to start the off hopping signal for a certain time (the time may be at least one clock period), so as to know that the current valid is available first.
  • the pixel display duration, and then the third timing module starts timing and determines whether the current timing duration and the effective pixel display duration T1 are equal.
  • the effective pixel display duration T1 can be automatically obtained by means of the fourth generation module and the fourth timing module. Therefore, the display driving circuit provided in this embodiment can be applied to a display device in which the effective pixel display duration T1 is unknown, so that the display driving circuit can be improved. Applicability and practicality.
  • the fourth generation module and the fourth timing module are not required to automatically acquire the effective pixel display duration T1, and the known effective pixel display duration T1 is directly set in the third timing module in advance.
  • the embodiment provides that the display driving circuit further includes a clock module configured to output a clock signal of a preset period.
  • the clock module is respectively connected to the first timing module and the second timing module, and the first timing module and the second timing module are respectively configured to accumulate the number of cycles of the clock signal as the timing duration when counting.
  • the third generation module is configured to trigger the idle driver chip off within the non-effective pixel display time length T2 in the present embodiment, the present invention is not limited thereto. In an actual application, the third generation module may also turn off other non-working devices such as a light source that triggers the backlight module in the non-effective pixel display duration T2.
  • the present invention further provides a display device including a display driving circuit using the display driving circuit provided in the first embodiment.
  • the display device provided in this embodiment adopts the display driving circuit provided by the first embodiment of the present invention, which can prevent the idle driving chip from being turned on and generate power consumption, thereby meeting the current requirements for energy saving of the display device and improving The quality of the display device.
  • the present invention further provides a display device including a display driving circuit, which uses the display driving circuit provided in the second embodiment.
  • the display device provided in this embodiment adopts the display driving circuit provided by the second embodiment of the present invention, which can prevent the idle driving chip from being turned on and generate power consumption, thereby meeting the current energy saving requirements of the display device and improving The quality of the display device.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种显示驱动电路及显示装置，显示驱动电路包括时间控制器和驱动芯片，时间控制器包括第一产生模块和第一计时模块。第一产生模块分别与第一计时模块和驱动芯片相连，配置成产生行开始信号以触发第一计时模块开始计时和空闲的驱动芯片开启。第一计时模块与驱动芯片相连，配置成在其当前计时时长等于有效像素显示时长（T1）时触发在非有效像素显示时长（T2）内空闲的驱动芯片关闭。该显示驱动电路可以避免空闲的驱动芯片处于开启状态而产生功耗，从而可以满足目前对显示装置的节能性的要求，提高显示装置的品质。

Description

显示驱动电路及显示装置 技术领域
本发明属于液晶显示技术领域，具体涉及一种显示驱动电路及显示装置。
背景技术
阵列基板行驱动(Gate-driver On Array，GOA)技术是目前液晶显示领域的一种广泛使用的技术。具体地，在GOA中，栅极驱动芯片被安装在阵列基板上，以节约栅极驱动芯片成本和降低栅极侧的显示像素区到边框的距离。但是，GOA需要电压变化的压差远远大于一般数字电压范围的驱动信号来驱动。为此，需要在时间控制器(Timing Controller，Tcon)和GOA之间连接电平转换芯片(Level Shift IC)，借助电平转换芯片将时间控制器产生的驱动GOA的驱动信号转换成所需的电压变化压差较大的GOA信号。
然而，采用上述具有电平转换芯片的显示驱动电路在实际应用中发现仍然存在以下问题。由于在每一帧图像显示的过程中，系统设定的显示像素(设定像素或v-total)的个数比实际显示的像素(有效像素)的个数多。设定像素显示时长为一个帧周期，有效像素显示时长少于一个帧周期。因此，在一帧图像的有效像素显示完成之后且下一帧开始之前存在一定的时间空闲(即，帧周期减去有效像素显示时长)。该时间空闲被称为非有效像素显示时长(或Blanking时长)。由于在Blanking时长内，显示驱动不需要对像素单元充电，但是电平转换芯片仍然出于开启状态。也就是说，电平转换芯片仍然会产生一定功耗，从而不满足目前对显示装置的节能性的要求，造成显示装置的品质差。
因此，目前亟需一种节能性较好的显示驱动器和显示装置。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提出了一种显示驱动电路及显示装置，可以避免空闲的驱动芯片处于开启状态而产生功耗，从而可以满足目前对显示装置的节能性的要求，提高显示装置的品质。
为解决上述问题之一，本发明提供了一种显示驱动电路，其包括时间控制器和驱动芯片，所述时间控制器包括第一产生模块和第一计时模块；其中，所述第一产生模块分别与所述第一计时模块和所述驱动芯片相连，配置成产生行开始信号触发所述第一计时模块开始计时和空闲的所述驱动芯片开启；所述第一计时模块与驱动芯片相连，配置成在其当前计时时长等于有效像素显示时长时触发在非有效像素显示时长内空闲的所述驱动芯片关闭。
优选地，所述时间控制器还包括第二产生模块和第二计时模块，其中，所述第二产生模块与所述第二计时模块相连，配置成接收数据使能启动跳变信号触发所述第二计时模块开始计时，以及接收所述数据使能关闭跳变信号触发所述第二计时模块停止计时；所述第二计时模块与所述第一计时模块相连，配置成记录在所述第二产生模块触发下的当前计时时长为第一计时模块的当前有效像素显示时长。
其中，所述时间控制器还包括配置成输出预设周期的时钟信号的时钟模块；所述时钟模块分别与所述第一计时模块和所述第二计时模块相连，第一计时模块和所述第二计时模块分别配置成在其计时时累积所述时钟信号的周期数作为计时时长。
其中，空闲的所述驱动芯片包括栅极驱动芯片、源极驱动芯片、电平转换芯片或电源管理芯片。
本发明还提供一种显示驱动电路，包括时间控制器和驱动芯片，所述时间控制器包括第三产生模块和第三计时模块，其中所述第三产生模块分别与所述第三计时模块和所述驱动芯片相连，配置成产生行开始跳变信号时触发所述第三计时模块开始计时和空闲的所述驱动芯片开启，以及产生行结束跳变信号触发在非有效像素显示时长内空闲的所述驱动芯片关闭；所述第三计时模块与所述第三产生模块相连，配置成在其当前计时时长等于所述有效像素显示时长时触发所述第三产生模块产生所述行结束跳变信号。
优选地，所述时间控制器还包括第四产生模块和第四计时模块，其中，所述第四产生模块与所述第四计时模块相连，配置成接收数据使能启动跳变信号触发所述第四计时模块开始计时，以及接收所述数据使能关闭跳变信号触发所述第四计时模块停止计时；第四计时模块与所述第三计时模块相连，配置成记录在所述第四产生模块触发下的 当前计时时长为所述第三计时模块的当前有效像素显示时长。
其中，所述时间控制器还包括用于输出预设周期的时钟信号的时钟模块；所述时钟模块分别与所述第三计时模块和第四计时模块相连，第三计时模块和所述第四计时模块分别配置成在其计时时累积所述时钟信号的周期数作为计时时长。
其中，空闲的所述驱动芯片包括栅极驱动芯片、源极驱动芯片、电平转换芯片或电源管理芯片。
本发明还提供一种显示装置，包括显示驱动电路，所述显示驱动电路采用上述第一种显示驱动电路。
本发明还提供一种显示装置，包括显示驱动电路，所述显示驱动电路采用上述第二种显示驱动电路。
本发明具有以下有益效果：
本发明提供的第一种显示驱动电路，其借助第一产生模块分别与第一计时模块和驱动芯片相连，第一产生模块产生行开始信号会触发第一计时模块开始计时和触发空闲的驱动芯片开启，所谓行开始信号是指表示一帧图像开始的触发信号，所谓空闲的驱动芯片是指在非有效像素显示时长内不需要工作的驱动芯片；另外，还借助第一计时模块与驱动芯片相连，第一计时模块在其当前计时时长等于有效像素显示时长时触发在非有效像素显示时长内空闲的驱动芯片关闭。由上可知，采用该显示驱动电路不仅可以在有效像素显示时长内开启空闲的驱动芯片，以保证有效像素正常输出；而且还可以在非有效像素显示时长内关闭空闲的驱动芯片，以避免空闲的驱动芯片处于开启状态而产生功耗，从而可以满足目前对显示装置的节能性的要求，提高显示装置的品质。
本发明提供的第二种显示驱动电路，其借助第三产生模块分别与第三计时模块和驱动芯片相连，第三产生模块产生行开始跳变信号触发第三计时模块开始计时和空闲的驱动芯片开启，以及产生行结束跳变信号时触发在非有效像素显示时长内空闲的驱动芯片关闭，所谓行开始跳变信号是指表示一帧图像开始的跳变信号，所谓行结束跳变信号是指表示一帧图像的有效像素显示结束的跳变信号，所谓空闲的驱动芯片是指在非有效像素显示时长内不需要工作的驱动芯片；另外，借助第三计时模块与驱动芯片相连，第三计时模块在其当前计时时长 等于有效像素显示时长时触发第三产生模块产生行结束跳变信号。由上可知，采用该显示驱动电路不仅可以在有效像素显示时长内开启驱动芯片，以保证有效像素正常输出；而且还可以在非有效像素显示时长内关闭空闲的驱动芯片，以避免空闲的驱动芯片处于开启状态而产生功耗，从而可以满足目前对显示装置的节能性的要求，提高显示装置的品质。
本发明提供第一种显示装置，其采用本发明提供的第一种显示驱动电路，可以避免空闲的驱动芯片处于开启状态而产生功耗，从而可以满足目前对显示装置的节能性的要求，提高显示装置的品质。
本发明提供第二种显示装置，其采用本发明提供的第二种显示驱动电路，可以避免空闲的驱动芯片处于开启状态而产生功耗，从而可以满足目前对显示装置的节能性的要求，提高显示装置的品质。
附图说明
图1为本发明第一实施例提供的显示驱动电路的原理框图；
图2为应用图1所示的显示驱动电路的示意图；
图3为图2的显示驱动电路的信号的时序图；
图4为本发明第二实施例提供的显示驱动电路的原理框图；
图5为应用图4所示的显示驱动电路的示意图；以及
图6为图5的显示驱动电路的信号的时序图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图来对本发明提供的显示驱动电路及显示装置进行详细描述。
图1为本发明第一实施例提供的显示驱动电路的原理框图；图2为应用图1所示的显示驱动电路的示意图；并且图3为图2的显示驱动电路的信号的时序图。请一并参阅图1、图2和图3，本实施例提供的显示驱动电路配置成向阵列基板10上的栅极线101和数据线102输出扫描电压信号和数据电压信号，例如图3中的数据(Data)输出信号。具体地，显示驱动电路包括时间控制器(Tcon)和驱动芯片。驱动芯片包括设置在阵列基板10上的栅极驱动芯片(GOA芯片)、设置在柔性线路板上的源极驱动芯片(Source COF)、连接在时间控制器和源极 驱动芯片之间的电平转换芯片(level shift IC)和电源管理芯片(PMIC)等；电平转换芯片借助源极驱动芯片和栅极驱动芯片相连，将时间控制器产生的驱动GOA的驱动信号转换成所需的电压变化压差较大的GOA信号。
时间控制器包括第一产生模块和第一计时模块。第一产生模块分别与第一计时模块和驱动芯片相连，配置成产生行开始信号以触发第一计时模块开始计时和空闲的驱动芯片开启。此处，行开始信号是指表示一帧图像开始的触发信号，又称为“帧开始信号”。空闲的驱动芯片是指在非有效像素显示时长T2内不需要工作的驱动芯片。具体地，在本实施例中，空闲的驱动芯片可包括栅极驱动芯片、源极驱动芯片、电平转换芯片和电源管理芯片。为此，第一计时模块触发栅极驱动芯片、源极驱动芯片、电平转换芯片和/或电源管理芯片开启或关闭。可以理解，第一计时模块可以根据实际显示驱动电路中各个空闲的驱动芯片的供电线路的连接关系，来实现开启或关闭所有或部分空闲的驱动芯片。例如，若电源管理芯片配置成向其他所有的空闲的驱动芯片供电，则仅需要第一计时模块开启或关闭该电源管理芯片即可实现开启或关闭所有空闲的驱动芯片。
第一计时模块与驱动芯片相连，配置成在其当前计时时长等于有效像素显示时长T1时触发在非有效像素显示时长T2内空闲的驱动芯片关闭，其中T1+T2＝T，T为帧周期。在这种情况下，第一计时模块触发空闲的驱动芯片关闭的信号被称为非有效像素显示开始信号SBlankingStart，如图3所示。
本发明并不限定第一计时模块触发空闲的驱动芯片开启或关闭的方式，不仅可以采用直接触发方式，还可以通过间接触发方式，所谓间接触发方式是指通过其他器件触发。
由上可知，采用该显示驱动电路不仅可以在有效像素显示时长T1内开启空闲的驱动芯片，以保证有效像素正常输出；而且还可以在非有效像素显示时长T2内关闭空闲的驱动芯片，以避免空闲的驱动芯片处于开启状态而产生功耗，从而可以满足目前对显示装置的节能性的要求，提高显示装置的品质。
优选地，在本实施例中，显示驱动电路还包括第二产生模块和第二计时模块。第二产生模块与第二计时模块相连，配置成接收数据使 能启动跳变信号以触发第二计时模块开始计时，以及接收数据使能关闭跳变信号以触发第二计时模块停止计时。此处，数据使能启动跳变信号是指表示一帧图像的有效像素显示的开始信号，具体为低电平跳变为高电平的信号。数据使能关闭跳变信号是指表示一帧图像的有效像素显示的关闭信号，具体为高电平跳变为低电平的信号。当然，在实际应用中，数据使能启动跳变信号还可以为高电平跳变为低电平的信号。对应地，数据使能关闭跳变信号为低电平跳变为高电平的信号。
第二计时模块与第一计时模块相连，配置成记录在第二产生模块触发下的当前计时时长为第一计时模块的当前有效像素显示时长。由于第二计时模块自接收数据使能启动跳变信号时开始计时，并且直至接收数据使能关闭跳变信号时停止计时，因此在一个帧周期中，当前有效像素显示时长自初始值逐渐累积至有效像素显示时长T1。
可以理解，第一产生模块产生的行开始信号相对第二产生模块产生的数据使能启动关闭跳变信号延迟一定时间(该时间可以为至少一个时钟周期或一个帧周期)，以便于先获知当前有效像素显示时长，再使第一计时模块开始计时以及判断其当前计时时长和有效像素显示时长T1是否相等。
由上可知，借助第二产生模块和第二计时模块可以自动获得有效像素显示时长T1。因此，本实施例提供的显示驱动电路可以应用在有效像素显示时长T1未知的显示装置中，从而可以提高显示驱动电路的适用性和实用性。当然，在实际应用中，还可以不需要借助第二产生模块和第二计时模块自动获得有效像素显示时长T1，而预先直接在第一计时模块内设置已知的有效像素显示时长T1。
另外，为实现第一定时模块和第二定时模块定时，本实施例提供显示驱动电路还包括配置成输出预设周期的时钟信号的时钟模块。时钟模块分别与第一计时模块和第二计时模块相连，第一计时模块和第二计时模块分别配置成在其计时时累积时钟信号的周期数作为计时时长。
需要说明的是，尽管在本实施例中第一计时模块配置成在非有效像素显示时长T2内触发空闲的驱动芯片关闭，但是本发明并不局限于此。在实际应用中，第一计时模块还可以在非有效像素显示时长T2内触发背光源模组的光源等其他不需要工作的器件关闭。
图4为本发明第二实施例提供的显示驱动电路的原理框图，图5为应用图4所示的显示驱动电路的示意图，并且图6为图5的显示驱动电路的信号的时序图。请一并参阅图4、图5和图6，本实施例提供的显示驱动电路用于向阵列基板10上的栅极线101和数据线102输出扫描电压信号和数据电压信号，例如图6中的数据(Data)输出信号。具体地，显示驱动电路包括时间控制器(Tcon)和驱动芯片。驱动芯片包括设置在阵列基板10上的GOA、设置在柔性线路板上的源极驱动芯片、连接在时间控制器和源极驱动芯片之间的电平转换芯片和电源管理芯片等。电平转换芯片借助源极驱动芯片和栅极驱动芯片相连，将时间控制器产生的驱动GOA的驱动信号转换成所需的电压变化压差较大的GOA信号。
时间控制器包括第三产生模块和第三计时模块。第三产生模块分别与第三计时模块和驱动芯片相连，配置成产生行开始跳变信号以触发第三计时模块开始计时和空闲的驱动芯片开启，以及产生行结束跳变信号以触发在非有效像素显示时长T2内空闲的驱动芯片关闭。此处，行开始跳变信号是指表示一帧图像开始的跳变信号，行结束跳变信号是指表示一帧图像的有效像素显示结束的跳变信号。具体地，第三产生模块触发驱动芯片开启或关闭的信号被称为“行开始结束跳变信号”。如图6所示，行开始跳变信号具体为低电平跳变为高电平的信号，并且行结束跳变信号具体为高电平跳变为低电平的信号。当然，在实际应用中，行开始跳变信号还可以为高电平跳变为低电平的信号。对应地，行结束跳变信号为低电平跳变为高电平的信号。
空闲的驱动芯片是指在非有效像素显示时长T2内不需要工作的芯片，并且可包括栅极驱动芯片、源极驱动芯片、电平转换芯片和电源管理芯片。为此，第三产生模块触发栅极驱动芯片、源极驱动芯片、电平转换芯片和/或电源管理芯片开启或关闭。可以理解，第一计时模块可以根据实际显示驱动电路中各个空闲的驱动芯片的供电线路的连接关系，来实现开启或关闭所有或部分空闲的驱动芯片。例如，若电源管理芯片配置成向其他所有的空闲的驱动芯片供电，则仅需要第一计时模块开启或关闭该电源管理芯片即可实现开启或关闭所有空闲的驱动芯片。
第三计时模块与第三产生模块相连，配置成在其当前计时时长等 于有效像素显示时长T1时触发第三产生模块产生行结束跳变信号，其中T1+T2＝T，T为帧周期。
本发明并不限定第三产生模块触发空闲的驱动芯片开启或关闭的方式，不仅可以采用直接触发方式，还可以通过间接触发方式，所谓间接触发方式是指通过其他器件触发。
由上可知，采用该显示驱动电路不仅可以在有效像素显示时长T 1内开启空闲的驱动芯片，以保证有效像素正常输出；而且还可以在非有效像素显示时长T2内关闭空闲的驱动芯片，以避免空闲的驱动芯片处于开启状态而产生功耗，从而可以满足目前对显示装置的节能性的要求，提高显示装置的品质。
优选地，在本实施例中，显示驱动电路还包括第四产生模块和第四计时模块。第四产生模块与第四计时模块相连，配置成接收数据使能启动跳变信号以触发第四计时模块开始计时，以及接收数据使能关闭跳变信号以触发第四计时模块停止计时。此处，数据使能启动跳变信号是指表示一帧图像的有效像素显示的开始信号，具体为低电平跳变为高电平的信号。数据使能关闭跳变信号是指表示一帧图像的有效像素显示的关闭信号，具体为高电平跳变为低电平的信号。当然，在实际应用中，数据使能启动跳变信号还可以为高电平跳变为低电平的信号。对应地，数据使能关闭跳变信号为低电平跳变为高电平的信号。
第四计时模块与第三计时模块相连，配置成记录在第四产生模块触发下的当前计时时长为第三计时模块的当前有效像素显示时长。由于第四计时模块自接收数据使能启动跳变信号时开始计时，并且直至接收数据使能关闭跳变信号时停止计时，因此在一个帧周期中，当前有效像素显示时长自初始值逐渐累积至有效像素显示时长T1。
可以理解，第三产生模块产生的行开始结束跳变信号相对第四产生模块产生的数据使能启动关闭跳变信号延迟一定时间(该时间可以为至少一个时钟周期)，以便于先获知当前有效像素显示时长，再使第三计时模块开始计时以及判断其当前计时时长和有效像素显示时长T1是否相等。
由上可知，借助第四产生模块和第四计时模块可以自动获得有效像素显示时长T1。因此，本实施例提供的显示驱动电路可以应用在有效像素显示时长T1未知的显示装置中，从而可以提高显示驱动电路的 适用性和实用性。当然，在实际应用中，还可以不需要第四产生模块和第四计时模块自动获取有效像素显示时长T1，而预先直接在第三计时模块内设置已知的有效像素显示时长T1。
另外，为实现第三定时模块和第四定时模块定时，本实施例提供显示驱动电路还包括配置成输出预设周期的时钟信号的时钟模块。时钟模块分别与第一计时模块和第二计时模块相连，第一计时模块和第二计时模块分别配置成在其计时时累积时钟信号的周期数作为计时时长。
需要说明的是，尽管在本实施例中第三产生模块配置成在非有效像素显示时长T2内触发空闲的驱动芯片关闭，但是本发明并不局限于此。在实际应用中，第三产生模块还可以在非有效像素显示时长T2内触发背光源模组的光源等其他不需要工作的器件关闭。
作为另外一个技术方案，本发明还提供一种显示装置，包括显示驱动电路，该显示驱动电路采用上述第一实施例提供的显示驱动电路。
本实施例提供的显示装置，其采用本发明第一实施例提供的显示驱动电路，可以避免空闲的驱动芯片处于开启状态而产生功耗，从而可以满足目前对显示装置的节能性的要求，提高显示装置的品质。
再作为另外一个技术方案，本发明还提供一种显示装置，包括显示驱动电路，该显示驱动电路采用上述第二实施例提供的显示驱动电路。
本实施例提供的显示装置，其采用本发明第二实施例提供的显示驱动电路，可以避免空闲的驱动芯片处于开启状态而产生功耗，从而可以满足目前对显示装置的节能性的要求，提高显示装置的品质。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (10)

  1. 一种显示驱动电路，其包括时间控制器和驱动芯片，其特征在于，所述时间控制器包括第一产生模块和第一计时模块；
    其中所述第一产生模块分别与所述第一计时模块和所述驱动芯片相连，配置成产生信号以触发所述第一计时模块开始计时和空闲的所述驱动芯片开启；以及
    其中所述第一计时模块与驱动芯片相连，配置成在其当前计时时长等于有效像素显示时长时触发在非有效像素显示时长内空闲的所述驱动芯片关闭。
  2. 根据权利要求1所述的显示驱动电路，其特征在于，所述时间控制器还包括第二产生模块和第二计时模块，
    其中所述第二产生模块与所述第二计时模块相连，配置成接收数据使能启动跳变信号以触发所述第二计时模块开始计时，以及接收所述数据使能关闭跳变信号以触发所述第二计时模块停止计时；以及
    其中所述第二计时模块与所述第一计时模块相连，配置成记录在所述第二产生模块触发下的当前计时时长为所述第一计时模块的当前有效像素显示时长。
  3. 根据权利要求1或2所述的显示驱动电路，其特征在于，所述时间控制器还包括配置成输出预设周期的时钟信号的时钟模块；
    所述时钟模块分别与所述第一计时模块和所述第二计时模块相连，所述第一计时模块和所述第二计时模块分别配置成在其计时时累积所述时钟信号的周期数作为计时时长。
  4. 根据权利要求1所述的显示驱动电路，其特征在于，空闲的所述驱动芯片包括栅极驱动芯片、源极驱动芯片、电平转换芯片或电源管理芯片。
  5. 一种显示驱动电路，包括时间控制器和驱动芯片，其特征在于，所述时间控制器包括第三产生模块和第三计时模块，其中
    所述第三产生模块分别与所述第三计时模块和所述驱动芯片相连，配置成产生行开始跳变信号以触发所述第三计时模块开始计时和空闲的所述驱动芯片开启，以及产生行结束跳变信号以触发在非有效像素显示时长内空闲的所述驱动芯片关闭；
    所述第三计时模块与所述第三产生模块相连，配置成在其当前计时时长等于所述有效像素显示时长时触发所述第三产生模块产生所述行结束跳变信号。
  6. 根据权利要求5所述的显示驱动电路，其特征在于，所述时间控制器还包括第四产生模块和第四计时模块，其中
    所述第四产生模块与所述第四计时模块相连，配置成接收数据使能启动跳变信号以触发所述第四计时模块开始计时，以及接收所述数据使能关闭跳变信号以触发所述第四计时模块停止计时；
    所述第四计时模块与所述第三计时模块相连，配置成记录在所述第四产生模块触发下的当前计时时长为所述第三计时模块的当前有效像素显示时长。
  7. 根据权利要求5或6所述的显示驱动电路，其特征在于，所述时间控制器还包括配置成输出预设周期的时钟信号的时钟模块；
    所述时钟模块分别与所述第三计时模块和第四计时模块相连，所述第三计时模块和所述第四计时模块分别配置成在其计时时累积所述时钟信号的周期数作为计时时长。
  8. 根据权利要求5所述的显示驱动电路，其特征在于，空闲的所述驱动芯片包括栅极驱动芯片、源极驱动芯片、电平转换芯片或电源管理芯片。
  9. 一种显示装置，包括如权利要求1-4中任意一项所述的显示驱动电路。
  10. 一种显示装置，包括如权利要求5-8中任意一项所述的显示驱动电路。
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