WO2016150114A1 - 阵列基板、阵列基板的制造方法和显示装置 - Google Patents
阵列基板、阵列基板的制造方法和显示装置 Download PDFInfo
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- WO2016150114A1 WO2016150114A1 PCT/CN2015/089445 CN2015089445W WO2016150114A1 WO 2016150114 A1 WO2016150114 A1 WO 2016150114A1 CN 2015089445 W CN2015089445 W CN 2015089445W WO 2016150114 A1 WO2016150114 A1 WO 2016150114A1
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- test
- array substrate
- interface
- test line
- working circuit
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Definitions
- the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method of fabricating an array substrate, and a display device.
- the array substrate is an important component of the display device, and the display area and the peripheral area of the array substrate are both provided with working circuits.
- some array substrates have complex structures, such as Low Temperature Poly-Silicon (LTPS) array substrates, and need to perform relevant tests on the working circuits on the LTPS array substrate in the production stage.
- LTPS Low Temperature Poly-Silicon
- the present disclosure provides an array substrate, a method of manufacturing the array substrate, and a display device.
- the technical solution is as follows:
- an array substrate comprising:
- test circuit connecting the working circuit interface and the test interface
- the test circuit includes at least one break point, and both ends of each of the break points on the test line are provided with conductive contacts penetrating to an upper surface of the array substrate.
- a disconnection point is set at a midpoint of at least one of the test lines.
- At least one of the test lines is provided with a disconnection point at both ends.
- the conductive contact penetrates from one end of the breaking point to the upper surface of the array substrate a via hole in which a conductive material extending to an upper surface of the array substrate is disposed.
- the distance between the conductive contacts at both ends of each of the break points is greater than 5 microns.
- the conductive contacts at both ends of each of the breaking points are electrically connected by a conductive silver paste.
- the at least one breaking point divides the test circuit into a plurality of sub-test lines, and the plurality of sub-test lines are formed on the same layer or different layers on the array substrate.
- the working circuit interface includes a working circuit interface of the display area and a working circuit interface of the peripheral area;
- the test interface includes a test interface of the display area and a test interface of the peripheral area;
- the test circuit includes a test line of the display area and a test line of the peripheral area;
- the test circuit of the display area is connected to the working circuit interface of the display area and the test interface of the display area;
- the test line of the peripheral area connects the working circuit interface of the peripheral area and the test interface of the peripheral area.
- a method of fabricating an array substrate comprising:
- test line including at least one break point on the substrate, the two ends of the test line being respectively connected to the working circuit interface and the test interface;
- a disconnection point is set at a midpoint of at least one of the test lines.
- At least one of the test lines is provided with a disconnection point at both ends.
- the conductive contact is a via formed with a conductive material
- a conductive substance extending to an upper surface of the array substrate is formed in the via hole.
- the distance between the conductive contacts at both ends of each of the break points is greater than 5 microns.
- the conductive contacts that open all ends of the disconnection point include:
- Conductive contacts at both ends of all of the break points are conducted by conductive silver paste.
- the forming a test circuit including at least one break point on the substrate includes:
- test line and the source/drain pattern including at least one break point are formed on the substrate on which the insulating layer is formed.
- the forming a test circuit including at least one break point on the substrate includes:
- the working circuit interface includes a working circuit interface of the display area and a working circuit interface of the peripheral area;
- the test interface includes a test interface of the display area and a test interface of the peripheral area;
- the test circuit includes a test line of the display area and a test line of the peripheral area;
- the test circuit of the display area is connected to the working circuit interface of the display area and the test interface of the display area;
- the test line of the peripheral area connects the working circuit interface of the peripheral area and the test interface of the peripheral area.
- a display device comprising: the array substrate provided by the first aspect.
- the test circuit When the test circuit is formed, at least one disconnection point is set on the test line, and the sub-test line formed by dividing the disconnection point is not too long, thereby reducing the antenna effect generated when the test line is too long, and solving the problem.
- the slender test circuit in the related art tends to accumulate more charges due to the antenna effect, which may damage the working circuit; and the effect that the test circuit does not damage the working circuit due to the antenna effect is achieved.
- FIG. 1 is a schematic structural diagram of an array substrate according to an exemplary embodiment
- Figure 2 is a left side cross-sectional view of the array substrate shown in Figure 1 at a break point;
- FIG. 3 is a schematic structural diagram of another array substrate according to an exemplary embodiment
- Figure 4 is a left side cross-sectional view of the array substrate shown in Figure 3 at a break point;
- FIG. 5 is a schematic structural view showing a plurality of sub-test lines formed in different layers on the array substrate in the array substrate shown in FIG. 3;
- FIG. 6 is a flow chart showing a method of fabricating an array substrate according to an exemplary embodiment
- FIG. 7 is a flow chart showing another method of fabricating an array substrate according to an exemplary embodiment
- FIG. 8 to 14 are schematic views showing the structure of the substrate in the embodiment shown in Fig. 7.
- an array substrate is provided with test lines respectively connected to working circuit interfaces (working circuit interfaces and working circuits electrically connected) at one end in the longitudinal direction of the array substrate and on the array substrate
- working circuit interfaces working circuit interfaces and working circuits electrically connected
- the test interface at the other end of the length direction is then directly input to the test line through the test interface during the test. Since the test circuit is connected to the working circuit, the working circuit can be tested.
- the length of the test line is usually long, and the elongated test line is likely to accumulate more charges due to the antenna effect, which may damage the working circuit.
- FIG. 1 is a schematic structural diagram of an array substrate according to an exemplary embodiment.
- the array substrate can include:
- test circuit 103 connecting the working circuit interface 101 and the test interface 102.
- test line 103 includes at least one break point A, and both ends of each break point on the test line 103 are provided with conductive contacts (not shown in FIG. 1) penetrating to the upper surface of the array substrate.
- the conduction of the test line can be achieved by turning on the conductive contacts at both ends of all the breaking points.
- the array substrate provided by the embodiment of the present disclosure is configured such that at least one break point is set on the test line when the test line is formed, and the sub-test line formed by dividing the break point is not too long.
- the antenna effect generated when the test line is too long is solved, and the slender test circuit in the related art is easy to accumulate more charges due to the antenna effect, and these charges may damage the working circuit; the test circuit is not caused by the antenna. The effect of damaging the working circuit.
- FIG. 2 it is a left-side cross-sectional view at the break point A in the array substrate shown in FIG. 1, and both ends of each break point A on the test line 103 are provided with a through-surface S on the array substrate. Conductive contacts 105.
- FIG. 3 shows a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure, which adds more preferable components to the array substrate shown in FIG.
- the array substrate provided by the embodiment of the present disclosure is made to have better performance.
- the working circuit interface 101 includes a working circuit interface 1011 of the display area and a working circuit interface 1012 of the peripheral area.
- the test interface 102 includes a test interface 1021 of a display area and a test interface 1022 of a peripheral area.
- Test line 103 includes test line 1031 for the display area and test line 1032 for the peripheral area.
- the test interface 102 can be an indium tin oxide (ITO) interface on the ITO layer. It should be noted that the embodiment of the present disclosure does not limit the position of the test interface, and the actual position may be adjusted.
- ITO indium tin oxide
- connection mode is: the test circuit 1031 of the display area is connected to the working circuit interface 1011 of the display area and the test interface 1021 of the display area; the test line 1032 of the peripheral area is connected to the surrounding area.
- the working circuit interface 1012 and the test interface 1022 of the peripheral area are connected to the test circuit interface 1031 of the display area.
- test line 1031 of the display area and the disconnection point of the test line 1032 of the peripheral area may be the same or different, and the test line 103 may further include a circuit for testing other working circuits. No restrictions are imposed.
- a break point A is provided, that is, the break point A divides at least one line in the test line 103 into two sub test lines of equal length, and thus the midpoint Setting the break point A can greatly reduce the antenna effect produced by the test line with a break point.
- at least one of the test lines 103 is provided with a break point A at both ends thereof, and the break point A disconnects the test line from the working circuit, thereby preventing the charge accumulated by the test line due to the antenna effect from being transmitted to the working circuit. .
- a disconnection point is set in such a manner that the test line 1031 of the display area and the test line 1032 of the peripheral area are all provided with at least one break point A.
- the test line of the break point A is set in the display area.
- the both ends of the test line 1031 of the display area and the test line 1032 of the peripheral area are also provided with a break point A.
- the conductive contact 105 is a via hole extending from one end of the break point to the S surface on the array substrate.
- the conductive material 1051 extending to the upper surface of the array substrate is disposed in the via hole.
- the distance 1 between the conductive contacts at each end of each break point is greater than 5 microns.
- the conductive material 1051 may be metal or ITO or the like.
- the conductive contacts at both ends of each break point can be electrically connected by conductive silver glue (adhesive with certain conductivity after drying).
- conductive silver glue adheresive with certain conductivity after drying.
- Conductive silver glue is dropped at the breaking point, so that the conductive contacts at both ends of each breaking point are respectively connected. It should be noted that the conductive contacts at both ends of each breaking point can also be connected by soldering.
- At least one break point divides the test line into a plurality of sub-test lines, and the plurality of sub-test lines are formed on the same layer or different layers on the array substrate.
- a plurality of sub-test lines divided by the break point A in the array substrate shown in FIG. 4 are formed in the same layer on the array substrate, wherein the sub-test line 103a and the sub-test line 103b are formed in the same layer.
- the test lines may be formed in the same layer as the gate line pattern or in the same layer as the source and drain patterns.
- FIG. 5 it is a schematic structural diagram of an array substrate when a plurality of sub-test lines are formed on different layers on the array substrate, and the sub-test lines formed on the substrate may be referred to as a first sub-test line and formed on the insulating layer.
- the sub-test line is referred to as a second sub-test line
- the first sub-test line 103 c and the second sub-test line 103d are formed in different layers
- a disconnection point can be considered to be disposed between adjacent sub-test lines formed in different layers A, and both ends of the breaking point A are provided with conductive contacts 105 penetrating to the upper surface S of the array substrate.
- a plurality of sub-test lines may have multiple arrangements. For example, there are five sub-test lines, three of which are formed in the same layer as the gate line pattern, and two are formed in the same source and drain pattern. Layers, embodiments of the present disclosure are not limited.
- At least one line in the test line is divided into two sub-test lines of equal length by a disconnect point set at a midpoint of at least one line in the test line. The effect of reducing the antenna effect produced by the test line by a large break point is achieved.
- the array substrate provided by the embodiment of the present disclosure disconnects the test circuit from the working circuit by setting a disconnection point provided at both ends of at least one line in the test line, thereby achieving charge conduction avoidance accumulated in the test line. To the effect in the working circuit.
- the array substrate provided by the embodiment of the present disclosure is configured such that at least one break point is set on the test line when the test line is formed, and the sub-test line formed by dividing the break point is not too long.
- the antenna effect generated when the test line is too long is solved, and the slender test circuit in the related art is easy to accumulate more charges due to the antenna effect, and these charges may damage the working circuit; the test circuit is not caused by the antenna. The effect of damaging the working circuit.
- FIG. 6 is a flowchart illustrating a method of fabricating an array substrate according to an exemplary embodiment, and an embodiment of the present disclosure is exemplified by the method applied to fabricating an array substrate.
- the array substrate manufacturing method can include the following steps:
- step 601 a test line including at least one break point is formed on the substrate, and both ends of the test line are respectively connected to the working circuit interface and the test interface.
- step 602 conductive contacts are formed through the ends of each of the break points on the test line to the upper surface of the array substrate.
- the method for manufacturing the array substrate provided by the embodiment of the present disclosure is that when the test circuit is formed, at least one break point is set on the test line, and the sub-test line formed by dividing the break point is not passed. Long, the antenna effect generated when the test line is too long is reduced, and the slender test circuit in the related art is easy to accumulate more charges due to the antenna effect, and these charges may damage the working circuit; the test circuit is not The effect of the working circuit is damaged by the antenna effect.
- FIG. 7 is a flow chart showing a method of fabricating another array substrate according to an exemplary embodiment.
- the embodiment of the present disclosure is exemplified by the method applied to fabricating an array substrate.
- the array substrate manufacturing method can include the following steps:
- step 701 a test line including at least one break point is formed on the substrate, and both ends of the test line are respectively connected to the working circuit interface and the test interface.
- a test circuit including at least one break point may be formed on the substrate, and the two ends of the test line are respectively connected to the working circuit interface and the test interface.
- at least one of the test lines is provided with a break point at a midpoint, that is, the break point divides at least one line in the test line into two subtest lines of equal length, so that the break point can be set at the midpoint
- the antenna effect produced by the test line is greatly reduced by a disconnect point.
- at least one of the lines in the test circuit is provided with a disconnection point, that is, the disconnection point disconnects the test line from the working circuit, thereby preventing conduction of accumulated charge of the test line to the working circuit.
- the distance between the conductive contacts at both ends of each break point is greater than 5 microns.
- the working circuit interface includes a working circuit interface of the display area and a working circuit interface of the peripheral area
- the test interface includes a test interface of the display area and a test interface of the peripheral area
- the test circuit includes a test line of the display area and a test of the surrounding area. line.
- the connection mode is as follows: the test circuit of the display area is connected to the working circuit interface of the display area and the test interface of the display area; the test circuit of the peripheral area is connected to the working circuit interface of the peripheral area and the test interface of the surrounding area. It should be noted that the embodiment of the present disclosure does not limit the position of the test interface, and the actual position may be adjusted.
- step 701 may include the following three cases depending on the location of the test line formation.
- a test line and a gate pattern including at least one break point on the substrate are then formed on the substrate on which the test lines and the gate pattern are formed.
- Other film layers and patterns such as an insulating layer, a source drain pattern, and a protective layer
- the structure of the array substrate can be referred to FIG. 8 (the gate pattern is not shown in FIG. 8), wherein the test line 103 is formed on the substrate 10.
- the second case forming a test line and a source/drain pattern including at least one break point on the substrate on which the insulating layer is formed, and then forming the array substrate on the substrate on which the test line and the source and drain patterns are formed Film layer and pattern (such as protective layer).
- the structure of the substrate can be referred to FIG. 9 (the source drain pattern is not shown in FIG. 9), wherein the test line 103 is formed on the insulating layer 106.
- the third case is a first case.
- Sub-step (1) forms a pattern and a gate pattern of the first sub-test line 103c on the substrate 10.
- the structure of the substrate at the end of the sub-step (1) is as shown in FIG. 10 (the gate pattern is not shown in FIG. 10).
- Sub-step (2) forms an insulating layer 106 on the substrate 10 on which the pattern of the first sub-test line 103c and the gate pattern are formed.
- the structure of the substrate at the end of the sub-step (2) is as shown in Fig. 11 (the gate pattern is not shown in Fig. 11).
- Sub-step (3) forming a pattern and a source-drain pattern of the second sub-test line on the substrate 10 on which the insulating layer 106 is formed, the pattern of the first sub-test line and the pattern composition of the second sub-test line including at least one disconnection Point test line.
- other film layers and patterns such as a protective layer
- film layers and patterns rear substrate structures required for forming the array substrate are as shown in FIG.
- the gate pattern and the source-drain pattern are not shown in FIG. 12, in which the first sub-test line 103c is formed on the substrate 10, and the second sub-test line 103d is formed on the insulating layer 106.
- step 702 vias are formed through the ends of each of the break points on the test line to the upper surface of the array substrate.
- via holes penetrating to the upper surface of the array substrate may be formed at both ends of each of the break points on the test line, for example, on the test line by a patterning process Both ends of each break point form a via hole penetrating to the upper surface of the array substrate.
- the structure of the substrate is as shown in FIG. 13 , wherein the via G passes from both ends of the breaking point A to the upper surface S of the array substrate, and the first sub-test The line 103c and the second sub-test line 103d are formed in different layers.
- step 703 a conductive substance extending to the upper surface of the array substrate is formed in the via hole.
- a conductive material extending to the upper surface of the array substrate may be formed in the via holes.
- a conductive material extending to the upper surface of the array substrate may be formed in the via holes by a patterning process. The substance is used to facilitate the electrical connection of the ends of each break point.
- the structure of the substrate is as shown in FIG. 5.
- the structure of the substrate is as shown in FIG. 4; taking the second case of step 701 as an example, when the step 703 is finished, the structure of the substrate is as shown in FIG. It is shown that both the sub-test line 103a and the sub-test line 103b are formed on the insulating layer 106, and both ends of the break point A are provided with conductive contacts 105 penetrating to the upper surface S of the array substrate.
- step 704 conductive contacts at both ends of all break points are conducted through the conductive silver paste.
- the conductive contacts of all the breaking points can be turned on by the conductive silver glue. It should be noted that when only the working circuit of the display area needs to be tested, it can be turned on only.
- the conductive contacts at both ends of all the break points on the test line of the display area can only conduct the conductive contacts at both ends of all the break points on the test line of the peripheral area when only the working circuit of the peripheral area needs to be tested.
- At least one line in the test line is divided into two equal lengths by setting a break point at a midpoint of at least one line in the test line.
- the strip test circuit achieves the effect of reducing the antenna effect produced by the test line by a large amount of cut-off point.
- the test circuit is disconnected from the working circuit by setting a disconnection point at both ends of at least one line in the test circuit, thereby avoiding accumulation of the test circuit. The effect of the conduction of charge into the working circuit.
- the method for manufacturing the array substrate provided by the embodiment of the present disclosure is that when the test circuit is formed, at least one break point is set on the test line, and the sub-test line formed by dividing the break point is not passed. Long, the antenna effect generated when the test line is too long is reduced, and the slender test circuit in the related art is easy to accumulate more charges due to the antenna effect, and these charges may damage the working circuit; the test circuit is not The effect of the working circuit is damaged by the antenna effect.
- a display device which includes an array substrate provided by any embodiment of the present disclosure, such as the array substrate provided in the embodiment shown in FIG. 1 or the array provided in the embodiment shown in FIG. Substrate.
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Abstract
Description
Claims (18)
- 一种阵列基板,包括:工作电路接口;测试接口;连接所述工作电路接口和所述测试接口的测试线路;其中,所述测试线路上包含至少一个断开点,所述测试线路上每个所述断开点的两端都设置有贯通到所述阵列基板上表面的导电接点。
- 根据权利要求1所述的阵列基板,其中,所述测试线路中的至少一条线路的中点处设置有断开点。
- 根据权利要求2所述的阵列基板,其中,所述测试线路中的至少一条线路的两端设置有断开点。
- 根据权利要求1所述的阵列基板,其中,所述导电接点为从所述断开点一端贯通到所述阵列基板上表面的过孔,所述过孔中设置有延伸到所述阵列基板上表面的导电物质。
- 根据权利要求4所述的阵列基板,其中,每个所述断开点的两端的导电接点之间的距离大于5微米。
- 根据权利要求1所述的阵列基板,其中,每个所述断开点的两端的导电接点通过导电银胶电连接。
- 根据权利要求1至6任一所述的阵列基板,其中,所述至少一个断开点将所述测试线路划分为多条子测试线路,所述多条子测试线路形成于所述阵列基板上的同一层或不同层。
- 根据权利要求1至6任一所述的阵列基板,其中,所述工作电路接口包括显示区域的工作电路接口和周边区域的工作电路接口;所述测试接口包括显示区域的测试接口和周边区域的测试接口;所述测试线路包括显示区域的测试线路和周边区域的测试线路;其中,所述显示区域的测试线路连接所述显示区域的工作电路接口和所述显示区域的测试接口;所述周边区域的测试线路连接所述周边区域的工作电路接口和所述周边区域的测试接口。
- 一种阵列基板的制造方法,包括:在基板上形成包含至少一个断开点的测试线路,所述测试线路的两端分别连接工作电路接口和测试接口;在所述测试线路上每个所述断开点的两端形成贯通到所述阵列基板上表面的导电接点;在对所述工作电路进行测试时,导通所有所述断开点的两端的导电接点以实现所述测试线路的导通。
- 根据权利要求9所述的方法,其中,所述测试线路中的至少一条线路的中点处设置有断开点。
- 根据权利要求10所述的方法,其中,所述测试线路中的至少一条线路的两端设置有断开点。
- 根据权利要求9所述的方法,其中,所述导电接点为形成有导电物质的过孔;所述在所述测试线路上每个所述断开点的两端形成贯通到所述阵列基板上表面的导电接点,包括:在所述测试线路上每个所述断开点的两端形成贯通到所述阵列基板上表 面的过孔;在所述过孔中形成延伸到所述阵列基板上表面的导电物质。
- 根据权利要求12所述的方法,其中,每个所述断开点的两端的导电接点之间的距离大于5微米。
- 根据权利要求9所述的方法,其中,所述导通所有所述断开点的两端的导电接点包括:通过导电银胶导通所有所述断开点的两端的导电接点。
- 根据权利要求9至14任一所述的方法,其中,所述在基板上形成包含至少一个断开点的测试线路,包括:在基板上形成所述包含至少一个断开点的测试线路与栅极图案;或者,在形成有绝缘层的基板上形成所述包含至少一个断开点的测试线路与源漏极图案。
- 根据权利要求9至14任一所述的方法,其中,所述在基板上形成包含至少一个断开点的测试线路,包括:在基板上形成第一子测试线路的图案与栅极图案;在形成有所述第一子测试线路的图案与栅极图案的基板上形成绝缘层;在形成有绝缘层的基板上形成第二子测试线路的图案与源漏极图案,所述第一子测试线路的图案和所述第二子测试线路的图案组成所述包含至少一个断开点的所述测试线路。
- 根据权利要求9至14任一所述的方法,其中,所述工作电路接口包括显示区域的工作电路接口和周边区域的工作电路接口;所述测试接口包括显示区域的测试接口和周边区域的测试接口;所述测试线路包括显示区域的测试线路和周边区域的测试线路;其中,所述显示区域的测试线路连接所述显示区域的工作电路接口和所述显示区域的测试接口;所述周边区域的测试线路连接所述周边区域的工作电路接口和所述周边区域的测试接口。
- 一种显示装置,包括权利要求1至8任一所述的阵列基板。
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