WO2016150053A1 - 移位寄存器、栅极驱动电路、显示面板及显示装置 - Google Patents

移位寄存器、栅极驱动电路、显示面板及显示装置 Download PDF

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Publication number
WO2016150053A1
WO2016150053A1 PCT/CN2015/084995 CN2015084995W WO2016150053A1 WO 2016150053 A1 WO2016150053 A1 WO 2016150053A1 CN 2015084995 W CN2015084995 W CN 2015084995W WO 2016150053 A1 WO2016150053 A1 WO 2016150053A1
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Prior art keywords
node
module
signal
output
switching transistor
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Ceased
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PCT/CN2015/084995
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English (en)
French (fr)
Inventor
黄飞
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to US14/904,816 priority Critical patent/US9934744B2/en
Publication of WO2016150053A1 publication Critical patent/WO2016150053A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register, a gate driving circuit, a display panel, and a display device.
  • the gate electrode The driving circuit is arranged at an edge portion of the display panel, the gate driving circuit comprises a plurality of shift registers, each shift register corresponds to one gate line, and the plurality of shift registers are arranged in series, between two adjacent shift registers There is a trigger signal transmitted step by step. After receiving the trigger signal, each shift register outputs a gate line scan signal to the corresponding gate line, and supplies the trigger signal to the next stage unit circuit to implement the gate drive function.
  • the design can omit the separate setting of the gate driving chip in the frame area of the display panel, which is beneficial to realize the narrow frame design of the display panel, reduces the production cost of related products, and improves the market competitiveness of the display product.
  • the circuit structure of the existing shift register is as shown in FIG. 1 , and its corresponding input and output timing diagram is shown in FIG. 2 .
  • the first The potential of a node PU is pulled high in the first time period, and is continuously pulled high in the second phase, thereby controlling the switching transistor T7 to be turned on, so that the scan signal output end corresponds to the output scan signal, but due to the voltage signal output by the first node PU
  • There is noise (as shown in area A marked in Figure 2), and the potential of the signal generated by the first node PU when it is pulled high for the first time is high, and the scanning signal output is easily caused by the charging and discharging process of the capacitor C1.
  • the output scan signal has a large noise (as shown in the area B marked in FIG. 2), which causes the shift register circuit to consume a large amount of power and reduces the yield of the display panel.
  • the embodiment of the present disclosure provides a shift register, a gate driving circuit, a display panel, and a display device for solving the problem that the scanning signal outputted by the shift register existing in the prior art has large noise and large power consumption.
  • An embodiment of the present disclosure provides a shift register, including: an input module, a first node pull-down module, a second node pull-up module, a second node pull-down module, an output control module, and an output noise reduction module;
  • the first input end of the input module is connected to the first signal input end, the second input end is connected to the second signal input end, the first control end is connected to the first reference signal end, and the second control end and the second reference signal are Connected to the first node, the output terminal is connected to the first node, and the input module is configured to pull down the potential of the first node at the control of the first reference signal end and the second reference signal end;
  • the input end of the first node pull-down module is connected to the low-level signal end, the control end is connected to the second node, the output end is connected to the first node, and the first node pull-down module is used in the second The control of the node pulls down the potential of the first node;
  • the input end of the second node pull-up module is connected to the high-level signal end, the control end is connected to the first clock signal end, the output end is connected to the second node, and the second node pull-up module is used to Controlling the first clock signal terminal to pull down a potential of the second node;
  • the first input end and the second input end of the second node pull-down module are respectively connected to the low-level signal end, the first control end is connected to the first node, and the second control end is connected to the scan signal output end.
  • the output end is connected to the second node, and the second node pull-down module is configured to pull down the potential of the second node at the control of the first node or the scan signal output end;
  • the first input end of the output control module is connected to the low level signal end, the second input end is connected to the second clock signal end, the first control end is connected to the third node, and the second control end is connected to the first
  • the two nodes are connected, and the output end is connected to the scan signal output end, and the output control module is configured to control the scan signal output end to select and output the first control under the control of the third node or the second node a signal of the second clock signal end or a signal of the low level signal end;
  • An input end of the output noise reduction module is connected to the first node, a control end is connected to the high level signal end, an output end is connected to the third node, and the output noise reduction module is configured to The signal of the first node is filtered and noise-reduced and output to the third node.
  • the output noise reduction module specifically includes: a first switching transistor
  • the gate of the first switching transistor is connected to the high-level signal terminal, the source is connected to the first node, and the drain is connected to the third node.
  • the foregoing shift register provided by the embodiment of the present disclosure further includes: a first node noise reduction module;
  • the first node noise reduction module is connected between the first node, the high level signal end, and a source of the first switching transistor, and the first node noise reduction module is configured to The signal of one node is further filtered and noise-reduced and output to the source of the first switching transistor.
  • the first node noise reduction module specifically includes: a second switching transistor and a third switching transistor; wherein
  • a gate of the second switching transistor is connected to the first node, a source is connected to a drain of the third switching transistor, and a drain is connected to a source of the first switching transistor;
  • the gate and the source of the third switching transistor are respectively connected to the high-level signal terminal.
  • the foregoing shift register provided by the embodiment of the present disclosure further includes: a second node noise reduction module;
  • the second node noise reduction module is connected between the high level signal end, the output end of the second node pull up module, and the second node, and the second node noise reduction module is used for
  • the signal outputted by the output of the second node pull-up module is filtered and noise-reduced and output to the second node.
  • the second node noise reduction module specifically includes: a fourth switching transistor
  • the gate of the fourth switching transistor is connected to the high-level signal end, the source is connected to the output end of the second node pull-up module, and the drain is connected to the second node.
  • the second node pull-up module specifically includes: a fifth switch transistor;
  • the gate of the fifth switching transistor is connected to the first clock signal terminal, the source is connected to the high-level signal terminal, and the drain is connected to the source of the fourth switching transistor.
  • the foregoing shift register provided by the embodiment of the present disclosure further includes Includes: protection module;
  • the protection module is connected between the first signal input end, the second signal input end, the high level signal end, and the output end of the second node pull-up module, where the protection module is used When an abnormal current signal is input to the first signal input terminal or the second signal input terminal, the abnormal current signal is shunted.
  • the protection module specifically includes: a sixth switching transistor and a seventh switching transistor; wherein
  • a gate of the sixth switching transistor is connected to the first signal input end, a source is connected to the high level signal end, and a drain is connected to a source of the seventh switching transistor;
  • the gate of the seventh switching transistor is connected to the second signal input end, and the drain is connected to the output end of the second node pull-up module.
  • the foregoing shift register provided by the embodiment of the present disclosure further includes: a maintenance module;
  • the input end of the maintenance module is connected to the high-level signal end, and the control end and the output end are respectively connected to the scan signal output end, and the maintenance module is configured to output a scan signal when the scan signal output end outputs The potential of the output of the scan signal is maintained.
  • the maintaining module specifically includes: an eighth switching transistor;
  • the gate and the drain of the eighth switching transistor are respectively connected to the scan signal output end, and the source is connected to the high level signal end.
  • the output control module specifically includes: a first output control module and a second output control module;
  • the first output control module is connected between the third node, the second clock signal end, and the scan signal output end, and the first output control module is used for control at the third node And controlling the scan signal output end to output the signal of the second clock signal end;
  • the second output control module is connected between the low level signal end, the second node, and the scan signal output end, and the second output control module is used for control at the second node And controlling the scan signal output end to output the signal of the low level signal end.
  • the first output control module specifically includes: a ninth switching transistor and a first capacitor; wherein
  • a gate of the ninth switching transistor is connected to the third node, a source is connected to the second clock signal end, and a drain is connected to the scan signal output end;
  • the first capacitor is connected between the third node and the scan signal output end.
  • the second output control module specifically includes: a tenth switch transistor
  • the gate of the tenth switching transistor is connected to the second node, the source is connected to the low level signal end, and the drain is connected to the scan signal output end.
  • the second output control module further includes: a second capacitor
  • the second capacitor is coupled between the second node and the low level signal terminal.
  • the second node pull-down module specifically includes: a first pull-down module and a second pull-down module;
  • An input end of the first pull-down module is connected to the low-level signal end, a control end is connected to the first node, and an output end is connected to the second node, where the first pull-down module is used to The control of the first node pulls down the potential of the second node;
  • the input end of the second pull-down module is connected to the low-level signal end, the control end is connected to the scan signal output end, the output end is connected to the second node, and the second pull-down module is used in the When the scan signal output terminal outputs the scan signal, the potential of the second node is further pulled down.
  • the first pull-down module specifically includes: an eleventh switching transistor
  • the gate of the eleventh switching transistor is connected to the first node, the source is connected to the low level signal end, and the drain is connected to the second node.
  • the second pull-down module specifically includes: a twelfth switching transistor
  • the gate of the twelfth switching transistor is connected to the scan signal output end, the source is connected to the low level signal end, and the drain is connected to the second node.
  • the input module specifically includes: a thirteenth switching transistor and a fourteenth switching transistor;
  • a gate of the thirteenth switching transistor is connected to the first reference signal terminal, a source is connected to the first signal input terminal, and a drain is respectively connected to a source of the fourteenth switching transistor and the first Connected to a node;
  • the gate of the fourteenth switching transistor is connected to the second reference signal terminal, and the source is connected to the second signal input terminal.
  • the first node pull-down module specifically includes: a fifteenth switch transistor
  • the gate of the fifteenth switching transistor is connected to the output end of the second node pull-up module, the source is connected to the low-level signal end, and the drain is connected to the input end of the output noise reduction module.
  • the embodiment of the present disclosure provides a gate driving circuit, including the above-mentioned shift register provided by a plurality of cascaded embodiments of the present disclosure, except for the last shift register, the scan signal output end of each of the shift registers The trigger signal is input to the signal input terminal of the next shift register adjacent thereto.
  • An embodiment of the present disclosure provides a display panel including the above-described gate driving circuit provided by an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a display device including the above display panel provided by an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a shift register, a gate driving circuit, a display panel, and a display device.
  • the shift register includes an input module, a first node pull-down module, a second node pull-up module, and a second node pull-down module.
  • An output control module, and an output noise reduction module wherein the input module is configured to pull down a potential of the first node at a first reference signal end or a second reference signal end; the first node pull-down module is used for control at the second node Pulling down the potential of the first node; the second node pull-up module is used to pull down the potential of the second node at the control of the first clock signal; the second node pull-down module is used to pull down the control at the first node and the scan signal output The potential of the second node; the output control module is configured to control the output of the second clock signal end or the signal of the low level signal end under the control of the third node and the second node, thereby implementing the shift register Output scan at the corresponding time period The function of the signal, at the same time, the output noise reduction module is used for filtering and noise-reducing the signal of the first node, and transmitting the filtered noise-reduced signal to the third node, so that the output control module outputs low under the control of the
  • the noise scans the signal, and can prevent the first capacitor from outputting a noise signal at the output of the scan signal under the influence of a large noise signal, thereby improving the lossless transmission of the signal, reducing power consumption, and thereby improving the yield of the display panel.
  • FIG. 3 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 8 is a timing diagram of input and output of a shift register according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a shift register, as shown in FIG. 3, which may include: an input module 01, a first node pull-down module 02, a second node pull-up module 03, a second node pull-down module 04, and an output control module. 05, and an output noise reduction module 06; wherein
  • the first input end of the input module 01 is connected to the first signal input end Input1, the second input end is connected to the second signal input end Input2, the first control end is connected to the first reference signal terminal CN, and the second control end is connected.
  • the output terminal is connected to the first node P1
  • the input module 01 is configured to pull down the potential of the first node P1 at the control of the first reference signal terminal CN or the second reference signal terminal CNB;
  • the input end of the first node pull-down module 02 is connected to the low-level signal end VGL, the control end is connected to the second node P2, the output end is connected to the first node P1, and the first node pull-down module 02 is used at the second node P2. Controlling the potential of the first node P1 to be pulled down;
  • the input end of the second node pull-up module 03 is connected to the high-level signal terminal VGH, the control terminal is connected to the first clock signal terminal CLK, the output terminal is connected to the second node P2, and the second node pull-up module 03 is used in the first The control of a clock signal terminal CLK pulls down the potential of the second node P2;
  • the first input end and the second input end of the second node pull-down module 04 are respectively connected to the low-level signal end VGL, the first control end is connected to the first node P1, and the second control end is connected to the scan signal output end Out, and the output is The terminal is connected to the second node P2, and the second node pull-down module 04 is configured to pull down the potential of the second node P2 at the control of the first node P1 or the scan signal output terminal Out;
  • the first input end of the output control module 05 is connected to the low level signal end VGL, the second input end is connected to the second clock signal end CLKB, the first control end is connected to the third node P3, and the second control end and the second node are connected.
  • P2 is connected, the output end is connected to the scan signal output end Out, and the output control module 05 is configured to control the scan signal output end Out to select and output the signal of the second clock signal end CLKB under the control of the third node P3 or the second node P2 or a signal of a low level signal terminal VGL;
  • the input end of the output noise reduction module 06 is connected to the first node P1, the control end is connected to the high level signal terminal VGH, the output end is connected to the third node P3, and the output noise reduction module 06 is configured to perform the signal of the first node P1. After filtering and noise reduction, the output is output to the third node P3.
  • the above shift register provided by the embodiment of the present disclosure includes an input module 01, a first node pull-down module 02, a second node pull-up module 03, a second node pull-down module 04, an output control module 05, and an output noise reduction module 06.
  • the input module 01 is used to pull up the potential of the first node P1;
  • the first node pull-down module 02 is used to pull down the potential of the first node P1;
  • the second node pull-up module 03 is used to pull up the second node P2.
  • the second node pull-down module 04 is configured to pull down the potential of the second node P2; the output control module 05 is configured to control the scan signal output terminal Out to select the signal of the second clock signal terminal CLKB or the signal of the low-level signal terminal VGL.
  • the output noise reduction module is used for filtering and noise-reducing the signal of the first node, and transmitting the signal after filtering and noise reduction.
  • the output control module outputs a low-noise scan signal under the control of the third node, and can prevent the first capacitor from outputting a noise signal at the scan signal output end under the influence of a large noise signal, thereby improving the signal without Loss transmission, reducing power consumption, and thus improving the yield of the display panel.
  • the output noise reduction module 06 may specifically include: a first switching transistor T1; a gate of the first switching transistor T1 and a high voltage
  • the flat signal terminal VGH is connected, the source is connected to the first node P1, and the drain is connected to the third node P3.
  • the first switching transistor T1 since the gate of the first switching transistor T1 is connected to the high-level signal terminal VGH, the first switching transistor T1 is in a normally-on state and operates as a single-tube transmission gate, so the first switching transistor T1 can be paired with the first node.
  • the signal of P1 is filtered and noise-reduced, and the filtered noise-reduced signal is transmitted to the third node P3.
  • the above shift register provided by the embodiment of the present disclosure may further include: a first node noise reduction module 07; the first node noise reduction module 07 is connected to the first node P1, high
  • the first node noise reduction module 07 is configured to connect the high level signal terminal VGH and the source of the first switching transistor T1 under the control of the first node P1 between the level signal terminal VGH and the source of the first switching transistor T1. Turn on.
  • the first node noise reduction module 07 turns on the high-level signal terminal VGH and the source of the first switching transistor T1, that is, the signal of the first node P1 can be performed.
  • the DC is pulled high to further filter the noise reduction, reduce the signal noise of the first node P1, and then output the signal of the first node P1 after noise reduction to the source of the first switching transistor T1, and then pass the signal through the first switching transistor T1. Filtering and noise reduction further reduces signal noise and improves lossless transmission of signals, thereby reducing power consumption.
  • the first node noise reduction module 07 may specifically include: a second switching transistor T2 and a third switching transistor T3;
  • the gate of the second switching transistor T2 is connected to the first node P1, the source is connected to the drain of the third switching transistor T3, the drain is connected to the source of the first switching transistor T1, and the gate and source of the third switching transistor T3.
  • the poles are respectively connected to the high level signal terminal VGH.
  • the third switching transistor T3 is in a normally open state and operates as a single-tube transmission gate. Therefore, when the potential of the first node P1 is pulled high, the signal of the high-level signal terminal VGH passes through the third switching transistor T3 and is turned on.
  • the second switching transistor T2 is output to the source of the first switching transistor T1, and the signal of the source of the first switching transistor T1 is DC pulled high to further reduce signal noise, instead of outputting the signal of the first node P1 without noise reduction. To the source of the first switching transistor T1, the noise of the signal of the source of the first switching transistor T1 can be reduced.
  • the above shift register provided by the embodiment of the present disclosure, as shown in FIG. 6 and FIG. 7 , may further include: a second node noise reduction module 08; the second node noise reduction module 08 is connected to a high level. Between the signal terminal VGH, the output end of the second node pull-up module 03 and the second node P2, the second node noise reduction module 08 is configured to filter and noise the signal of the output end of the second node pull-up module 03, and filter The noise-reduced signal is output to the second node P2, further reducing the signal noise of the second node P2.
  • the second node noise reduction module 08 is in a normally open state under the control of the high level signal terminal VGH, and functions as a transmission gate to filter and denoise the signal of the output end of the second node pull-up module 03, and filter The noise-reduced signal is output to the second node P2, further reducing the signal noise of the second node P2.
  • the second node noise reduction module 08 may specifically include: a fourth switching transistor T4; and a fourth switching transistor T4.
  • the gate is connected to the high level signal terminal VGH, the source is connected to the output end of the second node pull-up module 03, and the drain is connected to the second node P2.
  • the fourth switching transistor T4 since the gate of the fourth switching transistor T4 is connected to the high-level signal terminal VGH, the fourth switching transistor T4 is in a normally-on state, and operates as a single-tube transmission gate to the output terminal of the second node pull-up module 03.
  • the signal is filtered and noise-reduced, and the filtered and noise-reduced signal is output to the second node P2 to further reduce the signal noise of the second node P2.
  • the second node pull-up module 03 may specifically include: a fifth switching transistor T5; and a fifth switching transistor T5.
  • the gate is connected to the first clock signal terminal CLK, the source is connected to the high level signal terminal VGH, and the drain is connected to the source of the fourth switching transistor T4.
  • the fifth switching transistor T5 when the second node pull-up module 03 inputs a high-level signal at the first clock signal terminal CLK, The fifth switching transistor T5 is in an on state, and the turned-on fifth switching transistor T5 turns on the high-level signal terminal VGH and the source of the fourth switching transistor T4 to raise the potential of the source of the fourth switching transistor T4. Since the fourth switching transistor T4 is in the normally open state, the potential of the second node P2 can be raised.
  • the above shift register provided by the embodiment of the present disclosure may further include: a protection module 09; the protection module 09 is connected to the first input signal terminal Input1 and the second signal input.
  • the protection module 09 is configured to input an abnormal current signal when the first signal input terminal Input1 or the second signal input terminal Input2 inputs an abnormal current signal between the terminal Input2, the high-level signal terminal VGH and the output terminal of the second node pull-up module 03. The current signal is shunted.
  • the protection module 09 is in a closed state when the shift register is normally operated, and when the first signal input terminal Input1 or the second signal input terminal Input2 inputs an abnormal current signal, wherein the abnormal current signal is a high current higher than the normal current signal.
  • the signal for example, the signal input terminal has a normal input signal of 1V.
  • the signal input to the signal input terminal is a 10V signal
  • the signal input terminal inputs an abnormal signal.
  • the input large current signal may damage the shift register. Transistor, so the protection module 09 can shunt the abnormal current signal at this time to protect the shift register from being damaged by the input of the abnormal current signal.
  • the protection module 09 may specifically include: a sixth switching transistor T6 and a seventh switching transistor T7; wherein, the sixth The gate of the switching transistor T6 is connected to the first signal input terminal Input1, the source is connected to the high level signal terminal VGH, and the drain is connected to the source of the seventh switching transistor T7;
  • the gate of the seventh switching transistor T7 is connected to the second signal input terminal Input2, and the drain is connected to the output terminal of the second node pull-up module 03.
  • the sixth switching transistor T6 and the seventh switching transistor T7 are both in an off state, and when a first current input terminal Input1 or a second signal input terminal Input2 inputs a large current signal, Corresponding to the sixth switching transistor T6 or the seventh switching transistor T7 being in an on state, the input abnormal current signal is shunt buffered, and the shift register is protected to prevent the shift register from being damaged due to the input of the abnormal current signal.
  • the above shift register provided by the embodiment of the present disclosure, as shown in FIG. 6 and FIG. 7 , may further include: a maintenance module 10; the input end of the maintenance module 10 is connected to the high-level signal terminal VGH, The control terminal and the output terminal are respectively connected to the scan signal output terminal Out, and the maintenance module 10 is configured to maintain the potential of the scan signal output terminal Out when the scan signal output terminal Out outputs the scan signal.
  • the maintenance module 10 when the scan signal output terminal Out outputs the scan signal, the maintenance module 10 is in an on state, and the high level signal terminal VGH and the scan signal output terminal Out are turned on, and then the high level signal is output to the scan signal output terminal Out. Further, the potential of the scan signal output terminal Out is further maintained.
  • the sustain mode 10 may specifically include: an eighth switch transistor T8; a gate and a drain of the eighth switch transistor T8.
  • the poles are respectively connected to the scan signal output terminal Out, and the source is connected to the high level signal terminal VGH.
  • the eighth switch transistor T8 when the scan signal output terminal Out outputs the scan signal, the eighth switch transistor T8 is in an on state, and the turned-on eighth switch transistor T8 turns on the high level signal terminal VGH and the scan signal output terminal Out to further maintain The potential of the signal output terminal Out is scanned.
  • the output control module 05 may specifically include: a first output control module 051 and a second output control module 052; ,
  • the first output control module 051 is connected between the third node P3, the second clock signal terminal CLKB, and the scan signal output terminal Out.
  • the first output control module 051 is configured to control the scan signal output under the control of the third node P3.
  • the terminal Out outputs a signal of the second clock signal terminal CLKB;
  • the second output control module 052 is connected between the low level signal terminal VGL, the second node P2, and the scan signal output terminal Out, and the second output control module 052 is configured to control the scan signal output under the control of the second node P2.
  • the terminal Out outputs a signal of the low-level signal terminal VGL.
  • the first output control module 051 and the second output control module 052 respectively output the signal of the second clock signal end CLKB and the signal of the low level signal end VGL under the control of the third node P3 and the second node P2,
  • the shift register is implemented to output a scan signal to the corresponding gate line in the corresponding time period, and the display panel is driven to realize progressive scan.
  • the first output control module 051 may specifically include: a ninth switching transistor T9 and a first capacitor C1; The gate of the ninth switching transistor T9 is connected to the third node P3, the source is connected to the second clock signal terminal CLKB, and the drain is connected to the scan signal output terminal Out; the first capacitor C1 is connected to the third node P3. Between the scan signal output terminal Out and the scan signal output terminal Out.
  • the ninth switching transistor T9 when the potential of the third node P3 is pulled high, the ninth switching transistor T9 is in an on state, and the turned-on ninth switching transistor T9 turns on the second clock signal terminal CLKB and the scan signal output terminal Out.
  • the first capacitor C1 acts as a bootstrap action on the potential of the third node P3 to further maintain the potential of the third node P3.
  • the second output control module 052 may specifically include: a tenth switching transistor T10; a gate and a tenth of the tenth switching transistor T10.
  • the two nodes P2 are connected, the source is connected to the low level signal terminal VGL, and the drain is connected to the scan signal output terminal Out.
  • the tenth switching transistor T10 when the potential of the second node P2 is pulled high, the tenth switching transistor T10 is in an on state, and the turned-on tenth switching transistor T10 turns on the low-level signal terminal VGL and the scan signal output terminal Out, and simultaneously The potential of the second node P2 can also be maintained by the parasitic capacitance of the tenth switching transistor T10.
  • the second output control module 052 may further include: a second capacitor C2; the second capacitor C2 is connected to the second node P2 and Low level signal between VGL.
  • the tenth switching transistor T10 when the potential of the second node P2 is pulled high, the tenth switching transistor T10 is in an on state, and the turned-on tenth switching transistor T10 turns on the low-level signal terminal VGL and the scan signal output terminal Out, and simultaneously
  • the second capacitor C2 can further maintain the potential of the second node P2, reducing the noise of the voltage signal of the second node P2.
  • the second node pull-down module 04 may specifically include: a first pull-down module 041 and a second pull-down module 042;
  • the input end of the first pull-down module 041 is connected to the low-level signal end VGL, the control end is connected to the first node P1, the output end is connected to the second node P2, and the first pull-down module 041 is used at the first node.
  • the control of P1 pulls down the potential of the second node P2; the input end of the second pull-down module 042 is connected to the low-level signal terminal VGL, the control terminal is connected to the scan signal output terminal Out, and the output terminal is connected to the second node P2, the second The pull-down module 042 is configured to further pull down the potential of the second node P2 when the scan signal output terminal Out outputs the scan signal.
  • the first pull-down module 041 and the second pull-down module 042 are respectively at the potential of the first node P1.
  • the scan signal is output when pulled high and the scan signal output terminal Out, the potential of the second node P2 is pulled low, and the signal noise of the second node P2 is lowered.
  • the first pull-down module 041 may specifically include: an eleventh switching transistor T11; an eleventh switching transistor T11 The gate is connected to the first node P1, the source is connected to the low-level signal terminal VGL, and the drain is connected to the second node P2.
  • the eleventh switching transistor T11 when the potential of the first node P1 is pulled high, the eleventh switching transistor T11 is in an on state, and the turned-on eleventh switching transistor T11 turns on the low-level signal terminal VGL and the second node P2. Pulling down the potential of the second node P2 reduces the noise of the signal of the second node P2.
  • the second pull-down module 042 may specifically include: a twelfth switching transistor T12; and a twelfth switching transistor T12.
  • the gate is connected to the scan signal output terminal Out, the source is connected to the low level signal terminal VGL, and the drain is connected to the second node P2.
  • the twelfth switch transistor T12 when the scan signal output terminal Out outputs the scan signal, the twelfth switch transistor T12 is in an on state, and the turned on twelfth switch transistor T12 turns on the low level signal terminal VGL and the second node P2, pulling The potential of the second node P2 is lowered to reduce the noise of the signal of the second node P2.
  • the input module 01 may specifically include: a thirteenth switching transistor T13 and a fourteenth switching transistor T14;
  • the gate of the three-switching transistor T13 is connected to the first reference signal terminal CN, the source is connected to the first signal input terminal Input1, and the drain is connected to the source of the fourteenth switching transistor T14 and the first node P1, respectively;
  • the gate of the switching transistor T14 is connected to the second reference signal terminal CNB, and the source is connected to the second signal input terminal Input2.
  • the thirteenth switching transistor T13 is in the forward scanning direction.
  • the corresponding thirteenth switching transistor T13 in the on state turns on the first signal input terminal Input1 and the first node P1, and then the first signal input terminal Input1
  • the signal is output to the first node P1; the fourteenth switching transistor T14 is in an on state during reverse scanning, and the corresponding signal is input when the second signal input terminal Input2 inputs a signal.
  • the fourteenth switching transistor T14 turns on the second signal input terminal Input2 and the first node P1, and outputs the signal of the second signal input terminal Input2 to the first node P1.
  • the first node pull-down module 02 may specifically include: a fifteenth switching transistor T15; and a fifteenth switching transistor T15.
  • the gate is connected to the output of the second node pull-up module 03, the source is connected to the low-level signal terminal VGL, and the drain is connected to the input terminal of the output noise reduction module 06.
  • the fifteenth switching transistor T15 when the potential of the second node P2 is pulled high, that is, when the output end of the second node pull-up module 03 outputs a high-level signal, the fifteenth switching transistor T15 is also in an on state, and the tenth is turned on.
  • the five-switching transistor T15 turns on the low-level signal terminal VGL and the input end of the output noise-reducing module 06, thereby lowering the potential of the input terminal of the output noise-reducing module 06. Since the output noise-reducing module 06 is in the normally-on state, it also pulls The potential of the third node P3 is lowered.
  • the switching transistor mentioned in the above embodiments of the present disclosure may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS) (Metal Oxide Scmiconductor), which is not limited herein. .
  • TFT thin film transistor
  • MOS metal oxide semiconductor field effect transistor
  • the sources and drains of these transistors can be interchanged without specific distinction.
  • a thin film transistor will be described as an example in describing a specific embodiment.
  • first signal input terminal Input1 and the second signal input terminal Input2 are symmetrically designed in the above-mentioned shift register provided by the embodiment of the present disclosure, the function interchange can be implemented, and thus the above shift register provided by the embodiment of the present disclosure is provided. Two-way scanning is possible.
  • the first reference signal terminal CN when the forward scan is initiated, the first reference signal terminal CN provides a high level signal, and the second reference signal terminal CNB provides a low level signal.
  • the first reference signal terminal CN provides a low level signal, and the second reference signal terminal CNB provides a high level signal.
  • the input terminal 1 and the gate of the second switching transistor T2 are turned on, so the second switching transistor T2 is turned on, and the third switching transistor T3 is in a normally open state, so the signal of the high level signal terminal VGH passes through the third switching transistor T3.
  • the second switching transistor T2 that is turned on is output to the source of the first switching transistor T1. Since the first switching transistor T1 is in the normally-on state, the signal of the first node P1 is filtered and noise-reduced by the first switching transistor T1.
  • the potential of the third node P3 is pulled high, and at the same time, the first capacitor C1 is charged, at this time, the ninth switching transistor T9 is in an on state, and the turned-on ninth switching transistor T9 is turned on the second clock signal end.
  • the t1 phase is the charging phase.
  • the tenth switching transistor T10 turns on the low-level signal terminal VGL and the scan signal output terminal Out, so the scan signal output terminal Out outputs a low-level signal, and at the same time, since the potential of the source of the fourth switching transistor T4 is pulled high, The fifteenth switching transistor T15 is in an on state, and the turned-on fifteenth switching transistor T15 turns on the source of the first switching transistor T1 and the low-level signal terminal VGL, and thus the potential of the source of the first switching transistor T1 When the first switching transistor T1 is in the normally open state, the potential of the third node P3 is pulled low, and the ninth switching transistor T9 is in the off state.
  • the t3 phase is the non-scanning signal output phase.
  • the scan signal output terminal Out will always output a low level signal until the first signal input terminal Input1 inputs a high level signal again in a certain period of time, then the shift register will repeat the above work.
  • an embodiment of the present disclosure provides a gate driving circuit including a plurality of cascaded shift registers provided by the embodiments of the present disclosure, except for the last shift register.
  • the scan signal output of each shift register inputs a trigger signal to the signal input of the next shift register adjacent thereto.
  • shift registers are a first-stage shift register, a second-stage shift register, a third-stage shift register, a fourth-stage shift register, and an N-th 3-stage shift register, N-2th shift register, N-1th shift register, Nth shift register.
  • the scan signal output end Out of each of the shift registers not only outputs a gate turn-on signal to the gate line connected thereto, but also outputs a trigger signal to the next-stage shift register adjacent thereto. .
  • each of the shift registers in the above-mentioned gate driving circuit is identical in function and structure to the above-described shift register provided by the present disclosure, and the repeated portions are not described again.
  • an embodiment of the present disclosure provides a display panel including the above-described gate driving circuit provided by an embodiment of the present disclosure. Since the principle of solving the problem of the display panel is similar to that of the gate driving circuit, the implementation of the display panel can be referred to the implementation of the above-mentioned gate driving circuit, and the repeated description is omitted.
  • an embodiment of the present disclosure provides a display device, including the above display panel provided by an embodiment of the present disclosure.
  • the display device can be applied to any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. Since the principle of solving the problem is similar to that of the display panel, the implementation of the display device can be referred to the implementation of the above display panel, and the repeated description is omitted.
  • Embodiments of the present disclosure provide a shift register, a gate driving circuit, a display panel, and a display device.
  • the shift register includes an input module, a first node pull-down module, a second node pull-up module, and a second node pull-down module.
  • An output control module, and an output noise reduction module wherein the input module is configured to pull down a potential of the first node at a signal input end; the first node pull-down module is configured to pull down a potential of the first node at a control of the second node; The second node pull-up module is configured to pull down the potential of the second node at the control of the first clock signal end; the second pull-down module is configured to pull down the potential of the second node at the control of the first node and the scan signal output end; the output control module For controlling the scan signal output end to select the signal of the second clock signal end or the signal of the low level signal end under the control of the third node and the second node, thereby realizing the function of the shift register outputting the scan signal in the corresponding time period At the same time, the output noise reduction module is used for filtering and denoising the signal of the first node, and filtering the noise-reduced signal The first transmission to The three nodes, so that the output control module outputs a low-noi

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Abstract

公开了一种移位寄存器、栅极驱动电路、显示面板和显示装置。该移位寄存器包括输入模块（01）、第一节点下拉模块（02）、第二节点上拉模块（03）、第二节点下拉模块（04）、输出控制模块（05），以及输出降噪模块（06）；输入模块（01）用于拉高第一节点（P1）的电位；第一节点下拉模块（02）用于拉低第一节点（P1）的电位；第二节点上拉模块（03）用于拉高第二节点（P2）的电位；第二节点下拉模块（04）用于拉低第二节点（P2）的电位；输出控制模块（05）用于控制扫描信号输出端（Out）选择输出第二时钟信号端（CLKB）的信号或低电平信号端（VGL）的信号，输出降噪模块（06）将第一节点（P1）的信号进行滤波降噪，且将滤波降噪后的信号传输到第三节点（P3），从而输出控制模块（05）可以在第三节点（P3）的控制下输出低噪声扫描信号。

Description

移位寄存器、栅极驱动电路、显示面板及显示装置
相关申请的交叉引用
本申请主张在2015年3月26日在中国提交的中国专利申请号No.201510137070.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器、栅极驱动电路、显示面板及显示装置。
背景技术
目前，随着液晶显示技术的发展，液晶面板业竞争越来越激烈，降低液晶显示面板的生产成本成为面板商提高竞争力的首选方案，而为了降低显示面板的生产成本，一般地，栅极驱动电路被布置在显示面板的边缘部分，栅极驱动电路包括多个移位寄存器，每个移位寄存器对应一条栅线，多个移位寄存器采用串联设置，相邻两个移位寄存器之间有逐级传递的触发信号，每个移位寄存器接收到触发信号后，向对应栅线输出栅线扫描信号，并把触发信号输送给下一级单元电路以实现栅极驱动的功能，这样的设计可以省去在显示面板的边框区域单独设置栅极驱动芯片，有利于实现显示面板的窄边框设计，同时降低了相关产品的生产成本，提高了显示产品的市场竞争力。
一般地，现有的移位寄存器的电路结构，如图1所示，其对应的输入输出时序图，如图2所示，从图2可以看出，移位寄存器在正常开启工作时，第一节点PU的电位在第一时间段被拉高，在第二阶段被继续拉高，进而控制开关晶体管T7开启，使得扫描信号输出端对应输出扫描信号，然而由于第一节点PU输出的电压信号有噪声(如图2中标注的区域A所示)，且第一节点PU在第一次被拉高时产生的信号的电位较高，通过电容C1的充放电过程，易造成扫描信号输出端输出的扫描信号有较大噪声(如图2中标注的区域B所示)，进而造成移位寄存器电路功耗较大，降低了显示面板的良率。
因此，如何降低移位寄存器输出的扫描信号的噪声，降低功耗，从而提高显示面板的良率，是本领域技术人员亟需解决的技术问题。
发明内容
本公开实施例提供一种移位寄存器，栅极驱动电路、显示面板及显示装置，用以解决现有技术中存在的移位寄存器输出的扫描信号的噪声较大，功耗较大的问题。
本公开实施例提供了一种移位寄存器，包括：输入模块、第一节点下拉模块、第二节点上拉模块、第二节点下拉模块、输出控制模块，以及输出降噪模块；其中，
所述输入模块的第一输入端与第一信号输入端相连，第二输入端与第二信号输入端相连，第一控制端与第一参考信号端相连，第二控制端与第二参考信号端相连，输出端与第一节点相连，所述输入模块用于在所述第一参考信号端和所述第二参考信号端的控制下拉高所述第一节点的电位；
所述第一节点下拉模块的输入端与低电平信号端相连，控制端与第二节点相连，输出端与所述第一节点相连，所述第一节点下拉模块用于在所述第二节点的控制下拉低所述第一节点的电位；
所述第二节点上拉模块的输入端与高电平信号端相连，控制端与第一时钟信号端相连，输出端与所述第二节点相连，所述第二节点上拉模块用于在所述第一时钟信号端的控制下拉高所述第二节点的电位；
所述第二节点下拉模块的第一输入端和第二输入端分别与所述低电平信号端相连，第一控制端与所述第一节点相连，第二控制端与扫描信号输出端相连，输出端与所述第二节点相连，所述第二节点下拉模块用于在所述第一节点或所述扫描信号输出端的控制下拉低所述第二节点的电位；
所述输出控制模块的第一输入端与所述低电平信号端相连，第二输入端与第二时钟信号端相连，第一控制端与第三节点相连，第二控制端与所述第二节点相连，输出端与所述扫描信号输出端相连，所述输出控制模块用于在所述第三节点或所述第二节点的控制下，控制所述扫描信号输出端选择输出所述第二时钟信号端的信号或所述低电平信号端的信号；
所述输出降噪模块的输入端与所述第一节点相连，控制端与所述高电平信号端相连，输出端与所述第三节点相连，所述输出降噪模块用于将所述第一节点的信号进行滤波降噪后输出到到所述第三节点。
在一种可能的实施方式中，本公开实施例提供的上述移位寄存器中，所述输出降噪模块，具体包括：第一开关晶体管；
所述第一开关晶体管的栅极与所述高电平信号端相连，源极与所述第一节点相连，漏极与所述第三节点相连。
在一种可能的实施方式中，本公开实施例提供的上述移位寄存器中，还包括：第一节点降噪模块；
所述第一节点降噪模块连接于所述第一节点、所述高电平信号端和所述第一开关晶体管的源极之间，所述第一节点降噪模块用于对所述第一节点的信号进行进一步滤波降噪后输出到所述第一开关晶体管的源极。
在一种可能的实施方式中，本公开实施例提供的上述移位寄存器中，所述第一节点降噪模块，具体包括：第二开关晶体管和第开关三晶体管；其中，
所述第二开关晶体管的栅极与所述第一节点相连，源极与所述第三开关晶体管的漏极相连，漏极与所述第一开关晶体管的源极相连；
所述第三开关晶体管的栅极和源极分别与所述高电平信号端相连。
在一种可能的实施方式中，本公开实施例提供的上述移位寄存器中，还包括：第二节点降噪模块；
所述第二节点降噪模块连接于所述高电平信号端、所述第二节点上拉模块的输出端和所述第二节点之间，所述第二节点降噪模块用于对所述第二节点上拉模块输出端输出的信号进行滤波降噪后输出到所述第二节点。
在一种可能的实施方式中，本公开实施例提供的上述移位寄存器中，所述第二节点降噪模块，具体包括：第四开关晶体管；
所述第四开关晶体管的栅极与所述高电平信号端相连，源极与所述第二节点上拉模块的输出端相连，漏极与所述第二节点相连。
在一种可能的实施方式中，本公开实施例提供的上述移位寄存器中，所述第二节点上拉模块，具体包括：第五开关晶体管；
所述第五开关晶体管的栅极与所述第一时钟信号端相连，源极与所述高电平信号端相连，漏极与所述第四开关晶体管的源极相连。
在一种可能的实施方式中，本公开实施例提供的上述移位寄存器中，还包 括：保护模块；
所述保护模块连接于所述第一信号输入端、所述第二信号输入端、所述高电平信号端和所述第二节点上拉模块的输出端之间，所述保护模块用于在所述第一信号输入端或所述第二信号输入端输入异常电流信号时，对异常电流信号进行分流。
在一种可能的实施方式中，本公开实施例提供的上述移位寄存器中，所述保护模块，具体包括：第六开关晶体管和第七开关晶体管；其中，
所述第六开关晶体管的栅极与所述第一信号输入端相连，源极与所述高电平信号端相连，漏极与所述第七开关晶体管的源极相连；
所述第七开关晶体管的栅极与所述第二信号输入端相连，漏极与所述第二节点上拉模块的输出端相连。
在一种可能的实施方式中，本公开实施例提供的上述移位寄存器中，还包括：维持模块；
所述维持模块的输入端与所述高电平信号端相连，控制端和输出端分别与所述扫描信号输出端相连，所述维持模块用于在所述扫描信号输出端输出扫描信号时，维持所述扫描信号输出端的电位。
在一种可能的实施方式中，本公开实施例提供的上述移位寄存器中，所述维持模块，具体包括：第八开关晶体管；
所述第八开关晶体管的栅极和漏极分别与所述扫描信号输出端相连，源极与所述高电平信号端相连。
在一种可能的实施方式中，本公开实施例提供的上述移位寄存器中，所述输出控制模块，具体包括：第一输出控制模块和第二输出控制模块；其中，
所述第一输出控制模块连接于所述第三节点、所述第二时钟信号端，以及所述扫描信号输出端之间，所述第一输出控制模块用于在所述第三节点的控制下，控制所述扫描信号输出端输出所述第二时钟信号端的信号；
所述第二输出控制模块连接于所述低电平信号端、所述第二节点，以及所述扫描信号输出端之间，所述第二输出控制模块用于在所述第二节点的控制下，控制所述扫描信号输出端输出所述低电平信号端的信号。
在一种可能的实施方式中，本公开实施例提供的上述移位寄存器中，所述第一输出控制模块，具体包括：第九开关晶体管和第一电容；其中，
所述第九开关晶体管的栅极与所述第三节点相连，源极与所述第二时钟信号端相连，漏极与所述扫描信号输出端相连；
所述第一电容连接于所述第三节点与所述扫描信号输出端之间。
在一种可能的实施方式中，本公开实施例提供的上述移位寄存器中，所述第二输出控制模块，具体包括：第十开关晶体管；
所述第十开关晶体管的栅极与所述第二节点相连，源极与所述低电平信号端相连，漏极与所述扫描信号输出端相连。
在一种可能的实施方式中，本公开实施例提供的上述移位寄存器中，所述第二输出控制模块，还包括：第二电容；
所述第二电容连接于所述第二节点和所述低电平信号端之间。
在一种可能的实施方式中，本公开实施例提供的上述移位寄存器中，所述第二节点下拉模块，具体包括：第一下拉模块和第二下拉模块；其中，
所述第一下拉模块的输入端与所述低电平信号端相连，控制端与所述第一节点相连，输出端与所述第二节点相连，所述第一下拉模块用于在所述第一节点的控制下拉低所述第二节点的电位；
所述第二下拉模块的输入端与所述低电平信号端相连，控制端与所述扫描信号输出端相连，输出端与所述第二节点相连，所述第二下拉模块用于在所述扫描信号输出端输出扫描信号时进一步拉低所述第二节点的电位。
在一种可能的实施方式中，本公开实施例提供的上述移位寄存器中，所述第一下拉模块，具体包括：第十一开关晶体管；
所述第十一开关晶体管的栅极与所述第一节点相连，源极与所述低电平信号端相连，漏极与所述第二节点相连。
在一种可能的实施方式中，本公开实施例提供的上述移位寄存器中，所述第二下拉模块，具体包括：第十二开关晶体管；
所述第十二开关晶体管的栅极与所述扫描信号输出端相连，源极与所述低电平信号端相连，漏极与所述第二节点相连。
在一种可能的实施方式中，本公开实施例提供的上述移位寄存器中，所述输入模块，具体包括：第十三开关晶体管和第十四开关晶体管；
所述第十三开关晶体管的栅极与所述第一参考信号端相连，源极与所述第一信号输入端相连，漏极分别与所述第十四开关晶体管的源极和所述第一节点相连；
所述第十四开关晶体管的栅极与所述第二参考信号端相连，源极与所述第二信号输入端相连。
在一种可能的实施方式中，本公开实施例提供的上述移位寄存器中，所述第一节点下拉模块，具体包括：第十五开关晶体管；
所述第十五开关晶体管的栅极与所述第二节点上拉模块的输出端相连，源极与所述低电平信号端相连，漏极与所述输出降噪模块的输入端相连。
本公开实施例提供了一种栅极驱动电路，包括级联的多个本公开实施例提供的上述移位寄存器，除最后一个移位寄存器之外，其余每个移位寄存器的扫描信号输出端均向与其相邻的下一个移位寄存器的信号输入端输入触发信号。
本公开实施例提供了一种显示面板，包括本公开实施例提供的上述栅极驱动电路。
本公开实施例提供了一种显示装置，包括本公开实施例提供的上述显示面板。
本公开实施例的有益效果包括：
本公开实施例提供了一种移位寄存器、栅极驱动电路、显示面板及显示装置，该移位寄存器包括输入模块、第一节点下拉模块、第二节点上拉模块、第二节点下拉模块、输出控制模块，以及输出降噪模块；其中，输入模块用于在第一参考信号端或第二参考信号端的控制下拉高第一节点的电位；第一节点下拉模块用于在第二节点的控制下拉低第一节点的电位；第二节点上拉模块用于在第一时钟信号端的控制下拉高第二节点的电位；第二节点下拉模块用于在第一节点和扫描信号输出端的控制下拉低第二节点的电位；输出控制模块用于在第三节点和第二节点的控制下，控制扫描信号输出端选择输出第二时钟信号端的信号或低电平信号端的信号，这样实现了移位寄存器在对应时间段输出扫描 信号的功能，同时，输出降噪模块用于将第一节点的信号进行滤波降噪，且将滤波降噪后的信号传输到第三节点，从而输出控制模块在第三节点的控制下输出低噪声扫描信号，并且可以避免第一电容在较大的噪声信号的影响下使扫描信号输出端输出噪声信号，提高信号的无损耗传输，降低功耗，进而提高显示面板的良率。
附图说明
图1为现有技术中移位寄存器的结构示意图；
图2为现有的移位寄存器的输入输出时序图；
图3为本公开实施例提供的移位寄存器的结构示意图；
图4-图7分别为本公开实施例提供的移位寄存器的具体结构示意图；
图8为本公开实施例提供的移位寄存器的输入输出时序图；
图9为本公开实施例提供的栅极驱动电路的结构示意图。
具体实施方式
下面结合附图，对本公开实施例提供的移位寄存器，栅极驱动电路、显示面板及显示装置的具体实施方式进行详细地说明。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
本公开实施例提供了一种移位寄存器，如图3所示，可以包括：输入模块01、第一节点下拉模块02、第二节点上拉模块03、第二节点下拉模块04、输出控制模块05，以及输出降噪模块06；其中，
输入模块01的第一输入端与第一信号输入端Input1相连，第二输入端与第二信号输入端Input2相连，第一控制端与第一参考信号端CN相连，第二控制端 与第二参考信号端CNB相连，输出端与第一节点P1相连，输入模块01用于在第一参考信号端CN或第二参考信号端CNB的控制下拉高第一节点P1的电位；
第一节点下拉模块02的输入端与低电平信号端VGL相连，控制端与第二节点P2相连，输出端与第一节点P1相连，第一节点下拉模块02用于在第二节点P2的控制下拉低第一节点P1的电位；
第二节点上拉模块03的输入端与高电平信号端VGH相连，控制端与第一时钟信号端CLK相连，输出端与第二节点P2相连，第二节点上拉模块03用于在第一时钟信号端CLK的控制下拉高第二节点P2的电位；
第二节点下拉模块04的第一输入端和第二输入端分别与低电平信号端VGL相连，第一控制端与第一节点P1相连，第二控制端与扫描信号输出端Out相连，输出端与第二节点P2相连，第二节点下拉模块04用于在第一节点P1或扫描信号输出端Out的控制下拉低第二节点P2的电位；
输出控制模块05的第一输入端与低电平信号端VGL相连，第二输入端与第二时钟信号端CLKB相连，第一控制端与第三节点P3相连，第二控制端与第二节点P2相连，输出端与扫描信号输出端Out相连，输出控制模块05用于在第三节点P3或第二节点P2的控制下，控制扫描信号输出端Out选择输出第二时钟信号端CLKB的信号或低电平信号端VGL的信号；
输出降噪模块06的输入端与第一节点P1相连，控制端与高电平信号端VGH相连，输出端与第三节点P3相连，输出降噪模块06用于将第一节点P1的信号进行滤波降噪后输出到第三节点P3。
本公开实施例提供的上述移位寄存器中，包括输入模块01、第一节点下拉模块02、第二节点上拉模块03、第二节点下拉模块04，输出控制模块05，以及输出降噪模块06；其中，输入模块01用于拉高第一节点P1的电位；第一节点下拉模块02用于拉低第一节点P1的电位；第二节点上拉模块03用于拉高第二节点P2的电位；第二节点下拉模块04用于拉低第二节点P2的电位；输出控制模块05用于控制扫描信号输出端Out选择输出第二时钟信号端CLKB的信号或低电平信号端VGL的信号，这样实现了移位寄存器输出扫描信号的功能，同时，输出降噪模块用于将第一节点的信号进行滤波降噪，且将滤波降噪后的信号传输 到第三节点，从而输出控制模块在第三节点的控制下输出低噪声扫描信号，并且可以避免第一电容在较大的噪声信号的影响下使扫描信号输出端输出噪声信号，提高信号的无损耗传输，降低功耗，进而提高显示面板的良率。
在具体实施时，本公开实施例提供的上述移位寄存器中，如图4所示，输出降噪模块06，可以具体包括：第一开关晶体管T1；第一开关晶体管T1的栅极与高电平信号端VGH相连，源极与第一节点P1相连，漏极与第三节点P3相连。
具体地，由于第一开关晶体管T1的栅极与高电平信号端VGH相连，因此第一开关晶体管T1处于常开状态，作为单管传输门工作，因此第一开关晶体管T1可以对第一节点P1的信号进行滤波降噪，并将滤波降噪后的信号传输到第三节点P3。
在具体实施时，本公开实施例提供的上述移位寄存器中，如图5所示，还可以包括：第一节点降噪模块07；第一节点降噪模块07连接于第一节点P1、高电平信号端VGH和第一开关晶体管T1的源极之间，第一节点降噪模块07用于在第一节点P1的控制下将高电平信号端VGH与第一开关晶体管T1的源极导通。
具体地，第一节点降噪模块07在第一节点的电位被拉高时，将高电平信号端VGH与第一开关晶体管T1的源极导通，即可以对第一节点P1的信号进行直流拉高，从而进一步滤波降噪，降低第一节点P1的信号噪声，进而将第一节点P1降噪后的信号输出到第一开关晶体管T1的源极，通过第一开关晶体管T1对信号再进行滤波降噪，进一步降低信号的噪声，提高信号的无损耗传输，从而降低功耗。
在具体实施时，本公开实施例提供的上述移位寄存器中，如图5所示，第一节点降噪模块07，可以具体包括：第二开关晶体管T2和第三开关晶体管T3；其中，第二开关晶体管T2的栅极与第一节点P1相连，源极与第三开关晶体管T3的漏极相连，漏极与第一开关晶体管T1的源极相连；第三开关晶体管T3的栅极和源极分别与高电平信号端VGH相连。
具体地，当第一节点P1的电位被拉高时，第二开关晶体管T2处于导通状态，而由于第三开关晶体管T3的栅极和源极分别与高电平信号端VGH相连， 因此第三开关晶体管T3处于常开状态，作为单管传输门工作，因此在第一节点P1的电位被拉高时，高电平信号端VGH的信号通过第三开关晶体管T3和导通的第二开关晶体管T2输出到第一开关晶体管T1的源极，对第一开关晶体管T1的源极的信号进行直流拉高，进一步降低信号噪声，而不是将第一节点P1未经降噪的信号输出到第一开关晶体管T1的源极，这样可以降低第一开关晶体管T1的源极的信号的噪声。
在具体实施时，本公开实施例提供的上述移位寄存器中，如图6和图7所示，还可以包括：第二节点降噪模块08；第二节点降噪模块08连接于高电平信号端VGH、第二节点上拉模块03的输出端和第二节点P2之间，第二节点降噪模块08用于对第二节点上拉模块03的输出端的信号进行滤波降噪，将滤波降噪后的信号输出到第二节点P2，进一步降低第二节点P2的信号噪声。
具体地，第二节点降噪模块08在高电平信号端VGH的控制下处于常开状态，作为传输门工作，对第二节点上拉模块03的输出端的信号进行滤波降噪，并将滤波降噪后的信号输出到第二节点P2，进一步降低第二节点P2的信号噪声。
在具体实施时，本公开实施例提供的上述移位寄存器中，如图6和图7所示，第二节点降噪模块08，可以具体包括：第四开关晶体管T4；第四开关晶体管T4的栅极与高电平信号端VGH相连，源极与第二节点上拉模块03的输出端相连，漏极与第二节点P2相连。
具体地，由于第四开关晶体管T4的栅极与高电平信号端VGH相连，因此第四开关晶体管T4处于常开状态，作为单管传输门工作，对第二节点上拉模块03的输出端的信号进行滤波降噪，且将滤波降噪后的信号输出到第二节点P2，进一步降低第二节点P2的信号噪声。
在具体实施时，本公开实施例提供的上述移位寄存器中，如图6和图7所示，第二节点上拉模块03，可以具体包括：第五开关晶体管T5；第五开关晶体管T5的栅极与第一时钟信号端CLK相连，源极与高电平信号端VGH相连，漏极与第四开关晶体管T4的源极相连。
具体地，第二节点上拉模块03在第一时钟信号端CLK输入高电平信号时， 第五开关晶体管T5处于导通状态，导通的第五开关晶体管T5将高电平信号端VGH与第四开关晶体管T4的源极导通，拉高第四开关晶体管T4的源极的电位，由于第四开关晶体管T4处于常开状态，因此可以拉高第二节点P2的电位。
在具体实施时，本公开实施例提供的上述移位寄存器中，如图6和图7所示，还可以包括：保护模块09；保护模块09连接于第一输入信号端Input1、第二信号输入端Input2、高电平信号端VGH和第二节点上拉模块03的输出端之间，保护模块09用于在第一信号输入端Input1或第二信号输入端Input2输入异常电流信号时，对异常电流信号进行分流。
具体地，保护模块09在移位寄存器正常工作时处于关闭状态，在第一信号输入端Input1或第二信号输入端Input2输入异常电流信号时，其中异常电流信号为高于正常电流信号的大电流信号，例如信号输入端正常输入信号为1V的信号，当信号输入端输入的信号为10V信号时，则信号输入端输入了异常信号，此时，输入的大电流信号可能损坏移位寄存器中的晶体管，因此保护模块09此时可以对异常电流信号进行分流，起保护作用，避免移位寄存器由于异常电流信号的输入而损坏。
在具体实施时，本公开实施例提供的上述移位寄存器中，如图6和图7所示，保护模块09，可以具体包括：第六开关晶体管T6和第七开关晶体管T7；其中，第六开关晶体管T6的栅极与第一信号输入端Input1相连，源极与高电平信号端VGH相连，漏极与第七开关晶体管T7的源极相连；
第七开关晶体管T7的栅极与第二信号输入端Input2相连，漏极与第二节点上拉模块03的输出端相连。
具体地，在移位寄存器正常工作时处于关闭状态，第六开关晶体管T6和第七开关晶体管T7均处于截止状态，在第一信号输入端Input1或第二信号输入端Input2输入大电流信号时，对应第六开关晶体管T6或第七开关晶体管T7处于导通状态，对输入的异常电流信号进行分流缓冲，对移位寄存器起保护作用，避免移位寄存器由于异常电流信号的输入而损坏。
在具体实施时，本公开实施例提供的上述移位寄存器中，如图6和图7所示，还可以包括：维持模块10；维持模块10的输入端与高电平信号端VGH相连， 控制端和输出端分别与扫描信号输出端Out相连，维持模块10用于在扫描信号输出端Out输出扫描信号时，维持扫描信号输出端Out的电位。
具体地，当扫描信号输出端Out输出扫描信号时，维持模块10处于开启状态，将高电平信号端VGH与扫描信号输出端Out导通，进而将高电平信号输出到扫描信号输出端Out，进一步维持扫描信号输出端Out的电位。
在具体实施时，本公开实施例提供的上述移位寄存器中，如图6和图7所示，维持模10，可以具体包括：第八开关晶体管T8；第八开关晶体管T8的栅极和漏极分别与扫描信号输出端Out相连，源极与高电平信号端VGH相连。
具体地，当扫描信号输出端Out输出扫描信号时，第八开关晶体管T8处于导通状态，导通的第八开关晶体管T8将高电平信号端VGH与扫描信号输出端Out导通，进一步维持扫描信号输出端Out的电位。
在具体实施时，本公开实施例提供的上述移位寄存器中，如图6和图7所示，输出控制模块05，可以具体包括：第一输出控制模块051和第二输出控制模块052；其中，
第一输出控制模块051连接于第三节点P3、第二时钟信号端CLKB，以及扫描信号输出端Out之间，第一输出控制模块051用于在第三节点P3的控制下，控制扫描信号输出端Out输出第二时钟信号端CLKB的信号；
第二输出控制模块052连接于低电平信号端VGL、第二节点P2，以及扫描信号输出端Out之间，第二输出控制模块052用于在第二节点P2的控制下，控制扫描信号输出端Out输出低电平信号端VGL的信号。
具体地，第一输出控制模块051和第二输出控制模块052分别在第三节点P3和第二节点P2的控制下对应输出第二时钟信号端CLKB的信号和低电平信号端VGL的信号，实现移位寄存器在对应时间段向对应栅线输出扫描信号，驱动显示面板实现逐行扫描。
在具体实施时，本公开实施例提供的上述移位寄存器中，如图6和图7所示，第一输出控制模块051，可以具体包括：第九开关晶体管T9和第一电容C1；其中，第九开关晶体管T9的栅极与第三节点P3相连，源极与第二时钟信号端CLKB相连，漏极与扫描信号输出端Out相连；第一电容C1连接于第三节点P3 与扫描信号输出端Out之间。
具体地，当第三节点P3的电位被拉高时，第九开关晶体管T9处于导通状态，导通的第九开关晶体管T9将第二时钟信号端CLKB与扫描信号输出端Out导通，同时第一电容C1对第三节点P3的电位起到自举作用，进一步保持第三节点P3的电位。
在具体实施时，本公开实施例提供的上述移位寄存器中，如图6所示，第二输出控制模块052，可以具体包括：第十开关晶体管T10；第十开关晶体管T10的栅极与第二节点P2相连，源极与低电平信号端VGL相连，漏极与扫描信号输出端Out相连。
具体地，当第二节点P2的电位被拉高时，第十开关晶体管T10处于导通状态，导通的第十开关晶体管T10将低电平信号端VGL与扫描信号输出端Out导通，同时通过第十开关晶体管T10的寄生电容也可以维持第二节点P2的电位。
在具体实施时，本公开实施例提供的上述移位寄存器中，如图7所示，第二输出控制模块052，还可以包括：第二电容C2；第二电容C2连接于第二节点P2和低电平信号端VGL之间。
具体地，当第二节点P2的电位被拉高时，第十开关晶体管T10处于导通状态，导通的第十开关晶体管T10将低电平信号端VGL与扫描信号输出端Out导通，同时第二电容C2可以进一步保持第二节点P2的电位，降低第二节点P2的电压信号的噪声。
在具体实施时，本公开实施例提供的上述移位寄存器中，如图6和图7所示，第二节点下拉模块04，可以具体包括：第一下拉模块041和第二下拉模块042；其中，第一下拉模块041的输入端与低电平信号端VGL相连，控制端与第一节点P1相连，输出端与第二节点P2相连，第一下拉模块041用于在第一节点P1的控制下拉低第二节点P2的电位；第二下拉模块042的输入端与低电平信号端VGL相连，控制端与扫描信号输出端Out相连，输出端与第二节点P2相连，第二下拉模块042用于在扫描信号输出端Out输出扫描信号时进一步拉低第二节点P2的电位。
具体地，第一下拉模块041和第二下拉模块042分别在第一节点P1的电位 被拉高时和扫描信号输出端Out输出扫描信号时，拉低第二节点P2的电位，降低第二节点P2的信号噪声。
在具体实施时，本公开实施例提供的上述移位寄存器中，如图6和图7所示，第一下拉模块041，可以具体包括：第十一开关晶体管T11；第十一开关晶体管T11的栅极与第一节点P1相连，源极与低电平信号端VGL相连，漏极与第二节点P2相连。
具体地，在第一节点P1的电位被拉高时，第十一开关晶体管T11处于导通状态，导通的第十一开关晶体管T11将低电平信号端VGL与第二节点P2导通，拉低第二节点P2的电位，降低第二节点P2的信号的噪声。
在具体实施时，本公开实施例提供的上述移位寄存器中，如图6和图7所示，第二下拉模块042，可以具体包括：第十二开关晶体管T12；第十二开关晶体管T12的栅极与扫描信号输出端Out相连，源极与低电平信号端VGL相连，漏极与第二节点P2相连。
具体地，在扫描信号输出端Out输出扫描信号时，第十二开关晶体管T12处于导通状态，导通的第十二开关晶体管T12将低电平信号端VGL与第二节点P2导通，拉低第二节点P2的电位，降低第二节点P2的信号的噪声。
在具体实施时，本公开实施例提供的上述移位寄存器中，如图6和图7所示，输入模块01，可以具体包括：第十三开关晶体管T13和第十四开关晶体管T14；第十三开关晶体管T13的栅极与第一参考信号端CN相连，源极与第一信号输入端Input1相连，漏极分别与第十四开关晶体管T14的源极和第一节点P1相连；第十四开关晶体管T14的栅极与第二参考信号端CNB相连，源极与第二信号输入端Input2相连。
具体地，由于第十三开关晶体管T13和第十四开关晶体管T14的栅极分别与第一参考信号端CN和第二参考信号端CNB相连，因此正向扫描时第十三开关晶体管T13处于导通状态，当第一信号输入端Input1输入信号时，对应的处于导通状态第十三开关晶体管T13将第一信号输入端Input1与第一节点P1导通，进而将第一信号输入端Input1的信号输出到第一节点P1；反向扫描时第十四开关晶体管T14处于导通状态，当第二信号输入端Input2输入信号时，对应的处 于导通状态第十四开关晶体管T14将第二信号输入端Input2与第一节点P1导通，进而将第二信号输入端Input2的信号输出到第一节点P1。
在具体实施时，本公开实施例提供的上述移位寄存器中，如图6和图7所示，第一节点下拉模块02，可以具体包括：第十五开关晶体管T15；第十五开关晶体管T15的栅极与第二节点上拉模块03的输出端相连，源极与低电平信号端VGL相连，漏极与输出降噪模块06的输入端相连。
具体地，在第二节点P2的电位被拉高时，即第二节点上拉模块03的输出端输出高电平信号时，第十五开关晶体管T15也处于导通状态，导通的第十五开关晶体管T15将低电平信号端VGL与输出降噪模块06的输入端导通，进而拉低输出降噪模块06的输入端的电位，由于输出降噪模块06处于常开状态，因此也拉低了第三节点P3的电位。
需要说明的是本公开上述实施例中提到的开关晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Scmiconductor)，在此不做限定。在具体实施中，这些晶体管的源极和漏极可以互换，不做具体区分。在描述具体实施例时以薄膜晶体管为例进行说明。
进一步地，由于在本公开实施例提供的上述移位寄存器中第一信号输入端Input1和第二信号输入端Input2为对称设计，可以实现功能互换，因此本公开实施例提供的上述移位寄存器可以实现双向扫描。
一般地，在启动正向扫描时，第一参考信号端CN提供高电平信号，第二参考信号端CNB提供低电平信号。一般地，在反向扫描时，第一参考信号端CN提供低电平信号，第二参考信号端CNB提供高电平信号。
下面结合图7所示的移位寄存器以及图8所示的图7的输入输出时序图，以正向扫描为例对本公开实施例提供的移位寄存器的工作过程作以描述。具体地，选取如图8所示的输入输出时序图中的t1～t3三个阶段。下述描述中以1表示高电平信号，0表示低电平信号。
在t1阶段，Input1＝1，CLKB＝0，CLK＝0，CN＝1，CNB＝0。由于CN＝1，因此第十三开关晶体管T13导通，导通的第十三开关晶体管T13将第一信号输 入端Input1与第二开关晶体管T2的栅极导通，因此第二开关晶体管T2导通，而第三开关晶体管T3处于常开状态，因此高电平信号端VGH的信号通过第三开关晶体管T3和导通的第二开关晶体管T2输出到第一开关晶体管T1的源极，由于第一开关晶体管T1处于常开状态，因此第一节点P1的信号经过第一开关晶体管T1的滤波降噪后输出到第三节点P3，第三节点P3的电位被拉高，同时对第一电容C1充电，此时第九开关晶体管T9处于导通状态，导通的第九开关晶体管T9将第二时钟信号端CLKB与扫描信号输出端Out导通，由于此时CLKB＝0，因此扫描信号输出端Out输出低电平信号。t1阶段为充电阶段。
在t2阶段，Input1＝0，CLKB＝1，CLK＝0，CN＝1，CNB＝0。由于第一电容C1的自举作用，第三节点P3的电位进一步升高，因此第九开关晶体管T9仍处于导通状态，而此时CLKB＝1，因此，扫描信号输出端Out输出高电平信号。t2阶段为扫描信号输出阶段。
在t3阶段，Input1＝0，CLKB＝0，CLK＝1，CN＝I，CNB＝0。由于CLK＝1，因此第五开关晶体管T5导通，导通的第五开关晶体管T5将高电平信号端VGH与第四开关晶体管T4的源极导通，而第四开关晶体管T4处于常开状态，因此，高电平信号端VGH的信号经过滤波降噪后输出到第二节点P2，第二节点P2的电位被拉高，此时，第十开关晶体管T10处于导通状态，导通的第十开关晶体管T10将低电平信号端VGL与扫描信号输出端Out导通，因此扫描信号输出端Out输出低电平信号，同时由于第四开关晶体管T4的源极的电位被拉高，因此第十五开关晶体管T15处于导通状态，导通的第十五开关晶体管T15将第一开关晶体管T1的源极与低电平信号端VGL导通，因此第一开关晶体管T1的源极的电位被拉低，而第一开关晶体管T1处于常开状态，因此第三节点P3的电位被拉低，第九开关晶体管T9处于截止状态。t3阶段为非扫描信号输出阶段。
在后续时间段，扫描信号输出端Out将一直输出低电平信号，直到某个时间段第一信号输入端Input1再次输入高电平信号时，则该移位寄存器将重复上述工作工程。
基于同一公开构思，本公开实施例提供了一种栅极驱动电路，包括级联的多个本公开实施例提供的上述移位寄存器，除最后一个移位寄存器之外，其余 每个移位寄存器的扫描信号输出端均向与其相邻的下一个移位寄存器的信号输入端输入触发信号。
为了方便说明，图9中仅示出了八个移位寄存器，分别为第1级移位寄存器、第2级移位寄存器、第3级移位寄存器、第4级移位寄存器、第N-3级移位寄存器、第N-2级移位寄存器、第N-1级移位寄存器、第N级移位寄存器。其中，除第N级移位寄存器外，其余每个移位寄存器的扫描信号输出端Out不仅向与其连接的栅线输出栅开启信号，还向与其相邻的下一级移位寄存器输出触发信号。
具体地，上述栅极驱动电路中的每个移位寄存器与本公开提供的上述移位寄存器在功能和结构上均相同，重复之处不再赘述。
基于同一公开构思，本公开实施例提供了一种显示面板，包括本公开实施例提供的上述栅极驱动电路。由于该显示面板解决问题的原理与栅极驱动电路相似，因此该显示面板的实施可以参见上述栅极驱动电路的实施，重复之处不再赘述。
基于同一公开构思，本公开实施例提供了一种显示装置，包括本公开实施例提供的上述显示面板。该显示装置可以应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。由于该显示装置解决问题的原理与显示面板相似，因此该显示装置的实施可以参见上述显示面板的实施，重复之处不再赘述。
本公开实施例提供了一种移位寄存器、栅极驱动电路、显示面板及显示装置，该移位寄存器包括输入模块、第一节点下拉模块、第二节点上拉模块、第二节点下拉模块、输出控制模块，以及输出降噪模块；其中，输入模块用于在信号输入端的控制下拉高第一节点的电位；第一节点下拉模块用于在第二节点的控制下拉低第一节点的电位；第二节点上拉模块用于在第一时钟信号端的控制下拉高第二节点的电位；第二下拉模块用于在第一节点和扫描信号输出端的控制下拉低第二节点的电位；输出控制模块用于在第三节点和第二节点的控制下，控制扫描信号输出端选择输出第二时钟信号端的信号或低电平信号端的信号，这样实现了移位寄存器在对应时间段输出扫描信号的功能，同时，输出降噪模块用于将第一节点的信号进行滤波降噪，且将滤波降噪后的信号传输到第 三节点，从而输出控制模块在第三节点的控制下输出低噪声扫描信号，并且可以避免第一电容在较大的噪声信号的影响下使扫描信号输出端输出噪声信号，提高信号的无损耗传输，降低功耗，进而提高显示面板的良率。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (23)

  1. 一种移位寄存器，包括：输入模块、第一节点下拉模块、第二节点上拉模块、第二节点下拉模块、输出控制模块，以及输出降噪模块；其中，
    所述输入模块的第一输入端与第一信号输入端相连，第二输入端与第二信号输入端相连，第一控制端与第一参考信号端相连，第二控制端与第二参考信号端相连，输出端与第一节点相连，所述输入模块用于在所述第一参考信号端或所述第二参考信号端的控制下拉高所述第一节点的电位；
    所述第一节点下拉模块的输入端与低电平信号端相连，控制端与第二节点相连，输出端与所述第一节点相连，所述第一节点下拉模块用于在所述第二节点的控制下拉低所述第一节点的电位；
    所述第二节点上拉模块的输入端与高电平信号端相连，控制端与第一时钟信号端相连，输出端与所述第二节点相连，所述第二节点上拉模块用于在所述第一时钟信号端的控制下拉高所述第二节点的电位；
    所述第二节点下拉模块的第一输入端和第二输入端分别与所述低电平信号端相连，第一控制端与所述第一节点相连，第二控制端与扫描信号输出端相连，输出端与所述第二节点相连，所述第二节点下拉模块用于在所述第一节点或所述扫描信号输出端的控制下拉低所述第二节点的电位；
    所述输出控制模块的第一输入端与所述低电平信号端相连，第二输入端与第二时钟信号端相连，第一控制端与第三节点相连，第二控制端与所述第二节点相连，输出端与所述扫描信号输出端相连，所述输出控制模块用于在所述第三节点或所述第二节点的控制下，控制所述扫描信号输出端选择输出所述第二时钟信号端的信号或所述低电平信号端的信号；
    所述输出降噪模块的输入端与所述第一节点相连，控制端与所述高电平信号端相连，输出端与所述第三节点相连，所述输出降噪模块用于将所述第一节点的信号进行滤波降噪后输出到所述第三节点。
  2. 如权利要求1所述的移位寄存器，其中，所述输出降噪模块，具体包括：第一开关晶体管；
    所述第一开关晶体管的栅极与所述高电平信号端相连，源极与所述第一节 点相连，漏极与所述第三节点相连。
  3. 如权利要求1或2所述的移位寄存器，还包括：第一节点降噪模块；
    所述第一节点降噪模块连接于所述第一节点、所述高电平信号端和所述第一开关晶体管的源极之间，所述第一节点降噪模块用于对所述第一节点的信号进行进一步的滤波降噪后输出到所述第一开关晶体管的源极。
  4. 如权利要求3所述的移位寄存器，其中，所述第一节点降噪模块，具体包括：第二开关晶体管和第三开关晶体管；其中，
    所述第二开关晶体管的栅极与所述第一节点相连，源极与所述第三开关晶体管的漏极相连，漏极与所述第一开关晶体管的源极相连；
    所述第三开关晶体管的栅极和源极分别与所述高电平信号端相连。
  5. 如权利要求1-4中任一项所述的移位寄存器，还包括：第二节点降噪模块；
    所述第二节点降噪模块连接于所述高电平信号端、所述第二节点上拉模块的输出端和所述第二节点之间，所述第二节点降噪模块用于对所述第二节点上拉模块输出端输出的信号进行滤波降噪后输出到所述第二节点。
  6. 如权利要求5所述的移位寄存器，其中，所述第二节点降噪模块，具体包括：第四开关晶体管；
    所述第四开关晶体管的栅极与所述高电平信号端相连，源极与所述第二节点上拉模块的输出端相连，漏极与所述第二节点相连。
  7. 如权利要求6所述的移位寄存器，其中，所述第二节点上拉模块，具体包括：第五开关晶体管；
    所述第五开关晶体管的栅极与所述第一时钟信号端相连，源极与所述高电平信号端相连，漏极与所述第四开关晶体管的源极相连。
  8. 如权利要求1-7中任一项所述的移位寄存器，还包括：保护模块；
    所述保护模块连接于所述第一信号输入端、所述第二信号输入端、所述高电平信号端和所述第二节点上拉模块的输出端之间，所述保护模块用于在所述第一信号输入端或所述第二信号输入端输入异常电流信号时，对异常电流信号进行分流。
  9. 如权利要求8所述的移位寄存器，其中，所述保护模块，具体包括：第六开关晶体管和第七开关晶体管；其中，
    所述第六开关晶体管的栅极与所述第一信号输入端相连，源极与所述高电平信号端相连，漏极与所述第七开关晶体管的源极相连；
    所述第七开关晶体管的栅极与所述第二信号输入端相连，漏极与所述第二节点上拉模块的输出端相连。
  10. 如权利要求1-9中任一项所述的移位寄存器，还包括：维持模块；
    所述维持模块的输入端与所述高电平信号端相连，控制端和输出端分别与所述扫描信号输出端相连，所述维持模块用于在所述扫描信号输出端输出扫描信号时，维持所述扫描信号输出端的电位。
  11. 如权利要求10所述的移位寄存器，其中，所述维持模块，具体包括：第八开关晶体管；
    所述第八开关晶体管的栅极和漏极分别与所述扫描信号输出端相连，源极与所述高电平信号端相连。
  12. 如权利要求1-11任一项所述的移位寄存器，其中，所述输出控制模块，具体包括：第一输出控制模块和第二输出控制模块；其中，
    所述第一输出控制模块连接于所述第三节点、所述第二时钟信号端，以及所述扫描信号输出端之间，所述第一输出控制模块用于在所述第三节点的控制下，控制所述扫描信号输出端输出所述第二时钟信号端的信号；
    所述第二输出控制模块连接于所述低电平信号端、所述第二节点，以及所述扫描信号输出端之间，所述第二输出控制模块用于在所述第二节点的控制下，控制所述扫描信号输出端输出所述低电平信号端的信号。
  13. 如权利要求12所述的移位寄存器，其中，所述第一输出控制模块，具体包括：第九开关晶体管和第一电容；其中，
    所述第九开关晶体管的栅极与所述第三节点相连，源极与所述第二时钟信号端相连，漏极与所述扫描信号输出端相连；
    所述第一电容连接于所述第三节点与所述扫描信号输出端之间。
  14. 如权利要求12所述的移位寄存器，其中，所述第二输出控制模块，具 体包括：第十开关晶体管；
    所述第十开关晶体管的栅极与所述第二节点相连，源极与所述低电平信号端相连，漏极与所述扫描信号输出端相连。
  15. 如权利要求14所述的移位寄存器，其中，所述第二输出控制模块还包括：第二电容；
    所述第二电容连接于所述第二节点和所述低电平信号端之间。
  16. 如权利要求1-15任一项所述的移位寄存器，其中，所述第二节点下拉模块，具体包括：第一下拉模块和第二下拉模块；其中，
    所述第一下拉模块的输入端与所述低电平信号端相连，控制端与所述第一节点相连，输出端与所述第二节点相连，所述第一下拉模块用于在所述第一节点的控制下拉低所述第二节点的电位；
    所述第二下拉模块的输入端与所述低电平信号端相连，控制端与所述扫描信号输出端相连，输出端与所述第二节点相连，所述第二下拉模块用于在所述扫描信号输出端输出扫描信号时进一步拉低所述第二节点的电位。
  17. 如权利要求16所述的移位寄存器，其中，所述第一下拉模块，具体包括：第十一开关晶体管；
    所述第十一开关晶体管的栅极与所述第一节点相连，源极与所述低电平信号端相连，漏极与所述第二节点相连。
  18. 如权利要求16所述的移位寄存器，其中，所述第二下拉模块，具体包括：第十二开关晶体管；
    所述第十二开关晶体管的栅极与所述扫描信号输出端相连，源极与所述低电平信号端相连，漏极与所述第二节点相连。
  19. 如权利要求1-18任一项所述的移位寄存器，其中，所述输入模块，具体包括：第十三开关晶体管和第十四开关晶体管；
    所述第十三开关晶体管的栅极与所述第一参考信号端相连，源极与所述第一信号输入端相连，漏极分别与所述第十四开关晶体管的源极和所述第一节点相连；
    所述第十四开关晶体管的栅极与所述第二参考信号端相连，源极与所述第 二信号输入端相连。
  20. 如权利要求1-19任一项所述的移位寄存器，其中，所述第一节点下拉模块，具体包括：第十五开关晶体管；
    所述第十五开关晶体管的栅极与所述第二节点上拉模块的输出端相连，源极与所述低电平信号端相连，漏极与所述输出降噪模块的输入端相连。
  21. 一种栅极驱动电路，包括级联的多个如权利要求1-20任一项所述的移位寄存器，除最后一个移位寄存器之外，其余每个移位寄存器的扫描信号输出端均向与其相邻的下一个移位寄存器的信号输入端输入触发信号。
  22. 一种显示面板，包括如权利要求21所述的栅极驱动电路。
  23. 一种显示装置，包括如权利要求22所述的显示面板。
PCT/CN2015/084995 2015-03-26 2015-07-24 移位寄存器、栅极驱动电路、显示面板及显示装置 Ceased WO2016150053A1 (zh)

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