WO2016149964A1 - 具有带冗余位的非二进制电容阵列的模数转换器及芯片 - Google Patents

具有带冗余位的非二进制电容阵列的模数转换器及芯片 Download PDF

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WO2016149964A1
WO2016149964A1 PCT/CN2015/076126 CN2015076126W WO2016149964A1 WO 2016149964 A1 WO2016149964 A1 WO 2016149964A1 CN 2015076126 W CN2015076126 W CN 2015076126W WO 2016149964 A1 WO2016149964 A1 WO 2016149964A1
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capacitor
binary
bit
capacitors
capacitor array
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PCT/CN2015/076126
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English (en)
French (fr)
Inventor
徐代果
徐世六
胡刚毅
陈光炳
刘璐
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中国电子科技集团公司第二十四研究所
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Priority to US15/555,071 priority Critical patent/US10084470B2/en
Publication of WO2016149964A1 publication Critical patent/WO2016149964A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/44—Sequential comparisons in series-connected stages with change in value of analogue signal
    • H03M1/442—Sequential comparisons in series-connected stages with change in value of analogue signal using switched capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
    • H03M1/069—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
    • H03M1/0678—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
    • H03M1/068—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array

Definitions

  • the present invention relates to the field of analog or digital-analog hybrid integrated circuit technology, and more particularly to a non-binary capacitor array with redundant bits, and an analog-to-digital converter and integrated chip implemented using a non-binary capacitor array with redundant bits.
  • the analog-to-digital converter is often packaged into an integrated chip, and in the production process of the integrated chip, the layout of the entire circuit needs to be designed. Since the existing successive approximation analog-to-digital converter capacitor array adopts a binary increment method, that is, a strict ordered capacitor arrangement design in a power-of-two increment manner, the design scheme is insufficient. The reason is that in the later chip layout design process, in view of the relatively fixed design of the capacitor array, the working speed and layout area of the whole circuit cannot be flexibly compromised, and the flexible design can not be flexibly changed according to the actual situation. Therefore, it cannot adapt to the requirements of high-speed and low power consumption of successive approximation analog-to-digital converters.
  • an object of the present invention is to provide an analog-to-digital converter and chip having a non-binary capacitor array with redundant bits for solving the prior art successive approximation analog-to-digital converter technology.
  • the design of the capacitor array is relatively fixed. In the actual chip layout design, the working speed and layout area of the whole circuit cannot be flexibly compromised, and it is not possible to flexibly change in the layout design according to the actual situation. The problem of high speed and low power consumption of approximating analog to digital converters.
  • a non-binary capacitor array with redundant bits for sampling an analog signal wherein the non-binary capacitor array includes at least a common mode voltage terminal, an analog signal input terminal, and at least one redundant bit capacitor and a plurality of Capacitor, the at least one redundant bit capacitor and each of the plurality of capacitors are disposed in parallel between the common mode voltage terminal and the analog signal input terminal, and are in the order of highest bit to lowest bit/lowest bit to highest bit All capacitors disposed between the common mode voltage terminal and the analog signal input terminal are sequentially labeled, and the sum of the capacitance values corresponding to the lowest bit capacitance to any one of the capacitors must be greater than or equal to the adjacent one of the capacitors
  • the capacitance value corresponding to the upper one capacitor is set, and the ratio of the capacitance of each of the at least one redundant bit capacitor and the plurality of capacitors to the capacitance of the unit capacitor is set to be a positive integer.
  • the capacitance of each of the redundant bit capacitors is greater than or equal to a minimum capacitance value of the other plurality of capacitors, and is less than or equal to the other plurality of capacitors. The maximum capacitance value.
  • the number of the at least one redundant bit capacitor is smaller than the number of the plurality of capacitors.
  • the at least one redundant capacitor is respectively connected to the common mode voltage terminal at both ends when performing analog signal sampling, and among the plurality of capacitors Each of the capacitors is respectively connected to the common mode voltage terminal and the analog signal input terminal when performing analog signal sampling.
  • each of said at least one capacitor and a capacitance of performing analog signal redundancy plurality of sampling capacitors are connected to both ends of the sequence corresponding to the Common mode voltage terminal and analog signal input.
  • the invention also applies the technical solution in the first scheme to the analog-to-digital converter, thereby obtaining a non-binary successive approximation analog-to-digital converter with redundant bits, at least comprising: a successive approximation switch; Any non-binary capacitor array with redundant bits in the preferred scheme for sampling an analog signal and obtaining a corresponding sampling signal; a comparator, an input terminal connected to the non-binary capacitor array, and an output terminal connected through the successive approximation switch The common mode voltage terminal, the comparator is configured to perform successive approximation comparison on the sampling signal output by the non-binary capacitor array, and output a binary digital signal; and a reconstruction module, the input end is connected to the output of the comparator And a digital conversion signal for performing addition reconstruction on the digital signal and outputting a binary; an overflow determination module, wherein the input end is connected to an output end of the reconstruction module, and is used for outputting the reconstruction module
  • the digital conversion signal is corrected after the high bit overflow judgment and the low bit overflow judgment
  • the reconstruction module is specifically a full adder.
  • the invention can also apply the technical solutions of the foregoing scheme 1 and scheme 2 to the integrated chip, that is, apply the non-binary capacitor array with redundant bits to the analog-to-digital conversion chip, or the non-redundant bit A binary successive approximation analog-to-digital converter is used to make an integrated chip.
  • the present invention has the following beneficial effects as compared with the prior art:
  • the capacitance value of the capacitor corresponding to each digit code can be flexibly designed according to the actual situation, and the optimal combination of speed, power consumption and area can be realized.
  • the capacitance of each set of capacitors can be flexibly designed, thereby reducing the difficulty of the back-end layout design, and the flexible shape can be flexibly placed according to the specific layout requirements of the layout and the specific shape of the capacitor provided by the process. capacitance.
  • the existence of the overflow judgment module can effectively avoid the non-monotonic problem caused by the overflow of the upper limit and the lower limit, and improve the reliability of the design.
  • the proposal of the reconstruction algorithm reveals the general law of the working principle of the successive approximation analog-to-digital converter, and deeply understands the working principle of such an analog-to-digital converter and further studies such an analog-to-digital converter correction algorithm. , all have a lot of help.
  • Figure 1 is a schematic diagram of a successive approximation analog-to-digital converter
  • Figure 2 is a schematic diagram of a non-redundant bit binary successive approximation analog-to-digital converter CDAC
  • Figure 3 is a schematic diagram of a CDAC with a redundant bit binary successive approximation analog-to-digital converter
  • FIG. 4 is a schematic diagram of a reconstruction algorithm of a binary successive approximation analog-to-digital converter with redundant bits
  • FIG. 5 is a schematic diagram of a reconstruction algorithm of a non-binary successive approximation analog-to-digital converter with redundant bits
  • Figure 6 is a schematic diagram of a reconstruction unit REBUILDER
  • Figure 7 is a comparison diagram of transmission curves before and after the overflow judgment
  • Figure 8 is a schematic diagram of the overflow judgment module OVERFLOW DETECT
  • FIG. 9 is a schematic diagram of a non-binary capacitor array CDAC with redundant bits in Example 2.
  • FIG. 10 is a schematic diagram of a non-binary capacitor array CDAC with redundant bits in Example 3.
  • Figure 11 is a schematic diagram of a non-binary successive approximation analog-to-digital converter with redundant bits.
  • FIG. 1 a schematic diagram of a capacitor array CDAC in a redundancy-free successive approximation analog-to-digital converter is shown.
  • equation (3) can be further reduced to:
  • FIG. 2 shows a schematic diagram of the structure principle of a conventional redundancy-free successive approximation analog-to-digital converter. It should be noted that, as shown in FIG. 1, the redundancy-free successive approximation analog-to-digital conversion In the structure of the comparator, the output of the comparator is the final output of the analog-to-digital converter, which is our most common form.
  • the switch corresponding to the capacitor K(n-1)C is switched to the switch corresponding to the capacitor K1C, and the successive approximation process is finally completed, and the capacitor is in the process.
  • the switch corresponding to K0C is always connected to the common mode voltage VCM.
  • the capacitance values of K0C, K1C, K2C, K3C, ..., KrC, ..., K(n-2)C, K(n-1)C, etc. in the capacitor array CDAC can be set in a natural number instead of The traditional binary way. In this way, the implementation of the capacitor array CDAC is very flexible, and the capacitor array under different capacitance combinations can be designed according to different requirements.
  • the reconstruction algorithm of the natural number capacitor array is introduced below.
  • the subscript j represents the highest bit capacitance.
  • the order of the lowest capacitance or the lowest capacitance to the highest capacitance For example, suppose there are 10 capacitors in the capacitor array (of course, there are redundant bit capacitors), and now the 10 capacitors are respectively labeled as the highest capacitance, the second highest capacitance, the third high capacitance, ... the ninth high capacitance.
  • the order of the lowest capacitance is sequentially marked; or sequentially labeled in the order of "lowest capacitance, second low capacitance, third low capacitance, ...
  • the capacitance of the high level capacitor must be less than or equal to the sum of the capacitance of the lowest bit capacitance to the third high level capacitor (again, if it is from the "lowest bit capacitance, the second low order capacitance, the third low order capacitance, ...
  • Nine low-level capacitors and highest-order capacitors can be selected in the order of one capacitor.
  • the capacitance of the fourth low-level capacitor must be less than or equal to the sum of the capacitances of the lowest-level capacitor and the third-lower capacitor.
  • the sum of the capacitances that must satisfy the lowest bit capacitance to any one of the capacitors must be greater than or equal to the capacitance value corresponding to the higher one bit capacitor adjacent to the one of the bit capacitances. For the same reason, the same is true below.
  • F_ADD is a full adder
  • the result of the stepwise addition of the reconstruction unit REBUILDER may have an overflow problem, as shown in a of FIG. 7, indicating the transmission curve before the overflow judgment, when the reconstruction unit REBUILDER
  • the output n-bit digital code is smaller than a certain value, a smaller value should be obtained. Since there is no upward overflow, a larger value is obtained; when the output n-digit code of the reconstructed unit REBUILDER is larger than a certain value I should have gotten a large value and got a smaller value because of an overflow.
  • the transmission graph is shown after the overflow judgment. In order to eliminate the error caused by this phenomenon, it is necessary to perform the overflow judgment.
  • the schematic diagram of the overflow judgment module is shown in Fig. 8.
  • the output n-bit digital code whose judgment lower limit is REBUILDER, some bits are all 0, and the upper limit of the output is the number of the n-digit digital code of REBUILDER, and some bits are all 1
  • the output n-bit digital code of REBUILDER is less than or equal to the lower limit, the voltage at the A input terminal of the MUX unit must be high, and the voltage at the B input terminal must be low. At this time, the output of the MUX unit is n low-level digital.
  • the output n-bit digital code of REBUILDER When the output n-bit digital code of REBUILDER is greater than or equal to the upper limit, the voltage at the A input terminal of the MUX unit must be low, and the voltage at the B input terminal must be high. At this time, the output of the MUX unit is n high. Digital code; when the output n-digit code of REBUILDER is between the upper limit and the lower limit, the voltage at the A input terminal and the voltage at the B input terminal are simultaneously low, and the MUX unit output is an n-bit input digital code, which is achieved. With the function of overflow judgment, the voltages at the A and B input terminals cannot be high at the same time. It should be understood that the foregoing is merely an example of an implementation of an overflow judging module.
  • the corresponding overflow judgment module also needs to be adjusted accordingly, but the principle is the same as that of the above embodiment.
  • other sequential judgment modules it is also possible to implement high-level judgment and status judgment.
  • the overflow judgment module having the functions in the above embodiments is OK, the specific structure may be more than the above one.
  • Kj K ⁇ K(j-1) + K(j-2) + ... + K1 + K0 (1 ⁇ j ⁇ n-1)
  • the input voltage range is ⁇ (VDD - VSS).
  • the present invention provides a non-binary capacitor array 10 with redundant bits for sampling an analog signal
  • the non-binary capacitor array includes at least a common mode voltage terminal, an analog signal input terminal, and at least one redundant bit capacitance and a plurality of capacitors, wherein each of the at least one redundant bit capacitance and the plurality of capacitors are disposed in parallel at the common mode voltage terminal and the analog signal
  • each of the at least one redundant bit capacitance and the plurality of capacitors are disposed in parallel at the common mode voltage terminal and the analog signal
  • the lowest bit capacitance is any The sum of the capacitances corresponding to the bit capacitances must be greater than or equal to the capacitance value corresponding to the higher one bit capacitor adjacent to the one of the bit capacitances, and set each of the at least one redundant bit capacitance and the plurality of capacitances
  • each of the redundant bit capacitors is greater than or equal to a minimum capacitance value of the other plurality of capacitors, and is less than or equal to a maximum capacitance value of the other plurality of capacitors. Additionally, the number of the at least one redundant bit capacitance is less than the number of the plurality of capacitances.
  • the at least one redundant capacitor is respectively connected to the common mode voltage terminal when performing analog signal sampling, and each of the plurality of capacitors is subjected to analog signal sampling. Correspondingly connected to the common mode voltage terminal and the analog signal input end respectively.
  • a non-binary capacitor array with redundant bits is also provided.
  • K(n-1) is a natural number, and satisfies Kj ⁇ K(j-1) + K(j-2) + ... + K1 + K0 (1 ⁇ j ⁇ n-1)
  • the working principle of the second embodiment is that when the capacitor array CDAC is sampling, the switch S1 is turned on, and the upper plate of the capacitor array is connected to the common mode voltage VCM.
  • the switch SW is turned on, the lower plate of the capacitor array is connected to the input signal INP/INN, and the redundant bit capacitor KrC is also sampled at this time.
  • the switch S1 is turned off, and after the switch SW is turned off, the successive approach switch SW_ARRAY is connected.
  • Mode voltage VCM for the first comparison.
  • the switch corresponding to the capacitor K(n-1)C is switched to the switch corresponding to the capacitor K1C, and the successive approximation process is finally completed.
  • the switch corresponding to the capacitor K0C is always connected to the common mode.
  • Voltage VCM The principle of reconstruction and the principle of overflow judgment are the same as those of the first embodiment. It should be noted that in the working mode of the implementation example 2, the input voltage range is:
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • the working principle of the embodiment is: when the capacitor array CDAC is sampling, the switch SW is turned on, and the upper plate of the capacitor array is connected with the input signal INP/INN, and the redundant bit capacitor KrC. At this time, sampling is also performed.
  • the lower plate of the capacitor array is connected to the common mode voltage VCM by the successive approximation switch SW_ARRAY.
  • the successive approach switch SW_ARRAY is kept connected to the common mode voltage VCM for the first comparison.
  • the switch corresponding to the capacitor K(n-1)C is switched to the switch corresponding to the capacitor K1C, and the successive approximation process is finally completed.
  • the switch corresponding to the capacitor K0C is always connected.
  • Mode voltage VCM Mode voltage
  • non-binary capacitor array 10 with redundant bits of the present invention more than one redundant bit capacitance can be set.
  • the working principle, reconstruction principle and overflow judgment principle introduced in the present invention are also applicable to The case of multiple bits of redundancy.
  • each of the at least one redundant capacitor and the plurality of capacitors are sequentially subjected to analog signal sampling. Correspondingly connected to the common mode voltage terminal and the analog signal input terminal.
  • the above embodiments 1 to 3 can be applied to a successive approximation analog-to-digital converter to obtain a non-binary successive approximation analog-to-digital converter with redundant bits, see FIG.
  • the non-binary successive approximation analog-to-digital converter with redundant bits includes at least: for analog signals A non-binary capacitor array 10 with redundant bits and a successive comparison switch as described in the above schemes 1 and 2, which are sampled and obtained corresponding sampling signals, and a comparator 20, the input terminal is connected to the non-binary capacitor The output terminal is connected to the common mode voltage terminal through the successive approximation switch 30, and the comparator 20 is configured to perform successive approximation comparison on the sampling signal output by the non-binary capacitor array, and output a binary digital signal.
  • a reconstruction module 40 the input end is connected to the output end of the comparator 20, for adding and reconstructing the digital signal and outputting a binary digital conversion signal;
  • the overflow determination module 50 the input end is connected to the weight
  • the output end of the configuration module 40 is configured to perform a high bit overflow determination and a low bit overflow judgment on the digital conversion signal output by the reconstruction module 40, and then correct the output.
  • non-binary capacitor array with redundant bits in the above embodiments 1 to 3 may be applied to an analog-to-digital converter to form an analog-to-digital converter chip having the non-binary capacitor array with redundant bits.
  • the non-binary successive approximation analog-to-digital converter with redundant bits can also be made into a corresponding integrated chip.
  • the capacitance value of the capacitor corresponding to each digit code can be flexibly designed according to the actual situation, and the optimal combination of speed, power consumption and area can be realized.
  • the capacitance of each set of capacitors can be flexibly designed, thereby reducing the difficulty of the back-end layout design, and the flexible shape can be flexibly placed according to the specific layout requirements of the layout and the specific shape of the capacitor provided by the process. capacitance.
  • the ratio of the capacitance value to the unit capacitance of each group of capacitors is a positive integer, instead of the power of 2 in the conventional structure, the selection of the capacitance value can be Very flexible, which also greatly enhances the flexibility of the back-end layout design, allowing designers to consider the layout of the layout, without sticking to the traditional binary capacitor array layout, but according to the area requirements, the shape of the layout and other specific factors. Flexible design of the capacitance value of the capacitor array.
  • the existence of the overflow judgment module can effectively avoid the non-monotonic problem caused by the overflow of the upper limit and the lower limit, and improve the reliability of the design.
  • the proposal of the reconstruction algorithm reveals the general law of the working principle of the successive approximation analog-to-digital converter, and deeply understands the working principle of such an analog-to-digital converter and further studies such an analog-to-digital converter correction algorithm. , all have a lot of help.

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Abstract

一种具有带冗余位的非二进制电容阵列的模数转换器及芯片，其中，带冗余位的非二进制电容阵列包括共模电压端、模拟信号输入端、至少一冗余位电容和多个电容，将每个电容并联设置于共模电压端和模拟信号输入端之间，并以最高位到最低位/最低位到最高位的顺序对设置于共模电压端和模拟信号输入端之间的所有电容进行依次标记，且最低位电容至任一位电容所对应的容值总和必须大于等于与所述任一位电容相邻的高一位电容所对应的电容容值，并设定每个电容的容值与单位电容的容值之比为正整数。另外，还将该电容阵列应用到模数转换器中或制成相应的芯片，这使得在后期芯片电路版图设计时可采用更加灵活的布局方式，降低了设计难度。

Description

具有带冗余位的非二进制电容阵列的模数转换器及芯片 技术领域
本发明涉及模拟或数模混合集成电路技术领域，特别是涉及一种带冗余位的非二进制电容阵列、以及利用带冗余位的非二进制电容阵列来实现的模数转换器和集成芯片。
背景技术
近年来，随着CMOS集成电路工艺水平的不断提高，对逐次逼近型模数转换器的研究也随之深入。但对于传统结构逐次逼近型模数转换器电容阵列中电容的设计，通常还是采用二进制递增的方式，这种设计方式的优点是重构比较简单，比较器的输出结果即为模数转换器的最终结果。
在实际应用中，往往会将模数转换器封装制成集成芯片，而在集成芯片的生产过程中，需要对整个电路的版图进行设计。由于现有的逐次逼近型模数转换器电容阵列采用的是二进制递增的方式，也即是以2的幂次方递增的方式进行严格的有序电容排布设计，这种设计方案的不足之处在于，在后期的芯片版图设计过程中，鉴于电容阵列的设计相对固定，整个电路的工作速度和版图面积不能进行灵活的折中设计，也不能根据实际情况，在版图设计中进行灵活的变化，从而不能适应对逐次逼近型模数转换器高速低功耗的要求。
所以，如何对现有模数转换器中的电容阵列进行改进以使其适应高精度和低功耗的工艺要求就成了本领域技术人员所亟待解决的问题。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种具有带冗余位的非二进制电容阵列的模数转换器及芯片，用于解决现有逐次逼近型模数转换器技术中电容阵列的设计相对固定，在实际的芯片版图设计时，整个电路的工作速度和版图面积不能进行灵活的折中设计，也不能根据实际情况，在版图设计中进行灵活的变化，不能适应对逐次逼近型模数转换器高速低功耗的要求的问题。
为实现上述目的及其他相关目的，本发明提供以下技术方案：
方案一
一种带冗余位的非二进制电容阵列，用于对模拟信号进行采样，其中，所述非二进制电容阵列至少包括一共模电压端、模拟信号输入端、及至少一个冗余位电容和多个电容，所述至少一个冗余位电容和多个电容中的每个电容均并联设置于共模电压端和模拟信号输入端之间，并以最高位到最低位/最低位到最高位的顺序对设置于所述共模电压端和模拟信号输入端之间的所有电容进行依次标记，且最低位电容至任一位电容所对应的容值总和必须大于等于与所述任一位电容相邻的高一位电容所对应的电容容值，并设定所述至少一个冗余位电容和多个电容中的每个电容的容值与单位电容的容值之比为正整数。
作为上述带冗余位的非二进制电容阵列的优选方案，每个所述冗余位电容的容值大于等于其他所述多个电容中的最小电容值，且小于等于其他所述多个电容中的最大电容值。
作为上述带冗余位的非二进制电容阵列的优选方案，所述至少一个冗余位电容的个数小于所述多个电容的个数。
作为上述带冗余位的非二进制电容阵列及其优选方案的进一步优化，所述至少一个冗余电容在进行模拟信号采样时两端分别连接所述共模电压端，且所述多个电容中的每个电容在进行模拟信号采样时两端分别对应连接于所述共模电压端和模拟信号输入端。
作为上述带冗余位的非二进制电容阵列及其优选方案的进一步优化，所述至少一个冗余电容和多个电容中的每个电容在进行模拟信号采样时两端依次对应连接于所-述共模电压端和模拟信号输入端。
方案二
本发明还将上述方案一中的技术方案应用到模数转换器中，从而得到一种带冗余位的非二进制逐次逼近型模数转换器，至少包括：逐次逼近开关；如方案一及其优选方案中任一带冗余位的非二进制电容阵列，用于对模拟信号进行采样并得到对应的采样信号；比较器，输入端连接所述非二进制电容阵列，输出端通过所述逐次逼近开关连接所述共模电压端，所述比较器用于对所述非二进制电容阵列所输出的采样信号进行逐次逼近比较，并予以输出二进制的数字信号；重构模块，输入端连接所述比较器的输出端，用于对所述数字信号进行加法重构并予以输出二进制的数字转换信号；溢出判断模块，输入端连接于所述重构模块的输出端，用于对所述重构模块所输出的的数字转换信号进行高位溢出判断和低位溢出判断后予以修正输出。
作为上述方案二的优选方案，所述重构模块具体为全加器。
方案三
本发明还可以将上述方案一和方案二的技术方案应用到集成芯片中，即将所述带冗余位的非二进制电容阵列应用到模数转换芯片中，或者将所述带冗余位的非二进制逐次逼近型模数转换器制成集成芯片。
综合上述技术方案来看，本发明相对于现有技术具有以下有益效果：
1、本发明中，可以在CDAC电容的设计中，根据实际情况，灵活的设计每一位数字码所对应的电容的容值，实现速度、功耗和面积的最优组合。
2、本发明中，每一组电容的容值都可以灵活设计，因此减小了后端版图设计的难度，可以根据版图的具体布局需要，结合工艺所提供电容的具体形状，灵活的放置各个电容。
3、本发明中，溢出判断模块的存在，可以有效的避免上限和下限两种溢出所带来的非单调问题，提高了设计的可靠性。
4、本发明中，重构算法的提出，揭示了逐次逼近型模数转换器工作原理的普遍规律，对于深入理解此类模数转换器的工作原理和进一步研究此类模数转换器校正算法，都有很大帮助。
附图说明
图1为逐次逼近型模数转换器原理图；
图2为无冗余位二进制逐次逼近型模数转换器CDAC原理图；
图3为带冗余位二进制逐次逼近型模数转换器CDAC原理图；
图4为带冗余位二进制逐次逼近型模数转换器重构算法示意图；
图5为带冗余位非二进制逐次逼近型模数转换器重构算法示意图；
图6为重构单元REBUILDER原理图；
图7为溢出判断前后的传输曲线对比图；
图8为溢出判断模块OVERFLOW DETECT原理图；
图9为一种带冗余位的非二进制电容阵列CDAC在实例二中的原理图；
图10为一种带冗余位的非二进制电容阵列CDAC在实例三中的原理图；
图11为一种带冗余位非二进制逐次逼近型模数转换器的原理图。
附图标号说明
10 带冗余位的非二进制电容阵列
20 比较器
30 逐次逼近开关
40 重构模块
50 溢出判断模块
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。
需要说明的是，以下实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
实施例一
参见图1，示出了一种无冗余位逐次逼近型模数转换器中电容阵列CDAC的原理图，如图所示，根据逐次逼近型模数转换器的一般原理知识可知，对于一个n位逐次逼近型模数转换器而言，K0＝K1＝1，K2＝21，K3＝22，…，K(n-2)＝2n-3，K(n-1)＝2n-2，其中C表示单位电容容值。另外，图1中的工作原理为，当电容阵列CDAC进行采样时，开关S1导通，电容阵列上极板接共模电压VCM，同时，开关SW导通，电容阵列下极板接输入信号INP/INN，采样结束后，开关S1断开，开关SW断开后，逐次逼近开关SW_ARRAY接共模电压VCM，进行第一次比较，此后，根据每次的比较结果，电容K(n-1)C对应的开关到电容K1C对应的开关进行依次切换，最终完成逐次逼近过程，此过程中电容K0C所对应的开关始终接共模电压VCM。
现在，对逐次逼近过程在数字域进行重构，为了方便理解，最终的二进制输出结果这里用十进制数进行对应表示，故：
DOUT＝2n-1+2n-2S(n-1)+2n-3S(n-2)+…+22S3+21S2+S1+0.5S0    (1)
式(1)中Si(i＝0，1，2，…，n-2，n-1)根据每次的比较结果取-1或者1，为 了和逐次逼近过程中比较器每次的输出相对应，令：
Si＝2Di-1    (2)
式(2)中Di(i＝0，1，2，…，n-2，n-1)根据每次的比较结果取0或者1，将式(2)带入式(1)并化简得：
DOUT＝2n-1D(n-1)+2n-2S(n-2)+…+22D2+21D1+D0+0.5    (3)
由于这里采用的是十进制表示，故式(3)可进一步化简为：
DOUT＝2n-1D(n-1)+2n-2S(n-2)+…+22D2+21D1+D0    (4)
式(4)中的Di(i＝0，1，2，…，n-2，n-1)即是n位模数转换器的最终输出数字码。
另外，见图2，示出了现有的一种无冗余位逐次逼近型模数转换器结构原理示意图，需要注意的是，如图1所示，无冗余位逐次逼近型模数转换器结构下，比较器的输出即是模数转换器的最终输出，这也是我们最常见的形式。
进一步地，见图3，示出了一种带冗余位的二进制逐次逼近型模数转换器电容阵列CDAC的原理图，其中，该电容阵列CDAC由n+1个电容构成，包括n个非冗余位电容和1个冗余位电容，所述冗余位电容为KrC，且K0＝K1＝1，K2＝21，K3＝22，…，Kr＝2r，…，K(n-2)＝2n-3，K(n-1)＝2n-2(1<r<n-1)。如图3所示，并参考逐次逼近型模数转换器的一般工作原理原理可知，当电容阵列CDAC进行采样时，开关S1导通，电容阵列上极板接共模电压VCM，同时，开关SW导通，电容阵列下极板接输入信号INP/INN，冗余位电容KrC此时接共模电压VCM，采样结束后，开关S1断开，开关SW断开后，逐次逼近开关SW_ARRAY接共模电压VCM，进行第一次比较，此后，根据每次的比较结果，电容K(n-1)C对应的开关到电容K1C对应的开关，进行依次切换，最终完成逐次逼近过程，此过程中电容K0C所对应的开关始终接共模电压VCM。
同样，对逐次逼近过程在数字域进行重构，为了方便理解，最终的二进制输出结果这里用十进制数进行对应表示，故：
DOUT＝2n-1+2n-2S(n-1)+2n-3S(n-2)+…+2rSr+…+22S3+21S2+S1+0.5S0    (5)
式(5)中Si(i＝0，1，2，…，r，…，n-2，n-1)根据每次的比较结果取-1或者1，将式(2)带入式(5)并化简得：
DOUT＝2n-1D(n-1)+2n-2S(n-2)+…+22D2+21D1+D0+2r+1Dr-2r    (6)
由于1<r<n-1，电容阵列CDAC为二进制电容阵列，所以可设：KrC＝KtC，其中 KtC为非冗余位电容中的一个电容，那么式(6)的重构算法如图4所示。
基于上述分析，可以设定K0＝K1＝1，K2，K3，…，Kr，…，K(n-2)，K(n-1)为自然数(一般实际应用中采用的正整数，这里是为了便于理解故采用自然数来进行说明，下文亦是这样)，且满足Kj≤K(j-1)+K(j-2)+…+K1+K0(1<j≤n-1)，就意味着可以以自然数的方式设置电容阵列CDAC中K0C，K1C，K2C，K3C，…，KrC，…，K(n-2)C，K(n-1)C等电容的容值，而不以传统的二进制的方式。这样，电容阵列CDAC的实现就很灵活，可以根据不同的需求，设计不同容值组合下的电容阵列，下面介绍这种自然数电容阵列的重构算法。
特别地，这里需要进行说明的是，上述Kj≤K(j-1)+K(j-2)+…+K1+K0(1<j≤n-1)中，下标j表示最高位电容到最低位电容或者最低位电容到最高位电容的顺序。举例来说，假设在电容阵列中有10个电容(当然里面包含冗余位电容)，现对该10个电容分别按“最高位电容、次高位电容、第三高位电容、…第九高位电容、最低位电容”的顺序进行依次标记；或者按照“最低位电容、次低位电容、第三低位电容、…第九低位电容、最高位电容”的顺序进行依次标记。其中，在这10个电容中，还必须满足：如果从“最高位电容、次高位电容、第三位电容、…第九位电容、最低位电容”的顺序中任选一位电容，比如选次高位电容，那么该次高位电容的容值必须小于等于最低位电容至第三高位电容所对应电容的总和(同样，如果是从“最低位电容、次低位电容、第三低位电容、…第九低位电容、最高位电容”顺序中任选一位电容，比如选第四低位电容，那么第四低位电容的容值必须小于等于最低位电容至第三低位电容所对应电容的总和)。简单来说，也即是必须满足最低位电容至任一位电容所对应的容值总和必须大于等于与所述任一位电容相邻的高一位电容所对应的电容容值。同理，下文亦是如此。
具体地，由上述分析同理可得：
DOUT＝2n-1+K(n-1)S(n-1)+K(n-2)S(n-2)+…+KrSr+…+K3S3+K2S2+K1S1+0.5S0(7)
式(7)中Si(i＝0，1，2，…，r，…，n-2，n-1)根据每次的比较结果取-1或者1，将式(2)带入式(7)化简得：
DOUT＝2K(n-1)D(n-1)+2K(n-2)D(n-2)+…2KrDr+…+2K3D3+2K2D2+2K1D1+D0+2n-1-K(n-1)-K(n-2)-…-Kr-…-K3-K2-K1-1(8)
式(8)的重构方式如图5所示，由式(8)可知，Di(i＝0，1，2，…，r，…，n-2，n-1)的系数2Ki(i＝0，1，2，…，r，…，n-2，n-1)可由2的幂求和表示，只要电容阵列CDAC中每个电容的容值确定，2Ki(i＝0，1，2，…，r，…，n-2，n-1)的表示形式就可以确定，也就是说，图5中除Di(i＝0，1，2，…，r，…，n-2，n-1)之外的所有系数都可以确定。在此基础上，我们进行重构单元REBUILDER的设计。
重构单元REBUILDER的原理图如图6所示，F_ADD为全加器，规定MUXi(i＝0，1，2，…，r，…，n-2，n-1)单元的工作方式为：当Di(i＝0，1，2，…，r，…，n-2，n-1)为0时，输出全0，当Di(i＝0，1，2，…，r，…，n-2，n-1)为1时，输出前文已经确定好的系数2Ki(i＝0，1，2，…，r，…，n-2，n-1)，这样随着逐次比较的进行，将每次的比较结果逐级进行相加，舍去溢出位后，最终得到n位数字码。
进一步地，由于电路存在一定偏差，经过重构单元REBUILDER逐级相加之后的结果可能存在溢出的问题，如图7中a所示，表示溢出判断前的传输曲线图，当重构单元REBUILDER的输出n位数字码小于某个值时，本来应该得到一个较小的值，由于没有向上溢出，却得到了一个较大的值；当重构单元REBUILDER的输出n位数字码大于某个值时，本来应该得到一个较大的值，由于发生了向上溢出，却得到了一个较小的值。如图7中b所示，表示表示溢出判断后的传输曲线图，为了消除这种现象带来的错误，需要进行溢出判断，因此对重构单元REBUILDER的输出n位数字码，需要设置一个判断上限和判断下限，当n位数字码小于判断下限时，DOUT输出为全0，当n位数字码大于判断上限时，DOUT输出为全1，当n位数字码介于判断下限和判断上限之间时，将REBUILDER的输出n位数字码作为DOUT直接输出。
溢出判断模块原理图如图8所示，设判断下限为REBUILDER的输出n位数字码中，某几位全为0，设判断上限为REBUILDER的输出n位数字码中，某几位全为1，当REBUILDER的输出n位数字码小于等于下限时，MUX单元的A输入端电压必为高电平，而B输入端电压必为低电平，此时MUX单元输出为n位低电平数字码；当REBUILDER的输出n位数字码大于等于上限时，MUX单元的A输入端电压必为低电平，而B输入端电压必为高电平，此时MUX单元输出为n位高电平数字码；当REBUILDER的输出n位数字码介于上限和下限之间时，A输入端电压和B输入端电压同时为低电平，此时MUX单元输出为n位输入数字码，这就实现了溢出判断的功能，A和B输入端电压不能同时为高电平。应当理解，上述只是给出一种溢出判断模块的实施方式示例，在实际应用中，如果采用不同数值的电容阵列结构，那么其所 对应的溢出判断模块也需要做相应调节，但是其原理与上述实施例一样，另外，如果采用其他的依次判断模块，只要能够实现高位判断和地位判断也是可以的。简单来说，只要具备上述实施例中的功能的溢出判断模块都行，其具体的结构可能不止上述一种。
需要理解的是，对于实施例一，其工作原理可以参见图3，且图3中的K0＝K1＝1，K2，K3，…，Kr，…，K(n-2)，K(n-1)均为自然数，并满足Kj≤K(j-1)+K(j-2)+…+K1+K0(1<j≤n-1)，输入电压范围为±(VDD-VSS)。
综合上述分析，并参看图3，可以概括地来讲，本发明提供了一种带冗余位的非二进制电容阵列10，用于对模拟信号进行采样，其中，所述非二进制电容阵列至少包括一共模电压端、模拟信号输入端、及至少一个冗余位电容和多个电容，所述至少一个冗余位电容和多个电容中的每个电容均并联设置于共模电压端和模拟信号输入端之间，并以最高位到最低位/最低位到最高位的顺序对设置于所述共模电压端和模拟信号输入端之间的所有电容进行依次标记，且最低位电容至任一位电容所对应的容值总和必须大于等于与所述任一位电容相邻的高一位电容所对应的电容容值，并设定所述至少一个冗余位电容和多个电容中的每个电容的容值与单位电容的容值之比为正整数。
其中，应当理解，所述每个所述冗余位电容的容值大于等于其他所述多个电容中的最小电容值，且小于等于其他所述多个电容中的最大电容值。另外，所述至少一个冗余位电容的个数小于所述多个电容的个数。
进一步地，还应当理解，所述至少一个冗余电容在进行模拟信号采样时两端分别连接所述共模电压端，且所述多个电容中的每个电容在进行模拟信号采样时两端分别对应连接于所述共模电压端和模拟信号输入端。
实施例二
本实施例中还提供了一种带冗余位的非二进制电容阵列，参见图9，如图所示，其中，K0＝K1＝1，K2，K3，…，Kr，…，K(n-2)，K(n-1)均为自然数，且满足Kj≤K(j-1)+K(j-2)+…+K1+K0(1<j≤n-1)，与实施例一的带冗余位的非二进制电容阵列10所不同的是，本实施例二的工作原理是：当电容阵列CDAC进行采样时，开关S1导通，电容阵列上极板接共模电压VCM，同时，开关SW导通，电容阵列下极板接输入信号INP/INN，冗余位电容KrC此时也进行采样，采样结束后，开关S1断开，开关SW断开后，逐次逼近开关SW_ARRAY接共模电压VCM，进行第一次比较， 此后，根据每次的比较结果，电容K(n-1)C对应的开关到电容K1C对应的开关，进行依次切换，最终完成逐次逼近过程，此过程中电容K0C所对应的开关始终接共模电压VCM。其重构原理和溢出判断原理和实施实例一是相同的。需要注意的一点是，在实施实例二的工作模式下，其输入电压范围为：
±(VDD-VSS)(K0+K1+K2+K3+…+K(n-2)+K(n-1))/(K0+K1+K2+K3+…+Kr+…+K(n-2)+K(n-1))    (9)
实施例三：
进一步地，本发明还供了另外一种带冗余位的非二进制电容阵列原理图，请参见图10，如图所示，其中，K0＝K1＝1，K2，K3，…，Kr，…，K(n-2)，K(n-1)均为自然数，并满足Kj≤K(j-1)+K(j-2)+…+K1+K0(1<j≤n-1)。本实施例与实施例一所不同的是，本实施例的工作原理是：当电容阵列CDAC进行采样时，开关SW导通，电容阵列上极板接输入信号INP/INN，冗余位电容KrC此时也进行采样，同时，电容阵列下极板通过逐次逼近开关SW_ARRAY接共模电压VCM，采样结束后，开关SW断开后，逐次逼近开关SW_ARRAY保持接共模电压VCM，进行第一次比较，此后，根据每次的比较结果，电容K(n-1)C对应的开关到电容K1C对应的开关，进行依次切换，最终完成逐次逼近过程，此过程中电容K0C所对应的开关始终接共模电压VCM。其重构原理和溢出判断原理和实施实例一是相同的。需要注意的一点是，在实施实例三的工作模式下，其输入电压范围为：
±(VDD-VSS)(K0+K1+K2+K3+…+K(n-2)+K(n-1))/(K0+K1+K2+K3+…+Kr+…+K(n-2)+K(n-1))    (10)
另外，需要特别说明的是，本发明带冗余位的非二进制电容阵列10中，冗余位电容可以设置不止一位，本发明书介绍的工作原理、重构原理和溢出判断原理同样适用于多位冗余位的情况。
进一步地讲，与实施例一中所不同的是，在上述实施例二和实施例三中，所述至少一个冗余电容和多个电容中的每个电容在进行模拟信号采样时两端依次对应连接于所述共模电压端和模拟信号输入端。
实施例四
进一步地，还可以将上述实施例一至实施例三的方案应用到到逐次逼近型模数转换器中，以得到一种带冗余位的非二进制逐次逼近型模数转换器，请参见图11，如图所示，所述带冗余位的非二进制逐次逼近型模数转换器至少包括：用于对模拟信号 进行采样并得到对应的采样信号的如上述方案一和方案二中所述的带冗余位的非二进制电容阵列10和逐次比较开关，以及还包括比较器20，输入端连接所述非二进制电容阵列，输出端通过所述逐次逼近开关30连接所述共模电压端，所述比较器20用于对所述非二进制电容阵列所输出的采样信号进行逐次逼近比较，并予以输出二进制的数字信号；重构模块40，输入端连接所述比较器20的输出端，用于对所述数字信号进行加法重构并予以输出二进制的数字转换信号；溢出判断模块50，输入端连接于所述重构模块40的输出端，用于对所述重构模块40所输出的的数字转换信号进行高位溢出判断和低位溢出判断后予以修正输出。
进一步地，还可以将上述实施例一至实施例三中的带冗余位的非二进制电容阵列应用模数转换器中，制作成具有带冗余位的该非二进制电容阵列的模数转换器芯片，同时，也可以将所述带冗余位的非二进制逐次逼近型模数转换器制成相应的集成芯片。
综上来说，本发明的有益效果在于：
1、本发明中，可以在CDAC电容的设计中，根据实际情况，灵活的设计每一位数字码所对应的电容的容值，实现速度、功耗和面积的最优组合。
2、本发明中，每一组电容的容值都可以灵活设计，因此减小了后端版图设计的难度，可以根据版图的具体布局需要，结合工艺所提供电容的具体形状，灵活的放置各个电容。
3、本发明中，由于采用了灵活的重构算法，每一组电容的容值和单位电容之比为正整数即可，而不是传统结构中的2的幂，所以电容容值的选择可以非常灵活，由此也大大提高了后端版图设计的灵活性，使得设计人员在考虑版图设计时，不用拘泥于传统的二进制电容阵列进行布局，而可以根据面积的要求、版图的形状等具体因素，对电容阵列中电容容值的大小，进行灵活的设计。
4、本发明中，溢出判断模块的存在，可以有效的避免上限和下限两种溢出所带来的非单调问题，提高了设计的可靠性。
5、本发明中，重构算法的提出，揭示了逐次逼近型模数转换器工作原理的普遍规律，对于深入理解此类模数转换器的工作原理和进一步研究此类模数转换器校正算法，都有很大帮助。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改 变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (9)

  1. 一种带冗余位的非二进制电容阵列，用于对模拟信号进行采样，其特征在于：所述非二进制电容阵列至少包括一共模电压端、模拟信号输入端、及至少一个冗余位电容和多个电容，所述至少一个冗余位电容和多个电容中的每个电容均并联设置于共模电压端和模拟信号输入端之间，并以最高位到最低位/最低位到最高位的顺序对设置于所述共模电压端和模拟信号输入端之间的所有电容进行依次标记，且最低位电容至任一位电容所对应的容值总和必须大于等于与所述任一位电容相邻的高一位电容所对应的电容容值，并设定所述至少一个冗余位电容和多个电容中的每个电容的容值与单位电容的容值之比为正整数。
  2. 根据权利要求1所述的带冗余位的非二进制电容阵列，其特征在于，每个所述冗余位电容的容值大于等于其他所述多个电容中的最小电容值，且小于等于其他所述多个电容中的最大电容值。
  3. 根据权利要求1所述的带冗余位的非二进制电容阵列，其特征在于，所述至少一个冗余位电容的个数小于所述多个电容的个数。
  4. 根据权利要求1-3任一项所述的带冗余位的非二进制电容阵列，其特征在于，所述至少一个冗余电容在进行模拟信号采样时两端分别连接所述共模电压端，且所述多个电容中的每个电容在进行模拟信号采样时两端分别对应连接于所述共模电压端和模拟信号输入端。
  5. 根据权利要求1-3任一项所述的带冗余位的非二进制电容阵列，其特征在于，所述至少一个冗余电容和多个电容中的每个电容在进行模拟信号采样时两端依次对应连接于所述共模电压端和模拟信号输入端。
  6. 一种带冗余位的非二进制逐次逼近型模数转换器，其特征在于，包括：
    逐次逼近开关；
    权利要求1-5任一项的所述带冗余位的非二进制电容阵列，用于对模拟信号进行采样并得到对应的采样信号；
    比较器，输入端连接所述非二进制电容阵列，输出端通过所述逐次逼近开关连接所述共模电压端，所述比较器用于对所述非二进制电容阵列所输出的采样信号进行逐次逼近比较，并予以输出二进制的数字信号；
    重构模块，输入端连接所述比较器的输出端，用于对所述数字信号进行加法重构并予以输出二进制的数字转换信号；
    溢出判断模块，输入端连接于所述重构模块的输出端，用于对所述重构模块所输出的的数字转换信号进行高位溢出判断和低位溢出判断后予以修正输出。
  7. 根据权利要求6所述的带冗余位的非二进制逐次逼近型模数转换器，其特征在于，所述重构模块为全加器。
  8. 一种模数转换芯片，其特征在于，具有权利要求1-5中任一项所述的带冗余位的非二进制电容阵列。
  9. 一种模数转换芯片，其特征在于，具有权利要求6或7中所述的带冗余位的非二进制逐次逼近型模数转换器的电路结构。
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