WO2016115797A1 - 触控电路、触控面板及显示装置 - Google Patents

触控电路、触控面板及显示装置 Download PDF

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Publication number
WO2016115797A1
WO2016115797A1 PCT/CN2015/079501 CN2015079501W WO2016115797A1 WO 2016115797 A1 WO2016115797 A1 WO 2016115797A1 CN 2015079501 W CN2015079501 W CN 2015079501W WO 2016115797 A1 WO2016115797 A1 WO 2016115797A1
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WIPO (PCT)
Prior art keywords
node
signal
control
touch
pull
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/079501
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English (en)
French (fr)
Inventor
黄飞
乔赟
樊君
李付强
孙建
李成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Application filed by BOE Technology Group Co Ltd, Ordos Yuansheng Optoelectronics Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US14/902,422 priority Critical patent/US9703416B2/en
Publication of WO2016115797A1 publication Critical patent/WO2016115797A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3262—Power saving in digitizer or tablet

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a touch circuit, a touch panel, and a display device.
  • the human-computer interaction mode has evolved from the original mechanical button mode to the touch-aware mode. Therefore, the touch circuit in the display device plays a vital role.
  • a known touch panel adopts a touch circuit as shown in FIG. 1 to implement a touch scan function, and the circuit structure includes a plurality of gates such as a transfer gate A, a non-gate B, a tri-state gate C, and a switching transistor.
  • T while the transmission gate A and the NAND gate B circuit both require two thin film transistors to achieve their corresponding functions, and the three-state gate C circuit requires four thin film transistors to perform their functions. Therefore, the touch circuit as a whole needs at least 32 The thin film transistor is realized, the structure is relatively complicated, and the number of thin film transistors required is large, so that the power consumption thereof is large.
  • the embodiments of the present disclosure provide a touch control circuit, a touch panel, and a display device, which can solve the problem that the known touch circuit structure is complicated and the power consumption is large.
  • the embodiment of the present disclosure provides a touch control circuit, including: an input module, a reset module, a pull-up module, a pull-down module, and a touch signal output control module, where:
  • the control end of the input module is connected to the signal input end, the input end is connected to the high level signal end, the output end is connected to the first node, and the input module is used to control the signal input end to pull down the first The potential of the node;
  • the control end of the reset module is connected to the reset signal end, the input end is connected to the first node, the output end is connected to the low level signal end, and the reset module is configured to pull down the control at the reset signal end.
  • the control end of the pull-up module is connected to the first node, and the input end and the first clock signal end Connected, the output end is connected to the control signal output end, and the pull-up module is configured to raise the potential of the output end of the control signal under the control of the first node and the first clock signal end;
  • the pull-down module is connected to the high-level signal end, the low-level signal end, the second clock signal end, the third clock signal end, the control signal output end, and the first node.
  • the pull-down module is configured to pull down the potentials of the first node and the control signal output end under the control of the second clock signal end and the third clock signal end;
  • the touch signal output control module is connected to the high level signal end, the low level signal end, the control signal output end, the low frequency signal end, the high frequency signal end, the common voltage signal end, and the cutoff signal end. And the touch signal output control module is configured to control the touch signal output end to select an output high frequency signal or a common voltage signal under the control of the control signal output end.
  • the pull-down module specifically includes: a first pull-down unit, a second pull-down unit, a first pull-down control unit, and a second pull-down control unit;
  • the first pull-down control unit is connected to the second clock signal end, the third clock signal end, the high level signal end, the low level signal end, the first node, and the second Between the nodes, the first pull-down control unit is configured to raise the potential of the second node under the control of the second clock signal end and the third clock signal end;
  • a control end of the second pull-down control unit is connected to the first node, an input end is connected to the second node, an output end is connected to the low-level signal end, and the second pull-down control unit is used to When the potential of the first node is pulled high, the potential of the second node is pulled down;
  • the control end of the first pull-down unit is connected to the second node, the input end is connected to the control signal output end, the output end is connected to the low-level signal end, and the first pull-down unit is used for When the potential of the second node is pulled high, the potential of the output end of the control signal is pulled down;
  • a control end of the second pull-down unit is connected to the second node, an input end is connected to the first node, an output end is connected to the low-level signal end, and the second pull-down unit is used in the When the potential of the second node is pulled high, the potential of the first node is pulled low.
  • the first pull-down unit specifically includes: a first switching transistor and a first capacitor;
  • a gate of the first switching transistor is connected to the second node, a source is connected to the output end of the control signal, and a drain is connected to the low-level signal end;
  • the first capacitor is coupled between the second node and the low level signal terminal.
  • the second pull-down unit specifically includes: a second switch transistor
  • the gate of the second switching transistor is connected to the second node, the source is connected to the first node, and the drain is connected to the low-level signal terminal.
  • the first pull-down control unit specifically includes: a third switch transistor, a fourth switch transistor, and a fifth switch transistor;
  • a gate of the third switching transistor is connected to the second clock signal end, a source is connected to the high level signal end, and a drain is respectively connected to a source of the fourth switching transistor and the fifth switch The gates of the transistors are connected;
  • a gate of the fourth switching transistor is connected to the third clock signal end, and a drain is connected to the low level signal end;
  • the source of the fifth switching transistor is connected to the high level signal end, and the drain is connected to the second node.
  • the second pull-down control unit specifically includes: a sixth switch transistor
  • the gate of the sixth switching transistor is connected to the first node, the source is connected to the second node, and the drain is connected to the low-level signal terminal.
  • the touch signal output control module specifically includes: a high frequency signal output control unit, a common voltage signal output control unit, a third node pull-up unit, and a Three-node pull-down unit;
  • the control end of the third node pull-up unit is connected to the control signal output end, the input end is connected to the low-frequency signal end, the output end is connected to the third node, and the third node pull-up unit is used for Raising the potential of the third node when the potential of the output of the control signal is pulled high;
  • the control end of the third node pull-down unit is connected to the cut-off signal end, the input end is connected to the third node, the output end is connected to the low-level signal end, and the third node pull-down unit is used for Under the control of the cutoff signal end, the potential of the third node is pulled down;
  • the control end of the high frequency signal output control unit is connected to the third node, the input end is connected to the high frequency signal end, and the output end is connected to the touch signal output end, and the high frequency signal output control unit When the potential of the third node is pulled high, controlling the output of the touch signal to output a high frequency signal;
  • the common voltage signal output control unit is connected to the third node, the low level signal end, the high level signal end, the common voltage signal end, and the touch signal output end,
  • the common voltage signal output control unit is configured to control the touch signal output end to output a common voltage signal when the potential of the third node is pulled low.
  • the third node pull-up unit specifically includes: a seventh switch transistor
  • the gate of the seventh switching transistor is connected to the output of the control signal, the source is connected to the low frequency signal end, and the drain is connected to the third node.
  • the third node pull-down unit specifically includes: an eighth switch transistor;
  • the gate of the eighth switching transistor is connected to the cut-off signal end, the source is connected to the third node, and the drain is connected to the low-level signal end.
  • the high frequency signal output control unit specifically includes: a ninth switch transistor and a second capacitor;
  • a gate of the ninth switching transistor is connected to the third node, a source is connected to the high frequency signal end, and a drain is connected to the touch signal output end;
  • the second capacitor is connected between the third node and the touch signal output end.
  • the common voltage signal output control unit specifically includes: a tenth switch transistor, an eleventh switch transistor, and a third capacitor;
  • a gate of the tenth switching transistor is connected to the third node, and a source is respectively connected to the high level signal end and a gate of the eleventh switching transistor, and the drain and the low level signal Connected to each other;
  • a source of the eleventh switching transistor is connected to the common voltage signal end, and a drain is connected to the touch signal output end;
  • the third capacitor is connected between the high level signal end and the low level signal end.
  • the common voltage signal output control unit further includes: a twelfth switching transistor
  • a gate and a source of the twelfth switching transistor are connected to the high level signal terminal, and a drain is connected to a source of the tenth switching transistor and a gate of the eleventh switching transistor, respectively.
  • the input module specifically includes: a thirteenth switching transistor
  • the gate of the thirteenth switching transistor is connected to the signal input end, the source is connected to the high level signal end, and the drain is connected to the first node.
  • the reset module specifically includes: a fourteenth switch transistor
  • the gate of the fourteenth switching transistor is connected to the reset signal terminal, the source is connected to the first node, and the drain is connected to the low-level signal terminal.
  • the pull-up module specifically includes: a fifteenth switching transistor and a fourth capacitor;
  • a gate of the fifteenth switching transistor is connected to the first node, a source is connected to the first clock signal end, and a drain is connected to the control signal output end;
  • the fourth capacitor is coupled between the first node and the control signal output.
  • An embodiment of the present disclosure provides a touch panel including a plurality of touch circuits provided by the embodiments of the present disclosure, except for the first-level touch circuit and the final touch circuit.
  • the output end of the control signal is connected to the signal input end of the adjacent touch circuit of the adjacent first stage, and is connected to the reset signal end of the adjacent touch circuit of the adjacent first stage; the control signal output end of the first touch circuit and The signal input end of the second-level touch circuit is connected; the control signal output end of the last-level touch circuit is connected to the reset signal end of the upper-level touch circuit.
  • the embodiment of the present disclosure provides a display device including the above touch panel provided by the embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a touch control circuit, a touch panel, and a display device.
  • the touch control circuit includes an input module, a reset module, a pull-up module, a pull-down module, and a touch signal output control module.
  • the control at the signal input pulls down the potential of the first node;
  • the reset module is used to pull down the potential of the first node at the control of the reset signal terminal;
  • the pull-up module is used to pull up under the control of the first node and the first clock signal end Controlling the potential of the signal output end;
  • the pull-down module is configured to pull down the potential of the first node and the control signal output terminal under the control of the second clock signal end and the third clock signal end;
  • the touch signal output control module is used at the output end of the control signal Under control, the control touch signal output terminal selects the output high frequency signal or the common voltage signal, thereby realizing the function of the touch circuit outputting the touch signal, and constructing the transmission gate and inverting relative to the
  • 1 is a schematic structural view of a known touch circuit
  • FIG. 2 is a schematic structural diagram of a touch circuit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a pull-down module in a touch circuit according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of a pull-down module in a touch circuit according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a touch signal output control module in a touch circuit according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a touch signal output control module in a touch circuit according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of a touch circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram showing the operation timing of a touch circuit according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram showing the operation timing of the cascaded touch circuits sequentially outputting touch signals according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a touch control circuit, as shown in FIG. 2, which may include: an input module 01, a reset module 02, a pull-up module 03, a pull-down module 04, and a touch signal output control module 05, wherein:
  • the control terminal of the input module 01 is connected to the signal input terminal Input, the input terminal is connected to the high level signal terminal VGH, the output terminal is connected to the first node P1, and the input module 01 is used for controlling the input of the signal input terminal Input to the first node.
  • the control terminal of the reset module 02 is connected to the reset signal terminal Reset, the input terminal is connected to the first node P1, the output terminal is connected to the low-level signal terminal VGL, and the reset module 02 is used to pull down the first node at the reset signal terminal Reset. Potential of P1;
  • the control terminal of the pull-up module 03 is connected to the first node P1, the input terminal is connected to the first clock signal terminal CLK1, the output terminal is connected to the control signal output terminal OUT, and the pull-up module 03 is used at the first node P1 and the first clock. Under the control of the signal terminal CLK1, the potential of the control signal output terminal OUT is pulled up;
  • the pull-down module 04 is connected to the high-level signal terminal VGH, the low-level signal terminal VGL, and the second clock.
  • the signal terminal CLK2, the third clock signal terminal CLK3, the control signal output terminal OUT and the first node P1, the pull-down module 04 is used to pull down the second clock signal terminal CLK2 and the third clock signal terminal CLK3 a potential of a node P1 and a control signal output terminal OUT;
  • the touch signal output control module 05 is connected to the high level signal terminal VGH, the low level signal terminal VGL, the control signal output terminal OUT, the low frequency signal terminal TL, the high frequency signal terminal TH, the common voltage signal terminal VCOM, and the cutoff signal terminal END. And between the touch signal output terminal TX, the touch signal output control module 05 is configured to control the touch signal output terminal TX to select an output high frequency signal or a common voltage signal under the control of the control signal output terminal OUT.
  • the touch control circuit provided by the embodiment of the present disclosure includes an input module 01, a reset module 02, a pull-up module 03, a pull-down module 04, and a touch signal output control module 05, wherein the input module 01 is used for inputting at a signal input end.
  • the control pulls down the potential of the first node P1; the reset module 02 is used to pull down the potential of the first node P1 at the control of the reset signal end Reset; the pull-up module 03 is used at the first node P1 and the first clock signal terminal CLK1 Under the control, the potential of the control signal output terminal OUT is pulled up; the pull-down module 04 is used to pull down the first node P1 and the control signal output terminal OUT under the control of the second clock signal terminal CLK2 and the third clock signal terminal CLK3.
  • the touch signal output control module 05 is configured to control the touch signal output terminal TX to select and output a high frequency signal or a common voltage signal under the control of the control signal output terminal OUT, thereby realizing the function of the touch circuit outputting the touch signal.
  • the touch control provided by the embodiment of the present disclosure is different from the touch circuit that is configured by using a thin film transistor to construct a transmission gate, an inverter, and a three-state gate circuit. The circuit structure is simple and the power consumption is low.
  • the pull-down module 04 may specifically include: a first pull-down unit 041, a second pull-down unit 042, and a first pull-down control unit. 043 and a second pull-down control unit 044;
  • the first pull-down control unit 043 is connected between the second clock signal terminal CLK2, the third clock signal terminal CLK3, the high-level signal terminal VGH, the low-level signal terminal VGL, the first node P1, and the second node P2.
  • a pull-down control unit 043 is configured to raise the potential of the second node P2 under the control of the second clock signal terminal CLK2 and the third clock signal terminal CLK3;
  • the control terminal of the second pull-down control unit 044 is connected to the first node P1, the input terminal is connected to the second node P2, the output terminal is connected to the low-level signal terminal VGL, and the second pull-down control unit 044 is used at the first node P1.
  • the potential is pulled high, the potential of the second node P2 is pulled down;
  • the control end of the first pull-down unit 041 is connected to the second node P2, and the input end and the control signal output The terminal OUT is connected, the output terminal is connected to the low-level signal terminal VGL, and the first pull-down unit 041 is configured to pull down the potential of the control signal output terminal OUT when the potential of the second node P2 is pulled high;
  • the control terminal of the second pull-down unit 042 is connected to the second node P2, the input terminal is connected to the first node P1, the output terminal is connected to the low-level signal terminal VGL, and the second pull-down unit 042 is used for the potential at the second node P2. When pulled high, the potential of the first node P1 is pulled low.
  • the first pull-down control unit 043 raises the potential of the second node P2 under the control of the second clock signal terminal CLK2 and the third clock signal terminal CLK3,
  • a pull-down unit 041 pulls down the potential of the control signal output terminal OUT when the potential of the second node P2 is pulled high;
  • the second pull-down unit 042 pulls down the first when the potential of the second node P2 is pulled high
  • the potential of the node P1 whereby the pull-down module 04 realizes the function of pulling down the potentials of the first node P1 and the control signal output terminal OUT under the control of the second clock signal terminal CLK2 and the third clock signal terminal CLK3.
  • the first pull-down unit 041 may specifically include: a first switching transistor T1 and a first capacitor C1;
  • the gate of the first switching transistor T1 is connected to the second node P2, the source is connected to the control signal output terminal OUT, and the drain is connected to the low-level signal terminal VGL;
  • the first capacitor C1 is connected between the second node P2 and the low level signal terminal VGL.
  • the first switching transistor T1 when the potential of the second node P2 is pulled high, the first switching transistor T1 is in an on state, and the first switching transistor T1 that is turned on has a low level signal end.
  • the VGL is turned on with the control signal output terminal OUT, thereby pulling down the potential of the control signal output terminal OUT.
  • the second pull-down unit 042 may specifically include: a second switching transistor T2;
  • the gate of the second switching transistor T2 is connected to the second node P2, the source is connected to the first node P1, and the drain is connected to the low-level signal terminal VGL.
  • the second switching transistor T2 when the potential of the second node P2 is pulled high, the second switching transistor T2 is in an on state, and the second switching transistor T2 that is turned on is a low level signal end.
  • the VGL is turned on with the first node P1, thereby pulling down the potential of the first node P1.
  • the first pull-down control unit 043 may specifically include: a third switching transistor T3, a fourth switching transistor T4, and a fifth switch.
  • the gate of the third switching transistor T3 is connected to the second clock signal terminal CLK2, the source is connected to the high level signal terminal VGH, and the drain is connected to the source of the fourth switching transistor T4 and the gate of the fifth switching transistor T5, respectively. ;
  • the gate of the fourth switching transistor T4 is connected to the third clock signal terminal CLK3, and the drain is connected to the low-level signal terminal VGL;
  • the source of the fifth switching transistor T5 is connected to the high level signal terminal VGH, and the drain is connected to the second node P2.
  • the third switching transistor T3 when the second clock signal terminal CLK2 inputs a high level signal and the third clock signal terminal CLK3 inputs a low level signal, the third switching transistor T3 is in an on state.
  • the fourth switching transistor T4 is in an off state, and the turned-on third switching transistor T3 turns on the high level signal terminal VGH and the gate of the fifth switching transistor T5, and controls the fifth switching transistor T5 to be turned on.
  • the five-switch transistor T5 turns on the high-level signal terminal VGH and the second node P2 to pull up the potential of the second node P2.
  • the touch control circuit provided by the embodiment of the present disclosure, as shown in FIG. 4, the second pull-down control unit 044 may specifically include: a sixth switching transistor T6;
  • the gate of the sixth switching transistor T6 is connected to the first node P1, the source is connected to the second node P2, and the drain is connected to the low-level signal terminal VGL.
  • the sixth switching transistor T6 when the potential of the first node P1 is pulled high, the sixth switching transistor T6 is in an on state, and the sixth switching transistor T6 that is turned on is a low level signal end.
  • the VGL is turned on with the second node P2, thereby pulling down the potential of the second node P2.
  • the touch signal output control module 05 may specifically include: a high frequency signal output control unit 051 and a common voltage signal output control unit 052. a third node pull-up unit 053 and a third node pull-down unit 054;
  • the control end of the third node pull-up unit 053 is connected to the control signal output terminal OUT, the input end is connected to the low-frequency signal terminal TL, the output terminal is connected to the third node P3, and the third node pull-up unit 053 is used at the control signal output end.
  • the potential of OUT is pulled high, the potential of the third node P3 is raised;
  • the control terminal of the third node pull-down unit 054 is connected to the cut-off signal terminal END, the input terminal is connected to the third node P3, the output terminal is connected to the low-level signal terminal VGL, and the third node pull-down unit 054 is used for the cut-off signal terminal END. Under control, pull down the potential of the third node P3;
  • the control end of the high frequency signal output control unit 051 is connected to the third node P3, and the input end and the high frequency
  • the signal terminal TH is connected, and the output terminal is connected to the touch signal output terminal TX.
  • the high frequency signal output control unit 051 is configured to control the touch signal output terminal TX to output a high frequency signal when the potential of the third node P3 is pulled high.
  • the common voltage signal output control unit 052 is connected to the third node P3, the low level signal terminal VGL, the high level signal terminal VGH, the common voltage signal terminal VCOM, and the touch signal output terminal TX, and the common voltage signal output control unit The 052 is configured to control the touch signal output terminal TX to output a common voltage signal when the potential of the third node P3 is pulled down.
  • the third node pull-up unit 053 raises the potential of the third node P3 when the potential of the control signal output terminal OUT is pulled high, and the third node pull-down unit 054 When the high-level signal is input to the cut-off signal terminal END, the potential of the third node P3 is pulled down; when the potential of the third node P3 is pulled high, the high-frequency signal output control unit 051 controls the touch signal output terminal TX to output the high frequency.
  • the signal; the common voltage signal output control unit 052 controls the touch signal output terminal TX to output a common voltage signal when the potential of the third node P3 is pulled down, thereby implementing the touch signal output control module 05 at the control signal output terminal OUT. Under control, the function of outputting a high frequency signal or a common voltage signal is selected.
  • the third node pull-up unit 053 may specifically include: a seventh switch transistor T7;
  • the gate of the seventh switching transistor T7 is connected to the control signal output terminal OUT, the source is connected to the low frequency signal terminal TL, and the drain is connected to the third node P3.
  • the seventh switching transistor T7 when the potential of the control signal output terminal OUT is pulled high, the seventh switching transistor T7 is in an on state, and the turned on seventh switching transistor T7 is a low frequency signal terminal TL. It is electrically connected to the third node P3, thereby pulling up the potential of the third node P3.
  • the third node pull-down unit 054 may specifically include: an eighth switch transistor T8;
  • the gate of the eighth switching transistor T8 is connected to the off signal terminal END, the source is connected to the third node P3, and the drain is connected to the low level signal terminal VGL.
  • the eighth switching transistor T8 when the cut-off signal terminal END inputs a high-level signal, the eighth switching transistor T8 is in an on state, and the turned-on eighth switching transistor T8 is in a low-level signal end.
  • the VGL is turned on with the third node P3, thereby pulling down the potential of the third node P3.
  • the high-frequency signal output control unit 051 may specifically include: a ninth switching transistor T9 and a second capacitor. C2;
  • the gate of the ninth switching transistor T9 is connected to the third node P3, the source is connected to the high-frequency signal terminal TH, and the drain is connected to the touch signal output terminal TX;
  • the second capacitor C2 is connected between the third node P3 and the touch signal output terminal TX.
  • the ninth switching transistor T9 when the potential of the third node P3 is pulled high, the ninth switching transistor T9 is in an on state, and the turned on ninth switching transistor T9 is a high frequency signal terminal TH.
  • the touch signal output terminal TX is turned on, so that the touch signal output terminal TX outputs a high frequency signal.
  • the common voltage signal output control unit 052 may specifically include: a tenth switch transistor T10, an eleventh switch transistor T11, and a third Capacitor C3;
  • the gate of the tenth switching transistor T10 is connected to the third node P3, and the source is connected to the gate of the high level signal terminal VGH and the eleventh switching transistor T11, respectively, and the drain is connected to the low level signal terminal VGL;
  • the source of the eleventh switching transistor T11 is connected to the common voltage signal terminal VCOM, and the drain is connected to the touch signal output terminal TX;
  • the third capacitor C3 is connected between the high level signal terminal VGH and the low level signal terminal VGL.
  • the tenth switching transistor T10 when the potential of the third node P3 is pulled high, the tenth switching transistor T10 is in an on state, and the turned on tenth switching transistor T10 is an eleventh switching transistor.
  • the gate of T11 is turned on with the low-level signal terminal VGL, so that the eleventh switching transistor T11 is turned off, and the size of the tenth switching transistor T10 is large, so that the function of dividing the voltage can be increased, and the voltage can be pulled down well.
  • the gate voltage of the eleventh switching transistor T11 ensures that the eleventh switching transistor T11 is in a completely off state; when the potential of the third node P3 is pulled low, the tenth switching transistor T10 is in an off state, due to the eleventh switching transistor T11
  • the gate is connected to the high-level signal terminal VGH, so that the eleventh switching transistor T11 is in an on state, and the turned-on eleventh switching transistor T11 turns on the common voltage signal terminal VCOM and the touch signal output terminal TX, thereby further
  • the touch signal output terminal TX outputs a common voltage signal.
  • the common voltage signal output control unit may further include: a twelfth switching transistor T12;
  • the gate and source of the twelfth switching transistor T12 are connected to the high level signal terminal VGH, and the drain is connected to the source of the tenth switching transistor T10 and the gate of the eleventh switching transistor T11, respectively.
  • the twelfth switching transistor T12 connects the high level signal terminal VGH and the source of the tenth switching transistor T10 and the eleventh switching transistor T11 by diode connection.
  • the gate connection is always in the normally open state, and when the tenth switching transistor T10 is in the off state, the high level signal input from the high level signal terminal VGH is transmitted to the gate of the eleventh switching transistor T11, so that the tenth A switching transistor T11 is in an on state, and the turned-on eleventh switching transistor T11 turns on the common voltage signal terminal VCOM and the touch signal output terminal TX, thereby causing the touch signal output terminal TX to output a common voltage signal.
  • the input module 01 may specifically include: a thirteenth switching transistor T13;
  • the gate of the thirteenth switching transistor T13 is connected to the signal input terminal Input, the source is connected to the high level signal terminal VGH, and the drain is connected to the first node P1.
  • the thirteenth switching transistor T13 when the signal input terminal Input inputs a high level signal, the thirteenth switching transistor T13 is in an on state, and the turned on thirteenth switching transistor T13 is at a high level.
  • the signal terminal VGH is turned on with the first node P1 to pull up the potential of the first node P1.
  • the reset module 02 may specifically include: a fourteenth switch transistor T14;
  • the gate of the fourteenth switching transistor T14 is connected to the reset signal terminal Reset, the source is connected to the first node P1, and the drain is connected to the low-level signal terminal VGL.
  • the fourteenth switching transistor T14 when the reset signal end Reset inputs a high level signal, the fourteenth switching transistor T14 is in an on state, and the turned on fourteenth switching transistor T14 is in a low level.
  • the signal terminal VGL is turned on with the first node P1 to pull down the potential of the first node P1.
  • the pull-up module 03 may specifically include: a fifteenth switching transistor T15 and a fourth capacitor C4;
  • the gate of the fifteenth switching transistor T15 is connected to the first node P1, the source is connected to the first clock signal terminal CLK1, and the drain is connected to the control signal output terminal OUT;
  • the fourth capacitor C4 is connected between the first node P1 and the control signal output terminal OUT.
  • the fifteenth switching transistor T15 when the potential of the first node P1 is pulled high, the fifteenth switching transistor T15 is in an on state, and the fifteenth switching transistor T15 that is turned on will be the first clock.
  • the signal terminal CLK1 is turned on with the control signal output terminal OUT, and transmits the signal of the first clock signal terminal CLK1 to the control signal output terminal OUT.
  • an embodiment of the present disclosure provides a touch panel including a plurality of the touch control circuits provided by the embodiments of the present disclosure, except for the first-level touch circuit and the final touch circuit.
  • the control signal output ends of the touch circuits are connected to the signal input end of the adjacent touch circuit of the adjacent touch circuit, and are connected to the reset signal end of the adjacent touch circuit of the adjacent first stage;
  • the control signal output end is connected to the signal input end of the second-level touch circuit;
  • the control signal output end of the final touch circuit is connected to the reset signal end of the upper-level touch circuit.
  • the switching transistor mentioned in the above embodiments of the present disclosure may be an N-type thin film transistor (TFT).
  • TFT thin film transistor
  • the sources and drains of these transistors can be interchanged without specific distinction.
  • the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable.
  • one of the poles is referred to as a source and the other pole is referred to as a drain. If the source is selected as the signal input, the drain acts as the signal output and vice versa.
  • the modules in the touch circuit provided by the embodiments of the present disclosure may all be configured by using N-type thin film transistors, that is, a total of fifteen NMOS transistors and four capacitors are required to form a touch circuit, and the display panel is used to drive the display panel to realize the display function.
  • the N-type thin film transistor driving circuit has better matching performance
  • the touch control circuit is constructed by using a plurality of thin film transistors to construct a transmission gate, an inverter, and a tri-state gate circuit.
  • the touch circuit adopts a small number of N-type thin film transistors. Therefore, the touch control circuit provided by the embodiment of the present disclosure has a simple structure and low power consumption.
  • each level of the touch circuit has three clock signal ends, starting from the first-level touch circuit, with four adjacent cascades.
  • the touch circuit is a group, and the clock signals input by the first touch circuit of each group to the first clock signal end CLK1 of the fourth touch circuit are clock signals CK1, CK2, CK3, and CK4, respectively.
  • the clock signal input from the touch circuit to the second clock signal terminal CLK2 of the fourth touch circuit is clock signal CK2, CK3, CK4, CK1, and the first touch circuit to the fourth touch in each group.
  • the clock signal input to the third clock signal terminal CLK3 of the circuit is sequentially clock signals CK4, CK1, CK2, CK3.
  • the pulse width of the low frequency signal input by the low frequency signal terminal TL is at least twice the pulse width of the high frequency signal input by the high frequency signal terminal TH, at the output end of the touch signal.
  • the TX outputs a high frequency signal
  • the high frequency signal outputted by the touch signal output terminal TX is sampled and selected within the pulse width of the low frequency signal input by the low frequency signal terminal TL, and the touch signal output terminal TX is output every time the high frequency signal is output.
  • there are several high frequency signals output for example, low
  • the pulse width of the frequency signal is twice the pulse width of the high frequency signal, and the touch signal output terminal TX outputs two high frequency signals each time the high frequency signal is output.
  • the working process of the touch circuit provided by the embodiment of the present disclosure is described in detail below with reference to the touch circuit and the working timing provided by the embodiment of the present disclosure.
  • the working process of the touch circuit provided by the embodiment of the present disclosure is described by the touch circuit shown in FIG. 7 and the input/output timing chart shown in FIG. 8 . Specifically, two stages t1 to t2 in the input/output timing chart shown in FIG. 8 are selected. In the following description, a high level signal is indicated by 1 and a low level signal is indicated by 0.
  • the first switching transistor T11 is turned off, and the turned-on ninth switching transistor T9 turns on the high-frequency signal terminal TH and the touch signal output terminal TX, so that the touch signal output terminal TX is based on the low-frequency signal terminal TL.
  • the pulse width of the input low frequency signal outputs a high frequency signal.
  • the t1 phase is a stage in which the touch signal output terminal TX outputs a high frequency signal.
  • the turned-on fifth switching transistor T5 turns on the high-level signal terminal VGH and the second node P2, so that the potential of the second node P2 is pulled high to the high level, so the first switching transistor T1 and the second switching transistor T2 Turn-on, turn-on first switching transistor T1 turns on the control signal output terminal OUT and the low-level signal terminal VGL. Therefore, the potential of the control signal output terminal OUT is pulled low to the low level, so the seventh switching transistor T7 is turned off, resulting in the ninth switching transistor T9 and the The ten-switching transistor T10 is turned off, and the turned-on second switching transistor T2 turns on the low-level signal terminal VGL and the first node P1 to further lower the potential of the first node P1.
  • the twelfth switching transistor T12 Since the twelfth switching transistor T12 is in a normally open state, and the tenth switching transistor T10 is in an off state at this time, the gate of the eleventh switching transistor T11 is turned on by the twelfth switching transistor T12 and the high level signal terminal VGH. Therefore, the eleventh switching transistor T11 is turned on, and the turned-on eleventh switching transistor T11 turns on the common voltage signal terminal VCOM and the touch signal output terminal TX, so that the touch signal output terminal TX outputs a common voltage signal.
  • the t2 phase is a stage in which the touch signal output terminal TX outputs a common voltage signal.
  • the touch signal output terminal will always output the common voltage signal until the signal input terminal Input is input to the high level again for a certain period of time.
  • the above process is a working process in which a touch circuit respectively outputs a high frequency signal and a common voltage signal.
  • a touch circuit respectively outputs a high frequency signal and a common voltage signal.
  • each level of the touch circuit follows the above working process.
  • the high-frequency signal or the common voltage signal is respectively output, as shown in FIG. 9, finally realizing the function of the touch circuit outputting the high-frequency signal step by step, that is, the process of the touch panel progressive touch scanning is realized.
  • an embodiment of the present disclosure provides a display device, including the above touch panel provided by an embodiment of the present disclosure.
  • the display device can be applied to any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the principle of the display device is similar to that of the touch circuit. Therefore, the implementation of the display device can be referred to the implementation of the above touch circuit, and the repeated description is omitted.
  • the embodiment of the present disclosure provides a touch control circuit, a touch panel, and a display device.
  • the touch control circuit includes an input module, a reset module, a pull-up module, a pull-down module, and a touch signal output control module.
  • the control at the signal input pulls down the potential of the first node;
  • the reset module is used to pull down the potential of the first node at the control of the reset signal terminal;
  • the pull-up module is used to pull up under the control of the first node and the first clock signal end Controlling the potential of the signal output end;
  • the pull-down module is configured to pull down the potential of the first node and the control signal output terminal under the control of the second clock signal end and the third clock signal end;
  • the touch signal output control module is used at the output end of the control signal Under control, the control touch signal output terminal selects the output high-frequency signal or the common voltage signal, thereby realizing the function of the touch circuit outputting the touch signal, and constructing the transmission gate and the opposite with respect to

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Abstract

提供了一种触控电路、触控面板及显示装置；所述触控电路包括输入模块(01)用于拉高第一节点(P1)的电位；复位模块(02)用于拉低第一节点(P1)的电位；上拉模块(03)用于拉高控制信号输出端(OUT)的电位；下拉模块(04)用于拉低第一节点(P1)和控制信号输出端(OUT)的电位；触控信号输出控制模块(05)用于控制触控信号输出端(TX)选择输出高频信号(TH)或公共电压信号(VCOM )，以实现触控电路输出触控信号的功能。

Description

触控电路、触控面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种触控电路、触控面板及显示装置。
背景技术
目前，随着移动显示设备的不断发展，人机互动方式已由原来的机械按键模式发展到触控感知的模式，因此，显示设备中的触控电路起到至关重要的作用。
已知的一种触控面板采用如图1所示的触控电路来实现触控扫描功能，其电路结构包括多个传输门A、非门B、三态门C等门电路，以及开关晶体管T，而传输门A和非门B电路均需要两个薄膜晶体管组合实现其相应的功能，三态门C电路则需要四个薄膜晶体管实现其功能，因此，触控电路整体上需要至少32个薄膜晶体管来实现，其结构比较复杂，所需要的薄膜晶体管数量较多，因而其功耗较大。
因此，如何简化触控电路的结构，降低触控电路的功耗，是本领域技术人员亟待解决的问题。
发明内容
本公开实施例提供了一种触控电路、触控面板及显示装置，可以解决已知的触控电路结构较复杂，功耗较大的问题。
本公开实施例提供了一种触控电路，包括：输入模块、复位模块、上拉模块、下拉模块、触控信号输出控制模块，其中：
所述输入模块的控制端与信号输入端相连，输入端与高电平信号端相连，输出端与第一节点相连，所述输入模块用于在所述信号输入端的控制下拉高所述第一节点的电位；
所述复位模块的控制端与复位信号端相连，输入端与所述第一节点相连，输出端与低电平信号端相连，所述复位模块用于在所述复位信号端的控制下拉低所述第一节点的电位；
所述上拉模块的控制端与所述第一节点相连，输入端与第一时钟信号端 相连，输出端与控制信号输出端相连，所述上拉模块用于在所述第一节点和所述第一时钟信号端的控制下，拉高所述控制信号输出端的电位；
所述下拉模块连接于所述高电平信号端、所述低电平信号端、第二时钟信号端、第三时钟信号端、所述控制信号输出端以及所述第一节点之间，所述下拉模块用于在所述第二时钟信号端和第三时钟信号端的控制下，拉低所述第一节点和所述控制信号输出端的电位；
所述触控信号输出控制模块连接于所述高电平信号端、所述低电平信号端、所述控制信号输出端、低频信号端、高频信号端、公共电压信号端、截止信号端以及触控信号输出端之间，所述触控信号输出控制模块用于在所述控制信号输出端的控制下，控制所述触控信号输出端选择输出高频信号或公共电压信号。
可选地，本公开实施例提供的上述触控电路中，所述下拉模块，具体包括：第一下拉单元、第二下拉单元，第一下拉控制单元以及第二下拉控制单元；
所述第一下拉控制单元连接于所述第二时钟信号端、所述第三时钟信号端、所述高电平信号端、所述低电平信号端、所述第一节点以及第二节点之间，所述第一下拉控制单元用于在所述第二时钟信号端和所述第三时钟信号端的控制下，拉高所述第二节点的电位；
所述第二下拉控制单元的控制端与所述第一节点相连，输入端与所述第二节点相连，输出端与所述低电平信号端相连，所述第二下拉控制单元用于在所述第一节点的电位被拉高时，拉低所述第二节点的电位；
所述第一下拉单元的控制端与所述第二节点相连，输入端与所述控制信号输出端相连，输出端与所述低电平信号端相连，所述第一下拉单元用于在所述第二节点的电位被拉高时，拉低所述控制信号输出端的电位；
所述第二下拉单元的控制端与所述第二节点相连，输入端与所述第一节点相连，输出端与所述低电平信号端相连，所述第二下拉单元用于在所述第二节点的电位被拉高时，拉低所述第一节点的电位。
可选地，本公开实施例提供的上述触控电路中，所述第一下拉单元，具体包括：第一开关晶体管和第一电容；
所述第一开关晶体管的栅极与所述第二节点相连，源极与所述控制信号输出端相连，漏极与所述低电平信号端相连；
所述第一电容连接于所述第二节点和所述低电平信号端之间。
可选地，本公开实施例提供的上述触控电路中，所述第二下拉单元，具体包括：第二开关晶体管；
所述第二开关晶体管的栅极与所述第二节点相连，源极与所述第一节点相连，漏极与所述低电平信号端相连。
可选地，本公开实施例提供的上述触控电路中，所述第一下拉控制单元，具体包括：第三开关晶体管、第四开关晶体管和第五开关晶体管；
所述第三开关晶体管的栅极与所述第二时钟信号端相连，源极与所述高电平信号端相连，漏极分别与所述第四开关晶体管的源极和所述第五开关晶体管的栅极相连；
所述第四开关晶体管的栅极与所述第三时钟信号端相连，漏极与所述低电平信号端相连；
所述第五开关晶体管的源极与所述高电平信号端相连，漏极与所述第二节点相连。
可选地，本公开实施例提供的上述触控电路中，所述第二下拉控制单元，具体包括：第六开关晶体管；
所述第六开关晶体管的栅极与所述第一节点相连，源极与所述第二节点相连，漏极与所述低电平信号端相连。
可选地，本公开实施例提供的上述触控电路中，所述触控信号输出控制模块，具体包括：高频信号输出控制单元、公共电压信号输出控制单元、第三节点上拉单元以及第三节点下拉单元；
所述第三节点上拉单元的控制端与所述控制信号输出端相连，输入端与所述低频信号端相连，输出端与所述第三节点相连，所述第三节点上拉单元用于在所述控制信号输出端的电位被拉高时，拉高所述第三节点的电位；
所述第三节点下拉单元的控制端与所述截止信号端相连，输入端与所述第三节点相连，输出端与所述低电平信号端相连，所述第三节点下拉单元用于在所述截止信号端的控制下，拉低所述第三节点的电位；
所述高频信号输出控制单元的控制端与所述第三节点相连，输入端与所述高频信号端相连，输出端与所述触控信号输出端相连，所述高频信号输出控制单元用于在所述第三节点的电位被拉高时，控制所述触控信号输出端输出高频信号；
所述公共电压信号输出控制单元连接于所述第三节点、所述低电平信号端、所述高电平信号端、所述公共电压信号端，以及所述触控信号输出端之间，所述公共电压信号输出控制单元用于在所述第三节点的电位被拉低时，控制所述触控信号输出端输出公共电压信号。
可选地，本公开实施例提供的上述触控电路中，所述第三节点上拉单元，具体包括：第七开关晶体管；
所述第七开关晶体管的栅极与所述控制信号输出端相连，源极与所述低频信号端相连，漏极与所述第三节点相连。
可选地，本公开实施例提供的上述触控电路中，所述第三节点下拉单元，具体包括：第八开关晶体管；
所述第八开关晶体管的栅极与所述截止信号端相连，源极与所述第三节点相连，漏极与所述低电平信号端相连。
可选地，本公开实施例提供的上述触控电路中，所述高频信号输出控制单元，具体包括：第九开关晶体管和第二电容；
所述第九开关晶体管的栅极与所述第三节点相连，源极与所述高频信号端相连，漏极与所述触控信号输出端相连；
所述第二电容连接于所述第三节点和所述触控信号输出端之间。
可选地，本公开实施例提供的上述触控电路中，所述公共电压信号输出控制单元，具体包括：第十开关晶体管、第十一开关晶体管和第三电容；
所述第十开关晶体管的栅极与所述第三节点相连，源极分别与所述高电平信号端和所述第十一开关晶体管的栅极相连，漏极与所述低电平信号端相连；
所述第十一开关晶体管的源极与所述公共电压信号端相连，漏极与所述触控信号输出端相连；
所述第三电容连接于所述高电平信号端和所述低电平信号端之间。
可选地，本公开实施例提供的上述触控电路中，所述公共电压信号输出控制单元，还包括：第十二开关晶体管；
所述第十二开关晶体管的的栅极和源极与所述高电平信号端相连，漏极分别与所述第十开关晶体管的源极和所述第十一开关晶体管的栅极相连。
可选地，本公开实施例提供的上述触控电路中，所述输入模块，具体包括：第十三开关晶体管；
所述第十三开关晶体管的栅极与所述信号输入端相连，源极与所述高电平信号端相连，漏极与所述第一节点相连。
可选地，本公开实施例提供的上述触控电路中，所述复位模块，具体包括：第十四开关晶体管；
所述第十四开关晶体管的栅极与所述复位信号端相连，源极与所述第一节点相连，漏极与所述低电平信号端相连。
可选地，本公开实施例提供的上述触控电路中，所述上拉模块，具体包括：第十五开关晶体管和第四电容；
所述第十五开关晶体管的栅极与所述第一节点相连，源极与所述第一时钟信号端相连，漏极与所述控制信号输出端相连；
所述第四电容连接于所述第一节点和所述控制信号输出端之间。
本公开实施例提供了一种触控面板，包括级联的多个本公开实施例提供的上述触控电路，除首级触控电路和末级触控电路之外，其它各触控电路的控制信号输出端均向与其相邻的下一级触控电路的信号输入端相连，并与其相邻的上一级触控电路的复位信号端相连；首级触控电路的控制信号输出端与第二级触控电路的信号输入端相连；末级触控电路的控制信号输出端与上一级触控电路的复位信号端相连。
本公开实施例提供了一种显示装置，包括本公开实施例提供的上述触控面板。
本公开实施例提供了一种触控电路、触控面板及显示装置，该触控电路包括输入模块、复位模块、上拉模块、下拉模块、触控信号输出控制模块，其中，输入模块用于在信号输入端的控制下拉高第一节点的电位；复位模块用于在复位信号端的控制下拉低第一节点的电位；上拉模块用于在第一节点和第一时钟信号端的控制下，拉高控制信号输出端的电位；下拉模块用于在第二时钟信号端和第三时钟信号端的控制下，拉低第一节点和控制信号输出端的电位；触控信号输出控制模块用于在控制信号输出端的控制下，控制触控信号输出端选择输出高频信号或公共电压信号，这样实现了触控电路输出触控信号的功能，相对于已知的需要采用较多的薄膜晶体管搭建传输门、反相器以及三态门电路进而构成的触控电路，本公开实施例提供的触控电路结构简单，功耗较低。
附图说明
图1为一种已知的触控电路的结构示意图；
图2为本公开实施例提供的触控电路的结构示意图之一；
图3为本公开实施例提供的触控电路中下拉模块的结构示意图；
图4为本公开实施例提供的触控电路中下拉模块的具体结构示意图；
图5为本公开实施例提供的触控电路中触控信号输出控制模块的结构示意图；
图6为本公开实施例提供的触控电路中触控信号输出控制模块的具体结构示意图；
图7为本公开实施例提供的触控电路的具体结构示意图；
图8为本公开实施例提供的触控电路的工作时序示意图；
图9为本公开实施例提供的级联的触控电路依次输出触控信号的工作时序示意图。
具体实施方式
下面结合附图，对本公开实施例提供的触控电路、触控面板及显示装置的具体实施方式进行详细地说明。
本公开实施例提供了一种触控电路，如图2所示，可以包括：输入模块01、复位模块02、上拉模块03、下拉模块04、触控信号输出控制模块05，其中：
输入模块01的控制端与信号输入端Input相连，输入端与高电平信号端VGH相连，输出端与第一节点P1相连，输入模块01用于在信号输入端Input的控制下拉高第一节点P1的电位；
复位模块02的控制端与复位信号端Reset相连，输入端与第一节点P1相连，输出端与低电平信号端VGL相连，复位模块02用于在复位信号端Reset的控制下拉低第一节点P1的电位；
上拉模块03的控制端与第一节点P1相连，输入端与第一时钟信号端CLK1相连，输出端与控制信号输出端OUT相连，上拉模块03用于在第一节点P1和第一时钟信号端CLK1的控制下，拉高控制信号输出端OUT的电位；
下拉模块04连接于高电平信号端VGH、低电平信号端VGL、第二时钟 信号端CLK2、第三时钟信号端CLK3、控制信号输出端OUT以及第一节点P1之间，下拉模块04用于在第二时钟信号端CLK2和第三时钟信号端CLK3的控制下，拉低第一节点P1和控制信号输出端OUT的电位；
触控信号输出控制模块05连接于高电平信号端VGH、低电平信号端VGL、控制信号输出端OUT、低频信号端TL、高频信号端TH、公共电压信号端VCOM、截止信号端END以及触控信号输出端TX之间，触控信号输出控制模块05用于在控制信号输出端OUT的控制下，控制触控信号输出端TX选择输出高频信号或公共电压信号。
本公开实施例提供的上述触控电路中，包括输入模块01、复位模块02、上拉模块03、下拉模块04、触控信号输出控制模块05，其中，输入模块01用于在信号输入端Input的控制下拉高第一节点P1的电位；复位模块02用于在复位信号端Reset的控制下拉低第一节点P1的电位；上拉模块03用于在第一节点P1和第一时钟信号端CLK1的控制下，拉高控制信号输出端OUT的电位；下拉模块04用于在第二时钟信号端CLK2和第三时钟信号端CLK3的控制下，拉低第一节点P1和控制信号输出端OUT的电位；触控信号输出控制模块05用于在控制信号输出端OUT的控制下，控制触控信号输出端TX选择输出高频信号或公共电压信号，这样实现了触控电路输出触控信号的功能，相对于现有技术中需要采用较多的薄膜晶体管搭建传输门、反相器以及三态门电路进而构成的触控电路，本公开实施例提供的触控电路结构简单，功耗较低。
在具体实施时，本公开实施例提供的上述触控电路中，如图3所示，下拉模块04，可以具体包括：第一下拉单元041、第二下拉单元042，第一下拉控制单元043以及第二下拉控制单元044；
第一下拉控制单元043连接于第二时钟信号端CLK2、第三时钟信号端CLK3、高电平信号端VGH、低电平信号端VGL、第一节点P1以及第二节点P2之间，第一下拉控制单元043用于在第二时钟信号端CLK2和第三时钟信号端CLK3的控制下，拉高第二节点P2的电位；
第二下拉控制单元044的控制端与第一节点P1相连，输入端与第二节点P2相连，输出端与低电平信号端VGL相连，第二下拉控制单元044用于在第一节点P1的电位被拉高时，拉低第二节点P2的电位；
第一下拉单元041的控制端与第二节点P2相连，输入端与控制信号输出 端OUT相连，输出端与低电平信号端VGL相连，第一下拉单元041用于在第二节点P2的电位被拉高时，拉低控制信号输出端OUT的电位；
第二下拉单元042的控制端与第二节点P2相连，输入端与第一节点P1相连，输出端与低电平信号端VGL相连，第二下拉单元042用于在第二节点P2的电位被拉高时，拉低第一节点P1的电位。
具体地，本公开实施例提供的上述触控电路中，第一下拉控制单元043在第二时钟信号端CLK2和第三时钟信号端CLK3的控制下将第二节点P2的电位拉高，第一下拉单元041则在第二节点P2的电位被拉高时，拉低控制信号输出端OUT的电位；第二下拉单元042则在第二节点P2的电位被拉高时，拉低第一节点P1的电位，由此下拉模块04实现了在第二时钟信号端CLK2和第三时钟信号端CLK3的控制下，拉低第一节点P1和控制信号输出端OUT的电位的功能。
在具体实施时，本公开实施例提供的上述触控电路中，如图4所示，第一下拉单元041，可以具体包括：第一开关晶体管T1和第一电容C1；
第一开关晶体管T1的栅极与第二节点P2相连，源极与控制信号输出端OUT相连，漏极与低电平信号端VGL相连；
第一电容C1连接于第二节点P2和低电平信号端VGL之间。
具体地，本公开实施例提供的上述触控电路中，第二节点P2的电位被拉高时，第一开关晶体管T1处于导通状态，导通的第一开关晶体管T1将低电平信号端VGL与控制信号输出端OUT导通，进而拉低控制信号输出端OUT的电位。
在具体实施时，本公开实施例提供的上述触控电路中，如图4所示，第二下拉单元042，可以具体包括：第二开关晶体管T2；
第二开关晶体管T2的栅极与第二节点P2相连，源极与第一节点P1相连，漏极与低电平信号端VGL相连。
具体地，本公开实施例提供的上述触控电路中，第二节点P2的电位被拉高时，第二开关晶体管T2处于导通状态，导通的第二开关晶体管T2将低电平信号端VGL与第一节点P1导通，进而拉低第一节点P1的电位。
在具体实施时，本公开实施例提供的上述触控电路中，如图4所示，第一下拉控制单元043，可以具体包括：第三开关晶体管T3、第四开关晶体管T4和第五开关晶体管T5；
第三开关晶体管T3的栅极与第二时钟信号端CLK2相连，源极与高电平信号端VGH相连，漏极分别与第四开关晶体管T4的源极和第五开关晶体管T5的栅极相连；
第四开关晶体管T4的栅极与第三时钟信号端CLK3相连，漏极与低电平信号端VGL相连；
第五开关晶体管T5的源极与高电平信号端VGH相连，漏极与第二节点P2相连。
具体地，本公开实施例提供的上述触控电路中，在第二时钟信号端CLK2输入高电平信号且第三时钟信号端CLK3输入低电平信号时，第三开关晶体管T3处于导通状态，第四开关晶体管T4处于截止状态，导通的第三开关晶体管T3将高电平信号端VGH与第五开关晶体管T5的栅极导通，控制第五开关晶体管T5导通，导通的第五开关晶体管T5将高电平信号端VGH与第二节点P2导通，拉高第二节点P2的电位。
在具体实施时，本公开实施例提供的上述触控电路中，如图4所示，第二下拉控制单元044，可以具体包括：第六开关晶体管T6；
第六开关晶体管T6的栅极与第一节点P1相连，源极与第二节点P2相连，漏极与低电平信号端VGL相连。
具体地，本公开实施例提供的上述触控电路中，第一节点P1的电位被拉高时，第六开关晶体管T6处于导通状态，导通的第六开关晶体管T6将低电平信号端VGL与第二节点P2导通，进而拉低第二节点P2的电位。
在具体实施时，本公开实施例提供的上述触控电路中，如图5所示，触控信号输出控制模块05，可以具体包括：高频信号输出控制单元051、公共电压信号输出控制单元052、第三节点上拉单元053以及第三节点下拉单元054；
第三节点上拉单元053的控制端与控制信号输出端OUT相连，输入端与低频信号端TL相连，输出端与第三节点P3相连，第三节点上拉单元053用于在控制信号输出端OUT的电位被拉高时，拉高第三节点P3的电位；
第三节点下拉单元054的控制端与截止信号端END相连，输入端与第三节点P3相连，输出端与低电平信号端VGL相连，第三节点下拉单元054用于在截止信号端END的控制下，拉低第三节点P3的电位；
高频信号输出控制单元051的控制端与第三节点P3相连，输入端与高频 信号端TH相连，输出端与触控信号输出端TX相连，高频信号输出控制单元051用于在第三节点P3的电位被拉高时，控制触控信号输出端TX输出高频信号；
公共电压信号输出控制单元052连接于第三节点P3、低电平信号端VGL、高电平信号端VGH、公共电压信号端VCOM，以及触控信号输出端TX之间，公共电压信号输出控制单元052用于在第三节点P3的电位被拉低时，控制触控信号输出端TX输出公共电压信号。
具体地，本公开实施例提供的上述触控电路中，第三节点上拉单元053在控制信号输出端OUT的电位被拉高时，拉高第三节点P3的电位，第三节点下拉单元054在截止信号端END输入高电平信号时，拉低第三节点P3的电位；高频信号输出控制单元051在第三节点P3的电位被拉高时，控制触控信号输出端TX输出高频信号；公共电压信号输出控制单元052在第三节点P3的电位被拉低时，控制触控信号输出端TX输出公共电压信号，由此实现触控信号输出控制模块05在控制信号输出端OUT的控制下，选择输出高频信号或公共电压信号的功能。
在具体实施时，本公开实施例提供的上述触控电路中，如图6所示，第三节点上拉单元053，可以具体包括：第七开关晶体管T7；
第七开关晶体管T7的栅极与控制信号输出端OUT相连，源极与低频信号端TL相连，漏极与第三节点P3相连。
具体地，本公开实施例提供的上述触控电路中，控制信号输出端OUT的电位被拉高时，第七开关晶体管T7处于导通状态，导通的第七开关晶体管T7将低频信号端TL与第三节点P3导通，进而拉高第三节点P3的电位。
在具体实施时，本公开实施例提供的上述触控电路中，如图6所示，第三节点下拉单元054，可以具体包括：第八开关晶体管T8；
第八开关晶体管T8的栅极与截止信号端END相连，源极与第三节点P3相连，漏极与低电平信号端VGL相连。
具体地，本公开实施例提供的上述触控电路中，截止信号端END输入高电平信号时，第八开关晶体管T8处于导通状态，导通的第八开关晶体管T8将低电平信号端VGL与第三节点P3导通，进而拉低第三节点P3的电位。
在具体实施时，本公开实施例提供的上述触控电路中，如图6所示，高频信号输出控制单元051，可以具体包括：第九开关晶体管T9和第二电容 C2；
第九开关晶体管T9的栅极与第三节点P3相连，源极与高频信号端TH相连，漏极与触控信号输出端TX相连；
第二电容C2连接于第三节点P3和触控信号输出端TX之间。
具体地，本公开实施例提供的上述触控电路中，第三节点P3的电位被拉高时，第九开关晶体管T9处于导通状态，导通的第九开关晶体管T9将高频信号端TH与触控信号输出端TX导通，进而使触控信号输出端TX输出高频信号。
在具体实施时，本公开实施例提供的上述触控电路中，如图6所示，公共电压信号输出控制单元052，可以具体包括：第十开关晶体管T10、第十一开关晶体管T11和第三电容C3；
第十开关晶体管T10的栅极与第三节点P3相连，源极分别与高电平信号端VGH和第十一开关晶体管T11的栅极相连，漏极与低电平信号端VGL相连；
第十一开关晶体管T11的源极与公共电压信号端VCOM相连，漏极与触控信号输出端相连TX；
第三电容C3连接于高电平信号端VGH和低电平信号端VGL之间。
具体地，本公开实施例提供的上述触控电路中，第三节点P3的电位被拉高时，第十开关晶体管T10处于导通状态，导通的第十开关晶体管T10将第十一开关晶体管T11的栅极与低电平信号端VGL导通，使第十一开关晶体管T11截止，且第十开关晶体管T10的尺寸较大，这样可以增大其分压的作用，可以很好地拉低第十一开关晶体管T11的栅极电压，保证第十一开关晶体管T11处于完全截止状态；第三节点P3的电位被拉低时，第十开关晶体管T10处于截止状态，由于第十一开关晶体管T11的栅极与高电平信号端VGH相连，因此第十一开关晶体管T11处于导通状态，导通的第十一开关晶体管T11将公共电压信号端VCOM与触控信号输出端TX导通，进而使触控信号输出端TX输出公共电压信号。
在具体实施时，本公开实施例提供的上述触控电路中，如图7所示，公共电压信号输出控制单元，还可以包括：第十二开关晶体管T12；
第十二开关晶体管T12的的栅极和源极与高电平信号端VGH相连，漏极分别与第十开关晶体管T10的源极和第十一开关晶体管T11的栅极相连。
具体地，本公开实施例提供的上述触控电路中，第十二开关晶体管T12以二极管的的连接方式将高电平信号端VGH与第十开关晶体管T10的源极和第十一开关晶体管T11的栅极连接，一直处于常开状态，在第十开关晶体管T10处于截止状态时，将高电平信号端VGH输入的高电平信号传递给第十一开关晶体管T11的栅极，使第十一开关晶体管T11处于导通状态，导通的第十一开关晶体管T11将公共电压信号端VCOM与触控信号输出端TX导通，进而使触控信号输出端TX输出公共电压信号。
在具体实施时，本公开实施例提供的上述触控电路中，如图7所示，输入模块01，可以具体包括：第十三开关晶体管T13；
第十三开关晶体管T13的栅极与信号输入端Input相连，源极与高电平信号端VGH相连，漏极与第一节点P1相连。
具体地，本公开实施例提供的上述触控电路中，信号输入端Input输入高电平信号时，第十三开关晶体管T13处于导通状态，导通的第十三开关晶体管T13将高电平信号端VGH与第一节点P1导通，拉高第一节点P1的电位。
在具体实施时，本公开实施例提供的上述触控电路中，如图7所示，复位模块02，可以具体包括：第十四开关晶体管T14；
第十四开关晶体管T14的栅极与复位信号端Reset相连，源极与第一节点P1相连，漏极与低电平信号端VGL相连。
具体地，本公开实施例提供的上述触控电路中，复位信号端Reset输入高电平信号时，第十四开关晶体管T14处于导通状态，导通的第十四开关晶体管T14将低电平信号端VGL与第一节点P1导通，拉低第一节点P1的电位。
在具体实施时，本公开实施例提供的上述触控电路中，如图7所示，上拉模块03，可以具体包括：第十五开关晶体管T15和第四电容C4；
第十五开关晶体管T15的栅极与第一节点P1相连，源极与第一时钟信号端CLK1相连，漏极与控制信号输出端OUT相连；
第四电容C4连接于第一节点P1和控制信号输出端OUT之间。
具体地，本公开实施例提供的上述触控电路中，第一节点P1的电位被拉高时，第十五开关晶体管T15处于导通状态，导通的第十五开关晶体管T15将第一时钟信号端CLK1与控制信号输出端OUT导通，将第一时钟信号端CLK1的信号传递给控制信号输出端OUT。
基于同一发明构思，本公开实施例提供了一种触控面板，包括级联的多个本公开实施例提供的上述触控电路，除首级触控电路和末级触控电路之外，其它各触控电路的控制信号输出端均向与其相邻的下一级触控电路的信号输入端相连，并与其相邻的上一级触控电路的复位信号端相连；首级触控电路的控制信号输出端与第二级触控电路的信号输入端相连；末级触控电路的控制信号输出端与上一级触控电路的复位信号端相连。
需要说明的是本公开上述实施例中提到的开关晶体管可以为N型薄膜晶体管(TFT，Thin Film Transistor)。在具体实施中，这些晶体管的源极和漏极可以互换，不做具体区分。实际上，由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本发明实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。若选取源极作为信号输入端、则漏极作为信号输出端，反之亦然。本公开实施例提供的触控电路中各模块可以全部采用N型薄膜晶体管构成，即总共需要十五个NMOS晶体管和四个电容构成触控电路，与显示面板中用于驱动显示面板实现显示功能的N型薄膜晶体管驱动电路有更好的匹配性，相对于已知的需要采用较多的薄膜晶体管搭建传输门、反相器以及三态门电路进而构成的触控电路，本公开实施例提供的触控电路采用的N型薄膜晶体管数量较少，因此本公开实施例提供的触控电路结构简单，功耗较低。
另外，本公开实施例提供的触控面板的级联的触控电路中，每一级触控电路均有三个时钟信号端，从首级触控电路开始，以相邻的级联的四个触控电路为一组，每组中第一个触控电路到第四个触控电路的第一时钟信号端CLK1输入的时钟信号依次为时钟信号CK1、CK2、CK3、CK4，每组中第一个触控电路到第四个触控电路的第二时钟信号端CLK2输入的时钟信号依次为时钟信号CK2、CK3、CK4、CK1，每组中第一个触控电路到第四个触控电路的第三时钟信号端CLK3输入的时钟信号依次为时钟信号CK4、CK1、CK2、CK3。
此外，本公开实施例提供的上述触控电路中，低频信号端TL输入的低频信号的脉冲宽度至少为高频信号端TH输入的高频信号的脉冲宽度的两倍，在触控信号输出端TX输出高频信号时，在低频信号端TL输入的低频信号的脉冲宽度内对触控信号输出端TX输出高频信号进行采样选择，决定了触控信号输出端TX每一次输出高频信号时，输出的高频信号有几个，例如，低 频信号的脉冲宽度为高频信号的脉冲宽度的两倍，则触控信号输出端TX每次输出高频信号时，输出两个高频信号。
下面结合本公开实施例提供的触控电路和工作时序对本公开实施例提供的触控电路的工作过程进行详细描述。以如图7所示的触控电路以及图8所示的输入输出时序图，对本公开实施例提供的触控电路的工作过程作以描述。具体地，选取如图8所示的输入输出时序图中的t1～t2两个阶段。下述描述中以1表示高电平信号，0表示低电平信号。
在t1阶段，Input＝1，TL＝1，TH＝1，CK1＝1，CK2＝0，CK3＝0，CK4＝0，Reset＝0，END＝0。由于Input＝1，因此第十三开关晶体管T13导通，导通的第十三开关晶体管T13将高电平信号端VGH与第一节点P1导通，因此第一节点P1的电位被拉高为高电平，因此第六开关晶体管T6和第十五开关晶体管T15导通，导通的第六开关晶体管T6将低电平信号端VGL与第二节点P2导通，因此第二节点P2的电位被拉低，第一开关晶体管T1和第二开关晶体管T2截止；导通的第十五开关晶体管T15将第一时钟信号端CLK1与控制信号输出端OUT导通，由于CK1＝1，因此控制信号输出端OUT的电位被拉高，由此第七开关晶体管T7处于导通状态，导通的第七开关晶体管T7将低频信号端TL与第三节点P3导通，由于TL＝1，因此第三节点P3的电位被拉高，由此第九开关晶体管T9和第十开关晶体管T10处于导通状态，导通的第十开关晶体管T10将低电平信号端VGL与第十一开关晶体管的栅极和第十二开关晶体管的漏极导通，因此第十一开关晶体管T11截止，而导通的第九开关晶体管T9将高频信号端TH与触控信号输出端TX导通，使触控信号输出端TX根据低频信号端TL输入的低频信号的脉冲宽度输出高频信号。t1阶段为触控信号输出端TX输出高频信号的阶段。
在t2阶段，Input＝0，TL＝1，TH＝1，CK1＝0，CK2＝1，CK3＝0，CK4＝0，Reset＝1，END＝0。由于Reset＝1，因此第十四开关晶体管T14导通，导通的第十四开关晶体管T14将低电平信号端VGL与第一节点P1导通，因此第一节点P1的电位被拉低为低电平。由于CK2＝1，因此第三开关晶体管T3导通，导通的第三开关晶体管T3将高电平信号端VGH与第五开关晶体管T5的栅极导通，因此第五开关晶体管T5导通，导通的第五开关晶体管T5将高电平信号端VGH与第二节点P2导通，因此第二节点P2的电位被拉高为高电平，因此第一开关晶体管T1和第二开关晶体管T2导通，导通的第一开关晶体管 T1将控制信号输出端OUT与低电平信号端VGL导通，因此，控制信号输出端OUT的电位被拉低为低电平，因此第七开关晶体管T7截止，导致第九开关晶体管T9和第十开关晶体管T10截止，而导通的第二开关晶体管T2将低电平信号端VGL与第一节点P1导通，进一步拉低第一节点P1的电位。由于第十二开关晶体管T12处于常开状态，且此时第十开关晶体管T10处于截止状态，因此第十一开关晶体管T11的栅极通过第十二开关晶体管T12与高电平信号端VGH导通，因此第十一开关晶体管T11导通，导通的第十一开关晶体管T11将公共电压信号端VCOM与触控信号输出端TX导通，使触控信号输出端TX输出公共电压信号。t2阶段为触控信号输出端TX输出公共电压信号的阶段。
在后续时间段，触控信号输出端将一直输出公共电压信号，直到某个时间段信号输入端Input再次输入高电平为止。
上述过程为一个触控电路分别输出高频信号和公共电压信号的工作过程，在触控面板整个级联的触控电路中，在各个信号控制端的控制下，每级触控电路按照上述工作过程分别输出高频信号或公共电压信号，如图9所示，最终实现了触控电路逐级输出高频信号的功能，即实现了触控面板逐行触控扫描的过程。
基于同一发明构思，本公开实施例提供了一种显示装置，包括本公开实施例提供的上述触控面板。该显示装置可以应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。由于该显示装置解决问题的原理与触控电路相似，因此该显示装置的实施可以参见上述触控电路的实施，重复之处不再赘述。
本公开实施例提供了一种触控电路、触控面板及显示装置，该触控电路包括输入模块、复位模块、上拉模块、下拉模块、触控信号输出控制模块，其中，输入模块用于在信号输入端的控制下拉高第一节点的电位；复位模块用于在复位信号端的控制下拉低第一节点的电位；上拉模块用于在第一节点和第一时钟信号端的控制下，拉高控制信号输出端的电位；下拉模块用于在第二时钟信号端和第三时钟信号端的控制下，拉低第一节点和控制信号输出端的电位；触控信号输出控制模块用于在控制信号输出端的控制下，控制触控信号输出端选择输出高频信号或公共电压信号，这样实现了触控电路输出触控信号的功能，相对于已知的需要采用较多的薄膜晶体管搭建传输门、反 相器以及三态门电路进而构成的触控电路，本公开实施例提供的触控电路结构简单，功耗较低。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。
本申请要求于2015年1月21日递交的中国专利申请第201510030501.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (17)

  1. 一种触控电路，包括：输入模块、复位模块、上拉模块、下拉模块、触控信号输出控制模块，其中：
    所述输入模块的控制端与信号输入端相连，输入端与高电平信号端相连，输出端与第一节点相连，所述输入模块用于在所述信号输入端的控制下拉高所述第一节点的电位；
    所述复位模块的控制端与复位信号端相连，输入端与所述第一节点相连，输出端与低电平信号端相连，所述复位模块用于在所述复位信号端的控制下拉低所述第一节点的电位；
    所述上拉模块的控制端与所述第一节点相连，输入端与第一时钟信号端相连，输出端与控制信号输出端相连，所述上拉模块用于在所述第一节点和所述第一时钟信号端的控制下，拉高所述控制信号输出端的电位；
    所述下拉模块连接于所述高电平信号端、所述低电平信号端、第二时钟信号端、第三时钟信号端、所述控制信号输出端以及所述第一节点之间，所述下拉模块用于在所述第二时钟信号端和第三时钟信号端的控制下，拉低所述第一节点和所述控制信号输出端的电位；
    所述触控信号输出控制模块连接于所述高电平信号端、所述低电平信号端、所述控制信号输出端、低频信号端、高频信号端、公共电压信号端、截止信号端以及触控信号输出端之间，所述触控信号输出控制模块用于在所述控制信号输出端的控制下，控制所述触控信号输出端选择输出高频信号或公共电压信号。
  2. 如权利要求1所述的触控电路，其中，所述下拉模块包括：第一下拉单元、第二下拉单元，第一下拉控制单元以及第二下拉控制单元；
    所述第一下拉控制单元连接于所述第二时钟信号端、所述第三时钟信号端、所述高电平信号端、所述低电平信号端、所述第一节点以及第二节点之间，所述第一下拉控制单元用于在所述第二时钟信号端和所述第三时钟信号端的控制下，拉高所述第二节点的电位；
    所述第二下拉控制单元的控制端与所述第一节点相连，输入端与所述第二节点相连，输出端与所述低电平信号端相连，所述第二下拉控制单元用于 在所述第一节点的电位被拉高时，拉低所述第二节点的电位；
    所述第一下拉单元的控制端与所述第二节点相连，输入端与所述控制信号输出端相连，输出端与所述低电平信号端相连，所述第一下拉单元用于在所述第二节点的电位被拉高时，拉低所述控制信号输出端的电位；
    所述第二下拉单元的控制端与所述第二节点相连，输入端与所述第一节点相连，输出端与所述低电平信号端相连，所述第二下拉单元用于在所述第二节点的电位被拉高时，拉低所述第一节点的电位。
  3. 如权利要求2所述的触控电路，其中，所述第一下拉单元，包括：第一开关晶体管和第一电容；
    所述第一开关晶体管的栅极与所述第二节点相连，源极与所述控制信号输出端相连，漏极与所述低电平信号端相连；
    所述第一电容连接于所述第二节点和所述低电平信号端之间。
  4. 如权利要求2或3所述的触控电路，其中，所述第二下拉单元，包括：第二开关晶体管；
    所述第二开关晶体管的栅极与所述第二节点相连，源极与所述第一节点相连，漏极与所述低电平信号端相连。
  5. 如权利要求2-4任一项所述的触控电路，其中，所述第一下拉控制单元，包括：第三开关晶体管、第四开关晶体管和第五开关晶体管；
    所述第三开关晶体管的栅极与所述第二时钟信号端相连，源极与所述高电平信号端相连，漏极分别与所述第四开关晶体管的源极和所述第五开关晶体管的栅极相连；
    所述第四开关晶体管的栅极与所述第三时钟信号端相连，漏极与所述低电平信号端相连；
    所述第五开关晶体管的源极与所述高电平信号端相连，漏极与所述第二节点相连。
  6. 如权利要求2-5任一项所述的触控电路，其中，所述第二下拉控制单元，包括：第六开关晶体管；
    所述第六开关晶体管的栅极与所述第一节点相连，源极与所述第二节点相连，漏极与所述低电平信号端相连。
  7. 如权利要求1-6任一项所述的触控电路，其中，所述触控信号输出控制模块，包括：高频信号输出控制单元、公共电压信号输出控制单元、第三 节点上拉单元以及第三节点下拉单元；
    所述第三节点上拉单元的控制端与所述控制信号输出端相连，输入端与所述低频信号端相连，输出端与所述第三节点相连，所述第三节点上拉单元用于在所述控制信号输出端的电位被拉高时，拉高所述第三节点的电位；
    所述第三节点下拉单元的控制端与所述截止信号端相连，输入端与所述第三节点相连，输出端与所述低电平信号端相连，所述第三节点下拉单元用于在所述截止信号端的控制下，拉低所述第三节点的电位；
    所述高频信号输出控制单元的控制端与所述第三节点相连，输入端与所述高频信号端相连，输出端与所述触控信号输出端相连，所述高频信号输出控制单元用于在所述第三节点的电位被拉高时，控制所述触控信号输出端输出高频信号；
    所述公共电压信号输出控制单元连接于所述第三节点、所述低电平信号端、所述高电平信号端、所述公共电压信号端，以及所述触控信号输出端之间，所述公共电压信号输出控制单元用于在所述第三节点的电位被拉低时，控制所述触控信号输出端输出公共电压信号。
  8. 如权利要求7所述的触控电路，其中，所述第三节点上拉单元，包括：第七开关晶体管；
    所述第七开关晶体管的栅极与所述控制信号输出端相连，源极与所述低频信号端相连，漏极与所述第三节点相连。
  9. 如权利要求7或8所述的触控电路，其中，所述第三节点下拉单元，包括：第八开关晶体管；
    所述第八开关晶体管的栅极与所述截止信号端相连，源极与所述第三节点相连，漏极与所述低电平信号端相连。
  10. 如权利要求7-9任一项所述的触控电路，其中，所述高频信号输出控制单元，包括：第九开关晶体管和第二电容；
    所述第九开关晶体管的栅极与所述第三节点相连，源极与所述高频信号端相连，漏极与所述触控信号输出端相连；
    所述第二电容连接于所述第三节点和所述触控信号输出端之间。
  11. 如权利要求7-10任一项所述的触控电路，其中，所述公共电压信号输出控制单元，包括：第十开关晶体管、第十一开关晶体管和第三电容；
    所述第十开关晶体管的栅极与所述第三节点相连，源极分别与所述高电 平信号端和所述第十一开关晶体管的栅极相连，漏极与所述低电平信号端相连；
    所述第十一开关晶体管的源极与所述公共电压信号端相连，漏极与所述触控信号输出端相连；
    所述第三电容连接于所述高电平信号端和所述低电平信号端之间。
  12. 如权利要求11所述的触控电路，其中，所述公共电压信号输出控制单元，还包括：第十二开关晶体管；
    所述第十二开关晶体管的的栅极和源极与所述高电平信号端相连，漏极分别与所述第十开关晶体管的源极和所述第十一开关晶体管的栅极相连。
  13. 如权利要求1-12任一项所述的触控电路，其中，所述输入模块，包括：第十三开关晶体管；
    所述第十三开关晶体管的栅极与所述信号输入端相连，源极与所述高电平信号端相连，漏极与所述第一节点相连。
  14. 如权利要求1-13任一项所述的触控电路，其中，所述复位模块，包括：第十四开关晶体管；
    所述第十四开关晶体管的栅极与所述复位信号端相连，源极与所述第一节点相连，漏极与所述低电平信号端相连。
  15. 如权利要求1-14任一项所述的触控电路，其中，所述上拉模块，包括：第十五开关晶体管和第四电容；
    所述第十五开关晶体管的栅极与所述第一节点相连，源极与所述第一时钟信号端相连，漏极与所述控制信号输出端相连；
    所述第四电容连接于所述第一节点和所述控制信号输出端之间。
  16. 一种触控面板，包括级联的多个如权利要求1-15任一项所述的触控电路，除首级触控电路和末级触控电路之外，其它各触控电路的控制信号输出端均与其相邻的下一级触控电路的信号输入端相连，并与其相邻的上一级触控电路的复位信号端相连；首级触控电路的控制信号输出端与第二级触控电路的信号输入端相连；末级触控电路的控制信号输出端与上一级触控电路的复位信号端相连。
  17. 一种显示装置，包括如权利要求16所述的触控面板。
PCT/CN2015/079501 2015-01-21 2015-05-21 触控电路、触控面板及显示装置 Ceased WO2016115797A1 (zh)

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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104571710B (zh) 2015-01-21 2017-08-25 京东方科技集团股份有限公司 一种触控电路、触控面板及显示装置
CN104793805B (zh) 2015-05-13 2017-11-07 京东方科技集团股份有限公司 一种触控电路、触控面板及显示装置
CN104932747A (zh) * 2015-06-24 2015-09-23 京东方科技集团股份有限公司 一种触控驱动单元、触控面板及显示装置
CN107564458A (zh) * 2017-10-27 2018-01-09 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN109213380A (zh) * 2018-11-12 2019-01-15 京东方科技集团股份有限公司 输入控制电路及方法、输入控制装置、显示面板
KR102706077B1 (ko) * 2018-12-17 2024-09-13 삼성디스플레이 주식회사 스캔 구동부 및 이를 포함하는 표시 장치

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008193545A (ja) * 2007-02-07 2008-08-21 Mitsubishi Electric Corp 半導体装置およびシフトレジスタ回路
US20090167741A1 (en) * 2007-12-27 2009-07-02 Chi Mei Optoelectronics Corp. Flat panel display and driving method thereof
CN103218972A (zh) * 2013-04-15 2013-07-24 京东方科技集团股份有限公司 像素电路、像素电路驱动方法及显示装置
CN103761002A (zh) * 2013-12-31 2014-04-30 北京大学深圳研究生院 一种触控电路及其单元和触控显示面板及其装置
CN103943083A (zh) * 2014-03-27 2014-07-23 京东方科技集团股份有限公司 一种栅极驱动电路及其驱动方法、显示装置
CN203746393U (zh) * 2014-03-27 2014-07-30 京东方科技集团股份有限公司 一种栅极驱动电路及显示装置
CN103996370A (zh) * 2014-05-30 2014-08-20 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN104036738A (zh) * 2014-03-27 2014-09-10 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN104571710A (zh) * 2015-01-21 2015-04-29 京东方科技集团股份有限公司 一种触控电路、触控面板及显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8559247B2 (en) * 2011-05-16 2013-10-15 Apple Inc. Dynamic level shifter for interfacing signals referenced to different power supply domains
KR101382108B1 (ko) * 2012-06-15 2014-04-08 엘지디스플레이 주식회사 액정표시장치 및 그 구동방법
CN102750062B (zh) * 2012-06-29 2016-02-10 京东方科技集团股份有限公司 一种电容式内嵌触摸屏及显示装置
CN103943055B (zh) * 2014-03-27 2016-05-11 京东方科技集团股份有限公司 一种栅极驱动电路及其驱动方法、显示装置
CN104217763B (zh) * 2014-08-28 2018-01-02 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN204102544U (zh) * 2014-11-07 2015-01-14 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008193545A (ja) * 2007-02-07 2008-08-21 Mitsubishi Electric Corp 半導体装置およびシフトレジスタ回路
US20090167741A1 (en) * 2007-12-27 2009-07-02 Chi Mei Optoelectronics Corp. Flat panel display and driving method thereof
CN103218972A (zh) * 2013-04-15 2013-07-24 京东方科技集团股份有限公司 像素电路、像素电路驱动方法及显示装置
CN103761002A (zh) * 2013-12-31 2014-04-30 北京大学深圳研究生院 一种触控电路及其单元和触控显示面板及其装置
CN103943083A (zh) * 2014-03-27 2014-07-23 京东方科技集团股份有限公司 一种栅极驱动电路及其驱动方法、显示装置
CN203746393U (zh) * 2014-03-27 2014-07-30 京东方科技集团股份有限公司 一种栅极驱动电路及显示装置
CN104036738A (zh) * 2014-03-27 2014-09-10 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN103996370A (zh) * 2014-05-30 2014-08-20 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN104571710A (zh) * 2015-01-21 2015-04-29 京东方科技集团股份有限公司 一种触控电路、触控面板及显示装置

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