WO2016112688A1 - 阵列基板及其制造方法、和显示装置 - Google Patents

阵列基板及其制造方法、和显示装置 Download PDF

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Publication number
WO2016112688A1
WO2016112688A1 PCT/CN2015/087591 CN2015087591W WO2016112688A1 WO 2016112688 A1 WO2016112688 A1 WO 2016112688A1 CN 2015087591 W CN2015087591 W CN 2015087591W WO 2016112688 A1 WO2016112688 A1 WO 2016112688A1
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Prior art keywords
electrode layer
electric field
electrode
horizontal electric
array substrate
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Ceased
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PCT/CN2015/087591
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English (en)
French (fr)
Inventor
刘晓那
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US14/905,498 priority Critical patent/US9885928B2/en
Publication of WO2016112688A1 publication Critical patent/WO2016112688A1/zh
Anticipated expiration legal-status Critical
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1343—Electrodes
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    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method of fabricating the array substrate, and a display device including the array substrate.
  • FIG. 1 is a schematic structural view of a liquid crystal display panel of a conventional FFS (Fringe Field Switching) mode.
  • a pixel electrode 4 and a plate-shaped common electrode 2 are provided on an array substrate of the liquid crystal display panel.
  • the liquid crystal molecules are rotated by the horizontal component of the fringe electric field formed between the pixel electrode 4 and the plate-like common electrode 2.
  • the liquid crystal display panel shown in Fig. 1 Since the common electrode 2 is located below the pixel electrode 4, the liquid crystal display panel shown in Fig. 1 has a large vertical electric field, and the horizontal electric field is relatively small.
  • An object of the present invention is to provide an array substrate, a display device including the array substrate, and a method of manufacturing the array substrate.
  • a display device including the array substrate can generate a strong horizontal electric field when displayed.
  • an array substrate including a base substrate, a first electrode layer, and a second electrode layer insulated from the first electrode layer, the An electrode layer includes a plurality of first electrode strips arranged in a matrix, the second electrode layer includes a plurality of horizontal electric field generating portions, an upper surface of the plurality of horizontal electric field generating portions and the plurality of first electrode strips The upper surface is flush, and the orthographic projections of the plurality of first electrode strips and the plurality of horizontal electric field generating portions on the base substrate alternate with each other in the direction of the row or column of the matrix.
  • the array substrate further includes a plurality of insulating strips respectively disposed under the plurality of horizontal electric field generating portions such that an upper surface of the plurality of horizontal electric field generating portions and the plurality of The upper surfaces of the first electrode strips are flush.
  • the second electrode further includes a plurality of connecting portions, each of the connecting portions being connected between two adjacent horizontal electric field generating portions, wherein the plurality of first electrode strips are respectively located in the plurality of Above the connecting portion, the projections of the plurality of connecting portions and the plurality of horizontal electric field generating portions on the base substrate of the array substrate collectively form a rectangular region.
  • the second electrode further includes a plurality of connecting portions, each of the connecting portions connecting the same side end portions of two adjacent horizontal electric field generating portions.
  • the array substrate further includes an insulating layer covering a layer where the second electrode is located, and the first electrode is formed on the insulating layer.
  • the first electrode layer is a pixel electrode layer
  • the second electrode layer is a common electrode layer.
  • a display device comprising an array substrate, wherein the array substrate is any one of the above array substrates provided by the present invention.
  • a method of fabricating an array substrate comprising the steps of:
  • first electrode layer Forming a first electrode layer, the first electrode layer and the second electrode layer are insulated from each other, the first electrode layer includes a plurality of first electrode strips, and an upper surface of the plurality of first electrode strips The upper surfaces of the plurality of horizontal electric field generating portions are flush, and the orthogonal projections of the plurality of first electrode strips and the plurality of horizontal electric field generating portions on the base substrate alternate with each other.
  • the manufacturing method further comprises the steps of: forming a pattern comprising a plurality of insulating strips, the positions of the plurality of insulating strips corresponding to the plurality of horizontal electric field generating portions s position.
  • the manufacturing method further includes the steps of:
  • An insulating layer is formed, the insulating layer covering the base substrate on which the second electrode layer is formed.
  • the second electrode layer formed in the step of forming the second electrode layer further includes a plurality of connecting portions, each of the connecting portions being connected between two adjacent horizontal electric field generating portions, and
  • the orthographic projections of the plurality of connection portions and the plurality of horizontal electric field generating portions on the base substrate collectively form a rectangular region, and the plurality of first electrode strips formed in the step of forming the first electrode layer respectively Located above the plurality of connections.
  • the second electrode layer formed in the step of forming the second electrode layer further includes a plurality of connecting portions, each of the connecting portions connecting the same side end portions of two adjacent horizontal electric fields.
  • the level of the electric field formed between the first electrode strip and the horizontal electric field generating portion when the display device including the array substrate is electrically displayed The component is large and the vertical component is small. It is further known that when the display device including the array substrate is electrically displayed, the storage capacitance between the first electrode in the first electrode layer and the second electrode in the second electrode layer is small, thereby shortening The time required to charge the storage capacitor. Since the horizontal component of the electric field formed between the first electrode strip and the horizontal electric field generating portion is large, the liquid crystal molecules can be driven to rotate by providing a small driving voltage.
  • the display using the array substrate provided by the present invention can reduce the storage capacitance and the driving voltage of each pixel unit and improve the uniformity of the transmittance of the display area without losing the overall transmittance of the pixel region.
  • FIG. 1 is a schematic structural view of a conventional FFS mode liquid crystal display panel
  • FIG. 2 is a schematic structural view of a first embodiment of an array substrate provided by the present invention.
  • Figure 3 is a plan view of a second electrode in the array substrate shown in Figure 2;
  • FIG. 4 is a schematic structural view of a second embodiment of an array substrate provided by the present invention.
  • Figure 5 is a plan view of a second electrode in the array substrate shown in Figure 4.
  • 6(a) to 6(d) are schematic views showing a process of manufacturing the array substrate shown in Fig. 2.
  • an array substrate including a base substrate 50, a first electrode layer, and a second electrode layer insulated from the first electrode layer, the first electrode layer including a plurality of first electrode strips 40 arranged in a matrix, the second electrode layer including a plurality of horizontal electric field generating portions 21, an upper surface of the plurality of horizontal electric field generating portions 21 and an upper portion of the plurality of first electrode strips 40
  • the surface is flush, and the orthographic projections of the plurality of first electrode strips 40 and the plurality of horizontal electric field generating portions 21 on the base substrate 50 alternate with each other in the direction of the row or column of the matrix.
  • orientation word “upper” as used herein refers to the “upper” side in Figures 2 and 4.
  • the "upper surface of the plurality of horizontal electric field generating portions 21 is flush with the upper surfaces of the plurality of first electrode strips 40" means that the upper surface of each of the horizontal electric field generating portions 21 and the upper surface of each of the first electrode strips 40 are Located on the same plane.
  • horizontal refers to the left and right directions in Figures 2 and 4
  • vertical as used herein refers to the upper and lower directions in Figures 2 and 4.
  • flat flush herein does not mean that they are strictly on the same plane, but may be substantially on the same plane, that is, the upper surface distance of each horizontal electric field generating portion 21.
  • the difference between the distance of the upper surface of the base substrate 50 and the distance from the upper surface of each of the first electrode strips 40 from the upper surface of the base substrate 50 is as small as possible within the range achievable by industrial production.
  • one of the first electrode layer and the second electrode layer is a pixel electrode layer and the other is a common electrode layer. In a specific embodiment of the present invention, a description will be given by taking a first electrode layer as a pixel electrode layer and a second electrode layer as a common electrode layer.
  • each first The horizontal component of the electric field formed between the electrode strip 40 and the adjacent horizontal electric field generating portion 21 is large, and the vertical component is small. It is further known that when the display device including the array substrate is electrically displayed, the storage capacitance between the first electrode layer and the second electrode layer is small, thereby shortening the time required for charging the storage capacitor. . Since the horizontal component of the electric field formed between each of the first electrode strips 40 and the adjacent horizontal electric field generating portion 21 is large, it is only necessary to provide a small driving voltage Vop to drive the liquid crystal molecules to rotate.
  • the display using the array substrate provided by the present invention can reduce the storage capacitance and the driving voltage Vop of each pixel unit without losing the overall transmittance of the pixel region.
  • the first electrode strip 40 and the horizontal electric field generating portion 21 in each pixel unit have the structure described above, and each of the first electrode strips 40 and the adjacent horizontal electric field are generated.
  • the horizontal component of the electric field formed between the portions 21 is large, and therefore the horizontal component of the electric field generated in each pixel unit is large, so that the driving force of the electric field generated in each pixel unit to the liquid crystal molecules is correspondingly large,
  • the liquid crystal molecules corresponding to each pixel unit are reliably deflected, thereby improving the uniformity of the transmittance of the display area.
  • the thickness of the first electrode strip 40 and the horizontal electric field generating portion 21 is not particularly limited as long as the upper surface of each horizontal electric field generating portion 21 is flush with the upper surface of each of the first electrode strips 40.
  • the thickness of each horizontal electric field generating portion 21 may be increased such that the upper surface of each horizontal electric field generating portion 21 is flush with the upper surface of each of the first electrode strips 40.
  • the array substrate may further include a plurality of insulating strips 10 respectively disposed under the plurality of horizontal electric field generating portions 21 to cause the plurality of horizontal electric field generating portions
  • the upper surface of 21 is flush with the upper surface of the plurality of first electrode strips 40.
  • the array substrate may further include an insulating layer 30 covering the second electrode layer, and the first electrode layer is formed on the insulating layer 30 on.
  • the second electrode layer has the structure shown in FIGS. 2 and 3. As shown in FIG. 3, the second electrode layer further includes a plurality of connecting portions 22, each of which connects the same side end portions of the adjacent two horizontal electric field generating portions 21.
  • the second electrode layer has the structure of FIG. The structure shown. As shown in FIG. 4, the second electrode layer further includes a plurality of connecting portions 22, each connecting portion 22 is connected between two adjacent horizontal electric field generating portions 21, and the plurality of first electrode strips 40 are respectively Located above the plurality of connecting portions 22.
  • the orientation word "above” as used herein refers to the "upper" side of Figure 4.
  • the orthographic projections of the plurality of horizontal electric field generating portions 21 and the plurality of connecting portions 22 on the base substrate 50 collectively form a rectangular region as shown in FIG.
  • the row and the column of the matrix formed by the plurality of first electrodes of the present invention are not particularly limited.
  • the “row” is “column”.
  • the horizontal electric field generating portion 21 and the first electrode strip 40 alternate in the lateral direction of FIG. 2 or FIG. 4, and in the other direction. In the direction perpendicular to the paper surface or the extending direction of the horizontal electric field generating portion 21, only the horizontal electric field generating portion 21 or the electrode strip 40 is disposed.
  • the present invention does not specifically limit the specific configuration of the horizontal electric field generating portion 21 as long as it can ensure that the electric field generating portions 21 can be connected together, thereby ensuring stable input of the common electrode signal.
  • the array substrate further includes structures such as gate lines, data lines, thin film transistors, and the like.
  • the arrangement of these structures is well known to those skilled in the art and is not described in detail in the present invention.
  • the base substrate 50 may include a transparent substrate, a gate line layer formed on the transparent substrate, a gate insulating layer formed on the gate line layer, and a gate insulating layer formed on the gate line
  • An insulating strip 10 may be formed on the planarization layer (not shown).
  • the first electrode layer includes a first electrode of a plurality of pixel units
  • the second electrode layer includes a second electrode of the plurality of pixel units
  • the gate line layer includes a gate line, a common electrode line, a gate or the like
  • the active region layer includes an active region of a plurality of thin film transistors
  • the source/drain electrode layer includes a source and a drain of the plurality of thin film transistors.
  • the first electrode may be a pixel electrode and the second electrode may be a common electrode.
  • an alignment film 60 may also be formed on the array substrate as shown in FIGS. 2 and 4. The alignment film 60 is overlaid on the base substrate 50 on which the first electrode layer and the second electrode layer are formed.
  • a display device comprising an array substrate, wherein the array substrate is any one of the above array substrates provided by the present invention.
  • the display device includes any of the above array substrates provided by the present invention, the display device has a small storage capacitance and requires a small operating voltage when performing display.
  • the display device may further include a pair of cassette substrates for being disposed with the array substrate.
  • a liquid crystal material is filled between the pair of cassette substrates and the array substrate.
  • the pair of cassette substrates may be a color filter substrate.
  • the storage capacitance is reduced by 79.8%, the operating voltage is lowered by 0.3V, and the charging station is greatly reduced.
  • the time required and the overall energy consumption of the display device is reduced.
  • the fluctuation range of the maximum transmittance of the pixel region is reduced from 0.0184 to 0.0139, and it is understood that the uniformity of the transmittance of the display region of the display device including the array substrate shown in Fig. 2 is improved.
  • the storage capacitance is reduced by 1.5%, the operating voltage is lowered by 0.3V, the time required for charging is also reduced to some extent, and the display device is lowered.
  • Overall energy consumption Further, the fluctuation range of the maximum transmittance of the pixel region is reduced from 0.0184 to 0.0146, and it is understood that the uniformity of the transmittance of the display region of the display device including the array substrate shown in Fig. 4 is improved.
  • the display device provided by the present invention may be an electronic device such as a mobile phone, a tablet computer, a computer display, a television, a navigator, or an electronic photo frame.
  • a method for fabricating the above array substrate includes the steps of:
  • first electrode layer Forming a first electrode layer, the first electrode layer and the second electrode layer are insulated from each other, the first electrode layer includes a plurality of first electrode strips 40, and the upper surfaces of the plurality of first electrode strips 40 are The upper surface of the horizontal electric field generating portion 21 is flush (see FIG. 6(d)), and the orthographic projection phases of the plurality of first electrode strips 40 and the plurality of horizontal electric field generating portions 21 on the base substrate 50 Alternate.
  • the second electrode layer including the plurality of horizontal electric field generating portions 21 may be formed by a conventional photolithography patterning process, or the second electrode layer including the plurality of horizontal electric field generating portions 21 may be formed by a method such as mask evaporation.
  • the specific method of forming the first electrode layer is not particularly limited.
  • the first electrode layer including the plurality of first electrode strips 40 may be formed using a conventional photolithography patterning process, and the first electrode layer including the plurality of first electrode strips 40 may be formed by a method such as mask evaporation.
  • the manufacturing method further includes the steps of: forming The pattern of the plurality of insulating strips 10, the positions of the plurality of insulating strips 10 respectively correspond to the positions of the plurality of horizontal electric field generating portions 21 (see Fig. 6(b)). It is easily understood that the number and shape of the insulating strips 10 are the same as the number and shape of the horizontal electric field generating portion 21.
  • the insulating strip 10 may be made of an oxide of silicon (SiOx) or a nitride of silicon (SiNx), or the insulating strip 10 may be made of an organic resin material.
  • a pattern including a plurality of insulating stripes 10 may be formed on the base substrate 50 using a conventional photolithography process.
  • the step of forming a pattern including the plurality of insulating strips 10 may specifically include:
  • the insulating material layer is dry-etched or wet-etched by using the exposed photoresist layer as a mask to form a pattern including a plurality of insulating strips 10.
  • the manufacturing method may further include the steps performed after the step of forming the second electrode layer and before the step of forming the first electrode layer:
  • An insulating layer 30 is formed which covers the base substrate 50 on which the second electrode layer is formed (as shown in FIG. 6(c)).
  • the insulating layer 30 may be made of an oxide of silicon (SiOx) or a nitride of silicon (SiNx).
  • the insulating layer 30 may be formed on the base substrate 50 on which the second electrode layer is formed by vapor deposition or chemical vapor deposition.
  • the first electrode layer including the plurality of first electrode strips 40 is formed on the insulating layer 30 (as shown in FIG. 6(d)).
  • the manufacturing method further includes the steps performed after the step of forming a pattern including the plurality of first electrode strips 40:
  • An alignment layer is formed.
  • the alignment layer may be formed using a resin material.
  • the step of forming the alignment layer includes:
  • the alignment layer is obtained by a rubbing method.
  • the second electrode layer has the structure shown in FIGS. 2 and 3. As shown in FIG. 3, the second electrode layer further includes a plurality of connecting portions 22, each of which connects the same side end portions of the adjacent two horizontal electric field generating portions 21.
  • the second electrode layer has the structure shown in FIG. As shown in FIG. 4, the second electrode layer further includes a plurality of connecting portions 22, each connecting portion 22 is connected between two adjacent horizontal electric field generating portions 21, and the plurality of first electrode strips 40 are respectively located at a plurality of Above the connecting portion 22.
  • the orthographic projections of the plurality of horizontal electric field generating portions 21 and the plurality of connecting portions 22 on the base substrate 50 collectively form a rectangular region as shown in FIG.
  • the first electrode layer and the second electrode layer are separately formed using a transparent electrode material such as ITO.
  • the base substrate is further formed with a gate line, a data line, and a thin film.
  • Other components such as transistors.
  • the manufacturing method includes the steps performed before the step of forming a pattern including a plurality of insulating stripes:
  • a planarization layer is formed on the source/drain electrode layer.
  • the first electrode layer includes a first electrode of the plurality of pixel units
  • the second electrode layer includes a second electrode of the plurality of pixel units
  • the gate line layer includes a gate line, a common electrode line, a gate, and the like
  • the active region layer includes an active region of a plurality of thin film transistors
  • the source/drain electrode layer includes a source and a drain of a plurality of thin film transistors.
  • the first electrode may be a pixel electrode, and the second electrode may be a common electrode. Therefore, the first electrode may be connected to a drain in the source/drain electrode layer through a via, and the second electrode may be connected to a common electrode line located in the gate line layer through a via.

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Abstract

一种阵列基板，一种显示装置以及一种阵列基板的制造方法，阵列基板包括衬底基板（50）、第一电极层和与第一电极层互相绝缘的第二电极层，第一电极层包括呈矩阵排列的多个第一电极条（40），其中，第二电极层包括多个水平电场产生部（21），多个水平电场产生部（21）的上表面与多个第一电极条（40）的上表面平齐，并且在矩阵的行或列的方向上，多个第一电极条（40）和多个水平电场产生部（21）在衬底基板（50）上的正投影相互交替。利用该阵列基板进行显示可以在不损失像素区整体透过率的前提下，降低每个像素单元的存储电容和驱动电压，提高显示区透过率的均一性。

Description

阵列基板及其制造方法、和显示装置 技术领域
本发明涉及显示技术领域，具体地，涉及一种阵列基板、该阵列基板的制造方法和包括该阵列基板的显示装置。
背景技术
图1为现有的FFS(Fringe Field Switching，边缘场开关)模式的液晶显示面板的结构示意图。如图1所示，在所述液晶显示面板的阵列基板上设置有像素电极4和板状的公共电极2。利用像素电极4和板状的公共电极2之间形成的边缘电场的水平分量驱动液晶分子旋转。
由于公共电极2位于像素电极4的下方，因此，图1所示的液晶显示面板具有较大的竖直电场，而水平电场相对较小。
可见，如何增加FFS模式的液晶显示面板在显示时的水平电场成为本领域亟待解决的技术问题。
发明内容
本发明的目的在于提供一种阵列基板、一种包括该阵列基板的显示装置和所述阵列基板的制造方法。包括所述阵列基板的显示装置在进行显示时可以产生较强的水平电场。
为了实现上述目的，作为本发明的一个方面，提供一种阵列基板，所述阵列基板包括衬底基板、第一电极层和与所述第一电极层互相绝缘的第二电极层，所述第一电极层包括呈矩阵排列的多个第一电极条，所述第二电极层包括多个水平电场产生部，所述多个水平电场产生部的上表面与所述多个第一电极条的上表面平齐，并且在所述矩阵的行或列的方向上，所述多个第一电极条和所述多个水平电场产生部在所述衬底基板上的正投影相互交替。
优选地，所述阵列基板还包括多个绝缘条，所述多个绝缘条分别设置在所述多个水平电场产生部下方，以使得所述多个水平电场产生部的上表面与所述多个第一电极条的上表面平齐。
优选地，所述第二电极还包括多个连接部，每个所述连接部连接在相邻两个所述水平电场产生部之间，所述多个第一电极条分别位于所述多个连接部上方，且所述多个连接部和所述多个水平电场产生部在所述阵列基板的衬底基板上的投影共同形成矩形区域。
优选地，所述第二电极还包括多个连接部，每个所述连接部连接相邻两个所述水平电场产生部的同一侧端部。
优选地，所述阵列基板还包括绝缘层，所述绝缘层覆盖所述第二电极所在的层，所述第一电极形成在所述绝缘层上。
优选地，所述第一电极层为像素电极层，所述第二电极层为公共电极层。
作为本发明的另一个方面，提供一种显示装置，所述显示装置包括阵列基板，其中，所述阵列基板为本发明所提供的上述任意一种阵列基板。
作为本发明的还一个方面，提供一种阵列基板的制造方法，包括步骤：
形成第二电极层，其中所述第二电极层包括多个水平电场产生部；以及
形成第一电极层，所述第一电极层与所述第二电极层互相绝缘，所述第一电极层包括多个第一电极条，且所述多个第一电极条的上表面与所述多个水平电场产生部的上表面平齐，所述多个第一电极条与所述多个水平电场产生部在所述衬底基板上的正投影相互交替。
优选地，在所述形成第二电极层的步骤之前，所述制造方法还包括步骤：形成包括多个绝缘条的图形，所述多个绝缘条的位置对应于所述多个水平电场产生部的位置。
在所述形成第二电极层的步骤之后且在所述形成第一电极层的步骤之前，所述制造方法还包括步骤：
形成绝缘层，所述绝缘层覆盖形成有所述第二电极层的衬底基板。
优选地，在所述形成第二电极层的步骤中形成的第二电极层还包括多个连接部，每个所述连接部连接在相邻两个所述水平电场产生部之间，且所述多个连接部和所述多个水平电场产生部在所述衬底基板上的正投影共同形成矩形区域，并且在形成第一电极层的步骤中形成的所述多个第一电极条分别位于所述多个连接部的上方。
优选地，在所述形成第二电极层的步骤中形成的第二电极层还包括多个连接部，每个所述连接部连接相邻两个所述水平电场的同一侧端部。
由于第一电极条的上表面和水平电场产生部的上表面平齐，因此，当包括所述阵列基板的显示装置通电显示时，第一电极条和水平电场产生部之间形成的电场的水平分量较大，竖直分量较小。进一步可知，当包括所述阵列基板的显示装置在通电显示时，所述第一电极层中的第一电极和所述第二电极层中的第二电极之间的存储电容较小，从而缩短了对存储电容进行充电所需要的时间。由于第一电极条和水平电场产生部之间形成的电场的水平分量较大，因此，提供较小的驱动电压即可驱动液晶分子旋转。
因此，利用本发明所提供的阵列基板进行显示可以在不损失像素区整体透过率的前提下，降低每个像素单元的存储电容和驱动电压，并提高显示区透过率的均一性。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。在附图中：
图1是现有的FFS模式的液晶显示面板的结构示意图；
图2是本发明所提供的阵列基板的第一种实施方式的结构示意图；
图3是图2中所示的阵列基板中的第二电极俯视图；
图4是本发明所提供的阵列基板的第二种实施方式的结构示意图；
图5是图4中所示的阵列基板中的第二电极的俯视图；以及
图6(a)至图6(d)是制造图2中所示的阵列基板的过程示意图。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
作为本发明的一个方面，提供一种阵列基板，所述阵列基板包括衬底基板50、第一电极层和与该第一电极层互相绝缘的第二电极层，所述第一电极层包括呈矩阵排列的多个第一电极条40，所述第二电极层包括多个水平电场产生部21，所述多个水平电场产生部21的上表面与所述多个第一电极条40的上表面平齐，并且在所述矩阵的行或列的方向上，所述多个第一电极条40和所述多个水平电场产生部21在衬底基板50上的正投影相互交替。
需要指出的是，此处所用到的方位词“上”是指图2和图4中的“上”方。所谓的“多个水平电场产生部21的上表面与多个第一电极条40的上表面平齐”是指，各水平电场产生部21的上表面与各第一电极条40的上表面均位于同一平面上。此处所用到的“水平”是指图2和图4中的左、右方向，此处所用到的“竖直”是指图2和图4中的上、下方向。当然，本领域技术人员应当理解的是，此处的“平齐”并非是指严格的位于同一平面上，而是大致位于同一平面上即可，即，各水平电场产生部21的上表面距衬底基板50的上表面的距离与各第一电极条40的上表面距衬底基板50的上表面的距离之间的差值在工业生产可实现的范围内尽量的小。本领域技术人员容易理解的是，第一电极层和第二电极层中的一者为像素电极层，另一者为公共电极层。在本发明的具体实施方式中，以第一电极层为像素电极层，第二电极层为公共电极层为例进行说明。
由于各第一电极条40的上表面和各水平电场产生部21的上表面平齐，因此，当包括所述阵列基板的显示装置通电显示时，各第一 电极条40和相邻的水平电场产生部21之间形成的电场的水平分量较大，竖直分量较小。进一步可知，当包括所述阵列基板的显示装置在通电显示时，所述第一电极层和所述第二电极层之间的存储电容较小，从而缩短了对存储电容进行充电所需要的时间。由于各第一电极条40和相邻的水平电场产生部21之间形成的电场的水平分量较大，因此，只需提供较小的驱动电压Vop即可驱动液晶分子旋转。
因此，利用本发明所提供的阵列基板进行显示可以在不损失像素区整体透过率的前提下，降低每个像素单元的存储电容和驱动电压Vop。可以理解的是，在本发明中，每个像素单元内的第一电极条40和水平电场产生部21均具有上文中所描述的结构，而且各第一电极条40和相邻的水平电场产生部21之间形成的电场的水平分量较大，因此每个像素单元内产生的电场的水平分量均较大，所以，每个像素单元中产生的电场对液晶分子的驱动力也相应较大，可以使得每个像素单元对应的液晶分子都可靠地偏转，从而提高了显示区透过率的均一性。
在本发明中，对第一电极条40和水平电场产生部21的厚度没有特别限制，只要各水平电场产生部21的上表面与各第一电极条40的上表面平齐即可。例如，可以增加各水平电场产生部21的厚度，以使得各水平电场产生部21的上表面与各第一电极条40的上表面平齐。
作为本发明的一种优选实施方式，所述阵列基板还可以包括多个绝缘条10，多个绝缘条10分别设置在多个水平电场产生部21下方，以使得所述多个水平电场产生部21的上表面与所述多个第一电极条40的上表面平齐。为了使第一电极层和第二电极层之间相互绝缘，所述阵列基板还可以包括绝缘层30，该绝缘层30覆盖所述第二电极层，并且所述第一电极层形成在绝缘层30上。
作为本发明的第一种具体实施方式，所述第二电极层具有图2和图3中所示的结构。如图3中所示，所述第二电极层还包括多个连接部22，每个所述连接部22连接相邻两个水平电场产生部21的同一侧端部。
作为本发明的第二种具体实施方式，所述第二电极层具有图4所 示的结构。如图4中所示，所述第二电极层还包括多个连接部22，每个连接部22连接在相邻两个水平电场产生部21之间，所述多个第一电极条40分别位于所述多个连接部22上方。此处用到的方位词“上方”是指图4中的“上”方。在这种实施方式中，多个水平电场产生部21和多个连接部22在衬底基板50上的正投影共同形成如图5所示的矩形区域。
需要说明的是，本发明对多个第一电极形成的矩阵的行和列并没有具体限定，例如，通过旋转90度，“行”即为“列”。可以理解的是，当第二电极具有如图3或图5所示的结构时，水平电场产生部21和第一电极条40在图2或图4的横向方向上交替，而在另一方向(垂直于纸面的方向，或水平电场产生部21的延伸方向)上，则只布置有水平电场产生部21或电极条40。
此外，本发明对水平电场产生部21的具体结构不进行具体限定，只要能够确保各电场产生部21能够连接在一起，从而保证公共电极信号的稳定输入即可。
本领域技术人员应当理解的是，为了实现正常的显示，所述阵列基板还包括栅线、数据线、薄膜晶体管等结构。这些结构的设置是本领域人员所公知的，故本发明中并未对其进行详细描述。
当所述阵列基板中的薄膜晶体管具有底栅结构时，衬底基板50可以包括透明基板、形成在透明基板上的栅线层、形成在栅线层上的栅绝缘层、形成在所述栅绝缘层上的有源区层、形成在有源区层上的源漏电极层和形成在所述源漏电极层上的平坦化层。绝缘条10可以形成在所述平坦化层上(图中未示出)。
可以理解的是，所述第一电极层包括多个像素单元的第一电极，所述第二电极层包括多个像素单元的第二电极；所述栅线层包括栅线、公共电极线、栅极等；所述有源区层包括多个薄膜晶体管的有源区；所述源漏电极层包括多个薄膜晶体管的源极和漏极。第一电极可以为像素电极，第二电极可以为公共电极。为了实现液晶分子的初始取向，所述阵列基板上还可以形成有取向膜60，如图2和图4中所示。取向膜60覆盖在形成有第一电极层和第二电极层的衬底基板50上。
作为本发明的另一个方面，提供一种显示装置，所述显示装置包括阵列基板，其中，所述阵列基板为本发明所提供的上述任意一种阵列基板。
由于所述显示装置包括本发明所提供的上述任意一种阵列基板，因此，在进行显示时，所述显示装置具有较小的存储电容，并且需要较小的操作电压。
容易理解的是，所述显示装置还可以包括用于与所述阵列基板对盒设置的对盒基板。所述对盒基板与所述阵列基板之间填充有液晶材料。所述对盒基板可以是彩膜基板。
与图1中所示的现有技术相比，在利用包括图2中所示的阵列基板的显示装置进行显示时，存储电容降低了79.8％，操作电压降低了0.3V，大大降低了充电所需要的时间，并且降低了显示装置的总体能耗。此外，像素区最大透过率的波动范围由0.0184降低到0.0139，由此可知，包括图2中所示的阵列基板的显示装置的显示区透过率的均一性得到了提高。在利用包括图4中所示的阵列基板的显示装置进行显示时，存储电容降低了1.5％，操作电压降低了0.3V，也在一定程度上降低了充电所需要的时间，并且降低了显示装置的总体能耗。此外，像素区最大透过率的波动范围由0.0184降低到0.0146，由此可知，包括图4中所示的阵列基板的显示装置的显示区透过率的均一性得到了提高。
本发明所提供的显示装置可以为手机、平板电脑、电脑显示器、电视机、导航仪、电子相框等电子设备。
作为本发明的又一个方面，提供上述阵列基板的制造方法，所述阵列基板的制造方法包括步骤：
形成第二电极层，其中，所述第二电极层包括多个水平电场产生部21(参见图6(b))；以及
形成第一电极层，所述第一电极层与所述第二电极层互相绝缘，所述第一电极层包括多个第一电极条40，且多个第一电极条40的上表面与多个水平电场产生部21的上表面平齐(参见图6(d))，并且多个第一电极条40与多个水平电场产生部21在衬底基板50上的正投影相 互交替。
在本发明中，对形成第二电极层的具体方法没有特殊的限制。例如，可以利用传统的光刻构图工艺形成包括多个水平电场产生部21的第二电极层，也可以利用掩模蒸镀等方法形成包括多个水平电场产生部21的第二电极层。
同样地，在本发明中，对形成第一电极层的具体方法也不做特殊限制。例如，可以利用传统的光刻构图工艺形成包括多个第一电极条40的第一电极层，也可以利用掩模蒸镀等方法形成包括多个第一电极条40的第一电极层。
为了实现各第一电极条40的上表面与各水平电场产生部21的上表面互相平齐，优选地，在所述形成第二电极层的步骤之前，所述制造方法还包括步骤：形成包括多个绝缘条10的图形，多个绝缘条10的位置分别对应于多个水平电场产生部21(参见图6(b))的位置。容易理解的是，绝缘条10的数量以及形状与水平电场产生部21的数量和形状均相同。通过在各水平电场产生部21对应的位置形成各绝缘条10可以增加各水平电场产生部21距离衬底基板50的上表面的高度，从而有助于使得之后形成的各第一电极条40的上表面与各水平电场产生部21的上表面均平齐。在本发明中，可以利用硅的氧化物(SiOx)或硅的氮化物(SiNx)制成所述绝缘条10，也可以用有机树脂材料制成所述绝缘条10。
在本发明中，对形成绝缘条10的具体工艺并没有特殊的限制。例如，可以利用传统的光刻工艺在衬底基板50上形成包括多个绝缘条10的图形。
具体地，形成包括多个绝缘条10的图形的步骤可以具体包括：
在平坦化层上形成一层绝缘材料层；
在所述绝缘材料层上涂覆一层光刻胶层；
利用掩膜板对所述光刻胶层进行曝光显影；以及
以曝光显影后的光刻胶层为掩膜对所述绝缘材料层进行干刻或湿刻，以形成包括多个绝缘条10的图形。
为了实现所述第一电极层和所述第二电极层之间的互相绝缘，优 选地，所述制造方法还可以包括在所述形成第二电极层的步骤之后且在所述形成第一电极层的步骤之前进行的步骤：
形成绝缘层30，该绝缘层30覆盖形成有所述第二电极层的衬底基板50(如图6(c)所示)。
绝缘层30可以由硅的氧化物(SiOx)或硅的氮化物(SiNx)制成。可以利用蒸镀或者化学气相沉积的方法在形成有第二电极层的衬底基板50上形成绝缘层30。
相应地，包括多个第一电极条40的所述第一电极层形成在绝缘层30上(如图6(d)所示)。
所述制造方法还包括在所述形成包括多个第一电极条40的图形的步骤之后进行的步骤：
形成取向层。
所述取向层的作用是使得液晶分子具有预倾角。在本发明中，可以利用树脂材料形成所述取向层。具体地，形成取向层的步骤包括：
在形成有所述第一电极的衬底基板上涂敷树脂层；以及
利用摩擦法获得所述取向层。
作为本发明的第一种具体实施方式，所述第二电极层具有图2和图3中所示的结构。如图3中所示，所述第二电极层还包括多个连接部22，每个连接部22连接相邻两个水平电场产生部21的同一侧端部。
作为本发明的第二种具体实施方式，所述第二电极层具有图4所示的结构。如图4所示，所述第二电极层还包括多个连接部22，每个连接部22连接在相邻两个水平电场产生部21之间，多个第一电极条40分别位于多个连接部22上方。在这种实施方式中，所述多个水平电场产生部21和所述多个连接部22在衬底基板50上的正投影共同形成如图5所示的矩形区域。
本领域技术人员可以理解的是，形成图3所示的第二电极层和形成图5所示的第二电极层时所用到的掩膜板的图案不同。
在本发明中，利用透明电极材料(如，ITO)分别形成所述第一电极层和所述第二电极层。
如上文中所述，所述衬底基板上还形成有栅线、数据线、薄膜 晶体管等其他元件。当所述薄膜晶体管具有底栅结构时，所述制造方法包括在形成包括多个绝缘条的图形的步骤之前进行的步骤：
在透明基板上形成栅线层；
在栅线层上形成栅绝缘层；
在栅绝缘层上形成有源区层；
在有源区层上形成源漏电极层；以及
在源漏电极层上形成平坦化层。
可以理解的是，第一电极层包括多个像素单元的第一电极，第二电极层包括多个像素单元的第二电极；所述栅线层包括栅线、公共电极线、栅极等；所述有源区层包括多个薄膜晶体管的有源区；所述源漏电极层包括多个薄膜晶体管的源极和漏极。
所述第一电极可以为像素电极，所述第二电极可以为公共电极。因此，所述第一电极可以通过过孔与所述源漏电极层中的漏极相连，所述第二电极可以通过过孔与位于所述栅线层中的公共电极线相连。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (12)

  1. 一种阵列基板，包括衬底基板、第一电极层和与所述第一电极层互相绝缘的第二电极层，所述第一电极层包括呈矩阵排列的多个第一电极条，其特征在于，所述第二电极层包括多个水平电场产生部，所述多个水平电场产生部的上表面与所述多个第一电极条的上表面平齐，并且在所述矩阵的行或列的方向上，所述多个第一电极条和所述多个水平电场产生部在所述衬底基板上的正投影相互交替。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述阵列基板还包括多个绝缘条，所述多个绝缘条分别设置在所述多个水平电场产生部下方，以使得所述多个水平电场产生部的上表面与所述多个第一电极条的上表面平齐。
  3. 根据权利要求2所述的阵列基板，其特征在于，所述第二电极层还包括多个连接部，每个所述连接部连接在相邻两个所述水平电场产生部之间，所述多个第一电极条分别位于所述多个连接部上方，且所述多个连接部和所述多个水平电场产生部在所述衬底基板上的正投影共同形成矩形区域。
  4. 根据权利要求2所述的阵列基板，其特征在于，所述第二电极层还包括多个连接部，每个所述连接部连接相邻两个所述水平电场产生部的同一侧端部。
  5. 根据权利要求1至4中任意一项所述的阵列基板，其特征在于，所述阵列基板还包括绝缘层，所述绝缘层覆盖所述第二电极层，所述第一电极层形成在所述绝缘层上。
  6. 根据权利要求1至5中任意一项所述的阵列基板，其特征在于，所述第一电极层为像素电极层，所述第二电极层为公共电极层。
  7. 一种显示装置，包括阵列基板，其特征在于，所述阵列基板为权利要求1至6中任意一项所述的阵列基板。
  8. 一种阵列基板的制造方法，其特征在于，包括步骤：
    形成第二电极层，其中所述第二电极层包括多个水平电场产生部；以及
    形成第一电极层，所述第一电极层与所述第二电极层互相绝缘，所述第一电极层包括多个第一电极条，且所述多个第一电极条的上表面与所述多个水平电场产生部的上表面平齐，所述多个第一电极条与所述多个水平电场产生部在所述衬底基板上的正投影相互交替。
  9. 根据权利要求8所述的制造方法，其特征在于，在所述形成第二电极层的步骤之前，所述制造方法还包括步骤：
    形成包括多个绝缘条的图形，所述多个绝缘条的位置对应于所述多个水平电场产生部的位置。
  10. 根据权利要求8或9所述的制造方法，其特征在于，在所述形成第二电极层的步骤之后且在所述形成第一电极层的步骤之前，所述制造方法还包括步骤：
    形成绝缘层，所述绝缘层覆盖形成有所述第二电极层的衬底基板。
  11. 根据权利要求8-10中任一项所述的制造方法，其特征在于，在所述形成第二电极层的步骤中形成的第二电极层还包括多个连接部，每个所述连接部连接在相邻两个所述水平电场产生部之间，且所述多个连接部和所述多个水平电场产生部在所述阵列基板的衬底基板上的正投影共同形成矩形区域，并且在形成第一电极层的步骤中形成的所述多个第一电极条分别位于所述多个连接部的上方。
  12. 根据权利要求8-10中任一项所述的制造方法，其特征在于， 在所述形成第二电极层的步骤中形成的第二电极层还包括多个连接部，每个所述连接部连接相邻两个所述水平电场的同一侧端部。
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