WO2016107099A1 - 一种薄膜晶体管及电路结构 - Google Patents

一种薄膜晶体管及电路结构 Download PDF

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WO2016107099A1
WO2016107099A1 PCT/CN2015/081891 CN2015081891W WO2016107099A1 WO 2016107099 A1 WO2016107099 A1 WO 2016107099A1 CN 2015081891 W CN2015081891 W CN 2015081891W WO 2016107099 A1 WO2016107099 A1 WO 2016107099A1
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Prior art keywords
comb
thin film
comb teeth
film transistor
teeth
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PCT/CN2015/081891
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English (en)
French (fr)
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王孝林
姚星
严允晟
韩承佑
林允植
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京东方科技集团股份有限公司
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Priority to US14/900,960 priority Critical patent/US9793300B2/en
Publication of WO2016107099A1 publication Critical patent/WO2016107099A1/zh

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00

Definitions

  • the present disclosure relates to semiconductor devices, particularly a thin film transistor and circuit structure.
  • the existing TFT Thin Film Transistor
  • the existing TFT is one of the types of field effect transistors and has a wide range of applications.
  • the TFT includes a gate, a gate insulating layer, a semiconductor layer, a source electrode, and a drain electrode, and the like, which adjusts the conductivity of the channel layer by changing the voltage applied to the gate, thereby controlling the source electrode and the drain electrode. Between or off.
  • the threshold voltage determines the magnitude of the voltage applied to the gate.
  • the TFT when used as a switching transistor, the drift of its threshold voltage will cause it to fail to achieve accurate switching between the source and drain electrodes.
  • a change in the threshold voltage of a TFT as a driving transistor affects the brightness uniformity of the OLED, thereby affecting the display effect of the AMOLED panel.
  • the drift of the threshold voltage of the TFT affects the normal operation of the circuit structure.
  • an embodiment of the present disclosure provides a thin film transistor including: a gate electrode, a semiconductor layer, an etch barrier layer, and source and drain electrodes connected to the semiconductor layer, the thin film transistor further comprising:
  • a blocking structure disposed on the etch barrier layer
  • the blocking structure is electrically isolated from the source electrode and the drain electrode, and an orthographic projection of the blocking structure on the etch barrier layer and an orthographic projection of the semiconductor layer on the etch barrier layer at least partially overlap .
  • an orthographic projection of the blocking structure on the etch barrier layer is located in a region where an orthographic projection of the semiconductor layer on the etch barrier layer is located.
  • the barrier structure and the source and drain electrodes are formed by a single etching process.
  • the W /D is between 1/20-18/20.
  • the source electrode and the drain electrode are interposed plug-like structures, and the inserted comb teeth are divided into a plurality of comb-tooth groups, and the interval between adjacent comb-tooth groups is larger than that in the comb-tooth group
  • the distance between adjacent comb teeth, the blocking structure is located between the adjacent comb teeth as the source electrode and the comb teeth as the drain electrode, adjacent to but different comb teeth or combo
  • the source electrode and the drain electrode are interposed plug-like structures, wherein at least one pair of adjacent comb teeth as source electrodes are provided with two comb teeth as drain electrodes, the blocking The structure is located between adjacent comb teeth as source electrodes and comb teeth as drain electrodes.
  • drain electrode comprises:
  • the source electrode includes:
  • the barrier structure is located between adjacent comb teeth as source electrodes and comb teeth as drain electrodes.
  • the second comb handle and the third comb handle are U-shaped; the first comb handle, the third comb sequence and the fourth comb sequence are located in the U a type inside; the third comb sequence and the fourth comb sequence are located on both sides of the first comb.
  • the first comb sequence and the third comb sequence are located between the first comb and the second comb; the second comb sequence and the second A four comb sequence is located between the first comb handle and the third comb handle.
  • an embodiment of the present disclosure further provides a circuit structure including a thin film transistor including: a gate, a semiconductor layer, an etch barrier layer, and a source connected to the semiconductor layer An electrode and a drain electrode, the thin film transistor further comprising:
  • a blocking structure disposed on the etch barrier layer
  • the blocking structure is electrically isolated from the source electrode and the drain electrode, and an orthographic projection of the blocking structure on the etch barrier layer and an orthographic projection of the semiconductor layer on the etch barrier layer at least partially overlap .
  • an orthographic projection of the blocking structure on the etch barrier layer is located in a region where an orthographic projection of the semiconductor layer on the etch barrier layer is located.
  • the above circuit structure wherein the barrier structure and the source and drain electrodes are formed by a single etching process.
  • the source electrode and the drain electrode are inserted comb structures, and the inserted comb teeth are divided into a plurality of comb groups, and the distance between adjacent comb groups is larger than the comb group
  • the distance between adjacent comb teeth, the blocking structure is located adjacent to the comb teeth as the source electrode and as the drain electrode.
  • the comb teeth adjacent to each other but belonging to different comb tooth groups are either comb teeth as the drain electrode or comb teeth as the source electrode at the same time.
  • the above circuit structure wherein the source electrode and the drain electrode are interposed plug-like structures, wherein at least one pair of adjacent comb teeth as source electrodes are provided with two comb teeth as drain electrodes, the blocking The structure is located between adjacent comb teeth as source electrodes and comb teeth as drain electrodes.
  • circuit structure further comprises a capacitor structure, the capacitor structure comprising a first plate and a second plate formed by a gate of the thin film transistor, the first plate and the The source and drain electrodes of the thin film transistor are disposed in the same layer and are connected to the drain electrode of the thin film transistor.
  • the circuit structure is a shift register unit, the source-drain electrodes of the thin film transistor are respectively connected to a signal input node and an output node, the gate is connected to the pull-up node, and one end of the capacitor structure is connected to The node is pulled high and the other end is connected to the output node.
  • the drain electrode includes:
  • a first comb handle electrically connected to the first plate
  • the source electrode includes:
  • the barrier structure is located between adjacent comb teeth as source electrodes and comb teeth as drain electrodes.
  • the above circuit structure wherein the inserted comb teeth of at least one side of the first comb handle are divided into a plurality of comb teeth groups, and the spacing distance between adjacent comb tooth groups is greater than the adjacent ones in the comb tooth group The distance between the comb teeth, the comb teeth adjacent to each other but belonging to different comb tooth groups or the comb teeth as the drain electrode, or the comb teeth as the source electrode at the same time.
  • the first comb handle is further provided with an extension extending to a gap between the adjacent comb groups, and the active layer below the extension is removed.
  • the embodiment of the present disclosure further provides a thin film transistor including: a source electrode and a drain electrode,
  • the drain electrode includes:
  • the source electrode includes:
  • the interposing comb teeth of at least one side of the first comb handle are divided into a plurality of comb tooth groups, and the spacing distance between adjacent comb tooth groups is larger than the adjacent ones in the comb tooth group The distance between the comb teeth, the comb teeth adjacent to each other but belonging to different comb tooth groups or the comb teeth as the drain electrode, or the comb teeth as the source electrode at the same time.
  • a barrier structure on the etch barrier layer is formed, which improves the drift characteristic of the threshold voltage of the thin film transistor and improves Device performance.
  • FIG. 1 is a schematic structural view of a thin film transistor of an embodiment of the present disclosure
  • FIG. 2 is a view showing the structure of a thin film transistor provided with a via hole according to an embodiment of the present disclosure
  • FIG. 3 is a graph showing a test curve of a gate voltage Vg of a thin film transistor of the prior art and a current Ids between source and drain electrodes;
  • FIG. 5 is a view showing a pair of plug-and-loop structures of source and drain electrodes in a thin film transistor according to an embodiment of the present disclosure
  • FIG. 6 is a view showing another pair of insertion comb-like structures of source and drain electrodes in a thin film transistor according to an embodiment of the present disclosure
  • Fig. 7 shows still another pair of plug-and-loop structures of source and drain electrodes in the thin film transistor of the embodiment of the present disclosure.
  • a barrier structure on the etch barrier layer is formed, which improves the drift characteristic of the threshold voltage of the thin film transistor and improves Device performance.
  • the thin film transistor of the embodiment of the present disclosure includes a gate electrode, a semiconductor layer 101, an etch barrier layer, and a source electrode 102 and a drain electrode 103 connected to the semiconductor layer 101, wherein the thin film transistor A barrier structure 104 disposed on the etch stop layer is also included.
  • the blocking structure 104 is electrically isolated from the source electrode 102 and the drain electrode 103, and an orthographic projection of the blocking structure 104 on the etch barrier layer and the semiconductor layer 101 on the etch barrier layer The orthographic projections at least partially overlap.
  • the source and drain metal layers between the source and drain electrodes of the thin film transistor should be removed, which is a long-standing technical bias in the field of TFT fabrication.
  • the thin film transistor and the circuit structure of the embodiment of the present disclosure by overcoming the above-mentioned technical prejudice, by retaining a portion of the source/drain metal layer that is originally required to be removed, a barrier structure on the etch barrier layer is formed, and the thin film transistor is improved.
  • the drift characteristics of the threshold voltage improve device performance.
  • the orthographic projection of the blocking structure on the etch barrier layer and the orthographic projection of the semiconductor layer 101 on the etch barrier layer at least partially overlap:
  • the orthographic projection of the blocking structure 104 on the etch stop layer and the orthographic projection of the semiconductor layer 101 on the etch stop layer completely overlap, that is, the blocking structure 104 is in the etch
  • An orthographic projection on the barrier layer is located in the region of the semiconductor layer 101 where the orthographic projection of the semiconductor layer 101 is on the etch stop layer.
  • the above-described blocking structure 104 may be formed by a separate etching process, but in order to simplify the process flow and reduce the cost, in the specific embodiment of the present disclosure, the above-described blocking structure 104 and the The source electrode 102 and the drain electrode 103 are formed by one etching process.
  • D6 D9
  • D7 D10
  • L is the distance between the adjacent sides of the via 105 on the source electrode 102 and the drain electrode 103, namely:
  • the voltage difference between the source and drain electrodes is 9.1V;
  • Light source 10000 nits
  • the aspect ratio is 25:24;
  • the thin film transistor of the embodiment of the present disclosure is mainly more than the barrier structure 104 shown in FIG. 2 with respect to the transistor of the prior art, and the other portions are the same.
  • the gate voltage of the current Ids between the source and drain electrodes reaches 10 -8 A is about 0.4 V
  • the current between the source and drain electrodes is made.
  • the gate voltage of Ids reaching 10 -8 is about -1.5V
  • the gate voltage of the current Ids between the source and drain electrodes reaches 10 -8 A is about -2.2V, that is, After 600 seconds of operation, the threshold voltage drift of the prior art thin film transistor reaches about 1.9V (the difference between 0.4V and -1.5V), and after 1200 seconds of operation, the threshold voltage drifts to 2.6V (0.4V and -2.2V difference).
  • the gate voltage of the current Ids between the source and drain electrodes reaches 10 -8 A is about 1.2 V
  • the current between the source and drain electrodes is made.
  • the gate voltage of Ids reaching 10 -8 A is about 1V
  • the gate voltage of the current Ids between the source and drain electrodes reaches 10 -8 A is about 0.75V, that is, the present disclosure.
  • the TFT of the embodiment has a threshold voltage drift of about 0.2 V (1.2 V to 1 V difference) after 600 seconds of operation, and after 1200 seconds of operation, the threshold voltage drifts to 0.45 V (1.2 V and 0.75 V). Difference).
  • the threshold voltage drift of the thin film transistor of the embodiment of the present disclosure after operation for 600 seconds and 1200 seconds is 0.2V and 0.45V, respectively, compared with 1.9V and 2.6V after 600 seconds and 1200 seconds of operation of the thin film transistor of the prior art.
  • the threshold voltage drift is greatly reduced.
  • the threshold voltage is in the positive voltage range.
  • the threshold voltages of the prior art thin film transistors after operation for 600 seconds and 1200 seconds are -1.5 V and -2.2 V, respectively. At this time, even if the gate does not apply an electrical signal (ie, the gate voltage is 0), the source and drain electrodes The current Ids between the electrodes is also greater than 10 -8 A, which results in abnormal conduction of the thin film transistor.
  • the threshold voltages of the thin film transistors of the embodiments of the present disclosure are 1 V and 0.75 V after 600 seconds and 1200 seconds, respectively. At this time, when the gate does not apply an electrical signal (ie, the gate voltage is 0), the source and drain electrodes are The current Ids is much smaller than 10 -8 A, that is, the thin film transistor is in a normal off state.
  • the lengths of the perpendicular sides of the opposite parallel sides of the source electrode 102 and the drain electrode 103 are D (ie, D2+D3+D4), and the blocking structure 104 is parallel to the perpendicular line.
  • the width in the direction is W (ie D3).
  • the W/D is 5/16, but in the specific embodiment of the present disclosure, the threshold voltage drift can be reduced when the W/D is between 1/20 and 18/20.
  • the source electrode 102 and the drain electrode 103 are interposed plug-like structures, and the inserted comb teeth are divided into a plurality of comb-tooth groups 201, and a first spacer 501 between adjacent comb-tooth groups 201
  • the width is greater than the distance between adjacent comb teeth in the comb set 201, the blocking structure (not shown) being located between the adjacent comb teeth as the source electrode 102 and the comb teeth as the drain electrode 103.
  • the comb teeth adjacent to each other but belonging to different comb groups are either comb teeth as drain electrodes or comb teeth as source electrodes at the same time.
  • the aspect ratio W/L that is closely related to its electrical performance is predetermined.
  • the currents passing through the source and drain electrodes are also substantially the same under the same voltage driving conditions, so the heat generation is the same.
  • the heat dissipation performance of TFTs of different shapes is different.
  • the heat generated in the comb tooth group 201 can pass through the area.
  • the large first spacer 501 is emitted to improve the heat dissipation performance of the TFT device.
  • the first spacing between adjacent comb groups 201 is due to adjacent comb teeth belonging to different comb groups 201 or comb teeth as drain electrodes 103, or comb teeth as source electrodes 102 at the same time.
  • No current is generated in the region 501 (or the current is small), the heat dissipation capability of the first spacer 501 is improved, and the heat dissipation performance of the TFT device is further improved.
  • heat is dissipated through the first spacer 501 between the comb groups 201, and the heat dissipation performance of the TFT device is improved.
  • the second spacer 601 located inside the comb set 201 is used for heat dissipation.
  • the source electrode 102 and the drain electrode 103 are interposed comb structures, wherein at least one pair of adjacent comb teeth as the source electrodes 102 are provided with two comb teeth as the drain electrodes 103.
  • the blocking structure 104 is located between adjacent comb teeth as the source electrode 102 and comb teeth as the drain electrode 103.
  • the inserted comb teeth are divided into a plurality of comb tooth groups 201, and the comb teeth group 201 has the comb teeth adjacent to the drain electrode 103 at the same time, the same as the leakage current No current is generated between the comb teeth of the pole 103 (or the current is small), so that the second spacer 601 between adjacent comb teeth of the drain electrode 103 can achieve better heat dissipation effect and improve heat dissipation of the TFT. performance.
  • FIGS. 5 and 6 may be used alone or in combination.
  • the comb teeth of the TFT of the embodiment of the present disclosure as the source electrode 102 and
  • the comb teeth of the drain electrode 103 may be in a plurality of rows to further improve heat dissipation performance.
  • the drain electrode includes:
  • first comb tooth sequence and a second comb tooth sequence distributed on both sides of the first comb handle 701 and electrically connected to the first comb handle 701;
  • the source electrode includes:
  • a third comb handle 703 electrically connected to the second comb handle
  • the blocking structure (not shown) is located between adjacent comb teeth as the source electrode 102 and comb teeth as the drain electrode 103.
  • the comb teeth as the drain electrode 103 are arranged in two rows and are located in the TFT.
  • the first comb handle 701 of the portion can bear a better heat dissipating effect, and has a better heat dissipating effect than the prior art peripheral heat dissipating manner.
  • the arrangement of the comb groups shown in FIG. 5 and FIG. 6 can also be applied to the comb-tooth sequence of any one of the rows in FIG. 7 to improve the heat dissipation performance of the TFT shown in FIG.
  • the thin film transistor of the embodiment of the present disclosure may be used in various circuit structures, wherein the thin film transistor includes a gate electrode, a semiconductor layer 101, an etch barrier layer, and a connection with the semiconductor layer 101, as shown in FIG. a source electrode 102 and a drain electrode 103; the thin film transistor further includes:
  • a blocking structure 104 disposed on the etch barrier layer
  • the blocking structure 104 is electrically isolated from the source electrode 102 and the drain electrode 103, and an orthographic projection of the blocking structure 104 on the etch barrier layer and the semiconductor layer 101 on the etch barrier layer The orthographic projections at least partially overlap.
  • the orthographic projection of the blocking structure 104 on the etch barrier layer is located in a region where the orthographic projection of the semiconductor layer 101 on the etch barrier layer is located.
  • the blocking structure 104 may be formed by the one-time etching process with the source electrode 102 and the drain electrode 103.
  • the length of the perpendicular line of the opposite parallel sides of the source electrode 102 and the drain electrode 103 is D, and the width of the blocking structure 104 in the direction parallel to the perpendicular line is W, and the W/D is 1
  • the drift of the threshold voltage can be reduced between /20-18/20.
  • the source electrode 102 and the drain electrode 103 may be a paired comb structure, and the inserted comb teeth are divided into a plurality of comb groups 201, and the first interval between adjacent comb groups 201 is The width of the zone is greater than the distance between adjacent comb teeth in the comb set 201, which is located between the adjacent comb teeth as the source electrode 102 and the comb teeth as the drain electrode 103, adjacent but adjacent
  • the comb teeth of the different comb groups are either comb teeth as drain electrodes or comb teeth as source electrodes at the same time.
  • the heat generated in the comb group 201 can be dissipated through the first spacer 501 having a larger area, which improves the heat dissipation performance of the TFT device.
  • the first spacing between adjacent comb groups 201 is due to adjacent comb teeth belonging to different comb groups 201 or comb teeth as drain electrodes 103, or comb teeth as source electrodes 102 at the same time. No current is generated in the region 501 (or the current is small), the heat dissipation capability of the first spacer 501 is improved, and the heat dissipation performance of the TFT device is further improved.
  • the source electrode 102 and the drain electrode 103 are interposed plug-like structures, wherein at least one pair of adjacent comb teeth as the source electrode 102 are disposed between two The comb teeth of the drain electrode 103 are located between adjacent comb teeth as the source electrode 102 and comb teeth as the drain electrode 103.
  • the second spacer 601 between adjacent comb teeth can achieve better heat dissipation effect and improve the heat dissipation performance of the TFT.
  • a capacitor structure for use with a TFT when the circuit structure further includes a capacitor structure, and the capacitor structure includes a first plate and a thin film transistor a second plate formed by the gate, the first plate being disposed in the same layer as the source and drain electrodes of the thin film transistor, and connected to the drain electrode of the thin film transistor.
  • a typical structure of the above circuit structure is a shift register unit in a gate driving circuit, the source and drain electrodes of the thin film transistor are respectively connected to a signal input node and an output node, and the gate is connected to a pull-up node, the capacitor One end of the structure is connected to the pull-up node and the other end is connected to the output node.
  • the drain electrode includes:
  • first comb tooth sequence and a second comb tooth sequence distributed on both sides of the first comb handle 701 and electrically connected to the first comb handle 701;
  • the source electrode includes:
  • a third comb-tooth sequence electrically connected to the second comb handle 702 on one side of the second comb handle 702, and the first comb-tooth sequence being interposed;
  • the third comb handle 703 is electrically connected to the second comb handle 702;
  • a fourth comb tooth sequence electrically connected to the third comb handle 703 on one side of the third comb handle 703, and the second comb tooth sequence being interposed;
  • the blocking structure 104 is located between adjacent comb teeth as the source electrode 102 and comb teeth as the drain electrode 103.
  • the inserted comb teeth of at least one side of the first comb handle are divided into a plurality of comb groups, and the adjacent comb groups are The width of the first spacer is larger than the distance between adjacent comb teeth in the comb group, and the adjacent comb teeth belonging to different comb groups are either comb teeth as drain electrodes or as source electrodes at the same time. Comb teeth.
  • the inserted comb teeth are divided into a plurality of comb teeth groups, and the spacing distance between the comb tooth groups is large, the heat generated in the comb tooth groups can be dissipated through the first interval area having a larger area, thereby improving the TFT device. Thermal performance.
  • the adjacent comb teeth belonging to different comb groups or the comb teeth as the drain electrode, or the comb teeth as the source electrode there is no current in the first space between adjacent comb groups.
  • the generation (or the current is small) improves the heat dissipation capability of the first spacer region, and further improves the heat dissipation performance of the TFT device.
  • the active layer is characterized in that when the gate is applied with an electrical signal whose voltage value exceeds a threshold voltage, the active layer becomes a conductor, and when the gate is applied with a voltage value When an electrical signal is lower than the threshold voltage, the active layer becomes an insulator.
  • the capacitor structure includes a first plate and a second plate formed by a gate of the thin film transistor, and the first plate is in the same layer as the source and drain electrodes of the thin film transistor. Provided and connected to a drain electrode of the thin film transistor. If an active layer exists between the first plate and the second plate, a change in the properties of the active layer causes a change in the distance between the plates of the capacitor structure, thereby causing a change in capacitance, affecting the shift register unit. The normal work.
  • the active layer under the first comb handle is removed.
  • the first comb handle is further provided with an extension extending to a gap between adjacent comb groups. The active layer under the extension is removed.
  • the embodiment of the present disclosure further provides a thin film transistor including: a source electrode and a drain electrode, as shown in FIG. 7, the drain electrode includes:
  • first comb tooth sequence and a second comb tooth sequence distributed on both sides of the first comb handle 701 and electrically connected to the first comb handle 701;
  • the source electrode includes:
  • a third comb handle 703 electrically connected to the second comb handle
  • a fourth comb sequence electrically connected to the third comb is interposed with the second comb sequence.
  • the above thin film transistor structure is different from the existing thin film transistor structure, and the first comb handle 701 as a part of the drain electrode is located inside the entire thin film transistor, so that the entire thin film transistor can be generated from the center by the first comb handle 701 for the thin film transistor.
  • the heat is dissipated, which increases the heat dissipation capability of the thin film transistor.
  • the inserted comb teeth of at least one side of the first comb handle are divided into a plurality of comb groups, and the width of the first spacer between the adjacent comb groups is larger than the inner phase of the comb group.

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Abstract

公开了一种薄膜晶体管及电路结构。薄膜晶体管，包括：栅极、半导体层（101）、刻蚀阻挡层以及和半导体层连接的源电极（102）和漏电极（103），薄膜晶体管还包括：设置于刻蚀阻挡层上的阻挡结构（104）；阻挡结构与源电极、漏电极电隔离，且阻挡结构在刻蚀阻挡层上的正投影和半导体层在刻蚀阻挡层上的正投影至少部分重叠。改善了薄膜晶体管的阈值电压的漂移特性。

Description

一种薄膜晶体管及电路结构
相关申请的交叉引用
本申请主张在2014年12月31日在中国提交的中国专利申请号No.201410855068.8的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及半导体器件，特别是一种薄膜晶体管及电路结构。
背景技术
现有的TFT(Thin Film Transistor，薄膜晶体管)是场效应晶体管的种类之一，具有广泛的应用。
一般而言，TFT包括栅极、栅绝缘层、半导体层、源电极及漏电极等部分，它通过改变施加在栅极上的电压来调节沟道层的导电性，进而控制源电极与漏电极之间的导通或截止。
对于N型TFT而言，当加在栅极上的电压大于阈值电压时，源电极与漏电极之间导通，反之源电极与漏电极截止。而P型TFT则相反，即：当加在栅极上的电压小于阈值电压时，源电极与漏电极之间导通，反之源电极与漏电极截止。因此，阈值电压决定了施加到栅极上的电压的大小。
因此，当TFT作为开关管使用时，其阈值电压的漂移将会导致其无法实现准确的源电极与漏电极的导通和截止的切换。
又如AMOLED(Active Matrix Organic Light Emitting Diode，有源矩阵有机发光二极管)像素电路中，作为驱动晶体管的TFT的阈值电压的变化会影响OLED的亮度均一性，进而影响AMOLED面板的显示效果。
因此，不管TFT使用于何种电路结构，TFT的阈值电压的漂移都会影响电路结构的正常工作。
发明内容
本公开实施例的目的在于提供一种薄膜晶体管及电路结构，改善薄膜晶 体管的阈值电压的漂移特性。
为了实现上述目的，本公开实施例提供了一种薄膜晶体管，包括：栅极、半导体层、刻蚀阻挡层以及和所述半导体层连接的源电极和漏电极，所述薄膜晶体管还包括：
设置于所述刻蚀阻挡层上的阻挡结构；
所述阻挡结构与所述源电极、漏电极电隔离，且所述阻挡结构在所述刻蚀阻挡层上的正投影和所述半导体层在所述刻蚀阻挡层上的正投影至少部分重叠。
上述的薄膜晶体管，其中，所述阻挡结构在所述刻蚀阻挡层上的正投影位于所述半导体层在所述刻蚀阻挡层上的正投影所在的区域内。
上述的薄膜晶体管，其中，所述阻挡结构和所述源电极和漏电极通过一次刻蚀工艺形成。
上述的薄膜晶体管，其中，所述源电极和漏电极的相对的平行侧边的垂线的长度为D，所述阻挡结构在平行于所述垂线的方向上的宽度为W，所述W/D在1/20-18/20之间。
上述的薄膜晶体管，其中，所述源电极和漏电极为对插的梳状结构，对插的梳齿分为多个梳齿组，相邻的梳齿组之间的间隔距离大于梳齿组内相邻的梳齿之间的距离，所述阻挡结构位于相邻的作为源电极的梳齿和作为漏电极的梳齿之间，相邻但属于不同的梳齿组的梳齿或者同时为作为漏电极的梳齿，或者同时为作为源电极的梳齿。。
上述的薄膜晶体管，其中，所述源电极和漏电极为对插的梳状结构，其中至少一对相邻的作为源电极的梳齿之间设置有两个作为漏电极的梳齿，所述阻挡结构位于相邻的作为源电极的梳齿和作为漏电极的梳齿之间。
上述的薄膜晶体管，其中，所述漏电极包括：
第一梳柄；及
分布于所述第一梳柄两侧，与所述第一梳柄电连接的第一梳齿序列和第二梳齿序列；
所述源电极包括：
第二梳柄；
分布于所述第二梳柄一侧，与所述第二梳柄电连接的第三梳齿序列，和所述第一梳齿序列对插；
第三梳柄，与第二梳柄电连接；及
分布于所述第三梳柄一侧，与所述第三梳柄电连接的第四梳齿序列，和所述第二梳齿序列对插；
所述阻挡结构位于相邻的作为源电极的梳齿和作为漏电极的梳齿之间。
上述的薄膜晶体管，其中，所述第二梳柄和所述第三梳柄呈U型；所述第一梳柄、所述第三梳齿序列和所述第四梳齿序列位于所述U型内部；所述第三梳齿序列和所述第四梳齿序列位于所述第一梳柄两侧。
上述的薄膜晶体管，其中，所述第一梳齿序列和所述第三梳齿序列位于所述第一梳柄与所述第二梳柄之间；所述第二梳齿序列和所述第四梳齿序列位于所述第一梳柄与所述第三梳柄之间。
为了更好的实现上述目的，本公开实施例还提供了一种电路结构，包括一薄膜晶体管，所述薄膜晶体管包括：栅极、半导体层、刻蚀阻挡层以及和所述半导体层连接的源电极和漏电极，所述薄膜晶体管还包括：
设置于所述刻蚀阻挡层上的阻挡结构；
所述阻挡结构与所述源电极、漏电极电隔离，且所述阻挡结构在所述刻蚀阻挡层上的正投影和所述半导体层在所述刻蚀阻挡层上的正投影至少部分重叠。
上述的电路结构，其中，所述阻挡结构在所述刻蚀阻挡层上的正投影位于所述半导体层在所述刻蚀阻挡层上的正投影所在的区域内。
上述的电路结构，其中，所述阻挡结构和所述源电极和漏电极通过一次刻蚀工艺形成。
上述的电路结构，其中，所述源电极和漏电极的相对的平行侧边的垂线的长度为D，所述阻挡结构在平行于所述垂线的方向上的宽度为W，所述W/D在1/20-18/20之间。
上述的电路结构，其中，所述源电极和漏电极为对插的梳状结构，对插的梳齿分为多个梳齿组，相邻的梳齿组之间的间隔距离大于梳齿组内相邻的梳齿之间的距离，所述阻挡结构位于相邻的作为源电极的梳齿和作为漏电极 的梳齿之间，相邻但属于不同的梳齿组的梳齿或者同时为作为漏电极的梳齿，或者同时为作为源电极的梳齿。
上述的电路结构，其中，所述源电极和漏电极为对插的梳状结构，其中至少一对相邻的作为源电极的梳齿之间设置有两个作为漏电极的梳齿，所述阻挡结构位于相邻的作为源电极的梳齿和作为漏电极的梳齿之间。
上述的电路结构，其中，所述电路结构还包括电容结构，所述电容结构包括第一极板和由所述薄膜晶体管的栅极形成的第二极板，所述第一极板与所述薄膜晶体管的源、漏电极同层设置，且与所述薄膜晶体管的漏电极连接。
上述的电路结构，其中，所述电路结构为移位寄存器单元，所述薄膜晶体管的源漏电极分别连接到信号输入节点和输出节点，栅极连接拉高节点，所述电容结构的一端连接到拉高节点，另一端连接到所述输出节点。
上述的电路结构，其中，
所述漏电极包括：
第一梳柄，与所述第一极板电连接；及
分布于所述第一梳柄两侧，与所述第一梳柄电连接的第一梳齿序列和第二梳齿序列；
所述源电极包括：
第二梳柄；
分布于所述第二梳柄一侧，与所述第二梳柄电连接的第三梳齿序列，和所述第一梳齿序列对插；
第三梳柄，与第二梳柄电连接；及
分布于所述第三梳柄一侧，与所述第三梳柄电连接的第四梳齿序列，和所述第二梳齿序列对插；
所述阻挡结构位于相邻的作为源电极的梳齿和作为漏电极的梳齿之间。
上述的电路结构，其中，所述第一梳柄的至少一侧的对插的梳齿分为多个梳齿组，相邻的梳齿组之间的间隔距离大于梳齿组内相邻的梳齿之间的距离，相邻但属于不同的梳齿组的梳齿或者同时为作为漏电极的梳齿，或者同时为作为源电极的梳齿。
上述的电路结构，其中，所述第一梳柄下方的有源层被去除。
上述的电路结构，其中，所述第一梳柄上还设置有延伸到所述相邻的梳齿组之间的间隙的延伸部，所述延伸部下方的有源层被去除。
为了更好的实现上述目的，本公开实施例还提供了一种薄膜晶体管，包括：源电极和漏电极，
所述漏电极包括：
第一梳柄；及
分布于所述第一梳柄两侧，与所述第一梳柄电连接的第一梳齿序列和第二梳齿序列；
所述源电极包括：
第二梳柄；
分布于所述第二梳柄一侧，与所述第二梳柄电连接的第三梳齿序列，和所述第一梳齿序列对插；
第三梳柄，与第二梳柄电连接；及
分布于所述第三梳柄一侧，与所述第三梳柄电连接的第四梳齿序列，和所述第二梳齿序列对插；
上述的薄膜晶体管，其中，所述第一梳柄的至少一侧的对插的梳齿分为多个梳齿组，相邻的梳齿组之间的间隔距离大于梳齿组内相邻的梳齿之间的距离，相邻但属于不同的梳齿组的梳齿或者同时为作为漏电极的梳齿，或者同时为作为源电极的梳齿。
本公开实施例的薄膜晶体管及电路结构中，通过保留源漏金属层中一部分原本需要去除的膜层，形成位于刻蚀阻挡层上的阻挡结构，改善了薄膜晶体管的阈值电压的漂移特性，提高了器件性能。
附图说明
图1表示本公开实施例的薄膜晶体管的结构示意图；
图2表示表示本公开实施例的设置有过孔的薄膜晶体管的结构示意图；
图3表示现有技术的薄膜晶体管的栅极电压Vg和源漏电极之间的电流Ids的测试曲线；
图4表示本公开实施例的薄膜晶体管的栅极电压Vg和源漏电极之间的 电流Ids的测试曲线；
图5表示本公开实施例的薄膜晶体管中，源漏电极的一种对插梳状结构；
图6表示本公开实施例的薄膜晶体管中，源漏电极的另一种对插梳状结构；
图7表示本公开实施例的薄膜晶体管中，源漏电极的再一种对插梳状结构。
具体实施方式
本公开实施例的薄膜晶体管及电路结构中，通过保留源漏金属层中一部分原本需要去除的膜层，形成位于刻蚀阻挡层上的阻挡结构，改善了薄膜晶体管的阈值电压的漂移特性，提高了器件性能。
本公开实施例的薄膜晶体管，如图1所示，包括：栅极、半导体层101、刻蚀阻挡层以及和所述半导体层101连接的源电极102和漏电极103，其中，所述薄膜晶体管还包括设置于所述刻蚀阻挡层上的阻挡结构104。
所述阻挡结构104与所述源电极102、漏电极103电隔离，且所述阻挡结构104在所述刻蚀阻挡层上的正投影和所述半导体层101在所述刻蚀阻挡层上的正投影至少部分重叠。
对于TFT制作领域的普通技术人员而言，薄膜晶体管的源漏电极之间的源漏金属层都应该去除，这属于TFT制作领域长期以来固有的技术偏见。而本公开实施例的薄膜晶体管及电路结构中，克服上述的技术偏见，通过保留源漏金属层中一部分原本需要去除的膜层，形成位于刻蚀阻挡层上的阻挡结构，改善了薄膜晶体管的阈值电压的漂移特性，提高了器件性能。后续将通过仿真数据对本公开实施例的有益效果进行进一步说明。
在本公开的具体实施例中，上述的阻挡结构在所述刻蚀阻挡层上的正投影和所述半导体层101在所述刻蚀阻挡层上的正投影至少部分重叠为：
1、所述阻挡结构104在所述刻蚀阻挡层上的正投影和所述半导体层101在所述刻蚀阻挡层上的正投影只有部分重叠；或者
2、所述阻挡结构104在所述刻蚀阻挡层上的正投影和所述半导体层101在所述刻蚀阻挡层上的正投影完全重叠，即：所述阻挡结构104在所述刻蚀 阻挡层上的正投影位于所述半导体层101在所述刻蚀阻挡层上的正投影所在的区域内。
在本公开的具体实施例中，上述的阻挡结构104可以是通过单独的刻蚀工艺形成，但为了简化工艺流程，降低成本，在本公开的具体实施例中，上述的阻挡结构104和所述源电极102和漏电极103通过一次刻蚀工艺形成。
下面对本公开实施例的薄膜晶体管能够改善阈值电压的漂移说明如下。
如图2所示，对于TFT而言，与其电性能密切相关的因素为TFT结构的宽长比W/L。
如图2所示，当源电极102和漏电极103均通过过孔105和有源层连接时(应当理解的是，本公开实施例并不限定源电极102/漏电极103与有源层之间的连接方式，上述的源电极102/漏电极103通过过孔和有源层连接不应对本公开的保护范围造成限定)，W为过孔的宽度的总和，即：
W＝D6+D7+D8。
其中，一般情况下，D6＝D9、D7＝D10，D8＝D11，也就是说，源电极102和漏电极103上的过孔105的数量及形状都相同，在后续的测试中以图2所示的结构为例进行测试。
而L为源电极102和漏电极103上的过孔105的相邻的侧边之间的距离，即：
L＝D1+D2+D3+D4+D5
其中，在本公开实施例的测试实验中，以D1＝D5、D2和D4这种设计为例进行详细说明。
测试条件：
源漏电极之间的电压差为9.1V；
测试温度50℃；
光源10000尼特；
宽长比为25∶24；
D1＝D5＝4微米；
D2＝D4＝5.5微米；
D3＝5微米；
D6＝D7＝D9＝D10＝8微米；
D8＝D11＝8.5微米；
如图2所示，本公开实施例的薄膜晶体管相对于现有技术的晶体管主要多了图2中所示的阻挡结构104，其他部分均相同。
上述条件下，现有技术的薄膜晶体管在0秒、600秒和1200秒时测试得到的栅极电压Vg和源漏电极之间的电流Ids的对应曲线如图3所示。
从图3中可以发现，在第0秒时，使得源漏电极之间的电流Ids达到10-8A的栅极电压大约为0.4V，在第600秒时，使得源漏电极之间的电流Ids达到10-8的栅极电压大约为-1.5V，而在第1200秒时，使得源漏电极之间的电流Ids达到10-8A的栅极电压大约为-2.2V，也就是说，现有技术的薄膜晶体管在工作600秒之后，阈值电压的漂移达到约1.9V(0.4V与-1.5V的差值)，而在工作1200秒之后，阈值电压的漂移达到2.6V(0.4V与-2.2V的差值)。
上述条件下，本公开实施例的薄膜晶体管在0秒、600秒和1200秒时测试得到的栅极电压Vg和源漏电极之间的电流Ids的对应曲线如图4所示。
从图4中可以发现，在第0秒时，使得源漏电极之间的电流Ids达到10-8A的栅极电压大约为1.2V，在第600秒时，使得源漏电极之间的电流Ids达到10-8A的栅极电压大约为1V，而在第1200秒时，使得源漏电极之间的电流Ids达到10-8A的栅极电压大约为0.75V，也就是说，本公开实施例的薄膜晶体管在工作600秒之后，阈值电压的漂移达到约0.2V(1.2V与1V的差值)，而在工作1200秒之后，阈值电压的漂移达到0.45V(1.2V与0.75V的差值)。
从以上两个测试结果可以发现，本公开实施例的增加阻挡结构的薄膜晶体管与现有技术的薄膜晶体管相比，至少具有如下两方面的优点：
1、阈值电压的漂移大大降低
本公开实施例的薄膜晶体管在工作600秒及1200秒之后，阈值电压的漂移分别为0.2V和0.45V，相对于现有技术的薄膜晶体管在工作600秒及1200秒之后的1.9V和2.6V的阈值电压漂移大大降低。
2、阈值电压位于正电压区间
现有技术的薄膜晶体管在工作600秒及1200秒之后，其阈值电压分别为-1.5V和-2.2V，此时，即使栅极不施加电信号(即栅极电压为0)，源漏电极 之间的电流Ids也大于10-8A，也就是说导致了薄膜晶体管的不正常导通。
而本公开实施例的薄膜晶体管在工作600秒及1200秒之后，其阈值电压分别为1V和0.75V，此时，栅极不施加电信号(即栅极电压为0)时，源漏电极之间的电流Ids远小于10-8A，也就是薄膜晶体管处于正常的关断状态。
以上的实施例中，所述源电极102和漏电极103的相对的平行侧边的垂线的长度为D(即D2+D3+D4)，而所述阻挡结构104在平行于所述垂线的方向上的宽度为W(即D3)。
在上述的测试中，W/D为5/16，但本公开具体实施例中，所述W/D在1/20-18/20之间时，都可以降低阈值电压的漂移。
当宽长比W/L确定之后，即可采用各种结构来实现TFT，如图2所示的多过孔结构，但为了保证TFT良好的散热性，在本公开的具体实施例中，如图5所示，所述源电极102和漏电极103为对插的梳状结构，对插的梳齿分为多个梳齿组201，相邻的梳齿组201之间第一间隔区501的宽度大于梳齿组201内相邻的梳齿之间的距离，所述阻挡结构(图中未示出)位于相邻的作为源电极102的梳齿和作为漏电极103的梳齿之间，相邻但属于不同的梳齿组的梳齿或者同时为作为漏电极的梳齿，或者同时为作为源电极的梳齿。
一般情况下，对于TFT设计而言，都会预先确定与其电性能密切相关的宽长比W/L。当TFT的W/L相同时，在相同的电压驱动条件，经过源电极和漏电极的电流也基本相同，所以产生热量是相同的。但不同形状的TFT的散热性能不同。
如图5所示的结构中，由于对插的梳齿分为多个梳齿组201，而梳齿组201之间的间隔距离较大，使得梳齿组201内产生的热量可以通过面积较大的第一间隔区501散发，提高了TFT器件的散热性能。
同时，由于属于不同的梳齿组201的相邻梳齿或者同时为作为漏电极103的梳齿，或者同时为作为源电极102的梳齿，使得相邻梳齿组201之间的第一间隔区501中没有电流产生(或者电流很小)，提高了第一间隔区501的散热能力，进一步提高了TFT器件的散热性能。
上述的如图5所示的结构中，通过梳齿组201之间的第一间隔区501来进行散热，提高了TFT器件的散热性能。而本公开具体实施例中，也可以通 过位于梳齿组201内部的第二间隔区601来进行散热。
如图6所示，所述源电极102和漏电极103为对插的梳状结构，其中至少一对相邻的作为源电极102的梳齿之间设置有两个作为漏电极103的梳齿，所述阻挡结构104位于相邻的作为源电极102的梳齿和作为漏电极103的梳齿之间。
如图6所示的结构中，由于对插的梳齿分为多个梳齿组201，而梳齿组201内部，存在相邻的同时作为漏电极103的梳齿，因此，该同时作为漏电极103的梳齿之间没有电流产生(或者电流很小)，因此该同时作为漏电极103的相邻梳齿之间的第二间隔区601可以实现较好的散热效果，提高了TFT的散热性能。
应当理解的是，上述的图5和图6的结构可以单独使用，也可以配合使用。
本公开具体实施例的图5和图6所示的结构中，对插的梳齿只有一排，但为了进一步的提高散热性能，本公开实施例的TFT的作为源电极102的梳齿和作为漏电极103的梳齿可以是多排分布，以进一步提高散热性能。
如图7所示，所述漏电极包括：
第一梳柄701；及
分布于所述第一梳柄701两侧，与所述第一梳柄701电连接的第一梳齿序列和第二梳齿序列；
所述源电极包括：
第二梳柄702；
分布于所述第二梳柄702一侧，与所述第二梳柄电连接的第三梳齿序列，和所述第一梳齿序列对插；
第三梳柄703，与第二梳柄电连接；及
分布于所述第三梳柄703一侧，与所述第三梳柄电连接的第四梳齿序列，和所述第二梳齿序列对插；
所述阻挡结构(图中未示出)位于相邻的作为源电极102的梳齿和作为漏电极103的梳齿之间。
图7所示的结构中，作为漏电极103的梳齿分两行排布，而位于TFT内 部的第一梳柄701能够承担较好的散热作用，其相对于现有技术的周边散热的方式具有更好的散热效果。
同时，图5和图6所示的梳齿组的排布方式也可以应用于图7中任意一排对插的梳齿序列，以提高图7所示的TFT的散热性能。
本公开实施例的薄膜晶体管可以用于各种电路结构中，其中，所述薄膜晶体管如图2所示，包括：栅极、半导体层101、刻蚀阻挡层以及和所述半导体层101连接的源电极102和漏电极103；所述薄膜晶体管还包括：
设置于所述刻蚀阻挡层上的阻挡结构104；
所述阻挡结构104与所述源电极102、漏电极103电隔离，且所述阻挡结构104在所述刻蚀阻挡层上的正投影和所述半导体层101在所述刻蚀阻挡层上的正投影至少部分重叠。
其中，所述的阻挡结构104在所述刻蚀阻挡层上的正投影位于所述半导体层101在所述刻蚀阻挡层上的正投影所在的区域内。
所述阻挡结构104可以和所述源电极102和漏电极103通过一次刻蚀工艺形成。
所述源电极102和漏电极103的相对的平行侧边的垂线的长度为D，所述阻挡结构104在平行于所述垂线的方向上的宽度为W，所述W/D在1/20-18/20之间时，都可以降低阈值电压的漂移。
如图5所示，所述源电极102和漏电极103可以为对插的梳状结构，对插的梳齿分为多个梳齿组201，相邻的梳齿组201之间第一间隔区的宽度大于梳齿组201内相邻的梳齿之间的距离，所述阻挡结构104位于相邻的作为源电极102的梳齿和作为漏电极103的梳齿之间，相邻但属于不同的梳齿组的梳齿或者同时为作为漏电极的梳齿，或者同时为作为源电极的梳齿。
由于梳齿组201之间的间隔距离较大，使得梳齿组201内产生的热量可以通过面积较大的第一间隔区501散发，提高了TFT器件的散热性能。同时，由于属于不同的梳齿组201的相邻梳齿或者同时为作为漏电极103的梳齿，或者同时为作为源电极102的梳齿，使得相邻梳齿组201之间的第一间隔区501中没有电流产生(或者电流很小)，提高了第一间隔区501的散热能力，进一步提高了TFT器件的散热性能。
另外一种方式中，如图6所示，所述源电极102和漏电极103为对插的梳状结构，其中至少一对相邻的作为源电极102的梳齿之间设置有两个作为漏电极103的梳齿，所述阻挡结构104位于相邻的作为源电极102的梳齿和作为漏电极103的梳齿之间。
由于梳齿组201内部存在相邻的同时作为漏电极103的梳齿，因此，该同时作为漏电极103的梳齿之间没有电流产生(或者电流很小)，因此该同时作为漏电极103的相邻梳齿之间的第二间隔区601可以实现较好的散热效果，提高了TFT的散热性能。
在很多的电路结构中，都包括和TFT配合使用的电容结构，如栅极驱动电路，当所述电路结构还包括电容结构，且所述电容结构包括第一极板和由所述薄膜晶体管的栅极形成的第二极板，所述第一极板与所述薄膜晶体管的源、漏电极同层设置，且与所述薄膜晶体管的漏电极连接。
上述的电路结构很典型的一种结构是栅极驱动电路中的移位寄存器单元，所述薄膜晶体管的源漏电极分别连接到信号输入节点和输出节点，栅极连接拉高节点，所述电容结构的一端连接到拉高节点，另一端连接到所述输出节点。
在上述的移位寄存器单元中，如图7所示，所述漏电极包括：
第一梳柄701，与所述第一极板电连接；及
分布于所述第一梳柄701两侧，与所述第一梳柄701电连接的第一梳齿序列和第二梳齿序列；
所述源电极包括：
第二梳柄702；
分布于所述第二梳柄702一侧，与所述第二梳柄702电连接的第三梳齿序列，和所述第一梳齿序列对插；
第三梳柄703与第二梳柄702电连接；及
分布于所述第三梳柄703一侧，与所述第三梳柄703电连接的第四梳齿序列，和所述第二梳齿序列对插；
所述阻挡结构104位于相邻的作为源电极102的梳齿和作为漏电极103的梳齿之间。
在本公开的具体实施例中，为了提高移位寄存器单元的散热性能，所述第一梳柄的至少一侧的对插的梳齿分为多个梳齿组，相邻的梳齿组之间第一间隔区的宽度大于梳齿组内相邻的梳齿之间的距离，相邻但属于不同的梳齿组的梳齿或者同时为作为漏电极的梳齿，或者同时为作为源电极的梳齿。
由于对插的梳齿分为多个梳齿组，而梳齿组之间的间隔距离较大，使得梳齿组内产生的热量可以通过面积较大的第一间隔区散发，提高了TFT器件的散热性能。
同时，由于属于不同的梳齿组的相邻梳齿或者同时为作为漏电极的梳齿，或者同时为作为源电极的梳齿，使得相邻梳齿组之间的第一间隔区中没有电流产生(或者电流很小)，提高了第一间隔区的散热能力，进一步提高了TFT器件的散热性能。
众所周知，在TFT结构中存在一层有源层，而有源层的特性在于当栅极被施加电压值超过阈值电压的电信号时，则有源层成为导体，而当栅极被施加电压值低于阈值电压的电信号时，则有源层成为绝缘体。
而同时，本公开实施例中，电容结构包括第一极板和由所述薄膜晶体管的栅极形成的第二极板，所述第一极板与所述薄膜晶体管的源、漏电极同层设置，且与所述薄膜晶体管的漏电极连接。如果在第一极板和第二极板之间存在有源层时，有源层的性质发生变化会导致电容结构的极板间的距离发生变化，进而导致电容发生改变，影响移位寄存器单元的正常工作。
因此，为了保证移位寄存器单元的正常工作，在本公开具体实施例中，所述第一梳柄下方的有源层被去除。
从之前的描述中可以发现，当第一梳柄下方的有源层被去除时，则第一梳柄成为了电容结构的极板的一部分，能够起到很好的散热作用。
当相邻但属于不同的梳齿组的梳齿或者同时为作为漏电极的梳齿，或者同时为作为源电极的梳齿时，此时相邻的梳齿组之间并没有电流的传输，为了进一步提高移位寄存器的散热性能，同时也充分利用有限的空间，在本公开具体实施例中，所述第一梳柄上还设置有延伸到相邻的梳齿组之间的间隙的延伸部，所述延伸部下方的有源层被去除。
也就是说，当相邻但属于不同的梳齿组的梳齿或者同时为作为漏电极的 梳齿，或者同时为作为源电极的梳齿时，相邻的梳齿组之间不需要电流的传输，也就是说，相邻的梳齿组之间存在一块对于TFT而言属于多余的区域，而这块多余的区域在本公开实施例中并作为电容结构的极板的一部分，不但充分利用了空间，同时，该延伸到梳齿组之间的间隙的延伸部还能够起到对TFT进行散热的作用。
本公开实施例还提供了一种薄膜晶体管，包括：源电极和漏电极，如图7所示，所述漏电极包括：
第一梳柄701；及
分布于所述第一梳柄701两侧，与所述第一梳柄701电连接的第一梳齿序列和第二梳齿序列；
所述源电极包括：
第二梳柄702；
分布于所述第二梳柄702一侧，与所述第二梳柄电连接的第三梳齿序列，和所述第一梳齿序列对插；
第三梳柄703，与第二梳柄电连接；及
分布于所述第三梳柄703一侧，与所述第三梳柄电连接的第四梳齿序列，和所述第二梳齿序列对插。
上述的薄膜晶体管结构区别于现有的薄膜晶体管结构，作为漏电极的一部分的第一梳柄701位于整个薄膜晶体管的内部，使得整个薄膜晶体管能够从中心利用第一梳柄701对薄膜晶体管产生的热量进行散发，其提高了薄膜晶体管的散热能力。
上述的薄膜晶体管中，所述第一梳柄的至少一侧的对插的梳齿分为多个梳齿组，相邻的梳齿组之间第一间隔区的宽度大于梳齿组内相邻的梳齿之间的距离，相邻但属于不同的梳齿组的梳齿或者同时为作为漏电极的梳齿，或者同时为作为源电极的梳齿，提高了TFT器件的散热性能。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (23)

  1. 一种薄膜晶体管，包括：栅极、半导体层、刻蚀阻挡层以及和所述半导体层连接的源电极和漏电极；其中，所述薄膜晶体管还包括：
    设置于所述刻蚀阻挡层上的阻挡结构；
    所述阻挡结构与所述源电极、漏电极电隔离，且所述阻挡结构在所述刻蚀阻挡层上的正投影和所述半导体层在所述刻蚀阻挡层上的正投影至少部分重叠。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述阻挡结构在所述刻蚀阻挡层上的正投影位于所述半导体层在所述刻蚀阻挡层上的正投影所在的区域内。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述阻挡结构和所述源电极和漏电极通过一次刻蚀工艺形成。
  4. 根据权利要求1所述的薄膜晶体管，其中，所述源电极和漏电极的相对的平行侧边的垂线的长度为D，所述阻挡结构在平行于所述垂线的方向上的宽度为W，所述W/D在1/20-18/20之间。
  5. 根据权利要求1、2、3或4所述的薄膜晶体管，其中，所述源电极和漏电极为对插的梳状结构，对插的梳齿分为多个梳齿组，相邻的梳齿组之间的间隔距离大于梳齿组内相邻的梳齿之间的距离，所述阻挡结构位于相邻的作为源电极的梳齿和作为漏电极的梳齿之间，相邻但属于不同的梳齿组的梳齿或者同时为作为漏电极的梳齿，或者同时为作为源电极的梳齿。
  6. 根据权利要求1、2、3或4所述的薄膜晶体管，其中，所述源电极和漏电极为对插的梳状结构，其中至少一对相邻的作为源电极的梳齿之间设置有两个作为漏电极的梳齿，所述阻挡结构位于相邻的作为源电极的梳齿和作为漏电极的梳齿之间。
  7. 根据权利要求1、2、3或4所述的薄膜晶体管，其中，所述漏电极包括：
    第一梳柄；及
    分布于所述第一梳柄两侧，与所述第一梳柄电连接的第一梳齿序列和第 二梳齿序列；
    所述源电极包括：
    第二梳柄；
    分布于所述第二梳柄一侧，与所述第二梳柄电连接的第三梳齿序列，和所述第一梳齿序列对插；
    第三梳柄，与第二梳柄电连接；及
    分布于所述第三梳柄一侧，与所述第三梳柄电连接的第四梳齿序列，和所述第二梳齿序列对插；
    所述阻挡结构位于相邻的作为源电极的梳齿和作为漏电极的梳齿之间。
  8. 根据权利要求7所述的薄膜晶体管，其中，所述第二梳柄和所述第三梳柄呈U型；所述第一梳柄、所述第三梳齿序列和所述第四梳齿序列位于所述U型内部；所述第三梳齿序列和所述第四梳齿序列位于所述第一梳柄两侧。
  9. 根据权利要求8所述的薄膜晶体管，其中，所述第一梳齿序列和所述第三梳齿序列位于所述第一梳柄与所述第二梳柄之间；所述第二梳齿序列和所述第四梳齿序列位于所述第一梳柄与所述第三梳柄之间。
  10. 一种电路结构，包括一薄膜晶体管，所述薄膜晶体管包括：栅极、半导体层、刻蚀阻挡层以及和所述半导体层连接的源电极和漏电极，其中，所述薄膜晶体管还包括：
    设置于所述刻蚀阻挡层上的阻挡结构；
    所述阻挡结构与所述源电极、漏电极电隔离，且所述阻挡结构在所述刻蚀阻挡层上的正投影和所述半导体层在所述刻蚀阻挡层上的正投影至少部分重叠。
  11. 根据权利要求10所述的电路结构，其中，所述阻挡结构在所述刻蚀阻挡层上的正投影位于所述半导体层在所述刻蚀阻挡层上的正投影所在的区域内。
  12. 根据权利要求10所述的电路结构，其中，所述阻挡结构和所述源电极和漏电极通过一次刻蚀工艺形成。
  13. 根据权利要求10所述的电路结构，其中，所述源电极和漏电极的相对的平行侧边的垂线的长度为D，所述阻挡结构在平行于所述垂线的方向上 的宽度为W，所述W/D在1/20-18/20之间。
  14. 根据权利要求10、11、12或13所述的电路结构，其中，所述源电极和漏电极为对插的梳状结构，对插的梳齿分为多个梳齿组，相邻的梳齿组之间的间隔距离大于梳齿组内相邻的梳齿之间的距离，所述阻挡结构位于相邻的作为源电极的梳齿和作为漏电极的梳齿之间，相邻但属于不同的梳齿组的梳齿或者同时为作为漏电极的梳齿，或者同时为作为源电极的梳齿。
  15. 根据权利要求10、11、12或13所述的电路结构，其中，所述源电极和漏电极为对插的梳状结构，其中至少一对相邻的作为源电极的梳齿之间设置有两个作为漏电极的梳齿，所述阻挡结构位于相邻的作为源电极的梳齿和作为漏电极的梳齿之间。
  16. 根据权利要求10、11、12或13所述的电路结构，其中，所述电路结构还包括电容结构，所述电容结构包括第一极板和由所述薄膜晶体管的栅极形成的第二极板，所述第一极板与所述薄膜晶体管的源、漏电极同层设置，且与所述薄膜晶体管的漏电极连接。
  17. 根据权利要求16所述的电路结构，其中，所述电路结构为移位寄存器单元，所述薄膜晶体管的源漏电极分别连接到信号输入节点和输出节点，栅极连接拉高节点，所述电容结构的一端连接到拉高节点，另一端连接到所述输出节点。
  18. 根据权利要求17所述的电路结构，其中：
    所述漏电极包括：
    第一梳柄，与所述第一极板电连接；及
    分布于所述第一梳柄两侧，与所述第一梳柄电连接的第一梳齿序列和第二梳齿序列；
    所述源电极包括：
    第二梳柄；
    分布于所述第二梳柄一侧，与所述第二梳柄电连接的第三梳齿序列，和所述第一梳齿序列对插；
    第三梳柄，与第二梳柄电连接；及
    分布于所述第三梳柄一侧，与所述第三梳柄电连接的第四梳齿序列，和 所述第二梳齿序列对插；
    所述阻挡结构位于相邻的作为源电极的梳齿和作为漏电极的梳齿之间。
  19. 根据权利要求18所述的电路结构，其中，所述第一梳柄的至少一侧的对插的梳齿分为多个梳齿组，相邻的梳齿组之间的间隔距离大于梳齿组内相邻的梳齿之间的距离，相邻但属于不同的梳齿组的梳齿或者同时为作为漏电极的梳齿，或者同时为作为源电极的梳齿。
  20. 根据权利要求19所述的电路结构，其中，所述第一梳柄下方的有源层被去除。
  21. 根据权利要求20所述的电路结构，其中，所述第一梳柄上还设置有延伸到所述相邻的梳齿组之间的间隙的延伸部，所述延伸部下方的有源层被去除。
  22. 一种薄膜晶体管，包括：源电极和漏电极，其中，
    所述漏电极包括：
    第一梳柄；及
    分布于所述第一梳柄两侧，与所述第一梳柄电连接的第一梳齿序列和第二梳齿序列；
    所述源电极包括：
    第二梳柄；
    分布于所述第二梳柄一侧，与所述第二梳柄电连接的第三梳齿序列，和所述第一梳齿序列对插；
    第三梳柄，与第二梳柄电连接；及
    分布于所述第三梳柄一侧，与所述第三梳柄电连接的第四梳齿序列，和所述第二梳齿序列对插。
  23. 根据权利要求22所述的薄膜晶体管，其中，所述第一梳柄的至少一侧的对插的梳齿分为多个梳齿组，相邻的梳齿组之间的间隔距离大于梳齿组内相邻的梳齿之间的距离，相邻但属于不同的梳齿组的梳齿或者同时为作为漏电极的梳齿，或者同时为作为源电极的梳齿。
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