WO2016106891A1 - 阵列基板、显示装置及阵列基板的制备方法 - Google Patents

阵列基板、显示装置及阵列基板的制备方法 Download PDF

Info

Publication number
WO2016106891A1
WO2016106891A1 PCT/CN2015/071164 CN2015071164W WO2016106891A1 WO 2016106891 A1 WO2016106891 A1 WO 2016106891A1 CN 2015071164 W CN2015071164 W CN 2015071164W WO 2016106891 A1 WO2016106891 A1 WO 2016106891A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
drain
disposed
thickness
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/071164
Other languages
English (en)
French (fr)
Inventor
刘桓
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/435,512 priority Critical patent/US9589986B2/en
Publication of WO2016106891A1 publication Critical patent/WO2016106891A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00

Definitions

  • the present invention relates to the field of display, and in particular to an array substrate and a display device.
  • the liquid crystal display device is favored by users because of its low power consumption, small size, and light weight.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • pixels are generally divided into a main region and a sub region, and the pixel voltage of the sub region is lower than that.
  • the pixel voltage of the main area to improve the bias of the big view.
  • a pull-down capacitor is further disposed on the array substrate of the thin film transistor of the main region and the thin film transistor of the sub-region, and the pull-down capacitor cooperates with the thin film transistor of the sub-region to share a part of the charge on the thin film transistor of the sub-region.
  • the pull-down capacitor uses an MII structure.
  • the structure of the pull-down capacitor of the MII structure is generally a metal layer, a first insulating layer (such as G-SiNx), a second insulating layer (PA-SiNx), and a transparent conductive layer. It can be seen that the uppermost layer of the pull-down capacitor of the MII structure is usually a transparent conductive layer, such as Indium Tin Oxides (ITO).
  • ITO Indium Tin Oxides
  • the uppermost layer of the thin film transistor of the sub-region is also a transparent conductive layer (which may be a pixel electrode), and the uppermost transparent conductive layer of the thin film transistor of the sub-region and the uppermost transparent conductive layer of the pull-down capacitor of the MII structure are located on the same layer. And the interval between them is small.
  • the residual of the transparent conductive layer is easily generated, so that the uppermost transparent conductive layer of the sub-region thin film transistor (Sub TFT) and the uppermost layer of the pull-down capacitor of the MII structure are formed.
  • FIG. 1 is a transparent layer of the uppermost layer of the thin film transistor and the uppermost layer of the pull-down capacitor in the sub-region of the prior art.
  • FIG. 2 is a schematic diagram of a display device that produces micro-bright spots in the prior art.
  • a short circuit occurs between the transparent conductive layer of the uppermost layer of the thin film transistor of the sub-region and the transparent conductive layer of the uppermost layer of the pull-down capacitor to generate a micro bright spot, which is represented by SP in the figure, and the pull-down capacitor is represented by C. .
  • the present invention provides an array substrate having a high display quality.
  • the array substrate includes:
  • a substrate and a thin film transistor and a pull-down capacitor disposed on the same surface of the substrate, the pull-down capacitor being disposed adjacent to the thin film transistor;
  • the thin film transistor includes:
  • the source and the drain are disposed on the channel layer, and the source is spaced apart from the drain;
  • a passivation layer disposed on the source, the drain, and the channel layer, wherein the passivation layer is provided with a through hole, the through hole is disposed corresponding to the drain, and the pixel electrode passes through the a through hole is connected to the drain;
  • the pull-down capacitor includes:
  • the thickness of the filling layer is greater than the thickness of the source and the thickness of the filling layer is greater than the thickness of the drain.
  • the sum of the thickness of the filling layer and the thickness of the first isolation layer is greater than a sum of the thickness of the drain and the channel layer by 0.3 um to 0.6 um such that the second conductive layer is The pixel electrode is 0.3um to 0.6um higher.
  • the material of the filling layer is metal or alloy.
  • a display device comprising any of the above various embodiments An array substrate of an embodiment.
  • a method for preparing an array substrate comprises:
  • An insulating layer is disposed, and an insulating layer disposed on the source, the drain, and the channel layer is defined as a passivation layer, and an insulating layer disposed on the filling layer is defined as a second isolation layer;
  • the gate, the gate insulating layer, the channel layer, the source, and the drain are defined as thin film transistors;
  • the conductive layer, the first isolation layer, the filling layer, the second isolation layer and the second conductive layer are defined as pull-down capacitors;
  • a through hole is formed on the passivation layer corresponding to the drain, and a pixel electrode is disposed on the passivation layer corresponding to the through hole.
  • the filling layer is formed in the same process as the source and the drain.
  • first conductive layer and the gate are formed in the same process, and the first isolation layer and the channel layer are formed in the same process.
  • the second isolation layer and the passivation layer are formed in the same process.
  • the thickness of the filling layer is greater than the thickness of the source and the thickness of the filling layer is greater than the thickness of the drain.
  • a filling layer is added to the pull-down capacitor such that the second conductive layer of the pull-down capacitor is not in the same plane as the pixel electrode, thereby increasing The distance between the second conductive layer and the pixel electrode is described, so that a short circuit between the second conductive layer and the pixel electrode is less likely to occur, thereby improving the display quality of the display device.
  • FIG. 1 is a schematic diagram showing a short circuit between a transparent conductive layer of an uppermost layer of a thin film transistor of a sub-region and a transparent conductive layer of an uppermost layer of a pull-down capacitor in the prior art.
  • FIG. 2 is a schematic diagram of a display device generating micro-bright spots in the prior art.
  • FIG 3 is a cross-sectional structural view of an array substrate according to a preferred embodiment of the present invention.
  • FIG. 4 is a cross-sectional structural view of a display device according to a preferred embodiment of the present invention.
  • FIG. 5 is a flow chart of a method of fabricating an array substrate according to a preferred embodiment of the present invention.
  • FIG. 3 is a cross-sectional structural diagram of an array substrate according to a preferred embodiment of the present invention.
  • the array substrate 10 includes a substrate 110, and a thin film transistor 100 and a pull-down capacitor 200 stacked on the same side of the substrate 110.
  • the thin film transistor 100 may be a thin film transistor corresponding to a sub-pixel region, and the pull-down capacitor 200 is adjacent to The thin film transistor 100 is disposed.
  • the thin film transistor 100 includes a gate electrode 120, a gate insulating layer 130, and a channel layer 140 which are sequentially stacked on a surface of the substrate 110.
  • the thin film transistor 100 further includes a source 150, a drain 160, and a passivation layer 170.
  • the source 150 and the drain 160 are disposed on the channel layer 140, and the source 150 and the The drains 160 are spaced apart.
  • the passivation layer 170 is stacked on the source 150, the drain 160, and the channel layer 140.
  • the passivation layer 170 is provided with a through hole 171, and the through hole 171 corresponds to the drain.
  • the pole 160 is disposed, and the pixel electrode 300 is connected to the drain 160 through the through hole 171.
  • the pull-down capacitor 200 includes a first conductive layer 210, a first isolation layer 220, a filling layer 230, a second isolation layer 240, and a second conductive layer 250 which are sequentially stacked on the surface of the substrate 110. Said The second conductive layer 250 is located in a different plane from the pixel electrode 300. In other words, the second conductive layer 250 and the pixel electrode 300 are not in the same plane.
  • the substrate 110 includes a first surface a and a second surface b disposed opposite to each other.
  • the thin film transistor 100 and the pull-down capacitor 200 are disposed on the first surface a of the substrate 110.
  • the thin film transistor 100 and the pull-down capacitor 200 are disposed on the second surface b of the substrate 110.
  • the substrate 110 is a transparent substrate.
  • the substrate 110 is a glass substrate. It can be understood that in other embodiments, the substrate 110 can also be a plastic substrate.
  • the array substrate 100 further includes a buffer layer (not shown), and the buffer layer is disposed on the substrate 110.
  • the buffer layer is used to buffer stress received during the fabrication of the thin film transistor 100 and the pull-down capacitor 200 on the substrate 110 to avoid damage or cracking of the substrate 110.
  • the material of the buffer layer is selected from one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • the gate 120 is disposed in the middle of the first surface a of the substrate 110.
  • the material of the gate 120 is metal or alloy.
  • the material of the gate 120 is selected from the group consisting of copper, tungsten, and chromium. One of aluminum and its combination.
  • the gate insulating layer 130 covers the gate 120 and the first surface a of the substrate 110 that does not cover the gate 120.
  • the material of the gate insulating layer 130 may be one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • the channel layer 140 is disposed on the gate insulating layer 130, and the channel layer 140 is configured to generate a current under the control of the gate 120 or generate no current under the control of the gate 120.
  • the channel layer 140 is a channel through which current flows in the thin film transistor 100.
  • the source 150 and the drain 160 are disposed on the channel layer 140, and the source 150 and the drain 160 are spaced apart.
  • the gate 120 of the thin film transistor 100 controls the passage of current in the channel layer 140, the source 150 and the drain 160 are turned on, and the thin film transistor 100 is in an on state;
  • the gate 120 of the thin film transistor 100 controls that the channel layer 140 has no current, the source 150 and the drain 160 are turned off, and the thin film transistor 100 is turned off. status.
  • the passivation layer 170 covers the source 150, the drain 160, and the channel layer 140 that does not cover the source 150 and the drain 160.
  • a via hole 171 is disposed on the passivation layer 170, and the through hole 171 is disposed corresponding to the drain 160.
  • a pixel electrode 300 is connected to the drain electrode 160 through the through hole 171.
  • the material of the pixel electrode 300 is a transparent conductive material, and the pixel electrode 300 includes one or any combination of indium tin oxide, indium zinc oxide, indium oxide or zinc oxide.
  • the pull-down capacitor 200 includes a first conductive layer 210, a first isolation layer 220, a filling layer 230, a second isolation layer 240, and a second conductive layer 250 which are sequentially stacked on the surface of the substrate 100.
  • the first conductive layer 210 of the pull-down capacitor 200 is disposed at a middle portion of the first surface of the substrate 110.
  • the first conductive layer 210 is spaced apart from the gate 120 and is located on the same plane.
  • the material of the gate 210 is metal or alloy.
  • the material of the gate 210 is selected from one of copper, tungsten, chromium, aluminum, and combinations thereof.
  • the first conductive layer 210 of the pull-down capacitor 200 is formed in the same process as the gate 120 of the thin film transistor 100 to save the preparation process of the array substrate 10.
  • the first conductive layer 210 and the gate 120 may be formed as follows. First, a metal layer is formed on the first surface a of the substrate 110. For convenience of description, the metal layer here is referred to as a first metal layer; then, the first metal layer is patterned to form The gate 120 and the first conductive layer 210 are disposed at intervals.
  • the first isolation layer 220 of the pull-down capacitor 200 is formed in the same process as the channel layer 140 to save the preparation process of the array substrate 10.
  • the material of the first isolation layer 220 and the channel layer 140 may be amorphous silicon ( ⁇ -Si).
  • the filling layer 230 of the pull-down capacitor 200 is formed in the same process as the source 150 and the drain 160 to save the preparation process of the array substrate 10.
  • the material of the filling layer 230 is the same as the material of the source 150 and the drain 160.
  • the material of the filling layer 230, the source 150 and the drain 160 may be one selected from the group consisting of copper, tungsten, chromium, aluminum, and combinations thereof.
  • the preparation process of the filling layer 230, the source 150, and the drain 160 is as follows. First, a metal layer is formed on the channel layer 140 and the first isolation layer 220.
  • the metal layer here is referred to as a second metal layer; then, the second metal layer is patterned Forming the source 150 and the drain 160 disposed on the channel layer 140 and spaced apart, and The filling layer 230 disposed on the first isolation layer 220.
  • the second isolation layer 240 of the pull-down capacitor 200 is formed in the same process as the passivation layer 170 to save the preparation process of the array substrate 10.
  • the second conductive layer 250 and the pixel electrode 300 are also formed in the same process to save the preparation process of the array substrate 10.
  • the second conductive layer 250 is higher than the pixel electrode 300 by 0.3 um to 0.6 um. The height difference is sufficient for the second conductive layer 250 to be in a different plane from the pixel electrode 300, thereby effectively reducing the probability of a short circuit occurring between the second conductive layer 250 and the pixel electrode 300.
  • the filling layer 230 is added in the pull-down capacitor 200 such that the second conductive layer 250 of the pull-down capacitor 200 is not in the same plane as the pixel electrode 300, thereby The distance between the second conductive layer 250 and the pixel electrode 300 is increased. Therefore, a short circuit between the second conductive layer 250 and the pixel electrode 300 is less likely to occur, thereby improving the display of the array substrate 10. quality.
  • FIG. 4 is a cross-sectional structural diagram of a display device according to a preferred embodiment of the present invention.
  • the display device 1 includes an array substrate 10 and a color filter substrate 20, and the array substrate 10 and the color filter substrate 20 are oppositely disposed.
  • the specific structure of the array substrate 10 is as shown in FIG.
  • the display device 1 is a liquid crystal display device, and the display device 1 further includes a liquid crystal layer 30 disposed between the array substrate 10 and the color filter substrate 20.
  • the array substrate 10 includes a substrate 110, and a thin film transistor 100 and a pull-down capacitor 200 stacked on the same surface of the substrate 110, the pull-down capacitor 200 being disposed adjacent to the thin film transistor 100.
  • the thin film transistor 100 includes a gate electrode 120, a gate insulating layer 130, and a channel layer 140 which are sequentially stacked on a surface of the substrate 110.
  • the thin film transistor 100 further includes a source 150, a drain 160, and a passivation layer 170.
  • the source 150 and the drain 160 are disposed on the channel layer 140, and the source 150 and the The drains 160 are spaced apart.
  • the passivation layer 170 is stacked on the source 150, the drain 160, and the channel layer 140.
  • the passivation layer 170 is provided with a through hole 171, and the through hole 171 corresponds to the drain.
  • the pole 160 is disposed, and the pixel electrode 300 is connected to the drain 160 through the through hole 171.
  • the pull-down capacitor 200 includes a first conductive layer 210, a first isolation layer 220, a filling layer 230, a second isolation layer 240, and a second conductive layer 250 which are sequentially stacked on the surface of the substrate 110.
  • the second conductive layer 250 is different from the pixel electrode 300 In the plane. In other words, the second conductive layer 250 and the pixel electrode 300 are not in the same plane.
  • the substrate 110 includes a first surface a and a second surface b disposed oppositely.
  • the thin film transistor 100 and the pull-down capacitor 200 are disposed on the first surface a of the substrate 110.
  • the first surface a is disposed adjacent to the liquid crystal layer 30.
  • the thin film transistor 100 and the pull-down capacitor 200 are disposed on the second surface b of the substrate 110, and the second surface b is disposed adjacent to the liquid crystal layer 30.
  • the substrate 110 is a transparent substrate.
  • the substrate 110 is a glass substrate. It can be understood that in other embodiments, the substrate 110 can also be a plastic substrate.
  • the array substrate 100 further includes a buffer layer (not shown).
  • the thin film transistor 100 and the pull-down capacitor 200 are disposed on the surface of the substrate 100 through the buffer layer.
  • the buffer layer is used to buffer stress received during the fabrication of the thin film transistor 100 and the pull-down capacitor 200 on the substrate 110 to avoid damage or cracking of the substrate 110.
  • the material of the buffer layer is selected from one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • the gate 120 is disposed in the middle of the first surface a of the substrate 110.
  • the material of the gate 120 is metal or alloy.
  • the material of the gate 120 is selected from the group consisting of copper, tungsten, and chromium. One of aluminum and its combination.
  • the gate insulating layer 130 covers the gate 120 and the first surface a of the substrate 110 that does not cover the gate 120.
  • the material of the gate insulating layer 130 may be one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • the channel layer 140 is disposed on the gate insulating layer 130, and the channel layer 140 is configured to generate a current under the control of the gate 120 or generate no current under the control of the gate 120.
  • the channel layer 140 is a channel through which current flows in the thin film transistor 100.
  • the source 150 and the drain 160 are disposed on the channel layer 140, and the source 150 and the drain 160 are spaced apart.
  • the gate 120 of the thin film transistor 100 controls the passage of current in the channel layer 140, the source 150 and the drain 160 are turned on, and the thin film transistor 100 is in an on state;
  • the gate 120 of the thin film transistor 100 controls the channel layer 140 to be electrically When the flow passes, the source 150 and the drain 160 are turned off, and the thin film transistor 100 is in an off state.
  • the passivation layer 170 covers the source 150, the drain 160, and the channel layer 140 that does not cover the source 150 and the drain 160.
  • a via hole 171 is disposed on the passivation layer 170, and the through hole 171 is disposed corresponding to the drain 160.
  • a pixel electrode 300 is connected to the drain electrode 160 through the through hole 171.
  • the material of the pixel electrode 300 is a transparent conductive material, and the pixel electrode 300 includes one or any combination of indium tin oxide, indium zinc oxide, indium oxide or zinc oxide.
  • the pull-down capacitor 200 includes a first conductive layer 210, a first isolation layer 220, a filling layer 230, a second isolation layer 240, and a second conductive layer 250 which are sequentially stacked on the surface of the substrate 100.
  • the first conductive layer 210 of the pull-down capacitor 200 is disposed at a middle portion of the first surface of the substrate 110.
  • the first conductive layer 210 is spaced apart from the gate 120.
  • the material of the gate 210 is metal or alloy.
  • the material of the gate 210 is selected from one of copper, tungsten, chromium, aluminum, and combinations thereof.
  • the first conductive layer 210 of the pull-down capacitor 200 is formed in the same process as the gate 120 of the thin film transistor 100 to save the preparation process of the array substrate 10.
  • the first conductive layer 210 and the gate 120 may be formed as follows. First, a metal layer is formed on the first surface a of the substrate 110. For convenience of description, the metal layer here is referred to as a first metal layer; then, the first metal layer is patterned to form The gate 120 and the first conductive layer 210 are disposed at intervals.
  • the first isolation layer 220 of the pull-down capacitor 200 is formed in the same process as the channel layer 140 to save the preparation process of the array substrate 10.
  • the material of the first isolation layer 220 and the channel layer 140 may be amorphous silicon.
  • the filling layer 230 of the pull-down capacitor 200 is formed in the same process as the source 150 and the drain 160 to save the preparation process of the array substrate 10.
  • the material of the filling layer 230 is the same as the material of the source 150 and the drain 160.
  • the material of the filling layer 230, the source 150 and the drain 160 may be one selected from the group consisting of copper, tungsten, chromium, aluminum, and combinations thereof.
  • the preparation process of the filling layer 230, the source 150, and the drain 160 is as follows. First, a metal layer is formed on the channel layer 140 and the first isolation layer 220.
  • the metal layer here is referred to as a second metal layer; then, the second metal layer is patterned To The source 150 and the drain 160 disposed on the channel layer 140 and spaced apart from each other, and the filling layer 230 disposed on the first isolation layer 220 are formed.
  • the second isolation layer 240 of the pull-down capacitor 200 is formed in the same process as the passivation layer 170 to save the preparation process of the array substrate 10.
  • the second conductive layer 250 and the pixel electrode 300 are also formed in the same process to save the preparation process of the array substrate 10.
  • the second conductive layer 250 is higher than the pixel electrode 300 by 0.3 um to 0.6 um. The height difference is sufficient for the second conductive layer 250 to be in a different plane from the pixel electrode 300, thereby effectively reducing the probability of a short circuit occurring between the second conductive layer 250 and the pixel electrode 300.
  • the filling layer 230 is added in the pull-down capacitor 200 such that the second conductive layer 250 of the pull-down capacitor 200 is not in the same plane as the pixel electrode 300. Therefore, the distance between the second conductive layer 250 and the pixel electrode 300 is increased, and therefore, a short circuit between the second conductive layer 250 and the pixel electrode 300 is less likely to occur, thereby improving the display device. 1 display quality.
  • FIG. 5 is a flow chart of a method for fabricating an array substrate according to a preferred embodiment of the present invention.
  • the preparation method of the array substrate includes, but is not limited to, the following steps.
  • a substrate 101 is provided.
  • the substrate 101 includes opposing first and second surfaces a and b.
  • Step S102 a first metal layer is disposed on a surface of the substrate 101, the first metal layer is patterned to form a gate electrode 102 and a first conductive layer 210, and the gate electrode 102 and the first conductive layer 210 are spaced apart Settings.
  • Step S103 forming a gate insulating layer 130 on the gate 102.
  • Step S104 disposing a first semiconductor layer, patterning the first semiconductor layer to form a channel layer 140 disposed on the gate insulating layer 130, and first isolation disposed on the first conductive layer 120 Layer 220.
  • Step S105 providing a second metal layer, patterning the second metal layer to form a source 150 and a drain 160 disposed on both sides of the channel layer 140, and disposed on the first isolation layer 220
  • the filling layer 230; the sum of the thickness of the filling layer 230 and the first isolation layer 220 is greater than the sum of the thicknesses of the drain 160 and the channel layer 140.
  • Step S106 providing an insulating layer, defining an insulating layer disposed on the source 150, the drain 160, and the channel layer 140 as a passivation layer 170, defining an insulating layer disposed on the filling layer 230 Is the second isolation layer 240.
  • Step S107 forming a second conductive layer 250 on the second isolation layer 240.
  • the gate 120, the gate insulating layer 130, the channel layer 140, the source 150, and the drain 160 are defined as a thin film transistor 100; the first conductive layer 210, the first The isolation layer 220, the filling layer 230, the second isolation layer 240, and the second conductive layer 250 are defined as pull-down capacitors 200.
  • the thin film transistor 100 and the pull-down capacitor 200 are spaced apart.
  • step S108 a through hole 171 is formed on the passivation layer 170 corresponding to the drain 160, and a pixel electrode 300 is disposed on the passivation layer 170 corresponding to the through hole 171.
  • the filling layer 230 is formed in the same process as the source 150 and the drain 160 to save the preparation process.
  • the first conductive layer 210 and the gate electrode 120 are formed in the same process to save the preparation process.
  • the first isolation layer 220 and the channel layer 140 are formed in the same process to save the preparation process.
  • the second isolation layer 240 is formed in the same process as the passivation layer 170 to save the preparation process.

Landscapes

  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板(10)、显示装置(1)和阵列基板(10)的制备方法。阵列基板(10)包括：基板(110)，以及设置在基板(110)同一表面上的薄膜晶体管(100)及下拉电容(200)，下拉电容(200)邻近薄膜晶体管(100)设置；薄膜晶体管(100)包括：依次层叠设置在基板(110)的表面上的栅极(120)、栅极绝缘层(130)及沟道层(140)；源极(150)和漏极(160)，源极(150)和漏极(160)设置在沟道层(140)上，且源极(150)与漏极(160)间隔设置；钝化层(170)，层叠设置在源极(150)、漏极(160)及沟道层(140)上，钝化层(170)上设置贯穿孔(171)，贯穿孔(171)对应漏极(160)设置，像素电极(300)通过贯穿孔(171)与漏极(160)相连；下拉电容(200)包括：依次层叠设置在基板(110)的表面上的第一导电层(210)、第一隔离层(220)、填充层(230)、第二隔离层(240)及第二导电层(250)；所述填充层(230)的厚度与所述第一隔离层(220)的厚度之和大于漏极(160)与沟道层(140)的厚度之和，以使第二导电层(250)与像素电极(300)位于不同的平面内。

Description

阵列基板、显示装置及阵列基板的制备方法
本发明要求2014年12月31日递交的发明名称为“阵列基板、显示装置及阵列基板的制备方法”的申请号201410855413.8的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示领域，尤其涉及一种阵列基板及显示装置。
背景技术
液晶显示装置作为一种常见的显示装置，由于其具有低功耗、体积小、质量轻等特点，而备受用户的青睐。采用垂直配向技术的薄膜晶体管液晶显示装置(Thin Film Transistor Liquid Crystal Display,TFT-LCD)中，通常将像素划分为主(Main)区域和次(Sub)区域，并使次区域的像素电压低于主区域的像素电压，以改善大视角色偏。通常情况下，设置主区域的薄膜晶体管和次区域的薄膜晶体管的阵列基板上还设置下拉电容，所述下拉电容和所述次区域的薄膜晶体管配合，分担次区域的薄膜晶体管上的一部分电荷，以使次区域的像素电压降低到适当的比例。所述下拉电容采用的是MII结构。所述MII结构的下拉电容的结构通常为金属层、第一绝缘层(比如G-SiNx)、第二绝缘层(PA-SiNx)和透明导电层。由此可见，所述MII结构的下拉电容的最上层通常为透明导电层，比如氧化铟锡(Indium Tin Oxides，ITO)。次区域的薄膜晶体管的最上层也为透明导电层(可以为像素电极)，次区域的薄膜晶体管的最上层的透明导电层和MII结构的下拉电容的最上层的透明导电层位于同一层上，且彼此之间间隔较小。在阵列基板的制备过程中比如在蚀刻或者显影的过程中，容易产生透明导电层的残留，使得次区域的薄膜晶体管(Sub TFT)的最上层的透明导电层和MII结构的下拉电容的最上层的透明导电层之间发生短路，从而导致该下拉电容不能正常地拉低次区域的像素电压，从而导致所述像素产生微亮点，进而影响显示装置的显示品质。请参阅图1和图2，图1为现有技术中次区域的薄膜晶体管最上层的透明导电层与下拉电容最上层的透明 导电层之间发生短路的示意图；图2为现有技术中显示装置产生微亮点的示意图。在图1和图2中，所述次区域的薄膜晶体管最上层的透明导电层与下拉电容最上层的透明导电层之间发生短路而产生微亮点在图中以SP表示，下拉电容以C表示。
发明内容
本发明提供了一种阵列基板，所述阵列基板具有较高的显示品质。
所述阵列基板包括：
基板，以及设置在所述基板同一表面上的薄膜晶体管及下拉电容，所述下拉电容邻近所述薄膜晶体管设置；
所述薄膜晶体管包括：
依次层叠设置在所述基板的表面上的栅极、栅极绝缘层及沟道层；
源极和漏极，所述源极和所述漏极设置在所述沟道层上，且所述源极与所述漏极间隔设置；
钝化层，层叠设置在所述源极、所述漏极及所述沟道层上，所述钝化层上设置贯穿孔，所述贯穿孔对应所述漏极设置，像素电极通过所述贯穿孔与所述漏极相连；
所述下拉电容包括：
依次层叠设置在所述基板的表面上的第一导电层、第一隔离层、填充层、第二隔离层及第二导电层；所述填充层的厚度与所述第一隔离层的厚度之和大于所述漏极与所述沟道层的厚度之和，以使得所述第二导电层与所述像素电极位于不同的平面内。
其中，所述填充层的厚度大于所述源极的厚度且所述填充层的厚度大于所述漏极的厚度。
其中，所述填充层的厚度与所述第一隔离层的厚度之和大于所述漏极与所述沟道层的厚度之和0.3um～0.6um以使得所述第二导电层比所述像素电极高出0.3um～0.6um。
其中，所述填充层的材质为金属或者合金。
一方面提供了一种显示装置，所述显示装置包括上述各个实施方式中任意 一种实施方式的阵列基板。
一方面提供了一种阵列基板的制备方法，所述阵列基板的制备方法包括：
提供一基板；
在所述基板的表面设置第一金属层，图案化所述第一金属层以形成栅极和第一导电层，所述栅极和所述第一导电层间隔设置；
在所述栅极上形成栅极绝缘层；
设置第一半导体层，图案化所述第一半导体层，以形成设置在所述栅极绝缘层上的沟道层以及设置在所述第一导电层上的第一隔离层；
设置第二金属层，图案化所述第二金属层，以形成设置在所述沟道层两侧的源极和漏极，以及设置在所述第一隔离层上的填充层；所述填充层与所述第一隔离层的厚度之和大于所述漏极与所述沟道层的厚度之和；
设置绝缘层，定义设置在所述源极、所述漏极及所述沟道层上的绝缘层为钝化层，定义设置在所述填充层上的绝缘层为第二隔离层；
在所述第二隔离层上形成第二导电层；所述栅极、所述栅极绝缘层、所述沟道层、所述源极、所述漏极定义为薄膜晶体管；所述第一导电层、所述第一隔离层、所述填充层、所述第二隔离层及所述第二导电层定义为下拉电容；
在所述钝化层上对应所述漏极形成贯穿孔，在所述钝化层上对应所述贯穿孔设置像素电极。
其中，所述填充层与所述源极及所述漏极在同一制程中形成。
其中，所述第一导电层与所述栅极在同一制程中形成，所述第一隔离层与所述沟道层在同一制程中形成。
其中，所述第二隔离层与所述钝化层在同一制程中形成。
其中，所述填充层的厚度大于所述源极的厚度且所述填充层的厚度大于所述漏极的厚度。
在本发明的阵列基板及显示装置中，通过在所述下拉电容中增加了填充层，以使得所述下拉电容的所述第二导电层与所述像素电极不在同一平面内，从而增加了所述第二导电层与所述像素电极之间的距离，因此，第二导电层与所述像素电极之间不容易发生短路，从而提升了所述显示装置的显示品质。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中次区域的薄膜晶体管最上层的透明导电层与下拉电容最上层的透明导电层之间发生短路的示意图。
图2为现有技术中显示装置产生微亮点的示意图。
图3为本发明一较佳实施方式的阵列基板的剖面结构示意图。
图4为本发明一较佳实施方式的显示装置的剖面结构示意图。
图5为本发明一较佳实施方式的阵列基板的制备方法的流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图3，图3为本发明一较佳实施方式的阵列基板的剖面结构示意图。所述阵列基板10包括基板110，以及层叠设置在所述基板110的同一侧的薄膜晶体管100和下拉电容200，所述薄膜晶体管100可以为对应次像素区域的薄膜晶体管，所述下拉电容200邻近所述薄膜晶体管100设置。所述薄膜晶体管100包括依次层叠设置在所述基板110的表面上的栅极120、栅极绝缘层130及沟道层140。所述薄膜晶体管100还包括源极150、漏极160和钝化层170，所述源极150和所述漏极160设置在所述沟道层140上，且所述源极150和所述漏极160间隔设置。所述钝化层170层叠设置在所述源极150、所述漏极160及所述沟道层140上，所述钝化层170上设置贯穿孔171，所述贯穿孔171对应所述漏极160设置，像素电极300通过所述贯穿孔171与所述漏极160相连。所述下拉电容200包括依次层叠设置在所述基板110的表面上的第一导电层210、第一隔离层220、填充层230、第二隔离层240及第二导电层250。所述 第二导电层250与所述像素电极300位于不同的平面内。换句话说，所述第二导电层250与所述像素电极300不位于同一平面内。
所述基板110包括相对设置的第一表面a和第二表面b，在本实施方式中，所述薄膜晶体管100及所述下拉电容200设置在所述基板110的所述第一表面a上。在其他实施方式中，所述薄膜晶体管100及所述下拉电容200设置在所述基板110的所述第二表面b上。所述基板110为透明的基板，在本实施方式中，所述基板110为玻璃基板。可以理解地，在其他实施方式中，所述基板110也可以为塑料基板。
在一实施方式中，所述阵列基板100还包括缓冲层(图未示)，所述缓冲层设置在基板110上，此时，所述薄膜晶体管100以及所述下拉电容200通过所述缓冲层设置在所述基板100的表面上。所述缓冲层用于缓冲在所述基板110上制作所述薄膜晶体管100以及所述下拉电容200的过程中受到的应力，以避免所述基板110的损坏或者破裂。所述缓冲层的材质选自氧化硅层，氮化硅层，氮氧化硅层及其组合的其中之一。
所述栅极120设置在所述基板110的第一表面a的中部，所述栅极120的材质为金属或者合金，举例而言，所述栅极120的材质选自铜、钨、铬、铝及其组合的其中之一。
所述栅极绝缘层130覆盖在所述栅极120以及所述基板110的未覆盖所述栅极120的第一表面a上。所述栅极绝缘层130的材质可以为氧化硅层，氮化硅层，氮氧化硅层及其组合的其中之一。
所述沟道层140设置于所述栅极绝缘层130上，所述沟道层140用于在所述栅极120的控制下产生电流或者在所述栅极120的控制下不产生电流。当所述薄膜晶体管100导通时，所述沟道层140为所述薄膜晶体管100中电流流过的通道。
所述源极150和所述漏极160设置在所述沟道层140上，且所述源极150和所述漏极160间隔设置。当所述薄膜晶体管100的栅极120控制所述沟道层140中有电流通过时，所述源极150和所述漏极160导通，所述薄膜晶体管100处于导通状态；当所述薄膜晶体管100的栅极120控制所述沟道层140没有电流通过时，所述源极150和所述漏极160关断，所述薄膜晶体管100处于断开 状态。
所述钝化层170覆盖所述源极150、所述漏极160以及未覆盖所述源极150和所述漏极160的所述沟道层140。所述钝化层170上设置贯穿孔(via hole)171，所述贯穿孔171对应所述漏极160设置。一像素电极300通过所述贯穿孔171与所述漏极160相连。所述像素电极300的材质为透明导电材料，所述像素电极300包含铟锡氧化物、铟锌氧化物、氧化铟或者氧化锌等之一或者任意组合。
所述下拉电容200包括依次层叠设置在所述基板100的表面上的第一导电层210、第一隔离层220、填充层230、第二隔离层240及第二导电层250。
所述下拉电容200的所述第一导电层210设置在所述基板110的第一表面的中部。所述第一导电层210与所述栅极120间隔设置，并位于同一平面。所述栅极210的材质为金属或者合金，举例而言，所述栅极210的材质选自铜、钨、铬、铝及其组合的其中之一。优选地，所述下拉电容200的所述第一导电层210与所述薄膜晶体管100的所述栅极120在同一制程中形成，以节约所述阵列基板10的制备工序。所述第一导电层210及所述栅极120可以通过如下方式形成。首先，在所述基板110的所述第一表面a上形成一层金属层，为了方便描述，此处的金属层称为第一金属层；接着，图案化所述第一金属层，以形成间隔设置的所述栅极120和所述第一导电层210。
所述下拉电容200的所述第一隔离层220与所述沟道层140在同一制程中形成，以节约所述阵列基板10的制备工序。所述第一隔离层220和所述沟道层140的材质可以为非晶硅(amorphous silicon，α-Si)。
所述下拉电容200的所述填充层230与所述源极150及所述漏极160在同一制程中形成，以节约所述阵列基板10的制备工序。在本实施方式中，所述填充层230的材料与所述源极150及所述漏极160的材料相同。所述填充层230、所述源极150及所述漏极160的材质可以为选自铜、钨、铬、铝及其组合的其中之一。所述填充层230、所述源极150及所述漏极160的制备过程如下。首先，在所述沟道层140及所述第一隔离层220上形成一层金属层，为了方便描述，此处的金属层称为第二金属层；接着，图案化所述第二金属层，以形成设置在所述沟道层140上且间隔设置的所述源极150和所述漏极160，及 设置在所述第一隔离层220上的所述填充层230。
所述下拉电容200的所述第二隔离层240与钝化层170在同一制程中形成，以节约所述阵列基板10的制备工序。所述第二导电层250与所述像素电极300也在同一制程中形成，以节约所述阵列基板10的制备工序。在本实施方式中，所述第二导电层250比所述像素电极300高出0.3um～0.6um。此高度差足够使得所述第二导电层250与所述像素电极300位于不同的平面内，从而有效减小第二导电层250及所述像素电极300之间发生短路的几率。
在本发明的阵列基板10中，通过在所述下拉电容200中增加了填充层230，以使得所述下拉电容200的所述第二导电层250与所述像素电极300不在同一平面内，从而增加了所述第二导电层250与所述像素电极300之间的距离，因此，第二导电层250与所述像素电极300之间不容易发生短路，从而提升了所述阵列基板10的显示品质。
下面结合图3对本发明的显示装置进行介绍。请一并参阅图4，图4为本发明一较佳实施方式的显示装置的剖面结构示意图。所述显示装置1包括阵列基板10和彩色滤光基板20，所述阵列基板10和所述彩色滤光基板20相对设置。所述阵列基板10的具体结构如图3所示。在本实施方式中，所述显示装置1为液晶显示装置，所述显示装置1还包括设置在所述阵列基板10和所述彩色滤光基板20之间的液晶层30。
所述阵列基板10包括基板110，以及层叠设置在所述基板110的同一表面的薄膜晶体管100和下拉电容200，所述下拉电容200邻近所述薄膜晶体管100设置。所述薄膜晶体管100包括依次层叠设置在所述基板110的表面上的栅极120、栅极绝缘层130及沟道层140。所述薄膜晶体管100还包括源极150、漏极160和钝化层170，所述源极150和所述漏极160设置在所述沟道层140上，且所述源极150和所述漏极160间隔设置。所述钝化层170层叠设置在所述源极150、所述漏极160及所述沟道层140上，所述钝化层170上设置贯穿孔171，所述贯穿孔171对应所述漏极160设置，像素电极300通过所述贯穿孔171与所述漏极160相连。所述下拉电容200包括依次层叠设置在所述基板110的表面上的第一导电层210、第一隔离层220、填充层230、第二隔离层240及第二导电层250。所述第二导电层250与所述像素电极300位于不同的 平面内。换句话说，所述第二导电层250与所述像素电极300不位于同一平面内。
所述基板110包括相对设置的第一表面a和第二表面b，在本实施方式中，所述薄膜晶体管100及所述下拉电容200设置在所述基板110的所述第一表面a上，所述第一表面a邻近所述液晶层30设置。在其他实施方式中，所述薄膜晶体管100及所述下拉电容200设置在所述基板110的所述第二表面b上，所述第二表面b邻近所述液晶层30设置。所述基板110为透明的基板，在本实施方式中，所述基板110为玻璃基板。可以理解地，在其他实施方式中，所述基板110也可以为塑料基板。
在一实施方式中，所述阵列基板100还包括缓冲层(图未示)，此时，所述薄膜晶体管100以及所述下拉电容200通过所述缓冲层设置在所述基板100的表面上。所述缓冲层用于缓冲在所述基板110上制作所述薄膜晶体管100以及所述下拉电容200的过程中受到的应力，以避免所述基板110的损坏或者破裂。所述缓冲层的材质选自氧化硅层，氮化硅层，氮氧化硅层及其组合的其中之一。
所述栅极120设置在所述基板110的第一表面a的中部，所述栅极120的材质为金属或者合金，举例而言，所述栅极120的材质选自铜、钨、铬、铝及其组合的其中之一。
所述栅极绝缘层130覆盖在所述栅极120以及所述基板110的未覆盖所述栅极120的第一表面a上。所述栅极绝缘层130的材质可以为氧化硅层，氮化硅层，氮氧化硅层及其组合的其中之一。
所述沟道层140设置于所述栅极绝缘层130上，所述沟道层140用于在所述栅极120的控制下产生电流或者在所述栅极120的控制下不产生电流。当所述薄膜晶体管100导通时，所述沟道层140为所述薄膜晶体管100中电流流过的通道。
所述源极150和所述漏极160设置在所述沟道层140上，且所述源极150和所述漏极160间隔设置。当所述薄膜晶体管100的栅极120控制所述沟道层140中有电流通过时，所述源极150和所述漏极160导通，所述薄膜晶体管100处于导通状态；当所述薄膜晶体管100的栅极120控制所述沟道层140没有电 流通过时，所述源极150和所述漏极160关断，所述薄膜晶体管100处于断开状态。
所述钝化层170覆盖所述源极150、所述漏极160以及未覆盖所述源极150和所述漏极160的所述沟道层140。所述钝化层170上设置贯穿孔(via hole)171，所述贯穿孔171对应所述漏极160设置。一像素电极300通过所述贯穿孔171与所述漏极160相连。所述像素电极300的材质为透明导电材料，所述像素电极300包含铟锡氧化物、铟锌氧化物、氧化铟或者氧化锌等之一或者任意组合。
所述下拉电容200包括依次层叠设置在所述基板100的表面上的第一导电层210、第一隔离层220、填充层230、第二隔离层240及第二导电层250。
所述下拉电容200的所述第一导电层210设置在所述基板110的第一表面的中部。所述第一导电层210与所述栅极120间隔设置。所述栅极210的材质为金属或者合金，举例而言，所述栅极210的材质选自铜、钨、铬、铝及其组合的其中之一。优选地，所述下拉电容200的所述第一导电层210与所述薄膜晶体管100的所述栅极120在同一制程中形成，以节约所述阵列基板10的制备工序。所述第一导电层210及所述栅极120可以通过如下方式形成。首先，在所述基板110的所述第一表面a上形成一层金属层，为了方便描述，此处的金属层称为第一金属层；接着，图案化所述第一金属层，以形成间隔设置的所述栅极120和所述第一导电层210。
所述下拉电容200的所述第一隔离层220与所述沟道层140在同一制程中形成，以节约所述阵列基板10的制备工序。所述第一隔离层220和所述沟道层140的材质可以为非晶硅。
所述下拉电容200的所述填充层230与所述源极150及所述漏极160在同一制程中形成，以节约所述阵列基板10的制备工序。在本实施方式中，所述填充层230的材料与所述源极150及所述漏极160的材料相同。所述填充层230、所述源极150及所述漏极160的材质可以为选自铜、钨、铬、铝及其组合的其中之一。所述填充层230、所述源极150及所述漏极160的制备过程如下。首先，在所述沟道层140及所述第一隔离层220上形成一层金属层，为了方便描述，此处的金属层称为第二金属层；接着，图案化所述第二金属层，以 形成设置在所述沟道层140上且间隔设置的所述源极150和所述漏极160，及设置在所述第一隔离层220上的所述填充层230。
所述下拉电容200的所述第二隔离层240与钝化层170在同一制程中形成，以节约所述阵列基板10的制备工序。所述第二导电层250与所述像素电极300也在同一制程中形成，以节约所述阵列基板10的制备工序。在本实施方式中，所述第二导电层250比所述像素电极300高出0.3um～0.6um。此高度差足够使得所述第二导电层250与所述像素电极300位于不同的平面内，从而有效减小第二导电层250及所述像素电极300之间发生短路的几率。
在本发明显示装置1的阵列基板10中，通过在所述下拉电容200中增加了填充层230，以使得所述下拉电容200的所述第二导电层250与所述像素电极300不在同一平面内，从而增加了所述第二导电层250与所述像素电极300之间的距离，因此，第二导电层250与所述像素电极300之间不容易发生短路，从而提升了所述显示装置1的显示品质。
下面结合图3和图4对本发明的阵列基板的制备方法进行介绍。请参阅图5，图5为本发明一较佳实施方式的阵列基板的制备方法的流程图。所述阵列基板的制备方法包括但不仅限于以下步骤。
步骤S101，提供一基板101。所述基板101包括相对的第一表面a和第二表面b。
步骤S102，在所述基板101的表面设置第一金属层，图案化所述第一金属层以形成栅极102和第一导电层210，所述栅极102和所述第一导电层210间隔设置。
步骤S103，在所述栅极102上形成栅极绝缘层130。
步骤S104，设置第一半导体层，图案化所述第一半导体层，以形成设置在所述栅极绝缘层130上的沟道层140以及设置在所述第一导电层120上的第一隔离层220。
步骤S105，设置第二金属层，图案化所述第二金属层，以形成设置在所述沟道层140两侧的源极150和漏极160，以及设置在所述第一隔离层220上的填充层230；所述填充层230与所述第一隔离层220的厚度之和大于所述漏极160与所述沟道层140的厚度之和。
步骤S106，设置绝缘层，定义设置在所述源极150、所述漏极160及所述沟道层140上的绝缘层为钝化层170，定义设置在所述填充层230上的绝缘层为第二隔离层240。
步骤S107，在所述第二隔离层240上形成第二导电层250。所述栅极120、所述栅极绝缘层130、所述沟道层140、所述源极150、所述漏极160定义为薄膜晶体管100；所述第一导电层210、所述第一隔离层220、所述填充层230、所述第二隔离层240及所述第二导电层250定义为下拉电容200。所述薄膜晶体管100及所述下拉电容200间隔设置。
步骤S108，在所述钝化层170上对应所述漏极160形成贯穿孔171，在所述钝化层170上对应所述贯穿孔171设置像素电极300。
优选地，所述填充层230与所述源极150、所述漏极160在同一制程中形成，以节约制备工序。
优选地，所述第一导电层210与所述栅极120在同一制程中形成，以节约制备工序。
优选地，所述第一隔离层220与所述沟道层140在同一制程中形成，以节约制备工序。
优选地，所述第二隔离层240与所述钝化层170在同一制程中形成，以节约制备工序。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (13)

  1. 一种阵列基板，其中，所述阵列基板包括：
    基板，以及设置在所述基板同一表面上的薄膜晶体管及下拉电容，所述下拉电容邻近所述薄膜晶体管设置；
    所述薄膜晶体管包括：
    依次层叠设置在所述基板的表面上的栅极、栅极绝缘层及沟道层；
    源极和漏极，所述源极和所述漏极设置在所述沟道层上，且所述源极与所述漏极间隔设置；
    钝化层，层叠设置在所述源极、所述漏极及所述沟道层上，所述钝化层上设置贯穿孔，所述贯穿孔对应所述漏极设置，像素电极通过所述贯穿孔与所述漏极相连；
    所述下拉电容包括：
    依次层叠设置在所述基板的表面上的第一导电层、第一隔离层、填充层、第二隔离层及第二导电层；所述填充层的厚度与所述第一隔离层的厚度之和大于所述漏极与所述沟道层的厚度之和，以使得所述第二导电层与所述像素电极位于不同的平面内。
  2. 如权利要求1所述的阵列基板，其中，所述填充层的厚度大于所述源极的厚度且所述填充层的厚度大于所述漏极的厚度。
  3. 如权利要求2所述的阵列基板，其中，所述填充层的厚度与所述第一隔离层的厚度之和大于所述漏极与所述沟道层的厚度之和0.3um～0.6um以使得所述第二导电层比所述像素电极高出0.3um～0.6um。
  4. 如权利要求1所述的阵列基板，其中，所述填充层的材质为金属或者合金。
  5. 一种显示装置，其中，所述显示装置包括阵列基板，所述阵列基板包括：
    基板，以及设置在所述基板同一表面上的薄膜晶体管及下拉电容，所述下拉电容邻近所述薄膜晶体管设置；
    所述薄膜晶体管包括：
    依次层叠设置在所述基板的表面上的栅极、栅极绝缘层及沟道层；
    源极和漏极，所述源极和所述漏极设置在所述沟道层上，且所述源极与所述漏极间隔设置；
    钝化层，层叠设置在所述源极、所述漏极及所述沟道层上，所述钝化层上设置贯穿孔，所述贯穿孔对应所述漏极设置，像素电极通过所述贯穿孔与所述漏极相连；
    所述下拉电容包括：
    依次层叠设置在所述基板的表面上的第一导电层、第一隔离层、填充层、第二隔离层及第二导电层；所述填充层的厚度与所述第一隔离层的厚度之和大于所述漏极与所述沟道层的厚度之和，以使得所述第二导电层与所述像素电极位于不同的平面内。
  6. 如权利要求5所述的显示装置，其中，所述填充层的厚度大于所述源极的厚度且所述填充层的厚度大于所述漏极的厚度。
  7. 如权利要求6所述的显示装置，其中，所述填充层的厚度与所述第一隔离层的厚度之和大于所述漏极与所述沟道层的厚度之和0.3um～0.6um以使得所述第二导电层比所述像素电极高出0.3um～0.6um。
  8. 如权利要求5所述的显示装置，其中，所述填充层的材质为金属或者合金。
  9. 一种阵列基板的制备方法，其中，所述阵列基板的制备方法包括：
    提供一基板；
    在所述基板的表面设置第一金属层，图案化所述第一金属层以形成栅极和第一导电层，所述栅极和所述第一导电层间隔设置；
    在所述栅极上形成栅极绝缘层；
    设置第一半导体层，图案化所述第一半导体层，以形成设置在所述栅极绝缘层上的沟道层以及设置在所述第一导电层上的第一隔离层；
    设置第二金属层，图案化所述第二金属层，以形成设置在所述沟道层两侧的源极和漏极，以及设置在所述第一隔离层上的填充层；所述填充层与所述第一隔离层的厚度之和大于所述漏极与所述沟道层的厚度之和；
    设置绝缘层，定义设置在所述源极、所述漏极及所述沟道层上的绝缘层为钝化层，定义设置在所述填充层上的绝缘层为第二隔离层；
    在所述第二隔离层上形成第二导电层；所述栅极、所述栅极绝缘层、所述沟道层、所述源极、所述漏极定义为薄膜晶体管；所述第一导电层、所述第一隔离层、所述填充层、所述第二隔离层及所述第二导电层定义为下拉电容；
    在所述钝化层上对应所述漏极形成贯穿孔，在所述钝化层上对应所述贯穿孔设置像素电极。
  10. 如权利要求9所述的阵列基板的制备方法，其中，所述填充层与所述源极及所述漏极在同一制程中形成。
  11. 如权利要求9所述的阵列基板的制备方法，其中，所述第一导电层与所述栅极在同一制程中形成，所述第一隔离层与所述沟道层在同一制程中形成。
  12. 如权利要求9所述的阵列基板的制备方法，其中，所述第二隔离层与所述钝化层在同一制程中形成。
  13. 如权利要求9所述的阵列基板的制备方法，其中，所述填充层的厚度大于所述源极的厚度且所述填充层的厚度大于所述漏极的厚度。
PCT/CN2015/071164 2014-12-31 2015-01-21 阵列基板、显示装置及阵列基板的制备方法 Ceased WO2016106891A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/435,512 US9589986B2 (en) 2014-12-31 2015-01-21 Array substrate, display device and method for fabricating array substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410855413.8A CN104538394B (zh) 2014-12-31 2014-12-31 阵列基板、显示装置及阵列基板的制备方法
CN201410855413.8 2014-12-31

Publications (1)

Publication Number Publication Date
WO2016106891A1 true WO2016106891A1 (zh) 2016-07-07

Family

ID=52853897

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/071164 Ceased WO2016106891A1 (zh) 2014-12-31 2015-01-21 阵列基板、显示装置及阵列基板的制备方法

Country Status (2)

Country Link
CN (1) CN104538394B (zh)
WO (1) WO2016106891A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107145016A (zh) * 2017-07-13 2017-09-08 深圳市华星光电技术有限公司 阵列基板、液晶面板及显示设备及阵列基板的制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030122987A1 (en) * 2001-12-28 2003-07-03 Myung-Joon Kim Array substrate for a liquid crystal display device having multi-layered metal line and fabricating method thereof
CN1610110A (zh) * 2003-10-14 2005-04-27 Lg.菲利浦Lcd株式会社 显示器件的薄膜晶体管基板及其制造方法
CN1702531A (zh) * 2004-05-27 2005-11-30 Lg.菲利浦Lcd株式会社 液晶显示器件及其制造方法
CN101452162A (zh) * 2007-12-07 2009-06-10 上海广电Nec液晶显示器有限公司 液晶显示面板中的阵列基板及其制造方法
CN104167425A (zh) * 2013-05-15 2014-11-26 三星显示有限公司 有机发光显示设备及其制造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101041088B1 (ko) * 2003-06-10 2011-06-13 삼성전자주식회사 반사-투과형 어레이 기판과, 이의 제조 방법 및 이를 갖는액정 표시 장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030122987A1 (en) * 2001-12-28 2003-07-03 Myung-Joon Kim Array substrate for a liquid crystal display device having multi-layered metal line and fabricating method thereof
CN1610110A (zh) * 2003-10-14 2005-04-27 Lg.菲利浦Lcd株式会社 显示器件的薄膜晶体管基板及其制造方法
CN1702531A (zh) * 2004-05-27 2005-11-30 Lg.菲利浦Lcd株式会社 液晶显示器件及其制造方法
CN101452162A (zh) * 2007-12-07 2009-06-10 上海广电Nec液晶显示器有限公司 液晶显示面板中的阵列基板及其制造方法
CN104167425A (zh) * 2013-05-15 2014-11-26 三星显示有限公司 有机发光显示设备及其制造方法

Also Published As

Publication number Publication date
CN104538394B (zh) 2019-02-12
CN104538394A (zh) 2015-04-22

Similar Documents

Publication Publication Date Title
US9508755B2 (en) Pixel unit and method of fabricating the same, array substrate and display device
CN105390551B (zh) 薄膜晶体管及其制造方法、阵列基板、显示装置
WO2016026246A1 (zh) 薄膜晶体管及其制备方法、阵列基板及其制备方法和显示装置
WO2015180320A1 (zh) 阵列基板及其制作方法、显示装置、薄膜晶体管及其制作方法
WO2016029612A1 (zh) 薄膜晶体管及其制备方法、显示基板及显示装置
WO2020154876A1 (zh) 薄膜晶体管及其制造方法、阵列基板和显示装置
US10615282B2 (en) Thin-film transistor and manufacturing method thereof, array substrate, and display apparatus
WO2016000342A1 (zh) 阵列基板及其制作方法、显示装置
CN105470196A (zh) 薄膜晶体管、阵列基板及其制造方法、和显示装置
WO2016086531A1 (zh) 阵列基板及其制作方法
WO2016095639A1 (zh) 阵列基板及其制造方法、显示装置
WO2016173012A1 (zh) 薄膜晶体管阵列基板及其制作方法
CN105810693A (zh) 阵列基板及其制作方法、显示装置
WO2015096381A1 (zh) 阵列基板及其制造方法和显示装置
US20160284737A1 (en) Display substrate, its manufacturing method, and display device
US9627543B2 (en) Thin film transistor and method for manufacturing the same, array substrate including the thin film transistor and display device including the array substrate
US10205029B2 (en) Thin film transistor, manufacturing method thereof, and display device
CN104465670A (zh) 一种阵列基板及其制作方法、显示装置
US9478665B2 (en) Thin film transistor, method of manufacturing the same, display substrate and display apparatus
CN105140291B (zh) 薄膜晶体管及其制作方法、阵列基板以及显示装置
JP2010210732A (ja) 液晶表示パネル及びその製造方法
CN203502708U (zh) 像素单元、阵列基板和显示装置
CN102751333A (zh) 主动元件及其制造方法
WO2016106891A1 (zh) 阵列基板、显示装置及阵列基板的制备方法
WO2020232946A1 (zh) 改善金属氧化物tft特性的结构与其制作方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14435512

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15874584

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15874584

Country of ref document: EP

Kind code of ref document: A1