WO2016106805A1 - 一种薄膜晶体管、陈列基板及显示装置 - Google Patents

一种薄膜晶体管、陈列基板及显示装置 Download PDF

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WO2016106805A1
WO2016106805A1 PCT/CN2015/070351 CN2015070351W WO2016106805A1 WO 2016106805 A1 WO2016106805 A1 WO 2016106805A1 CN 2015070351 W CN2015070351 W CN 2015070351W WO 2016106805 A1 WO2016106805 A1 WO 2016106805A1
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electrode
source
drain
semiconductor layer
insulating layer
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French (fr)
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唐岳军
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/431,710 priority Critical patent/US9590021B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present invention relates to the field of electronics, and in particular to a thin film transistor, a display substrate, and a display device.
  • Thin film transistors are a key electronic component in modern microelectronics technology and have been widely used in flat panel displays and other fields.
  • the image acquisition rate of the panel of the liquid crystal display has also been continuously improved.
  • higher requirements have been placed on the aperture ratio of the panel of the liquid crystal display.
  • the aperture ratio is a ratio between the area of the light passing portion after removing the wiring portion and the transistor portion (usually hidden by the black matrix) of each sub-pixel and the area of the entire sub-pixel.
  • the panel of the liquid crystal display has more thin film transistors, thus affecting the aperture ratio of the liquid crystal display panel.
  • the technical problem to be solved by the present invention is to provide a thin film transistor, an array substrate and a display device to improve the aperture ratio of the display device.
  • the present invention provides a thin film transistor including a gate, a first source, a second source, a first drain, a second drain, a first semiconductor layer, a second semiconductor layer, a first insulating layer, and a second An insulating layer
  • the gate electrode includes a first surface and a second surface disposed opposite to each other, the first insulating layer is formed on the first surface and covers the first surface, and the first semiconductor layer is formed on On the first insulating layer, the first drain and the first source are formed on the first semiconductor layer at intervals, and the second insulating layer is formed on the second surface and covered The second surface, the second semiconductor layer is formed on the second insulating layer, and the second drain and the second source are formed at intervals on the second semiconductor layer on.
  • the first source corresponds to the second source
  • the first drain corresponds to the second drain
  • the material of the first and second insulating layers is silicon nitride, silicon oxide, benzocyclobutene, polyester or acrylic resin.
  • the material of the gate, the first and second source, and the first and second drains is a metal, an alloy, a conductive polymer or a conductive carbon nanotube.
  • the present invention also provides an array substrate including a substrate having a first surface, a first data line, a second data line, a gate line, a first electrode, a second electrode, and a thin film formed on the first surface of the substrate a transistor, wherein the gate line is connected to the gate, the first data line and the first electrode are respectively connected to the first source and the first drain, and the second data line And the second electrode is respectively connected to the second source and the second drain, wherein the thin film transistor comprises a gate, a first source, a second source, a first drain, and a second a drain, a first semiconductor layer, a second semiconductor layer, a first insulating layer and a second insulating layer, the gate electrode includes a first surface and a second surface disposed opposite to each other, and the first insulating layer is formed on the first surface a first semiconductor layer formed on the first insulating layer, the first drain and the first source being spaced apart from each other on the first semiconductor a second insulating layer formed on the second surface and
  • the first electrode and the second electrode are strip electrodes and are located in the same layer.
  • the first electrode is a block electrode
  • the second electrode is a strip electrode
  • the distance of the first electrode from the substrate is smaller than the distance of the second electrode from the substrate, the first The electrode is in a different layer than the second electrode.
  • the array substrate includes a main pixel region and a sub-pixel region in the same layer, the first electrode is located in the first pixel region, and the second electrode is located in the second pixel region.
  • the first electrode is a strip electrode
  • the second electrode is a block electrode
  • the first source corresponds to the second source
  • the first drain corresponds to the second drain
  • the material of the first and second insulating layers is silicon nitride, silicon oxide, benzocyclobutene, polyester or acrylic resin.
  • the material of the gate, the first and second sources, and the first and second drains is gold.
  • the present invention also provides a display device including an array substrate, the array substrate including a substrate having a first surface, a first data line, a second data line, a gate line, and a first surface formed on the first surface of the substrate An electrode, a second electrode, and a thin film transistor, wherein the gate line is connected to the gate, and the first data line and the first electrode are respectively connected to the first source and the first drain The second data line and the second electrode are respectively connected to the second source and the second drain, wherein the thin film transistor comprises a gate, a first source, and a second source a first drain, a second drain, a first semiconductor layer, a second semiconductor layer, a first insulating layer and a second insulating layer, the gate electrode includes a first surface and a second surface disposed opposite to each other An insulating layer is formed on the first surface and covers the first surface, the first semiconductor layer is formed on the first insulating layer, and the first drain and the first source are spaced apart Formed on the first semiconductor layer, the second
  • the first electrode and the second electrode are strip electrodes and are located in the same layer.
  • the first electrode is a block electrode
  • the second electrode is a strip electrode
  • the distance of the first electrode from the substrate is smaller than the distance of the second electrode from the substrate, the first The electrode is in a different layer than the second electrode.
  • the array substrate includes a main pixel region and a sub-pixel region in the same layer, the first electrode is located in the first pixel region, and the second electrode is located in the second pixel region.
  • the first electrode is a strip electrode
  • the second electrode is a block electrode
  • the first source corresponds to the second source
  • the first drain corresponds to the second drain
  • the material of the first and second insulating layers is silicon nitride, silicon oxide, benzocyclobutene, polyester or acrylic resin.
  • the material of the gate, the first and second source, and the first and second drains is a metal, an alloy, a conductive polymer or a conductive carbon nanotube.
  • the thin film transistor of the present invention includes a gate, a first source, a second source, a first drain, a second drain, a first semiconductor layer, a second semiconductor layer, a first insulating layer, and a second insulating layer.
  • the gate includes a first surface and a second surface disposed opposite each other.
  • the first insulating layer is formed on the first surface and covers the first surface.
  • the first semiconductor layer is formed on the first insulating layer.
  • the first A drain and the first source are formed on the first semiconductor layer at intervals.
  • the second insulating layer is formed on the second surface and covers the second surface.
  • the second semiconductor layer is formed on the second insulating layer.
  • the second drain and the second source are formed on the second semiconductor layer at intervals.
  • the first and second sources of the thin film transistor and the first and second drains share the gate.
  • the on and off of the first source and the first drain and the on and off of the second source and the second drain are simultaneously controlled by controlling the gate. That is, the thin film transistor can be applied as two separate thin film transistors. Therefore, when the thin film transistor of the present invention is applied to an array substrate of a display device, the number of use of the thin film transistor is reduced, that is, the number of thin film transistors that block light transmission is reduced. Therefore, the present invention improves the aperture ratio of the display device.
  • FIG. 1 is a partial cross-sectional view of a thin film transistor according to a preferred embodiment of the first aspect of the present invention
  • FIG. 2 is a schematic diagram of an array substrate according to a first preferred embodiment of the second aspect of the present invention.
  • FIG. 3 is a schematic diagram of an array substrate according to a second preferred embodiment of the second aspect of the present invention.
  • FIG. 4 is a schematic diagram of an array substrate according to a third preferred embodiment of the second aspect of the present invention.
  • FIG. 5 is a schematic diagram of a display device according to a preferred embodiment of the third aspect of the present invention.
  • a first embodiment of the present invention provides a thin film transistor 100.
  • the thin film transistor 100 includes a gate 10, a first source 11, a second source 12, a first drain 13, a second drain 14, a first semiconductor layer 15, a second semiconductor layer 16, and a first insulating layer. 17 and a second insulating layer 18.
  • the gate 10 includes a first surface 101 and a second surface 102 that are oppositely disposed.
  • the first insulating layer 17 is formed on the first surface 101 and covers the first surface 101.
  • the first A semiconductor layer 15 is formed on the first insulating layer 17.
  • the first drain 13 and the first source 11 are formed on the first semiconductor layer 15 at intervals.
  • the second insulating layer 18 is formed on the second surface 102 and covers the second surface 102.
  • the second semiconductor layer 16 is formed on the second insulating layer 18.
  • the second drain 14 and the second source 12 are formed on the second semiconductor layer 16 at intervals.
  • the first source 11 corresponds to the second source 12 .
  • the first drain 13 corresponds to the second drain 14 .
  • the thin film transistor 100 is disposed on the array substrate.
  • the first source 11 corresponds to the second source 12, and the first drain 13 and the second drain 14 correspond to the first source 11 on the array substrate.
  • Projection overlaps with projection of the second source 12 on the array substrate; projection of the first drain 13 on the array substrate and the second drain 14 on the array substrate The projections overlap.
  • the first semiconductor layer 15 includes a first ohmic contact layer 151 and a first active layer 152.
  • the first active layer 152 is formed on the first insulating layer 17.
  • the first ohmic contact layer 151 is formed between the first source 11 and the first drain 13 and the first active layer 152.
  • the first ohmic contact layer 151 has a first spacer region.
  • the first spacing region corresponds to a spacing region between the first source 11 and the first drain 13 .
  • the second semiconductor layer 116 includes a second ohmic contact layer 161 and a second active layer 162.
  • the second active layer 162 is formed on the second insulating layer 18.
  • the second ohmic contact layer 161 is formed between the second source 12 and the second drain 14 and the second active layer 162.
  • the second ohmic contact layer 161 has a second spacer region.
  • the second spacing region corresponds to a spacing region between the second source 12 and the second drain 14.
  • the materials of the first and second insulating layers 17 and 18 are silicon nitride, silicon oxide, benzocyclobutene, polyester or acrylic resin.
  • the material of the gate 10, the first source 11, the second source 12, the first drain 13 and the second drain 14 is a metal, an alloy, a conductive polymer or a conductive carbon nanometer. tube.
  • the thin film transistor 100 includes a gate 10 , a first source 11 , a second source 12 , a first drain 13 , a second drain 14 , a first semiconductor layer 15 , and a second semiconductor layer 16 .
  • the gate 10 includes a first surface 101 disposed opposite to each other and Second surface 102.
  • the first insulating layer 17 is formed on the first surface 101 and covers the first surface 101.
  • the first semiconductor layer 15 is formed on the first insulating layer 17.
  • the first drain 13 and the first source 11 are formed on the first semiconductor layer 15 at intervals.
  • the second insulating layer 18 is formed on the second surface 102 and covers the second surface 102.
  • the second semiconductor layer 16 is formed on the second insulating layer 18.
  • the second drain 14 and the second source 12 are formed on the second semiconductor layer 16 at intervals. Therefore, the first and second sources 11 and 12 and the first and second drains 13 and 14 of the thin film transistor 100 share the gate 10.
  • the on/off of the first source 11 and the first drain 13 and the on and off of the second source 12 and the second drain 14 are simultaneously controlled by controlling the gate 10 . That is, the thin film transistor 100 can be applied as two separate thin film transistors. Therefore, when the thin film transistor 100 of the present invention is applied to an array substrate of a display device, the number of use of the thin film transistor is reduced, that is, the number of the thin film transistors 100 that block light transmission is reduced. Therefore, the present invention improves the aperture ratio of the display device.
  • a first preferred embodiment of the second aspect of the present invention provides an array substrate 200.
  • the array substrate 200 includes a substrate 210 having a first surface, a first data line 220 formed on a first surface of the substrate 210, a second data line 230, a gate line 260, a first electrode 240, and a second electrode. 250 and thin film transistors.
  • the thin film transistor is the thin film transistor 100 provided in the above preferred embodiment of the first aspect.
  • the specific structure of the thin film transistor 100 has been described in detail in the above first embodiment, and details are not described herein again.
  • the gate line 260 is connected to the gate 10.
  • the first data line 220 and the first electrode 240 are respectively connected to the first source 11 and the first drain 13 .
  • the second data line 230 and the second electrode 250 are connected to the second source 12 and the second drain 14 respectively. Controlling the gate 10 by the gate line 260 to control the on and off of the first source 11 and the first drain 13 and simultaneously controlling the pass of the source 12 and the second drain 14 Broken.
  • first electrode 240 and the second electrode 250 are strip electrodes and are located in the same layer. In other embodiments, the first electrode 240 and the second electrode 250 may also be in different layers.
  • the array substrate 200 two electrodes can be connected by only one thin film transistor, thereby reducing the number of thin film transistors used, that is, reducing the thin film transistor that blocks light transmission.
  • the number of 100 Therefore, when the array substrate 200 is applied to a display device, the aperture ratio of the display device is improved.
  • the array basic 300 provided by the second preferred embodiment of the second aspect of the present invention is similar to the array substrate 200 provided by the first preferred embodiment of the second aspect.
  • the difference between the two is:
  • An electrode 340 is also a bulk electrode.
  • the second electrode 350 is a strip electrode, and the distance between the first electrode 340 and the array substrate is smaller than the distance of the second electrode 350 from the substrate, the first electrode 340 and the second electrode.
  • the 350 is on a different floor.
  • first electrode 340 and the array substrate are smaller than the distance between the second electrode 350 and the substrate to explain that the bulk electrode is disposed under the strip electrode.
  • the first electrode 340 and the second electrode 350 may be common electrodes and/or pixel electrodes, which are not limited herein.
  • the array basic 400 provided by the third preferred embodiment of the second aspect of the present invention is similar to the array substrate 200 provided by the first preferred embodiment of the second aspect, and the difference is that the array is
  • the substrate 400 includes a main pixel region 410 and a sub-pixel region 420 located in the same layer.
  • the first electrode 440 is located in the first pixel region 410.
  • the second electrode 450 is located in the second pixel region 420.
  • the first electrode 440 is a strip electrode.
  • the second electrode is a bulk electrode.
  • two electrodes can be connected by only one thin film transistor, thereby reducing the number of thin film transistors used, that is, reducing the number of thin film transistors 100 that block light transmission. Therefore, when the array substrate 400 is applied to a display device, the aperture ratio of the display device is improved.
  • a preferred embodiment of the third aspect of the present invention provides a display device 500.
  • the display device 500 includes an array substrate 200. Since the array substrate 200 has been described in detail in the above second embodiment, it will not be described herein. In the embodiment, the array substrate 200 may be the array substrate provided in any of the above preferred embodiments.
  • the thin film transistor 100 includes a gate 10, a first source 11, a second source 12, a first drain 13, a second drain 14, and a first (in conjunction with FIGS. 1 and 2).
  • the gate 10 includes a relative arrangement The first surface 101 and the second surface 102 are disposed.
  • the first insulating layer 17 is formed on the first surface 101 and covers the first surface 101.
  • the first semiconductor layer 15 is formed on the first insulating layer 17.
  • the first drain 13 and the first source 11 are formed on the first semiconductor layer 15 at intervals.
  • the second insulating layer 18 is formed on the second surface 102 and covers the second surface 102.
  • the second semiconductor layer 16 is formed on the second insulating layer 18.
  • the second drain 14 and the second source 12 are formed on the second semiconductor layer 16 at intervals. Therefore, the first and second sources 11 and 12 and the first and second drains 13 and 14 of the thin film transistor 100 share the gate 10.
  • the on/off of the first source 11 and the first drain 13 and the on and off of the second source 12 and the second drain 14 are simultaneously controlled by controlling the gate 10 . That is, the thin film transistor 100 can be applied as two separate thin film transistors. Therefore, the present invention reduces the number of use of the thin film transistors, that is, reduces the number of thin film transistors 100 that block light transmission. Therefore, the present invention improves the aperture ratio of the display device 500.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种薄膜晶体管(100)，包括栅极(10)、第一及第二源极(11,12)、第一及第二漏极(13,14)、第一及第二半导体层(15,16)、及第一及第二绝缘层(17,18)，栅极(10)包括相对设置的第一及第二表面(101,102)，第一绝缘层(17)形成于第一表面(101)上，并覆盖第一表面(101)，第一半导体层(15)形成于第一绝缘层(17)上，第一漏极(13)及第一源极(11)间隔地形成在第一半导体层(15)上，第二绝缘层(18)形成于第二表面(102)上，并覆盖第二表面(102)，第二半导体层(16)形成于所述第二绝缘层(18)上，第二漏极(14)及第二源极(12)间隔地形成在第二半导体层(16)上。提高了应用薄膜晶体管(100)的显示装置(500)的开口率。此外，还提供了阵列基板(200,300,400)及显示装置(500)。

Description

一种薄膜晶体管、陈列基板及显示装置
本发明要求2014年12月30日递交的发明名称为“一种薄膜晶体管、陈列基板及显示装置”的申请号201410853562.0的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及电子领域，尤其涉及一种薄膜晶体管、陈列基板及显示装置。
背景技术
薄膜晶体管是现代微电子技术中的一种关键性电子元件，目前已经被广泛的应用于平板显示器等领域。随着液晶显示技术的进步，液晶显示器的面板的图像采集率也不断提升。同时，对液晶显示器的面板的开口率也提出了更高的要求。其中，所谓的开口率即为除去每一个次像素的配线部、晶体管部(通常采用黑色矩阵隐藏)后的光线通过部分的面积和每一个次像素整体的面积之间的比例。但是，随着液晶显示器的面板的图像采集率的不断提升，液晶显示器的面板具有更多的薄膜晶体管，因此影响了液晶显示器面板的开口率。
发明内容
本发明所要解决的技术问题在于提供一种薄膜晶体管、阵列基板及显示装置，以提高显示装置的开口率。
为了实现上述目的，本发明实施方式提供如下技术方案：
本发明供了一种薄膜晶体管，包括栅极、第一源极、第二源极、第一漏极、第二漏极、第一半导体层、第二半导体层、第一绝缘层及第二绝缘层，所述栅极包括相对设置的第一表面及第二表面，所述第一绝缘层形成于所述第一表面上，并覆盖所述第一表面，所述第一半导体层形成于所述第一绝缘层上，所述第一漏极及所述第一源极间隔地形成在所述第一半导体层上，所述第二绝缘层形成于所述第二表面上，并覆盖所述第二表面，所述第二半导体层形成于所述第二绝缘层上，所述第二漏极及所述第二源极间隔地形成在所述第二半导体层 上。
其中，所述第一源极对应所述第二源极，所述第一漏极对应所述第二漏极。
其中，所述第一及第二绝缘层的材料为氮化硅、氧化硅、苯并环丁烯、聚酯或丙烯酸树脂。
其中，所述栅极、所述第一及第二源极及所述第一及第二漏极的材料为金属、合金、导电聚合物或导电性碳纳米管。
本发明还提供一种阵列基板，包括具有第一表面的基板、形成于所述基板的第一表面上的第一数据线、第二数据线、栅线、第一电极、第二电极及薄膜晶体管，其中，所述栅线连接至所述栅极，所述第一数据线及所述第一电极分别连接至所述第一源极及所述第一漏极，所述第二数据线及所述第二电极分别连接至所述第二源极及所述第二漏极，其中，所述薄膜晶体管包括栅极、第一源极、第二源极、第一漏极、第二漏极、第一半导体层、第二半导体层、第一绝缘层及第二绝缘层，所述栅极包括相对设置的第一表面及第二表面，所述第一绝缘层形成于所述第一表面上，并覆盖所述第一表面，所述第一半导体层形成于所述第一绝缘层上，所述第一漏极及所述第一源极间隔地形成在所述第一半导体层上，所述第二绝缘层形成于所述第二表面上，并覆盖所述第二表面，所述第二半导体层形成于所述第二绝缘层上，所述第二漏极及所述第二源极间隔地形成在所述第二半导体层上。
其中，所述第一电极及所述第二电极为条状电极，且位于同一层。
其中，所述第一电极为块状电极，所述第二电极为条状电极，所述第一电极距离所述基板的距离小于所述第二电极距离所述基板的距离，所述第一电极与所述第二电极位于不同层。
其中，所述阵列基板包括位于同层的主像素区及副像素区域，所述第一电极位于所述第一像素区域内，所述第二电极位于所述第二像素区域内。
其中，所述第一电极为条状电极，所述第二电极为块状电极。
其中，所述第一源极对应所述第二源极，所述第一漏极对应所述第二漏极。
其中，所述第一及第二绝缘层的材料为氮化硅、氧化硅、苯并环丁烯、聚酯或丙烯酸树脂。
其中，所述栅极、所述第一及第二源极及所述第一及第二漏极的材料为金 属、合金、导电聚合物或导电性碳纳米管。
本发明还提供一种显示装置，包括阵列基板，所述阵列基板包括具有第一表面的基板、形成于所述基板的第一表面上的第一数据线、第二数据线、栅线、第一电极、第二电极及薄膜晶体管，其中，所述栅线连接至所述栅极，所述第一数据线及所述第一电极分别连接至所述第一源极及所述第一漏极，所述第二数据线及所述第二电极分别连接至所述第二源极及所述第二漏极，其中，所述薄膜晶体管包括栅极、第一源极、第二源极、第一漏极、第二漏极、第一半导体层、第二半导体层、第一绝缘层及第二绝缘层，所述栅极包括相对设置的第一表面及第二表面，所述第一绝缘层形成于所述第一表面上，并覆盖所述第一表面，所述第一半导体层形成于所述第一绝缘层上，所述第一漏极及所述第一源极间隔地形成在所述第一半导体层上，所述第二绝缘层形成于所述第二表面上，并覆盖所述第二表面，所述第二半导体层形成于所述第二绝缘层上，所述第二漏极及所述第二源极间隔地形成在所述第二半导体层上。
其中，所述第一电极及所述第二电极为条状电极，且位于同一层。
其中，所述第一电极为块状电极，所述第二电极为条状电极，所述第一电极距离所述基板的距离小于所述第二电极距离所述基板的距离，所述第一电极与所述第二电极位于不同层。
其中，所述阵列基板包括位于同层的主像素区及副像素区域，所述第一电极位于所述第一像素区域内，所述第二电极位于所述第二像素区域内。
其中，所述第一电极为条状电极，所述第二电极为块状电极。
其中，所述第一源极对应所述第二源极，所述第一漏极对应所述第二漏极。
其中，所述第一及第二绝缘层的材料为氮化硅、氧化硅、苯并环丁烯、聚酯或丙烯酸树脂。
其中，所述栅极、所述第一及第二源极及所述第一及第二漏极的材料为金属、合金、导电聚合物或导电性碳纳米管。
本发明所述薄膜晶体管包括栅极、第一源极、第二源极、第一漏极、第二漏极、第一半导体层、第二半导体层、第一绝缘层及第二绝缘层。所述栅极包括相对设置的第一表面及第二表面。所述第一绝缘层形成于所述第一表面上，并覆盖所述第一表面。所述第一半导体层形成于所述第一绝缘层上。所述第一 漏极及所述第一源极间隔地形成在所述第一半导体层上。所述第二绝缘层形成于所述第二表面上，并覆盖所述第二表面。所述第二半导体层形成于所述第二绝缘层上。所述第二漏极及所述第二源极间隔地形成在所述第二半导体层上。因此，所述薄膜晶体管的第一及第二源极及第一及第二漏极共用所述栅极。通过控制所述栅极来同时控制所述第一源极与所述第一漏极的通断，及所述第二源极与所述第二漏极的通断。即所述薄膜晶体管可以相当于两个独立的薄膜晶体管来应用。因此，当本发明薄膜晶体管应用于显示装置的阵列基板上时，减少了薄膜晶体管的使用数量，即减少了阻挡光线传输的薄膜晶体管的数量。因此，本发明提高了显示装置的开口率。
附图说明
为了更清楚地说明本发明的技术方案，下面将对实施方式中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以如这些附图获得其他的附图。
图1是本发明第一方案较佳实施方式提供的薄膜晶体管的部分剖面图；
图2是本发明第二方案第一较佳实施方式提供的阵列基板的示意图；
图3是本发明第二方案第二较佳实施方式提供的阵列基板的示意图；
图4是本发明第二方案第三较佳实施方式提供的阵列基板的示意图；
图5是本发明第三方案较佳实施方式提供的显示装置的示意图。
具体实施方式
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述。
请参阅图1，本发明第一方案较佳实施方式提供一种薄膜晶体管100。所述薄膜晶体管100包括栅极10、第一源极11、第二源极12、第一漏极13、第二漏极14、第一半导体层15、第二半导体层16、第一绝缘层17及第二绝缘层18。所述栅极10包括相对设置的第一表面101及第二表面102。所述第一绝缘层17形成于所述第一表面101上，并覆盖所述第一表面101。所述第一 半导体层15形成于所述第一绝缘层17上。所述第一漏极13及所述第一源极11间隔地形成在所述第一半导体层15上。所述第二绝缘层18形成于所述第二表面102上，并覆盖所述第二表面102。所述第二半导体层16形成于所述第二绝缘层18上。所述第二漏极14及所述第二源极12间隔地形成在所述第二半导体层16上。
其中，所述第一源极11对应所述第二源极12。所述第一漏极13对应所述第二漏极14。
需要说明的是，所述薄膜晶体管100设置于阵列基板上。上述所述第一源极11与所述第二源极12对应，及所述第一漏极13与所述第二漏极14对应是指所述第一源极11在所述阵列基板上的投影与所述第二源极12在所述阵列基板上的投影重叠；所述第一漏极13在所述阵列基板上的投影与所述第二漏极14在所述阵列基板上的投影重叠。
具体地，所述第一半导体层15包括第一欧姆接触层151及第一有源层152。所述第一有源层152形成于所述第一绝缘层17上。所述第一欧姆接触层151形成于所述第一源极11及所述第一漏极13与所述第一有源层152之间。所述第一欧姆接触层151具有第一间隔区域。所述第一间隔区域对应所述第一源极11及所述第一漏极13之间的间隔区域。同理，所述第二半导体层116包括第二欧姆接触层161及第二有源层162。所述第二有源层162形成于所述第二绝缘层18上。所述第二欧姆接触层161形成于所述第二源极12及所述第二漏极14与所述第二有源层162之间。所述第二欧姆接触层161具有第二间隔区域。所述第二间隔区域对应所述第二源极12及所述第二漏极14之间的间隔区域。
在本实施方式中，所述第一及第二绝缘层17及18的材料为氮化硅、氧化硅、苯并环丁烯、聚酯或丙烯酸树脂。所述栅极10、所述第一源极11、所述第二源极12、所述第一漏极13及第二漏极14的材料为金属、合金、导电聚合物或导电性碳纳米管。
在实施方式中，所述薄膜晶体管100包括栅极10、第一源极11、第二源极12、第一漏极13、第二漏极14、第一半导体层15、第二半导体层16、第一绝缘层17及第二绝缘层18。所述栅极10包括相对设置的第一表面101及 第二表面102。所述第一绝缘层17形成于所述第一表面101上，并覆盖所述第一表面101。所述第一半导体层15形成于所述第一绝缘层17上。所述第一漏极13及所述第一源极11间隔地形成在所述第一半导体层15上。所述第二绝缘层18形成于所述第二表面102上，并覆盖所述第二表面102。所述第二半导体层16形成于所述第二绝缘层18上。所述第二漏极14及所述第二源极12间隔地形成在所述第二半导体层16上。因此，所述薄膜晶体管100的第一及第二源极11及12及第一及第二漏极13及14共用所述栅极10。通过控制所述栅极10来同时控制所述第一源极11与所述第一漏极13的通断，及所述第二源极12与所述第二漏极14的通断。即所述薄膜晶体管100可以相当于两个独立的薄膜晶体管来应用。因此，当本发明薄膜晶体管100应用于显示装置的阵列基板上时，减少了薄膜晶体管的使用数量，即减少了阻挡光线传输的薄膜晶体管100的数量。因此，本发明提高了显示装置的开口率。
请继续参阅图2，本发明第二方面第一较佳实施方式提供一种阵列基板200。所述阵列基板200包括具有第一表面的基板210、形成于所述基板210的第一表面上的第一数据线220、第二数据线230、栅线260、第一电极240、第二电极250及薄膜晶体管。
其中，所述薄膜晶体管为上述第一方案较佳实施方式提供的薄膜晶体管100。所述薄膜晶体管100的具体结构已在上述第一方案中进行了详细的阐述，在此不再赘述。
其中，所述栅线260连接至所述栅极10。所述第一数据线220及所述第一电极240分别连接至所述第一源极11及所述第一漏极13。所述第二数据线230及所述第二电极250分别连接至所述第二源极12及所述第二漏极14。通过所述栅线260控制所述栅极10来控制所述第一源极11与所述第一漏极13的通断，并同时控制所述的源极12及第二漏极14的通断。
在本实施方式中，所述第一电极240及所述第二电极250均为条状电极，且位于同一层。在其他的实施方式中，所述第一电极240及第二电极250也可以在不同层。
因此，在所述阵列基板200上，仅用一个薄膜晶体管即可连接两个所述电极，从而减少了薄膜晶体管的使用数量，即减少了阻挡光线传输的薄膜晶体管 100的数量。因此，当所述阵列基板200应用于显示装置中，提高了显示装置的开口率。
请继续参阅图3，本发明第二方案的第二较佳实施方式提供的阵列基本300与第二方案的第一较佳实施方式提供的阵列基板200相似，两者的区别在于：所述第一电极340也为块状电极。所述第二电极350为条状电极，所述第一电极340距离所述阵列基板的距离小于所述第二电极350距离所述基板的距离，所述第一电极340与所述第二电极350位于不同层。
需要说明的是，所述第一电极340距离所述阵列基板的距离小于所述第二电极350距离所述基板的距离是为了说明块状电极设置于条状电极的下面。其中，所述第一电极340及所述第二电极350可以为公共电极和/或像素电极，在这里不做限定。
请继续参阅图4，本发明第二方案的第三较佳实施方式提供的阵列基本400与第二方案的第一较佳实施方式提供的阵列基板200相似，两者的区别在于：所述阵列基板400包括位于同层的主像素区410及副像素区域420。所述第一电极440位于所述第一像素区域410内。所述第二电极450位于所述第二像素区域420内。
在本实施方式中，所述第一电极440为条状电极。所述第二电极为块状电极。
在本实施方式中，在所述阵列基板400上，仅用一个薄膜晶体管即可连接两个所述电极，从而减少了薄膜晶体管的使用数量，即减少了阻挡光线传输的薄膜晶体管100的数量。因此，当所述阵列基板400应用于显示装置中，提高了显示装置的开口率。
请继续参阅图5，本发明第三方案较佳实施方式提供一种显示装置500。所述显示装置500包括阵列基板200。由于在上述第二方案中已对所述阵列基板200进行了详细地描述，故在此不再赘述。在本实施方式中，所述阵列基板200也可以为上述第二方案的任一较佳实施方式提供的阵列基板。
在本实施方式中，(结合图1及图2)所述薄膜晶体管100包括栅极10、第一源极11、第二源极12、第一漏极13、第二漏极14、第一半导体层15、第二半导体层16、第一绝缘层17及第二绝缘层18。所述栅极10包括相对设 置的第一表面101及第二表面102。所述第一绝缘层17形成于所述第一表面101上，并覆盖所述第一表面101。所述第一半导体层15形成于所述第一绝缘层17上。所述第一漏极13及所述第一源极11间隔地形成在所述第一半导体层15上。所述第二绝缘层18形成于所述第二表面102上，并覆盖所述第二表面102。所述第二半导体层16形成于所述第二绝缘层18上。所述第二漏极14及所述第二源极12间隔地形成在所述第二半导体层16上。因此，所述薄膜晶体管100的第一及第二源极11及12及第一及第二漏极13及14共用所述栅极10。通过控制所述栅极10来同时控制所述第一源极11与所述第一漏极13的通断，及所述第二源极12与所述第二漏极14的通断。即所述薄膜晶体管100可以相当于两个独立的薄膜晶体管来应用。因此，本发明减少了薄膜晶体管的使用数量，即减少了阻挡光线传输的薄膜晶体管100的数量。因此，本发明提高了所述显示装置500的开口率。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (20)

  1. 一种薄膜晶体管，包括栅极、第一源极、第二源极、第一漏极、第二漏极、第一半导体层、第二半导体层、第一绝缘层及第二绝缘层，所述栅极包括相对设置的第一表面及第二表面，所述第一绝缘层形成于所述第一表面上，并覆盖所述第一表面，所述第一半导体层形成于所述第一绝缘层上，所述第一漏极及所述第一源极间隔地形成在所述第一半导体层上，所述第二绝缘层形成于所述第二表面上，并覆盖所述第二表面，所述第二半导体层形成于所述第二绝缘层上，所述第二漏极及所述第二源极间隔地形成在所述第二半导体层上。
  2. 如权利要求1所述的薄膜晶体管，其中，所述第一源极对应所述第二源极，所述第一漏极对应所述第二漏极。
  3. 如权利要求1所述的薄膜晶体管，其中，所述第一及第二绝缘层的材料为氮化硅、氧化硅、苯并环丁烯、聚酯或丙烯酸树脂。
  4. 如权利要求1所述的薄膜晶体管，其中，所述栅极、所述第一及第二源极及所述第一及第二漏极的材料为金属、合金、导电聚合物或导电性碳纳米管。
  5. 一种阵列基板，包括具有第一表面的基板、形成于所述基板的第一表面上的第一数据线、第二数据线、栅线、第一电极、第二电极及薄膜晶体管，其中，所述栅线连接至所述栅极，所述第一数据线及所述第一电极分别连接至所述第一源极及所述第一漏极，所述第二数据线及所述第二电极分别连接至所述第二源极及所述第二漏极，其中，所述薄膜晶体管包括栅极、第一源极、第二源极、第一漏极、第二漏极、第一半导体层、第二半导体层、第一绝缘层及第二绝缘层，所述栅极包括相对设置的第一表面及第二表面，所述第一绝缘层形成于所述第一表面上，并覆盖所述第一表面，所述第一半导体层形成于所述第一绝缘层上，所述第一漏极及所述第一源极间隔地形成在所述第一半导体层上，所述第二绝缘层形成于所述第二表面上，并覆盖所述第二表面，所述第二半导体层形成于所述第二绝缘层上，所述第二漏极及所述第二源极间隔地形成在所述第二半导体层上。
  6. 如权利要求5所述的阵列基板，其中，所述第一电极及所述第二电极为条状电极，且位于同一层。
  7. 如权利要求5所述的阵列基板，其中，所述第一电极为块状电极，所述第二电极为条状电极，所述第一电极距离所述基板的距离小于所述第二电极距离所述基板的距离，所述第一电极与所述第二电极位于不同层。
  8. 如权利要求5所述的阵列基板，其中，所述阵列基板包括位于同层的主像素区及副像素区域，所述第一电极位于所述第一像素区域内，所述第二电极位于所述第二像素区域内。
  9. 如权利要求8所述的阵列基板，其中，所述第一电极为条状电极，所述第二电极为块状电极。
  10. 如权利要求5所述的阵列基板，其中，所述第一源极对应所述第二源极，所述第一漏极对应所述第二漏极。
  11. 如权利要求5所述的阵列基板，其中，所述第一及第二绝缘层的材料为氮化硅、氧化硅、苯并环丁烯、聚酯或丙烯酸树脂。
  12. 如权利要求5所述的阵列基板，其中，所述栅极、所述第一及第二源极及所述第一及第二漏极的材料为金属、合金、导电聚合物或导电性碳纳米管。
  13. 一种显示装置，包括阵列基板，所述阵列基板包括具有第一表面的基板、形成于所述基板的第一表面上的第一数据线、第二数据线、栅线、第一电极、第二电极及薄膜晶体管，其中，所述栅线连接至所述栅极，所述第一数据线及所述第一电极分别连接至所述第一源极及所述第一漏极，所述第二数据线及所述第二电极分别连接至所述第二源极及所述第二漏极，其中，所述薄膜晶体管包括栅极、第一源极、第二源极、第一漏极、第二漏极、第一半导体层、第二半导体层、第一绝缘层及第二绝缘层，所述栅极包括相对设置的第一表面及第二表面，所述第一绝缘层形成于所述第一表面上，并覆盖所述第一表面，所述第一半导体层形成于所述第一绝缘层上，所述第一漏极及所述第一源极间隔地形成在所述第一半导体层上，所述第二绝缘层形成于所述第二表面上，并覆盖所述第二表面，所述第二半导体层形成于所述第二绝缘层上，所述第二漏极及所述第二源极间隔地形成在所述第二半导体层上。
  14. 如权利要求13所述的显示装置，其中，所述第一电极及所述第二电极为条状电极，且位于同一层。
  15. 如权利要求13所述的显示装置，其中，所述第一电极为块状电极，所述第二电极为条状电极，所述第一电极距离所述基板的距离小于所述第二电极距离所述基板的距离，所述第一电极与所述第二电极位于不同层。
  16. 如权利要求13所述的显示装置，其中，所述阵列基板包括位于同层的主像素区及副像素区域，所述第一电极位于所述第一像素区域内，所述第二电极位于所述第二像素区域内。
  17. 如权利要求16所述的显示装置，其中，所述第一电极为条状电极，所述第二电极为块状电极。
  18. 如权利要求13所述的显示装置，其中，所述第一源极对应所述第二源极，所述第一漏极对应所述第二漏极。
  19. 如权利要求13所述的显示装置，其中，所述第一及第二绝缘层的材料为氮化硅、氧化硅、苯并环丁烯、聚酯或丙烯酸树脂。
  20. 如权利要求13所述的显示装置，其中，所述栅极、所述第一及第二源极及所述第一及第二漏极的材料为金属、合金、导电聚合物或导电性碳纳米管。
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