WO2016106783A1 - 液晶显示面板、栅极驱动电路及其故障检测方法 - Google Patents

液晶显示面板、栅极驱动电路及其故障检测方法 Download PDF

Info

Publication number
WO2016106783A1
WO2016106783A1 PCT/CN2015/070098 CN2015070098W WO2016106783A1 WO 2016106783 A1 WO2016106783 A1 WO 2016106783A1 CN 2015070098 W CN2015070098 W CN 2015070098W WO 2016106783 A1 WO2016106783 A1 WO 2016106783A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate driving
gate
shift registers
clock
driving circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/070098
Other languages
English (en)
French (fr)
Inventor
胡宇彤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Publication of WO2016106783A1 publication Critical patent/WO2016106783A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a liquid crystal display panel, a gate driving circuit, and a fault detecting method thereof.
  • more and more liquid crystal display devices use a Gate Driver On Array (GOA) technology on an array substrate to reduce the width of the frame of the array substrate to meet the narrow frame design trend of the liquid crystal display device.
  • GOA Gate Driver On Array
  • the gate drive circuit is composed of a shift register. To ensure the normal operation and yield of the liquid crystal display panel, it is necessary to detect the fault.
  • the existing fault detection method usually connects the shift register of the last stage to the detection line, and determines whether the detection circuit works normally by analyzing the signal received by the detection line. However, the detection line is not connected to the shift registers of other stages, even if the last one The level does not output a normal signal, and it is not possible to determine the specific location where the fault occurred.
  • embodiments of the present invention provide a liquid crystal display panel, a gate driving circuit, and a fault detecting method thereof to determine a specific location where a gate driving circuit is faulty.
  • a technical solution adopted by the embodiment of the present invention is to provide a gate driving circuit, including: a plurality of shift registers, which sequentially output gate driving voltages at respective output ends in response to a gate driving clock; a detection line, the detection line is connected to the output ends of the plurality of shift registers, and further receives the gate driving voltage; the switch component, the switch component is connected to the reference voltage in response to the gate driving clock, so that the detection line receives different shifts
  • the gate drive voltages of the registers are separated by a reference voltage to form a gate drive voltage pulse sequence, wherein the reference voltage is different from the gate drive voltage.
  • the switch component includes a switch component and a switch drive circuit.
  • the switch component includes a control end, a first connection end, and a second connection end.
  • the control end is connected to the switch drive circuit, the first connection end is connected to the detection line, and the second connection end is connected to the reference voltage.
  • the switch driving circuit generates a switch driving clock at the control end in response to the gate driving clock, thereby controlling the first connection end and the second connection of the switching element
  • the terminals are periodically turned on.
  • the gate drive clock includes a positive phase gate drive clock and an inverted gate drive clock, and voltage changes of the positive phase gate drive clock and the inverted gate drive clock are staggered by a certain time interval, and the switch drive circuit generates a switch at a time interval. Drive the clock.
  • the gate driving circuit further includes a plurality of unidirectional conduction elements respectively connected between the output ends of the shift registers and the detection lines.
  • the unidirectional conduction element is a diode.
  • the one-way conduction component is a triode
  • the gate and the source of the triode are connected to the output ends of the shift registers, and the drain of the triode is connected to the detection line.
  • a liquid crystal display panel including an array substrate and a gate driving circuit integrated on the array substrate, the gate driving circuit including: a plurality of shifts a bit register, in response to the gate driving clock, sequentially outputting a gate driving voltage at respective output terminals; a detecting line connecting the output ends of the plurality of shift registers to receive a gate driving voltage; a switching component, a switching component responding to the gate
  • the driving clock connects the detecting line to the reference voltage such that the gate driving voltages of the different shift registers received by the detecting line are separated by a reference voltage, thereby forming a gate driving voltage pulse sequence, wherein the reference voltage is different from the gate Polar drive voltage.
  • the switch component includes a switch component and a switch drive circuit.
  • the switch component includes a control end, a first connection end, and a second connection end.
  • the control end is connected to the switch drive circuit, the first connection end is connected to the detection line, and the second connection end is connected to the reference voltage.
  • the switch driving circuit generates a switch driving clock at the control end in response to the gate driving clock, thereby controlling the periodic connection between the first connection end and the second connection end of the switching element.
  • the gate drive clock includes a positive phase gate drive clock and an inverted gate drive clock, and voltage changes of the positive phase gate drive clock and the inverted gate drive clock are staggered by a certain time interval, and the switch drive circuit generates a switch at a time interval. Drive the clock.
  • the gate driving circuit further includes a plurality of unidirectional conduction elements respectively connected between the output ends of the shift registers and the detection lines.
  • the unidirectional conduction element is a diode.
  • the one-way conduction component is a triode
  • the gate and the source of the triode are connected to the output ends of the shift registers, and the drain of the triode is connected to the detection line.
  • the gate driving circuit includes a plurality of shift registers, and output ends of the plurality of shift registers are connected.
  • the fault detection method comprises: outputting a gate drive clock to the plurality of shift registers and the switch component, so that the plurality of shift registers sequentially output the gates at the respective output ends in response to the gate drive clock a pole drive voltage, the switch component is responsive to the gate drive clock to connect the sense line to the reference voltage such that the gate drive voltages of the different shift registers received by the sense line are separated by a reference voltage to form a gate drive voltage And a pulse sequence, wherein the reference voltage is different from the gate driving voltage; detecting a voltage change of the gate driving voltage pulse sequence, thereby determining whether there is a fault in the plurality of shift registers.
  • the step of detecting a voltage change condition on the detection line further includes determining a specific position of the shift register having a fault in the plurality of shift registers according to a voltage change condition of the gate drive voltage pulse sequence.
  • determining the specific position of the faulty shift register in the plurality of shift registers according to the voltage change of the gate drive voltage pulse sequence comprises: in the gate drive voltage pulse sequence according to the gate drive voltage in which the abnormality occurs The location determines the specific location of the shift register in the plurality of shift registers that has a fault.
  • the liquid crystal display panel, the gate driving circuit and the fault detecting method thereof are connected to the output ends of the plurality of shift registers through the detecting lines to receive the gate driving voltage, and the gates are driven by the switching components.
  • the clock connects the sense line to the reference voltage for potential pull-down, so that the gate drive voltage of each stage of the shift register output can be detected to determine the specific location where the gate drive circuit fails.
  • FIG. 1 is a schematic diagram of a pixel structure of an embodiment of a liquid crystal display panel of the present invention
  • FIG. 2 is a schematic diagram showing the circuit structure of an embodiment of a gate driving circuit of the present invention.
  • 3 is a timing diagram of clock signals of each of the plurality of shift registers of the present invention.
  • FIG. 4 is a timing diagram of clock signals when a faulty shift register of the present invention is present
  • Fig. 5 is a flow chart showing a method of detecting a failure of an embodiment of a gate driving circuit of the present invention.
  • the array substrate 11 of the liquid crystal display panel includes a gate driver 11 , a data driver 12 , a plurality of gate lines G 1 , G 2 , . . . , G n and a plurality of parallel arrangement and
  • the gate lines G 1 , G 2 , . . . , G n are insulated from the intersecting data lines D 1 , D 2 , . . . , D n , wherein the plurality of gate lines G 1 , G 2 , . . . , G n and a plurality of data lines D 1 , D 2 , . . . , D n define a plurality of pixel regions arranged in an array manner.
  • FIG. 2 is a schematic diagram showing the circuit structure of an embodiment of a gate driving circuit integrated on the array substrate 11 shown in FIG. 1.
  • the gate driving circuit 20 includes a plurality of shift registers 21, a detection line 22, and a switch block 23.
  • the gate driving circuit 20 includes a plurality of shift registers 21, a detection line 22, and a switch block 23.
  • the gate driving circuit 20 includes a plurality of shift registers 21, a detection line 22, and a switch block 23.
  • the plurality of shift registers 21 are connected in one-to-one correspondence with the plurality of gate lines G 1 , G 2 , . . . , G n for responding to the gate driving clock outputted by the gate driver 11 so as to be sequentially at the respective output ends.
  • the gate drive voltage is output to drive the corresponding gate line.
  • the detection line 22 is connected to the output ends of the plurality of shift registers 21 for receiving the gate drive voltages corresponding to the outputs of the plurality of shift registers 21.
  • the switch component 23 is responsive to the gate drive clock output by the gate driver 11 for connecting the detection line 22 to the reference voltage VGL, and pulling down the potential of the test pad VT Pad connected to the detection line 22 to avoid the first stage shift.
  • the influence of the gate driving voltage outputted by the bit register 21, that is, the switching component 23 causes the gate driving voltages of the different shift registers 21 received by the detecting line 22 to be spaced apart by the reference voltage, thereby forming as shown in FIG.
  • the gate drive voltage pulse sequence VToutput is shown.
  • the reference voltage VGL to which the switch component 23 is connected is different from the gate drive voltage output by the gate driver 11.
  • the detecting line 22 is connected to the output end of the shift register 21 at each stage, according to
  • the voltage change of the gate drive voltage pulse sequence can determine the specific position of the faulty shift register, for example, as shown in FIG. 3 and FIG. 4, in the gate drive voltage pulse sequence according to the gate drive voltage in which the abnormality occurs. The position determines that the shift register 21 connected to the fourth gate line G 4 has a fault.
  • the switch assembly 23 includes a switching element 231 and a switch driving circuit 232.
  • the switching element 231 includes a control end g 1 , a first connection end s 1 and a second connection end d 1 , and the control end g 1 is connected to the switch.
  • the driving circuit 232, the first connecting end s 1 is connected to the detecting line 22, the second connecting end d 1 is connected to the reference voltage VGL, and the switch driving circuit 232 generates a switch driving clock CK 1 at the control end g 1 in response to the gate driving clock, thereby controlling
  • the first connection end s 1 and the second connection end d 1 of the switching element 231 are periodically turned on.
  • the gate drive clock includes a positive phase gate drive clock CK 2 and an inverted gate drive clock XCK 2 , a positive phase gate drive clock CK 2 and an inverted gate drive clock XCK 2
  • the voltage change is shifted by a certain time interval (as shown between adjacent two broken lines in the figure), and the switch drive circuit 232 generates the switch drive clock CK 1 at intervals.
  • the gate driving circuit 20 of the present embodiment further includes a plurality of unidirectional conduction elements M connected between the output ends of the shift registers 21 and the detection lines 22, respectively.
  • the unidirectional conduction element M can be a triode. As shown in FIG. 2, the gate g 2 and the source s 2 of the triode are connected to the output ends of the shift registers 21, and the drain d 2 of the triode is connected to the detection line 22, of course.
  • the one-way conduction element M can also be a diode.
  • Fig. 5 is a flow chart showing a method of detecting a failure of an embodiment of a gate driving circuit of the present invention.
  • the method of this embodiment is used for fault detection of the gate driving circuit 20 shown in FIG. 2, as shown in FIG. 5, the method includes:
  • Step S51 outputting a gate driving clock to the plurality of shift registers and the switching component, so that the plurality of shift registers sequentially output the gate driving voltages at the respective output ends in response to the gate driving clock, and the switching component responds to the gate driving clock.
  • the detection line is connected to the reference voltage such that the gate drive voltages of the different shift registers received by the detection line are separated by a reference voltage to form a gate drive voltage pulse sequence.
  • the reference voltage is different from the gate driving voltage
  • Step S52 detecting a voltage change of the gate drive voltage pulse sequence, thereby determining whether there is a fault in the plurality of shift registers.
  • the specific position of the shift register in which the fault exists in the plurality of shift registers may be determined according to the voltage variation of the gate drive voltage pulse sequence, for example, according to the gate in which the abnormality occurs.
  • the position of the pole drive voltage in the sequence of gate drive voltage pulses determines the specific location of the shift register in the plurality of shift registers that is faulty.
  • the failure detecting method of the present embodiment is executed correspondingly by the gate driving circuit 20 of the embodiment shown in Figs. 1 to 4 described above, and therefore has the same technical effects.
  • the embodiment of the present invention connects the output ends of the plurality of shift registers through the detection line to receive the gate driving voltage, and the switching component connects the detection line to the reference voltage in response to the gate driving clock to perform the potential pull-down. Therefore, the gate driving voltage outputted by each stage of the shift register can be detected to determine the specific position where the gate driving circuit is faulty.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种液晶显示面板、栅极驱动电路的故障检测方法。该栅极驱动电路（20）包括：多个移位寄存器（21），响应栅极驱动时钟依次在各自的输出端输出栅极驱动电压；检测线（22），连接多个移位寄存器（21）的输出端，以接收栅极驱动电压；开关组件（23），响应栅极驱动时钟将检测线（22）连接至参考电压，以使得检测线（22）所接收的不同移位寄存器（21）的栅极驱动电压之间由参考电压进行间隔，进而形成一栅极驱动电压脉冲序列。本方法能够确定栅极驱动电路发生故障的具体位置。还提供了一种液晶显示面板、栅极驱动电路。

Description

液晶显示面板、栅极驱动电路及其故障检测方法 【技术领域】
本发明涉及液晶显示技术领域，具体而言涉及一种液晶显示面板、栅极驱动电路及其故障检测方法。
【背景技术】
当前，越来越多的液晶显示装置采用在阵列基板上制作栅极驱动电路(Gate driver On Array，简称GOA)技术，减少阵列基板的边框宽度，以迎合液晶显示装置的窄边框设计趋势。
栅极驱动电路由移位寄存器组成，为保证液晶显示面板的正常工作及良率，需要对其进行故障检测。现有的故障检测方式通常是将最后一级的移位寄存器连接检测线，通过分析检测线接收的信号判定检测电路是否正常工作，然而检测线未连接其他各级的移位寄存器，即使最后一级未输出正常信号，也无法确定发生故障的具体位置。
【发明内容】
有鉴于此，本发明实施例提供一种液晶显示面板、栅极驱动电路及其故障检测方法，以确定栅极驱动电路发生故障的具体位置。
为解决上述技术问题，本发明实施例采用的一个技术方案是：提供一种栅极驱动电路，包括：多个移位寄存器，响应栅极驱动时钟依次在各自的输出端输出栅极驱动电压；检测线，检测线连接多个移位寄存器的输出端，进而接收栅极驱动电压；开关组件，开关组件响应栅极驱动时钟将检测线连接至参考电压，以使得检测线所接收的不同移位寄存器的栅极驱动电压之间由参考电压进行间隔，进而形成一栅极驱动电压脉冲序列，其中参考电压不同于栅极驱动电压。
其中，开关组件包括开关元件以及开关驱动电路，开关元件包括控制端、第一连接端和第二连接端，控制端连接开关驱动电路，第一连接端连接检测线，第二连接端连接参考电压，开关驱动电路响应栅极驱动时钟在控制端产生一开关驱动时钟，进而控制开关元件的第一连接端与第二连接 端之间周期性导通。
其中，栅极驱动时钟包括正相栅极驱动时钟和反相栅极驱动时钟，正相栅极驱动时钟和反相栅极驱动时钟的电压变化错开一定时间间隔，开关驱动电路于时间间隔产生开关驱动时钟。
其中，栅极驱动电路进一步包括多个单向导通元件，单向导通元件分别连接于各移位寄存器的输出端与检测线之间。
其中，单向导通元件为二极管。
其中，单向导通元件为三极管，三极管的栅极和源极连接各移位寄存器的输出端，三极管的漏极连接检测线。
为解决上述技术问题，本发明实施例采用的另一个技术方案是：提供一种液晶显示面板，包括阵列基板以及集成于阵列基板上的栅极驱动电路，该栅极驱动电路包括：多个移位寄存器，响应栅极驱动时钟依次在各自的输出端输出栅极驱动电压；检测线，检测线连接多个移位寄存器的输出端，进而接收栅极驱动电压；开关组件，开关组件响应栅极驱动时钟将检测线连接至参考电压，以使得检测线所接收的不同移位寄存器的栅极驱动电压之间由参考电压进行间隔，进而形成一栅极驱动电压脉冲序列，其中参考电压不同于栅极驱动电压。
其中，开关组件包括开关元件以及开关驱动电路，开关元件包括控制端、第一连接端和第二连接端，控制端连接开关驱动电路，第一连接端连接检测线，第二连接端连接参考电压，开关驱动电路响应栅极驱动时钟在控制端产生一开关驱动时钟，进而控制开关元件的第一连接端与第二连接端之间周期性导通。
其中，栅极驱动时钟包括正相栅极驱动时钟和反相栅极驱动时钟，正相栅极驱动时钟和反相栅极驱动时钟的电压变化错开一定时间间隔，开关驱动电路于时间间隔产生开关驱动时钟。
其中，栅极驱动电路进一步包括多个单向导通元件，单向导通元件分别连接于各移位寄存器的输出端与检测线之间。
其中，单向导通元件为二极管。
其中，单向导通元件为三极管，三极管的栅极和源极连接各移位寄存器的输出端，三极管的漏极连接检测线。
为解决上述技术问题，本发明实施例采用的又一个技术方案是：提供一种栅极驱动电路的故障检测方法，栅极驱动电路包括多个移位寄存器，多个移位寄存器的输出端连接检测线，检测线连接开关组件，该故障检测方法包括：向多个移位寄存器和开关组件输出栅极驱动时钟，以使得多个移位寄存器响应栅极驱动时钟依次在各自的输出端输出栅极驱动电压，开关组件响应栅极驱动时钟将检测线连接至参考电压，以使得检测线所接收的不同移位寄存器的栅极驱动电压之间由参考电压进行间隔，进而形成一栅极驱动电压脉冲序列，其中参考电压不同于栅极驱动电压；检测栅极驱动电压脉冲序列的电压变化情况，进而确定多个移位寄存器中是否存在故障。
其中，检测检测线上的电压变化情况的步骤进一步包括：根据栅极驱动电压脉冲序列的电压变化情况确定多个移位寄存器中存在故障的移位寄存器的具体位置。
其中，根据栅极驱动电压脉冲序列的电压变化情况确定多个移位寄存器中的存在故障的移位寄存器的具体位置的步骤包括：根据出现异常的栅极驱动电压在栅极驱动电压脉冲序列中的位置确定多个移位寄存器中存在故障的移位寄存器的具体位置。
基于上述方案，本发明实施例的液晶显示面板、栅极驱动电路及其故障检测方法，通过检测线连接多个移位寄存器的输出端以接收栅极驱动电压，并由开关组件响应栅极驱动时钟将检测线连接至参考电压以进行电位拉低，从而可以对每一级移位寄存器输出的栅极驱动电压进行检测，确定栅极驱动电路发生故障的具体位置。
【附图说明】
图1是本发明液晶显示面板一实施例的像素结构示意图；
图2是本发明栅极驱动电路一实施例的电路结构示意图；
图3是本发明多个移位寄存器均正常时各时钟信号的时序图；
图4是本发明存在故障的移位寄存器时各时钟信号的时序图；
图5是本发明栅极驱动电路一实施例的故障检测方法的流程图。
【具体实施方式】
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式仅仅是本发明一区域分实施方式，而不是全区域实施方式。基于本发明中的实施方式，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施方式，都属于本发明保护的范围。
图1是本发明液晶显示面板一实施例的像素结构示意图。如图1所示，液晶显示面板的阵列基板11包括栅极驱动器11、数据驱动器12、多条平行设置的栅极线G1，G2，...，Gn以及多条平行设置且与栅极线G1，G2，...，Gn绝缘交叉的数据线D1，D2，...，Dn，其中多条栅极线G1，G2，...，Gn和多条数据线D1，D2，...，Dn定义多个阵列方式排布的像素区域。
图2是图1所示阵列基板11上集成的栅极驱动电路一实施例的电路结构示意图。如图2所示，栅极驱动电路20包括多个移位寄存器21、检测线22以及开关组件23。在本实施例中：
多个移位寄存器21与多条栅极线G1，G2，...，Gn一一对应连接，用以响应栅极驱动器11输出的栅极驱动时钟，从而依次在各自的输出端输出栅极驱动电压，以驱动对应的栅极线。
检测线22连接多个移位寄存器21的输出端，用以接收多个移位寄存器21对应输出的栅极驱动电压。
开关组件23响应栅极驱动器11输出的栅极驱动时钟，用以将检测线22连接至参考电压VGL，对与检测线22连接的测试垫VT Pad的电位进行拉低，以避免上一级移位寄存器21输出的栅极驱动电压的影响，也就是说，开关组件23使得检测线22所接收的不同移位寄存器21的栅极驱动电压之间由参考电压进行间隔，从而形成如图3所示的栅极驱动电压脉冲序列VToutput。其中，开关组件23连接的参考电压VGL不同于栅极驱动器11输出的栅极驱动电压。
本实施例通过检测栅极驱动电压脉冲序列的电压变化情况，即可确定多个移位寄存器21中是否存在故障，具体地，检测线22连接位于各级的移位寄存器21的输出端，根据栅极驱动电压脉冲序列的电压变化情况，即可确定存在故障的移位寄存器的具体位置，例如结合图3和图4所示，根 据出现异常的栅极驱动电压在栅极驱动电压脉冲序列中的位置，确定与第四条栅极线G4连接的移位寄存器21存在故障。
请再次参阅图2所示，开关组件23包括开关元件231以及开关驱动电路232，开关元件231包括控制端g1、第一连接端s1和第二连接端d1，控制端g1连接开关驱动电路232，第一连接端s1连接检测线22，第二连接端d1连接参考电压VGL，开关驱动电路232响应栅极驱动时钟在控制端g1产生一开关驱动时钟CK1，进而控制开关元件231的第一连接端s1与第二连接端d1之间周期性导通。
参阅图3和图4所示，栅极驱动时钟包括正相栅极驱动时钟CK2和反相栅极驱动时钟XCK2，正相栅极驱动时钟CK2和反相栅极驱动时钟XCK2的电压变化错开一定时间间隔(如图中相邻两条虚线之间所示)，开关驱动电路232于时间间隔产生开关驱动时钟CK1。
本实施例的栅极驱动电路20进一步包括多个单向导通元件M，单向导通元件M分别连接于各移位寄存器21的输出端与检测线22之间。其中，单向导通元件M可以为三极管，如图2所示，三极管的栅极g2和源极s2连接各移位寄存器21的输出端，三极管的漏极d2连接检测线22，当然，单向导通元件M也可以为二极管。
图5是本发明栅极驱动电路一实施例的故障检测方法的流程图。本实施例的方法用于对图2所示的栅极驱动电路20进行故障检测，如图5所示，该方法包括：
步骤S51：向多个移位寄存器和开关组件输出栅极驱动时钟，以使得多个移位寄存器响应栅极驱动时钟依次在各自的输出端输出栅极驱动电压，开关组件响应栅极驱动时钟将检测线连接至参考电压，以使得检测线所接收的不同移位寄存器的栅极驱动电压之间由参考电压进行间隔，进而形成一栅极驱动电压脉冲序列。
其中，参考电压不同于栅极驱动电压
步骤S52：检测栅极驱动电压脉冲序列的电压变化情况，进而确定多个移位寄存器中是否存在故障。
具体地，可以根据栅极驱动电压脉冲序列的电压变化情况确定多个移位寄存器中存在故障的移位寄存器的具体位置，例如，根据出现异常的栅 极驱动电压在栅极驱动电压脉冲序列中的位置确定多个移位寄存器中存在故障的移位寄存器的具体位置。
本实施例的故障检测方法由上述图1～图4所示实施例的栅极驱动电路20对应执行，因此具有与其相同的技术效果。
综上所述，本发明实施例通过检测线连接多个移位寄存器的输出端以接收栅极驱动电压，并由开关组件响应栅极驱动时钟将检测线连接至参考电压以进行电位拉低，从而可以对每一级移位寄存器输出的栅极驱动电压进行检测，确定栅极驱动电路发生故障的具体位置。
再次说明，以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种栅极驱动电路，其中，所述栅极驱动电路包括：
    多个移位寄存器，所述多个移位寄存器响应栅极驱动时钟依次在各自的输出端输出栅极驱动电压；
    检测线，所述检测线连接所述多个移位寄存器的输出端，进而接收所述栅极驱动电压；
    开关组件，所述开关组件响应所述栅极驱动时钟将所述检测线连接至参考电压，以使得所述检测线所接收的不同移位寄存器的所述栅极驱动电压之间由所述参考电压进行间隔，进而形成一栅极驱动电压脉冲序列，其中所述参考电压不同于所述栅极驱动电压。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述开关组件包括开关元件以及开关驱动电路，其中所述开关元件包括控制端、第一连接端和第二连接端，所述控制端连接所述开关驱动电路，所述第一连接端连接所述检测线，所述第二连接端连接所述参考电压，所述开关驱动电路响应所述栅极驱动时钟在所述控制端产生一开关驱动时钟，进而控制所述开关元件的所述第一连接端与所述第二连接端之间周期性导通。
  3. 根据权利要求2所述的栅极驱动电路，其中，所述栅极驱动时钟包括正相栅极驱动时钟和反相栅极驱动时钟，其中所述正相栅极驱动时钟和所述反相栅极驱动时钟的电压变化错开一定时间间隔，所述开关驱动电路于所述时间间隔产生所述开关驱动时钟。
  4. 根据权利要求1所述的栅极驱动电路，其中，所述栅极驱动电路进一步包括多个单向导通元件，所述单向导通元件分别连接于各所述移位寄存器的输出端与所述检测线之间。
  5. 根据权利要求4所述的栅极驱动电路，其中，所述单向导通元件为二极管。
  6. 根据权利要求4所述的栅极驱动电路，其中，所述单向导通元件为三极管，其中所述三极管的栅极和源极连接所述各所述移位寄存器的输出端，所述三极管的漏极连接所述检测线。
  7. 一种液晶显示面板，其中包括阵列基板以及集成于所述阵列基板上 的栅极驱动电路，其中，所述栅极驱动电路包括：
    多个移位寄存器，所述多个移位寄存器响应栅极驱动时钟依次在各自的输出端输出栅极驱动电压；
    检测线，所述检测线连接所述多个移位寄存器的输出端，进而接收所述栅极驱动电压；
    开关组件，所述开关组件响应所述栅极驱动时钟将所述检测线连接至参考电压，以使得所述检测线所接收的不同移位寄存器的所述栅极驱动电压之间由所述参考电压进行间隔，进而形成一栅极驱动电压脉冲序列，其中所述参考电压不同于所述栅极驱动电压。
  8. 根据权利要求7所述的栅极驱动电路，其中，所述开关组件包括开关元件以及开关驱动电路，其中所述开关元件包括控制端、第一连接端和第二连接端，所述控制端连接所述开关驱动电路，所述第一连接端连接所述检测线，所述第二连接端连接所述参考电压，所述开关驱动电路响应所述栅极驱动时钟在所述控制端产生一开关驱动时钟，进而控制所述开关元件的所述第一连接端与所述第二连接端之间周期性导通。
  9. 根据权利要求8所述的栅极驱动电路，其中，所述栅极驱动时钟包括正相栅极驱动时钟和反相栅极驱动时钟，其中所述正相栅极驱动时钟和所述反相栅极驱动时钟的电压变化错开一定时间间隔，所述开关驱动电路于所述时间间隔产生所述开关驱动时钟。
  10. 根据权利要求7所述的栅极驱动电路，其中，所述栅极驱动电路进一步包括多个单向导通元件，所述单向导通元件分别连接于各所述移位寄存器的输出端与所述检测线之间。
  11. 根据权利要求10所述的栅极驱动电路，其中，所述单向导通元件为二极管。
  12. 根据权利要求10所述的栅极驱动电路，其中，所述单向导通元件为三极管，其中所述三极管的栅极和源极连接所述各所述移位寄存器的输出端，所述三极管的漏极连接所述检测线。
  13. 一种栅极驱动电路的故障检测方法，其中，所述栅极驱动电路包括多个移位寄存器，所述多个移位寄存器的输出端连接检测线，所述检测线连接开关组件，所述故障检测方法包括：
    向所述多个移位寄存器和所述开关组件输出栅极驱动时钟，以使得所述多个移位寄存器响应栅极驱动时钟依次在各自的输出端输出栅极驱动电压，所述开关组件响应所述栅极驱动时钟将所述检测线连接至参考电压，以使得所述检测线所接收的不同移位寄存器的所述栅极驱动电压之间由所述参考电压进行间隔，进而形成一栅极驱动电压脉冲序列，其中所述参考电压不同于所述栅极驱动电压；
    检测所述栅极驱动电压脉冲序列的电压变化情况，进而确定所述多个移位寄存器中是否存在故障。
  14. 根据权利要求13所述的故障检测方法，其中，所述检测所述检测线上的电压变化情况的步骤进一步包括：
    根据所述栅极驱动电压脉冲序列的电压变化情况确定所述多个移位寄存器中存在故障的移位寄存器的具体位置。
  15. 根据权利要求14所述的故障检测方法，其中，所述根据所述栅极驱动电压脉冲序列的电压变化情况确定所述多个移位寄存器中的存在故障的移位寄存器的具体位置的步骤包括：
    根据出现异常的所述栅极驱动电压在所述栅极驱动电压脉冲序列中的位置确定所述多个移位寄存器中存在故障的移位寄存器的具体位置。
PCT/CN2015/070098 2014-12-29 2015-01-05 液晶显示面板、栅极驱动电路及其故障检测方法 Ceased WO2016106783A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410848414.X 2014-12-29
CN201410848414.XA CN104505045B (zh) 2014-12-29 2014-12-29 液晶显示面板、栅极驱动电路及其故障检测方法

Publications (1)

Publication Number Publication Date
WO2016106783A1 true WO2016106783A1 (zh) 2016-07-07

Family

ID=52946752

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/070098 Ceased WO2016106783A1 (zh) 2014-12-29 2015-01-05 液晶显示面板、栅极驱动电路及其故障检测方法

Country Status (2)

Country Link
CN (1) CN104505045B (zh)
WO (1) WO2016106783A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10977971B2 (en) 2017-06-02 2021-04-13 Hefei Boe Optoelectronics Technology Co., Ltd. Driving module used for display panel, display panel and display device

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105355163B (zh) * 2015-12-22 2019-01-04 昆山国显光电有限公司 Gip信号检测电路、gip信号检测方法和平板显示装置
CN106571114B (zh) * 2016-10-28 2020-04-17 京东方科技集团股份有限公司 测试电路及其工作方法
CN106504708B (zh) * 2017-01-04 2019-07-02 昆山工研院新型平板显示技术中心有限公司 显示装置及其栅极驱动电路
CN106782246B (zh) * 2017-01-05 2020-07-31 昆山国显光电有限公司 Gip信号测试电路、gip信号测试方法和显示装置
CN106875877A (zh) * 2017-02-24 2017-06-20 京东方科技集团股份有限公司 栅极驱动电路的检测装置和方法
CN107068084A (zh) * 2017-03-20 2017-08-18 深圳市华星光电技术有限公司 Goa驱动电路、阵列基板、显示装置及面板的异常检测方法
CN107025870B (zh) * 2017-05-17 2021-02-19 昆山龙腾光电股份有限公司 检测电路、显示装置和检测方法
CN108154833A (zh) * 2018-01-03 2018-06-12 京东方科技集团股份有限公司 一种栅极驱动电路的输出检测电路及其方法、显示装置
CN108831360A (zh) * 2018-06-22 2018-11-16 京东方科技集团股份有限公司 栅极驱动信号检测电路、方法和显示装置
CN111599297B (zh) * 2020-06-19 2023-12-15 京东方科技集团股份有限公司 测试电路、测试方法和显示装置
US11244646B1 (en) * 2020-09-16 2022-02-08 Himax Technologies Limited Display device and display control method
CN113053275B (zh) 2021-03-15 2022-10-28 京东方科技集团股份有限公司 显示面板及其检测方法、补偿方法、显示装置
CN112908232B (zh) * 2021-03-26 2022-10-18 四川长虹电器股份有限公司 Led多分区背光故障检测系统及故障判断方法
CN114203079B (zh) * 2021-11-30 2023-10-13 长沙惠科光电有限公司 检测电路、信号检测方法及显示面板
CN115223470B (zh) * 2022-08-15 2025-01-17 上海中航光电子有限公司 一种检测电路、显示面板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101364022A (zh) * 2008-09-12 2009-02-11 昆山龙腾光电有限公司 阵列基板及其缺陷检测方法
CN101567160A (zh) * 2009-05-31 2009-10-28 上海广电光电子有限公司 Gip型液晶显示面板及其检测方法
US20110102388A1 (en) * 2009-11-02 2011-05-05 Chunghwa Picture Tubes, Ltd. Display and gate driver circuit thereof
CN103247276A (zh) * 2013-04-25 2013-08-14 北京京东方光电科技有限公司 栅极驱动电路和阵列基板
CN203870955U (zh) * 2014-04-15 2014-10-08 华映视讯（吴江）有限公司 显示面板

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101093229B1 (ko) * 2005-01-06 2011-12-13 삼성전자주식회사 어레이 기판 및 이를 갖는 표시장치
US8174477B2 (en) * 2006-03-17 2012-05-08 Lg Display Co., Ltd. Gate driver and repairing method thereof
US8665201B2 (en) * 2008-10-10 2014-03-04 Sharp Kabushiki Kaisha Display device and method for driving display device
KR101791192B1 (ko) * 2010-12-30 2017-10-27 엘지디스플레이 주식회사 디스플레이 장치 및 그 테스트 방법
CN102708815B (zh) * 2011-12-14 2014-08-06 京东方科技集团股份有限公司 栅极驱动电路及液晶显示装置
CN103928003B (zh) * 2013-12-31 2017-02-01 厦门天马微电子有限公司 一种栅极驱动电路及其修复方法、显示面板和显示装置
CN104062784B (zh) * 2014-06-25 2017-06-30 深圳市华星光电技术有限公司 一种面板检测电路及显示面板
CN104183225B (zh) * 2014-08-15 2017-08-15 上海天马微电子有限公司 一种驱动装置、阵列基板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101364022A (zh) * 2008-09-12 2009-02-11 昆山龙腾光电有限公司 阵列基板及其缺陷检测方法
CN101567160A (zh) * 2009-05-31 2009-10-28 上海广电光电子有限公司 Gip型液晶显示面板及其检测方法
US20110102388A1 (en) * 2009-11-02 2011-05-05 Chunghwa Picture Tubes, Ltd. Display and gate driver circuit thereof
CN103247276A (zh) * 2013-04-25 2013-08-14 北京京东方光电科技有限公司 栅极驱动电路和阵列基板
CN203870955U (zh) * 2014-04-15 2014-10-08 华映视讯（吴江）有限公司 显示面板

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10977971B2 (en) 2017-06-02 2021-04-13 Hefei Boe Optoelectronics Technology Co., Ltd. Driving module used for display panel, display panel and display device

Also Published As

Publication number Publication date
CN104505045A (zh) 2015-04-08
CN104505045B (zh) 2017-04-12

Similar Documents

Publication Publication Date Title
WO2016106783A1 (zh) 液晶显示面板、栅极驱动电路及其故障检测方法
US10241145B2 (en) Gate driving circuit and method for detecting same, array substrate and display apparatus
US10120482B2 (en) Driving method for in-cell type touch display panel
US9626925B2 (en) Source driver apparatus having a delay control circuit and operating method thereof
US20170124975A1 (en) Goa circuit and a liquid crystal display apparatus
JP4959974B2 (ja) アレイ基板及びこれを有する表示装置
US11087655B2 (en) Gate driving signal detection circuit, detection method, and display device
CN103000151B (zh) 一种栅极驱动装置及显示设备
CN106128351B (zh) 一种显示装置
US10290246B2 (en) Display apparatus and driving method thereof
US9443462B2 (en) Gate driving circuit, gate line driving method and display device
CN108269515B (zh) 一种用于检测goa电路失效的电路及方法、显示面板
EP2991069B1 (en) Gate electrode drive circuit and array substrate
US9799295B2 (en) Scan driving circuit and liquid crystal display device having the circuit
TW201525963A (zh) 顯示裝置及其閘極移位暫存器的初始化方法
WO2017219763A1 (zh) Goa信号判断电路及判断方法、栅极驱动电路及显示装置
WO2018223739A1 (zh) 显示驱动电路及其控制方法、显示装置
US20160284259A1 (en) Detection device and detection method of a goa circuit of a display panel
CN107025870B (zh) 检测电路、显示装置和检测方法
CN107895562A (zh) 高稳定性的脉冲宽度可调式移位寄存器
KR20130067989A (ko) 게이트 쉬프트 레지스터 및 이를 이용한 표시장치
JP2016206578A (ja) ドライバｉｃ及び電子機器
CN104299547B (zh) 一种测试电路、显示装置以及驱动电路的测试方法
EP2876642B1 (en) Gate driver on array reset circuit, array substrate and display
TWM484775U (zh) 顯示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15874476

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15874476

Country of ref document: EP

Kind code of ref document: A1