WO2016101506A1 - 栅极集成驱动电路、显示面板及显示装置 - Google Patents

栅极集成驱动电路、显示面板及显示装置 Download PDF

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Publication number
WO2016101506A1
WO2016101506A1 PCT/CN2015/078995 CN2015078995W WO2016101506A1 WO 2016101506 A1 WO2016101506 A1 WO 2016101506A1 CN 2015078995 W CN2015078995 W CN 2015078995W WO 2016101506 A1 WO2016101506 A1 WO 2016101506A1
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Prior art keywords
control signal
shift register
driving circuit
gate integrated
integrated driving
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English (en)
French (fr)
Inventor
杨通
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US14/898,650 priority Critical patent/US20160260365A1/en
Publication of WO2016101506A1 publication Critical patent/WO2016101506A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a gate integrated driving circuit, a display panel, and a display device.
  • a gate integrated driving circuit is required to output a gate scan signal to control the display panel to implement a progressive scan and a frame-by-frame refresh function, so that image data input to the display panel can be refreshed in real time, thereby Achieve dynamic display.
  • the gate integrated driving circuit includes a plurality of cascaded shift register units, and the function of gate driving is realized by a shift register unit. In this way, not only can the process of separately manufacturing the gate driving chip be eliminated, but also one manufacturing process can be reduced. This circuit not only reduces the manufacturing cost of flat panel displays, but also shortens the production cycle. Therefore, shift register technology has been widely used in flat panel display manufacturing in recent years.
  • the clock control signal is separated from the input due to the parasitic capacitance C and the resistance R of the signal line itself transmitting the clock control signal. There is a phenomenon of intensity decay at the end. Therefore, as the intensity of the control signal is attenuated, the image quality and performance of the display panel are affected.
  • the embodiments of the present disclosure provide a gate integrated driving circuit, a display panel, and a display device, which are used to solve the attenuation of the output control signal strength of the gate integrated driving circuit in the prior art as it is far from the input end of the control signal. , which affects the picture quality and performance of the display panel.
  • Embodiments of the present disclosure provide a gate integrated driving circuit including: a plurality of cascaded transmissions a memory unit and at least one signal line for inputting a control signal to the gate integrated driving circuit; wherein
  • the signal line has a signal output branch smaller than the number of the shifter register unit
  • At least one of the signal output branches is coupled to a control signal input terminal corresponding to at least two of the shift register units.
  • each of the signal output branches is connected to a control signal input end corresponding to at least two of the shift register units.
  • each of the signal output branches is connected to a control signal input end corresponding to a plurality of adjacent shift register units.
  • At least one of the signal output branches is connected to a control signal input end corresponding to a plurality of adjacent odd-numbered shift register units.
  • At least one of the signal output branches is connected to a control signal input end corresponding to a plurality of adjacent even-numbered shift register units.
  • the number of control signal input ends of each of the signal output branches is the same.
  • two adjacent signal output branches are connected to a control signal input end corresponding to the same shift register unit. .
  • the signal line is a low-level power signal line
  • the control signal input end corresponding to the shift register unit is a low-level signal.
  • the signal line is a high level power signal line, and the control signal input end corresponding to the shift register unit is a high level signal input end;
  • the signal line is a clock control signal line, and the control signal input end corresponding to the shift register unit is a clock signal input end.
  • An embodiment of the present disclosure provides a display panel including the above-described gate integrated driving circuit provided by an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a display device including the above display panel provided by an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a gate integrated driving circuit, a display panel, and a display device, the gate integrated driving circuit including a plurality of cascaded shift register units and at least one input for integrating the driving circuit into the gate a signal line of the control signal; wherein the signal line has a signal output branch smaller than the number of shifter register units; at least one signal output branch is connected to the control signal input end corresponding to the at least two shift register units, thereby ensuring The signal strength attenuation obtained by at least a portion of the shift register unit is slowed down.
  • the gate integrated driving circuit provided by the embodiment of the present disclosure can effectively reduce each control signal by inputting each control signal from one end of the display panel and sequentially passing through each shift register unit in the gate integrated driving circuit. The output intensity is attenuated, and the uniformity of the output intensity of each control signal can be effectively improved, thereby improving the driving capability of the gate integrated driving circuit to the entire display panel, and ensuring the picture quality and working performance of the display panel.
  • 1 is a schematic structural view of a known gate integrated driving circuit
  • FIG. 2 is a schematic diagram of capacitance and resistance generated by each signal line in the circuit shown in FIG. 1;
  • FIG. 3 is a schematic diagram showing waveforms of clock control signals of respective detection points on a clock control signal line in a gate integrated driving circuit in the circuit shown in FIG. 1;
  • FIG. 4 is a schematic diagram of a gate integrated driving circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of waveforms of clock control signals of respective detection points on a clock control signal line in a gate integrated driving circuit according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a comparison result between a clock control signal of each detection point and a delay time of a clock control signal of each detection point in the prior art according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of another gate integrated driving circuit according to an embodiment of the present disclosure.
  • FIG. 1 shows a schematic structural view of a known gate integrated driving circuit. As shown in FIG. 1 , taking the clock control signal line as an example, four points A to D are selected as detection points at different positions on the clock control signal line. The clock control signal is input from one end of the display panel and sequentially passes through each shift register unit.
  • FIG. 2 is a schematic diagram showing capacitance and resistance generated by respective signal lines in the circuit shown in FIG. As shown in FIG. 2, for the clock signal input to each shift register unit, due to the parasitic capacitance C and the resistance R of the signal line of the transmission clock control signal, the clock control signal may be intensified with distance from the input end. phenomenon.
  • FIG. 3 is a schematic diagram showing analog waveforms of clock control signals at respective detection points on a clock control signal line in the gate integrated driving circuit of the circuit shown in FIG. 1.
  • the clock control signals of the four detection points A to D in FIG. 1 can be simulated to obtain a waveform as shown in FIG. It can be seen that as the detection point is far away from the input end, the waveform of the clock control signal away from the input end and the waveform of the clock control signal close to the input end are different, that is, the output intensity of the clock control signal at the near end and the far end of the input end will appear. Great difference.
  • the picture quality and performance of the entire display panel often depend on the side with the worst output signal strength, that is, the control signal strength of the remote output of the input determines the picture quality and performance of the display panel. Away from the control signal input, the intensity of the control signal is attenuated, which will affect the picture quality and performance of the display panel.
  • FIG. 4 is a schematic diagram of a gate integrated driving circuit provided by an embodiment of the present disclosure.
  • the gate integrated driving circuit includes: a plurality of cascaded shift register units and at least one signal line for inputting a control signal to the gate integrated driving circuit.
  • the signal line has a signal output branch smaller than the number of shifter register units; at least one signal output branch has a control signal input corresponding to at least two shift register units. Connected.
  • the signal line has a signal output branch smaller than the number of shifter register units, and at least one signal output branch corresponds to at least two shift register units.
  • the control signal input terminal is connected, so that the gate integrated driving circuit provided by the embodiment of the present invention can be input through the shift register unit in the gate integrated driving circuit, which is input from one end of the display panel in the prior art. It is ensured that the signal intensity attenuation phenomenon of at least part of the shift register unit is slowed down, thereby improving the driving capability of the gate integrated driving circuit to the entire display panel, and ensuring the picture quality and working performance of the display panel.
  • At least part of the signal output branch may be connected to the control signal input end corresponding to the plurality of shift register units, and the remaining signal output branches and corresponding shifts
  • the control signal input ends corresponding to the register unit are connected one by one, so that each signal line inputs a corresponding control signal to the corresponding shift register through each signal output branch.
  • the control signal input end corresponding to the unit can ensure that the signal intensity attenuation of at least part of the shift register unit is slowed down.
  • each signal output branch can be connected to the control signal input end corresponding to at least two shift register units. That is, all the shift register units in the gate integrated driving circuit can be grouped by at least two shift register units, and each signal output branch is correspondingly connected to the control signal input end corresponding to each group of shift register units.
  • control signals in each signal line can be evenly distributed through the signal output branch, and then uniformly output to the corresponding control signal input end of each shift register unit, thereby effectively reducing the attenuation of the output intensity of each control signal. And can effectively improve the uniformity of the output intensity of each control signal.
  • each signal output branch may be connected to a control signal input end corresponding to a plurality of adjacent shift register units.
  • all shift register units in the gate integrated driving circuit can be grouped by at least two adjacent shift register units, and each signal output branch has a control signal corresponding to each group of shift register units.
  • the inputs are connected.
  • Such a wiring manner can make each signal line input a control signal to the control signal input end corresponding to each shift register unit more uniformly through each signal output branch, and can effectively reduce the attenuation of the output intensity of each control signal.
  • the utility model can effectively improve the uniformity of the output intensity of each control signal, and can make the layout and wiring of the gate integrated driving circuit on the display panel neat and orderly.
  • At least one signal output branch may be adjacent to a plurality of The control signal input end corresponding to the odd-numbered shift register unit is connected, or the at least one signal output branch is connected to the control signal input end corresponding to the plurality of adjacent even-numbered shift register units, thereby ensuring at least part of the shift register The attenuation of the signal strength obtained by the unit is slowed down, thereby improving the driving capability of the gate integrated driving circuit to the entire display panel, and ensuring the picture quality and working performance of the display panel.
  • the control signal input of each signal output branch may be input.
  • the number of ends is the same. That is, the gate can be integrated into the drive circuit
  • the shift register unit is grouped by at least two shift register units, and each group includes the same number of shift register units, and each signal output branch has a control signal input corresponding to each group of shift register units. The ends are connected so that each signal output branch outputs a control signal to the same number of corresponding signal inputs. Therefore, each signal line can evenly distribute and output each control signal to the corresponding control signal input end of each shift register unit through each signal output branch. This can effectively reduce the attenuation of the output intensity of each control signal, and can effectively improve the uniformity of the output intensity of each control signal.
  • FIG. 5 is a schematic diagram showing waveforms of clock control signals of respective detection points on a clock control signal line in a gate integrated driving circuit according to an embodiment of the present disclosure.
  • the clock control signal of the detection point of four different positions of A1 to D1 on the clock control signal line CLK can be detected, and the waveform of the clock control signal simulated by the simulation is as shown in the figure. 5 is shown. It can be seen from Fig. 5 that the waveforms of the clock control signals of the respective detection points are basically the same, and there is no large difference.
  • each signal line is output to the corresponding control signal input end of each shift register through the signal output branch L, which can effectively reduce the attenuation of the output intensity of the control signal.
  • the signal lines in the gate integrated driving circuit provided by the embodiments of the present disclosure can pass signals according to the input of the control signals from the display panel to the shift register unit in the gate integrated driving circuit.
  • the output branch L uniformly outputs the respective control signals to the respective control signal input terminals of the respective shift register units.
  • This can effectively reduce the attenuation of the output intensity of each control signal, and can effectively improve the uniformity of the output intensity of each control signal, thereby improving the driving capability of the gate integrated driving circuit to the entire display panel, and ensuring the picture quality displayed by the display panel. And work performance.
  • FIG. 6 is a schematic diagram showing a comparison result between a clock control signal of each detection point and a delay time of a clock control signal of each detection point in the prior art according to an embodiment of the present disclosure.
  • the gate integrated driving circuit provided by the embodiment of the present disclosure, the attenuation of the output intensity of each control signal can be effectively reduced, and the uniformity of the output intensity of each control signal can be effectively improved.
  • the gate integrated driving circuit and the gate integrated driving circuit in the prior art select one detection point according to every 100 shift register units, and select a total of nine detection points G0 to G800 for clock control signal detection and simulation.
  • the rising edge time and the falling edge time of the waveforms of each detection point are measured, and the rising edge time and the falling edge time of each detection point are summed and compared, and the comparison result is shown in FIG. 6.
  • the clock control signal line outputted by the clock control signal line in the gate integrated driving circuit provided by the embodiment of the present disclosure has a delay time of substantially one clock control signal. Therefore, in the prior art, the clock control signal line in the gate integrated driving circuit increases in delay time as the clock control signal is away from the input terminal. It can be seen that the control signal outputted by each signal line in the gate integrated driving circuit in the prior art may have uneven intensity attenuation along the input end.
  • the shift register unit in the entire gate integrated driving circuit may be grouped by at least two shift register units, and each signal output branch and a group The corresponding control signal input ends of the shift register unit are connected, so that the control signals can be uniformly output to the corresponding control signal input ends of the shift register units through the signal output branch, thereby effectively reducing the output of each control signal.
  • the phenomenon of intensity attenuation and can effectively improve the uniformity of the output intensity of each control signal.
  • the clock control signal lines CLK and CLKB may be alternately connected to the clock signal input ends of the shift register units.
  • a feasible solution is shown in Figure 4. That is, the clock signal control line CLK is connected to the clock signal input terminal CLK terminal of the odd-numbered stage shift register unit and to the clock signal input terminal CLKB terminal of the even-numbered stage shift register unit.
  • the clock control signal line CLKB is connected to the clock signal input terminal CLKB terminal of the odd-numbered stage shift register unit and to the clock signal input terminal CLK of the even-numbered stage shift register unit.
  • the clock control signal lines CLK and CLKB alternately output signals to the clock signal input end of the corresponding shift register unit, so that the corresponding shift register unit can output the corresponding clock signal at each time.
  • FIG. 7 is a schematic diagram of another gate integrated driving circuit provided by an embodiment of the present disclosure.
  • adjacent two signal output branches may correspond to the same shift register unit.
  • the control signal inputs are connected.
  • the clock control signal line CLK is shown.
  • Both signal output branches Ln and Ln+1 of the clock signal control line CLK are connected to the signal input terminal of the shift register unit Gn.
  • control signal input end of the last stage shift register unit connected to the previous signal output branch is connected to the latter signal output branch
  • the control signal input terminal of the primary shift register unit is the control signal input terminal of the same shift register unit. This helps to evenly distribute the control signals on each signal line to each shift register unit, which can effectively reduce the attenuation of the output intensity of each control signal, and can effectively improve the uniformity of the output intensity of each control signal.
  • the above-mentioned gate integrated driving circuit needs to implement a function of normally driving the display panel to perform image display under the control of each control signal.
  • Integration to the gate A signal line for inputting a control signal to each shift register unit in the driving circuit includes a low-level power signal line, a high-level power signal line, and a clock control signal line.
  • the control signal input end corresponding to the shift register unit connected to the signal line through the signal output branch is a low-level signal input end; if the signal line is a high-level power signal line, Then, the control signal input end corresponding to the shift register unit connected to the signal line through the signal output branch is a high level signal input end; if the signal line is a clock control signal line, the signal line is connected to the shift register via the signal output branch
  • the control signal input end corresponding to the unit is a clock signal input end.
  • an embodiment of the present disclosure provides a display panel including the above-described gate integrated driving circuit provided by an embodiment of the present disclosure. Since the principle of solving the problem of the display panel is similar to that of the gate integrated driving circuit, the implementation of the display device can be referred to the implementation of the above-described gate integrated driving circuit, and the repeated description will not be repeated.
  • an embodiment of the present disclosure provides a display device including the above display panel provided by an embodiment of the present disclosure.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. Since the principle of solving the problem is similar to that of the display panel, the implementation of the display device can be referred to the implementation of the above display panel, and the repeated description is omitted.
  • Embodiments of the present disclosure provide a gate integrated driving circuit, a display panel, and a display device, the gate integrated driving circuit including a plurality of cascaded shift register units and at least one input for integrating the driving circuit into the gate
  • the signal line of the control signal has a signal output branch that is smaller than the number of shifter register units, and at least one signal output branch is coupled to the control signal input terminal corresponding to at least two shift register units. This ensures that the signal strength decay of at least some of the shift register cells is slowed down.
  • the gate integrated driving circuit provided by the embodiment of the present disclosure can effectively reduce each control signal by inputting each control signal from one end of the display panel and sequentially passing through each shift register unit in the gate integrated driving circuit.
  • the output intensity is attenuated, and the uniformity of the output intensity of each control signal can be effectively improved, thereby improving the driving capability of the gate integrated driving circuit to the entire display panel, and ensuring the picture quality and working performance of the display panel.

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Abstract

一种栅极集成驱动电路、显示面板及显示装置，该栅极集成驱动电路包括级联的多个移位寄存器单元和至少一条用于向栅极集成驱动电路输入控制信号的信号线；其中，信号线具有小于移位寄存器单元个数的信号输出支路；至少一个信号输出支路与至少两个移位寄存器单元对应的控制信号输入端相连，这样能够保证至少部分移位寄存器单元得到的信号强度衰减现象减缓；相较于现有技术中各控制信号从显示面板一端输入，依次经过栅极集成驱动电路中的各移位寄存器单元，栅极集成驱动电路可以有效减小各控制信号输出强度的衰减，且可以有效提高各控制信号输出强度的均一性，保证了显示面板显示的画面质量及工作性能。

Description

栅极集成驱动电路、显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种栅极集成驱动电路、显示面板及显示装置。
背景技术
目前，显示技术被广泛应用于电视、手机以及公共信息的显示。用于显示画面的平板显示器因其超薄节能的优点而被大力推广。在多数的平板显示器中，都需要采用栅极集成驱动电路来输出栅极扫描信号，以控制显示面板实现逐行扫描和逐帧刷新的功能，使得输入到显示面板的图像数据能够实时刷新，从而实现动态显示。栅极集成驱动电路包括级联的多个移位寄存器单元，且通过移位寄存器单元来实现栅极驱动的功能。这样，不仅可以省去单独制作栅极驱动芯片的过程，而且还可以减少一道制作工序。这种电路不但可以降低平板显示器的制作成本，还能缩短其制作周期。因此，近几年来移位寄存器技术被广泛应用于平板显示制造。
然而，在大尺寸面板上采用栅极集成驱动电路设计时，以时钟控制信号线为例，由于传输时钟控制信号的信号线自身存在的寄生电容C和电阻R，使得时钟控制信号随着远离输入端会出现强度衰减的现象。因此，随着远离控制信号输入端，由于控制信号的强度的衰减，会影响显示面板显示的画面质量及工作性能。
因此，如何改善栅极集成驱动电路中随着远离控制信号输入端而出现的输出控制信号强度衰减，从而影响显示面板显示的画面质量及工作性能的问题，是本领域技术人员亟待解决的问题。
发明内容
本公开实施例提供了一种栅极集成驱动电路、显示面板及显示装置，用以解决现有技术中存在的栅极集成驱动电路中随着远离控制信号输入端而出现的输出控制信号强度衰减，从而影响显示面板显示的画面质量及工作性能的问题。
本公开实施例提供了一种栅极集成驱动电路，包括：级联的多个移位寄 存器单元和至少一条用于向所述栅极集成驱动电路输入控制信号的信号线；其中，
所述信号线具有小于所述移位器寄存器单元个数的信号输出支路；
至少一个所述信号输出支路与至少两个所述移位寄存器单元对应的控制信号输入端相连。
在一种可能的实施方式中，本公开实施例提供的上述栅极集成驱动电路中，各所述信号输出支路均与至少两个所述移位寄存器单元对应的控制信号输入端相连。
在一种可能的实施方式中，本公开实施例提供的上述栅极集成驱动电路中，各所述信号输出支路与多个相邻的所述移位寄存器单元对应的控制信号输入端相连。
在一种可能的实施方式中，本公开实施例提供的上述栅极集成驱动电路中，至少一个所述信号输出支路与多个相邻的奇数级移位寄存器单元对应的控制信号输入端相连。
在一种可能的实施方式中，本公开实施例提供的上述栅极集成驱动电路中，至少一个所述信号输出支路与多个相邻的偶数级移位寄存器单元对应的控制信号输入端相连。
在一种可能的实施方式中，本公开实施例提供的上述栅极集成驱动电路中，各所述信号输出支路连接的控制信号输入端的个数相同。
在一种可能的实施方式中，本公开实施例提供的上述栅极集成驱动电路中，相邻的两个所述信号输出支路与同一个所述移位寄存器单元对应的控制信号输入端相连。
在一种可能的实施方式中，本公开实施例提供的上述栅极集成驱动电路中，所述信号线为低电平电源信号线，移位寄存器单元对应的控制信号输入端为低电平信号输入端；
所述信号线为高电平电源信号线，移位寄存器单元对应的控制信号输入端为高电平信号输入端；
所述信号线为时钟控制信号线，移位寄存器单元对应的控制信号输入端为时钟信号输入端。
本公开实施例提供了一种显示面板，包括本公开实施例提供的上述栅极集成驱动电路。
本公开实施例提供了一种显示装置，包括本公开实施例提供的上述显示面板。
本公开实施例提供了一种栅极集成驱动电路、显示面板及显示装置，该栅极集成驱动电路包括级联的多个移位寄存器单元和至少一条用于向所述栅极集成驱动电路输入控制信号的信号线；其中，信号线具有小于移位器寄存器单元个数的信号输出支路；至少一个信号输出支路与至少两个移位寄存器单元对应的控制信号输入端相连，这样能够保证至少部分移位寄存器单元得到的信号强度衰减现象减缓。相较于现有技术中各控制信号从显示面板一端输入，依次经过栅极集成驱动电路中的各移位寄存器单元，本公开实施例提供的栅极集成驱动电路，可以有效减小各控制信号输出强度的衰减，且可以有效提高各控制信号输出强度的均一性，从而可以提高栅极集成驱动电路对整个显示面板的驱动能力，保证了显示面板显示的画面质量及工作性能。
附图说明
图1为已知的栅极集成驱动电路结构示意图；
图2为图1所示电路中各信号线自身产生的电容与电阻示意图；
图3为图1所示电路中栅极集成驱动电路中时钟控制信号线上各检测点的时钟控制信号模拟波形示意图；
图4为本公开实施例提供的一种栅极集成驱动电路示意图；
图5为本公开实施例提供的栅极集成驱动电路中时钟控制信号线上各检测点的时钟控制信号模拟波形示意图；
图6为本公开实施例提供的各检测点的时钟控制信号与现有技术中各检测点的时钟控制信号的延迟时间对比结果示意图；
图7为本公开实施例提供的另一种栅极集成驱动电路示意图。
具体实施方式
下面结合附图，对本公开实施例提供的栅极集成驱动电路、显示面板及显示装置的具体实施方式进行详细地说明。
图1示出已知的栅极集成驱动电路结构示意图。如图1所示，以时钟控制信号线为例，选取A～D四个点为时钟控制信号线上不同位置的检测点。时钟控制信号从显示面板一端输入，依次经过每一个移位寄存器单元。
图2示出图1所示电路中各信号线自身产生的电容与电阻的示意图。如图2所示，对于输入到各移位寄存器单元的时钟信号，由于传输时钟控制信号的信号线自身存在的寄生电容C和电阻R，使得时钟控制信号随着远离输入端会出现强度衰减的现象。
图3为图1所示电路中栅极集成驱动电路中时钟控制信号线上各检测点的时钟控制信号模拟波形示意图。
例如，可以将图1中A～D四个检测点的时钟控制信号进行模拟，得到如图3所示的波形。可以看出随着检测点远离输入端，远离输入端的时钟控制信号的波形与靠近输入端的时钟控制信号的波形差异较大，即时钟控制信号在输入端近端与远端的输出强度会出现较大差异。而对于整个显示面板显示的画面质量和工作性能往往取决于控制信号输出强度最差的一侧，即输入端远端输出的控制信号强度决定了显示面板显示的画面质量及工作性能，因此，随着远离控制信号输入端，由于控制信号的强度的衰减，会影响显示面板显示的画面质量及工作性能。
图4示出了本公开实施例提供的一种栅极集成驱动电路示意图。该栅极集成驱动电路包括：级联的多个移位寄存器单元和至少一条用于向栅极集成驱动电路输入控制信号的信号线。
在图4所示栅极集成驱动电路中，信号线具有少于移位器寄存器单元个数的信号输出支路；至少一个信号输出支路与至少两个移位寄存器单元对应的控制信号输入端相连。
在本发明实施例提供的上述栅极集成驱动电路中，因为信号线具有小于移位器寄存器单元个数的信号输出支路，且至少一个信号输出支路与至少两个移位寄存器单元对应的控制信号输入端相连，所以相较于现有技术中各控制信号从显示面板一端输入，依次经过栅极集成驱动电路中的各移位寄存器单元，本发明实施例提供的栅极集成驱动电路可以保证减缓至少部分移位寄存器单元的信号强度衰减现象，从而可以提高栅极集成驱动电路对整个显示面板的驱动能力，保证了显示面板显示的画面质量及工作性能。
示例性地，本发明实施例提供的上述栅极集成驱动电路中，至少部分信号输出支路可以与多个移位寄存器单元对应的控制信号输入端相连，其余信号输出支路与对应的移位寄存器单元对应的控制信号输入端一一对应相连，这样各信号线通过各信号输出支路将对应的控制信号输入到对应的移位寄存 器单元对应的控制信号输入端，能够保证减缓至少部分移位寄存器单元的信号强度衰减现象。
如图4所示(图中仅示出了时钟控制信号线CLK和CLKB)，在本公开实施例提供的上述栅极集成驱动电路中，为了更有效地减小各信号线在不同位置输出控制信号强度的衰减，提高各控制信号输出强度的均一性，各信号输出支路均可以与至少两个移位寄存器单元对应的控制信号输入端相连。即可以将栅极集成驱动电路中的所有移位寄存器单元以至少两个移位寄存器单元为一组进行分组，各信号输出支路与各组移位寄存器单元对应的控制信号输入端对应相连。这样可以将各信号线中的控制信号通过信号输出支路均匀分配，然后均匀输出到各移位寄存器单元中对应的控制信号输入端，从而可以有效减小各控制信号输出强度出现衰减的现象，且可以有效提高各控制信号输出强度的均一性。
可选择地，本公开实施例提供的上述栅极集成驱动电路中，为了简化各信号线的布线方式，可以将各信号输出支路与多个相邻的移位寄存器单元对应的控制信号输入端相连，即可以将栅极集成驱动电路中的所有移位寄存器单元以至少两个相邻的移位寄存器单元为一组进行分组，各信号输出支路与各组移位寄存器单元对应的控制信号输入端对应相连。这样的布线方式可以使各信号线通过每一个信号输出支路更均匀的向各移位寄存器单元对应的的控制信号输入端输入控制信号，而且可以有效减小各控制信号输出强度出现衰减的现象，有效提高各控制信号输出强度的均一性，并且可以使栅极集成驱动电路在显示面板上的布局布线整齐有序。
如图4所示(图中仅示出了时钟控制信号线CLK和CLKB)，在本公开实施例提供的上述栅极集成驱动电路中，可以将至少一个信号输出支路与多个相邻的奇数级移位寄存器单元对应的控制信号输入端相连，或者将至少一个信号输出支路与多个相邻的偶数级移位寄存器单元对应的控制信号输入端相连，这样可以保证至少部分移位寄存器单元得到的信号强度衰减现象减缓，从而可以提高栅极集成驱动电路对整个显示面板的驱动能力，保证了显示面板显示的画面质量及工作性能。
可选择地，在本公开实施例提供的上述栅极集成驱动电路中，为了提高输入到各移位寄存器单元中的各控制信号强度的均一性，可以使各信号输出支路连接的控制信号输入端的个数相同。即可以将栅极集成驱动电路中的所 有移位寄存器单元以至少两个移位寄存器单元为一组进行分组，且每组包含的移位寄存器单元的个数相同，各信号输出支路与各组移位寄存器单元对应的控制信号输入端对应相连，从而每一个信号输出支路向相同个数的对应信号输入端输出控制信号。因此，各信号线可以通过各信号输出支路将各控制信号均匀分配输出到各移位寄存器单元中对应的控制信号输入端。这样可以有效减小各控制信号输出强度出现衰减的现象，且可以有效提高各控制信号输出强度的均一性。
图5示出本公开实施例提供的栅极集成驱动电路中时钟控制信号线上各检测点的时钟控制信号模拟波形示意图。以图4所示的栅极集成驱动电路的结构示意图为例，可以通过检测时钟控制信号线CLK上A1～D1四个不同位置的检测点的时钟控制信号，模拟得到的时钟控制信号波形如图5所示。由图5可以看出各检测点的时钟控制信号波形基本一致，没有出现较大的差异。因此，在本公开实施例提供的栅极集成驱动电路中，各信号线通过信号输出支路L输出到各移位寄存器中对应的各控制信号输入端，可以有效减小控制信号输出强度的衰减。相较于现有技术中各控制信号从显示面板一端输入，依次经过栅极集成驱动电路中的各移位寄存器单元，本公开实施例提供的栅极集成驱动电路中的各信号线可以通过信号输出支路L将各控制信号均匀输出到各移位寄存器单元中对应的各控制信号输入端。这样可以有效减小各控制信号输出强度的衰减，且可以有效提高各控制信号输出强度的均一性，从而可以提高栅极集成驱动电路对整个显示面板的驱动能力，保证了显示面板显示的画面质量及工作性能。
图6示出了本公开实施例提供的各检测点的时钟控制信号与现有技术各检测点的时钟控制信号的延迟时间对比结果示意图。示例性地，为了更直观地说明本公开实施例提供的栅极集成驱动电路，可以有效减小各控制信号输出强度的衰减，且可以有效提高各控制信号输出强度的均一性，对本公开实施例提供的栅极集成驱动电路与现有技术中的栅极集成驱动电路按照每隔100个移位寄存器单元选取一个检测点，共选取G0～G800九个检测点进行时钟控制信号检测并进行模拟。将各检测点的波形中高电平上升沿时间和下降沿时间进行测量，并将每一个检测点的上升沿时间和下降沿时间进行求和后进行对比，对比结果如图6所示。可以看出本公开实施例提供的栅极集成驱动电路中时钟控制信号线在不同位置输出的时钟控制信号延迟时间基本一 致，而现有技术中栅极集成驱动电路中时钟控制信号线随着远离输入端时钟控制信号延迟时间增大。由此可以看出现有技术中栅极集成驱动电路中的各信号线输出的控制信号会随着远离输入端出现强度衰减不均匀的现象。本公开实施例提供的栅极集成驱动电路中，可以将整个栅极集成驱动电路中的移位寄存器单元以至少两个移位寄存器单元为一组进行分组，每一个信号输出支路与一组移位寄存器单元的对应的控制信号输入端相连，这样可以通过信号输出支路将各控制信号均匀输出到各移位寄存器单元中对应的各控制信号输入端，从而可以有效减小各控制信号输出强度衰减的现象，且可以有效提高各控制信号输出强度的均一性。
需要说明的是，本公开实施例提供的栅极集成驱动电路中，时钟控制信号线CLK与CLKB可以与各移位寄存器单元的时钟信号输入端交替连接。可行的一种方案如图4所示。即时钟信号控制线CLK与第奇数级的移位寄存器单元的时钟信号输入端CLK端相连以及和第偶数级的移位寄存器单元的时钟信号输入端CLKB端相连。而时钟控制信号线CLKB与第奇数级的移位寄存器单元的时钟信号输入端CLKB端相连以及和第偶数级的移位寄存器单元的时钟信号输入端CLK相连。时钟控制信号线CLK与CLKB交替输出信号到对应的移位寄存器单元的时钟信号输入端，这样保证在各个时刻对应的移位寄存器单元可以输出相应的时钟信号。
图7示出了本公开实施例提供的另一种栅极集成驱动电路示意图。如图7所示，在本公开实施例提供的上述栅极集成驱动电路中，为了提高各控制信号输出强度的均一性，相邻的两个信号输出支路可以与同一个移位寄存器单元对应的控制信号输入端相连。如图7所示，其中仅示出了时钟控制信号线CLK。时钟信号控制线CLK的两个信号输出支路Ln和Ln+1均与移位寄存器单元Gn的信号输入端相连。即相邻的两个信号输出支路连接的多个移位寄存器单元中，前一个信号输出支路连接的最后一级移位寄存器单元的控制信号输入端与后一个信号输出支路连接的第一级移位寄存器单元的控制信号输入端为同一个移位寄存器单元的控制信号输入端。这样有助于将各信号线上的控制信号均匀分配到各移位寄存器单元中，可以有效减小各控制信号输出强度出现衰减的现象，且可以有效提高各控制信号输出强度的均一性。
在具体实施时，本公开实施例提供的上述栅极集成驱动电路，需要在各控制信号的控制下实现正常驱动显示面板进行图像显示的功能。向栅极集成 驱动电路中各移位寄存器单元输入控制信号的信号线包括低电平电源信号线、高电平电源信号线，以及时钟控制信号线。如果信号线为低电平电源信号线，则信号线通过信号输出支路连接的移位寄存器单元对应的控制信号输入端为低电平信号输入端；如果信号线为高电平电源信号线，则信号线通过信号输出支路连接的移位寄存器单元对应的控制信号输入端为高电平信号输入端；如果信号线为时钟控制信号线，则信号线通过信号输出支路连接的移位寄存器单元对应的控制信号输入端为时钟信号输入端。这样各信号线上的控制信号可以通过各信号输出支路输出到移位寄存器单元中对应的控制信号输入端，控制栅极集成驱动电路实现正常驱动显示面板进行图像显示的功能。
基于同一发明构思，本公开实施例提供了一种显示面板，包括本公开实施例提供的上述栅极集成驱动电路。由于该显示面板解决问题的原理与栅极集成驱动电路相似，因此该显示装置的实施可以参见上述栅极集成驱动电路的实施，重复之处不再赘述。
基于同一发明构思，本公开实施例提供了一种显示装置，包括本公开实施例提供的上述显示面板。该显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。由于该显示装置解决问题的原理与显示面板相似，因此该显示装置的实施可以参见上述显示面板的实施，重复之处不再赘述。
本公开实施例提供了一种栅极集成驱动电路、显示面板及显示装置，该栅极集成驱动电路包括级联的多个移位寄存器单元和至少一条用于向所述栅极集成驱动电路输入控制信号的信号线。该信号线具有小于移位器寄存器单元个数的信号输出支路，至少一个信号输出支路与至少两个移位寄存器单元对应的控制信号输入端相连。这样能够保证减缓至少部分移位寄存器单元的信号强度衰减现象。相较于现有技术中各控制信号从显示面板一端输入，依次经过栅极集成驱动电路中的各移位寄存器单元，本公开实施例提供的栅极集成驱动电路，可以有效减小各控制信号输出强度的衰减，且可以有效提高各控制信号输出强度的均一性，从而可以提高栅极集成驱动电路对整个显示面板的驱动能力，保证了显示面板显示的画面质量及工作性能。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。
本申请要求于2014年12月22日递交的中国专利申请第201410808674.4号的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。

Claims (10)

  1. 一种栅极集成驱动电路，包括：
    级联的多个移位寄存器单元和至少一条用于向所述栅极集成驱动电路输入控制信号的信号线，其中，
    所述信号线具有小于所述移位器寄存器单元个数的信号输出支路；
    至少一个所述信号输出支路与至少两个所述移位寄存器单元对应的控制信号输入端相连。
  2. 如权利要求1所述的栅极集成驱动电路，其中，各所述信号输出支路均与至少两个所述移位寄存器单元对应的控制信号输入端相连。
  3. 如权利要求1所述的栅极集成驱动电路，其中，各所述信号输出支路与多个相邻的所述移位寄存器单元对应的控制信号输入端相连。
  4. 如权利要求2所述的栅极集成驱动电路，其中，至少一个所述信号输出支路与多个相邻的奇数级移位寄存器单元对应的控制信号输入端相连。
  5. 如权利要求2所述的栅极集成驱动电路，其中，至少一个所述信号输出支路与多个相邻的偶数级移位寄存器单元对应的控制信号输入端相连。
  6. 如权利要求2所述的栅极集成驱动电路，其中，各所述信号输出支路连接的控制信号输入端的个数相同。
  7. 如权利要求6所述的栅极集成驱动电路，其中，相邻的两个所述信号输出支路与同一个所述移位寄存器单元对应的控制信号输入端相连。
  8. 如权利要求1-7任一项所述的栅极集成驱动电路，其中，当所述信号线为低电平电源信号线时，移位寄存器单元对应的控制信号输入端为低电平信号输入端；
    当所述信号线为高电平电源信号线时，移位寄存器单元对应的控制信号输入端为高电平信号输入端；
    当所述信号线为时钟控制信号线时，移位寄存器单元对应的控制信号输入端为时钟信号输入端。
  9. 一种显示面板，其中，包括如权利要求1-8任一项所述的栅极集成驱动电路。
  10. 一种显示装置，其中，包括如权利要求9所述的显示面板。
PCT/CN2015/078995 2014-12-22 2015-05-14 栅极集成驱动电路、显示面板及显示装置 Ceased WO2016101506A1 (zh)

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