WO2016101401A1 - 低温多晶硅tft基板的制作方法及其结构 - Google Patents

低温多晶硅tft基板的制作方法及其结构 Download PDF

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WO2016101401A1
WO2016101401A1 PCT/CN2015/072558 CN2015072558W WO2016101401A1 WO 2016101401 A1 WO2016101401 A1 WO 2016101401A1 CN 2015072558 W CN2015072558 W CN 2015072558W WO 2016101401 A1 WO2016101401 A1 WO 2016101401A1
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polysilicon
segment
polysilicon segment
gate
tft substrate
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French (fr)
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卢改平
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

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  • the present invention relates to the field of display technologies, and in particular, to a method and a structure for fabricating a low temperature polysilicon TFT substrate.
  • Thin-film transisitor liquid cystal display is divided into polysilicon (Poly-Si) technology and amorphous silicon (a-Si) technology, and low temperature poly-silicon (LTPS) technology is The biggest difference between the manufacturing technology of the new generation of thin film transistor liquid crystal display and the traditional amorphous silicon display is that the low temperature polysilicon display has a faster reaction speed, and has the advantages of high brightness, high resolution and low power consumption.
  • the silicon crystal arrangement of the low-temperature polysilicon is more ordered than the amorphous silicon, so that the electron mobility is relatively one hundred times higher, and the peripheral driving circuit can be simultaneously fabricated on the glass substrate, which can save space and drive the cost of the IC. Since the driver IC circuit is directly fabricated on the panel, the external contact of the component can be reduced, the reliability is improved, the maintenance is simpler, the assembly process time is shortened, and the electromagnetic interference characteristic is reduced, thereby reducing the application system design time and expanding the design freedom.
  • FIG. 1 is a schematic structural view of a conventional low-temperature polysilicon TFT substrate, and the manufacturing method thereof generally comprises the following steps:
  • Step 1 providing a substrate 100, depositing a buffer layer 200 on the substrate 100;
  • Step 2 depositing an amorphous silicon layer on the buffer layer 200;
  • Step 3 performing an excimer laser annealing treatment on the amorphous silicon layer to crystallize and convert the amorphous silicon layer into a polysilicon layer.
  • Step 4 through the yellow light, etching process to pattern the polysilicon layer, forming a first polysilicon segment 310 and a second polysilicon segment 320 arranged at intervals;
  • Step 5 N-type heavily doped and N-type lightly doped regions are defined on the first polysilicon segment 310 and the second polysilicon segment 320, respectively, and are respectively N-type heavily doped and N-type lightly doped The region is doped with different doses of P31 to obtain a lightly doped drain region;
  • Step 6 depositing and patterning the gate insulating layer 500 on the buffer layer 2, the first polysilicon segment 310, and the second polysilicon segment 320;
  • Step 7 Depositing and patterning a first metal layer on the gate insulating layer 500 corresponding to the first polysilicon segment 310 and the second polysilicon segment 320, respectively forming a first gate 610 and a second gate. 620;
  • Step 8 forming an interlayer insulating layer 700 on the gate insulating layer 500, and in the gate insulating layer 500 Forming a via 701 over the N-type heavily doped region corresponding to the first polysilicon segment 310 and the second polysilicon segment 320 on the interlayer insulating layer 700;
  • Step 9 depositing and patterning a second metal layer on the interlayer insulating layer 700, forming a first source/drain 810, and a second source/drain 820;
  • the first source/drain 810 and the second source/drain 820 are respectively in contact with the N-type heavily doped regions on both sides of the first polysilicon segment 310 and the second polysilicon segment 320 via the via 701. Then, a complete low-temperature polysilicon TFT substrate structure is obtained by a subsequent conventional process.
  • the low-temperature polysilicon TFT substrate includes a display region and a driving region located in the non-display region.
  • the uniformity of the display region is poor, and the electron mobility of the driving region driving circuit is also to be treated.
  • the improvement affects the quality of the low temperature polysilicon TFT substrate.
  • An object of the present invention is to provide a method for fabricating a low-temperature polysilicon TFT substrate, which can form relatively large particles of polycrystalline silicon grains in a driving region, obtain a large electron mobility, improve driving circuit characteristics, and display regions are relatively formed.
  • the polycrystalline silicon grains having smaller particles and having better uniformity make the electrical properties of the TFTs in the display region more uniform, thereby improving the quality of the low temperature polysilicon TFT substrate.
  • Another object of the present invention is to provide a low-temperature polysilicon TFT substrate structure in which a crystal grain of a polysilicon segment located in a driving region is large, and a crystal grain of a polycrystalline silicon segment located in a display region is small but uniform, so that driving The circuit has good electrical characteristics, and the electrical conductivity of the TFT in the display region is more uniform, so that the TFT substrate has higher quality.
  • the present invention provides a method for fabricating a low temperature polysilicon TFT substrate, comprising the following steps:
  • Step 1 providing a substrate, depositing a buffer layer on the substrate;
  • Step 2 depositing and patterning an amorphous silicon layer on the buffer layer to obtain a first amorphous silicon segment in a display region and a second amorphous silicon segment in a driving region;
  • Step 3 depositing a silicon oxide layer on the first amorphous silicon segment, and patterning the silicon oxide layer by a yellow light or etching process to obtain a silicon oxide layer located in the display region;
  • Step 4 using the silicon oxide layer as a photomask, performing an excimer laser annealing treatment on the first amorphous silicon segment and the second amorphous silicon segment to crystallize and transform into a polysilicon layer;
  • Step 5 removing the silicon oxide layer to obtain a first polysilicon segment located in the display region and a second polysilicon segment located in the driving region.
  • Step 6 Defining N-type heavy doping on the first polysilicon segment and the second polysilicon segment respectively a hetero- and N-type lightly doped region, and doping different doses of P31 in the N-type heavily doped and N-type lightly doped regions, respectively, to obtain a lightly doped drain region;
  • Step 7 Depositing and patterning a gate insulating layer on the buffer layer, the first polysilicon segment, and the second polysilicon segment;
  • Step 8 Depositing and patterning a first metal layer on the gate insulating layer corresponding to the first polysilicon segment and the second polysilicon segment to form a first gate and a second gate;
  • Step 9 forming an interlayer insulating layer on the gate insulating layer, and corresponding to the two sides of the first polysilicon segment and the second polysilicon segment on the gate insulating layer and the interlayer insulating layer Forming a via hole above the N-type heavily doped region;
  • Step 10 depositing and patterning a second metal layer on the interlayer insulating layer to form a first source/drain and a second source/drain.
  • the first source/drain and the second source/drain are respectively in contact with the N-type heavily doped region on both sides of the first polysilicon segment and the second polysilicon segment via the via.
  • the material of the buffer layer is silicon nitride, silicon oxide, or a combination of the two.
  • the material of the interlayer insulating layer is silicon oxide, silicon nitride, or a combination of the two.
  • the material of the first gate and the second gate is a stacked combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the N-type heavily doped and N-type lightly doped regions are respectively defined by the yellow mask by the photomask, and the different doses of P31 are doped in the N-type heavily doped and N-type lightly doped regions, respectively.
  • a lightly doped drain region is obtained.
  • the gate insulating layer, the first gate, the second gate, the via, the first source/drain, and the second source/drain are obtained by a deposition, a yellow light, and an etching process.
  • the present invention also provides a low-temperature polysilicon TFT substrate structure, comprising a substrate, a buffer layer disposed on the substrate, a first polysilicon segment and a second polysilicon segment disposed on the buffer layer, respectively a first source/drain and a second source/drain disposed on the first polysilicon segment and the second polysilicon segment, disposed on the buffer layer, the first polysilicon segment, and the second a gate insulating layer on the polysilicon segment, a first gate and a second gate disposed on the gate insulating layer above the first polysilicon segment and the second polysilicon segment, respectively
  • the interlayer insulating layer on the gate insulating layer, the first gate and the second gate, the two sides of the first polysilicon segment and the second polysilicon segment are N-type heavily doped regions,
  • the first source/drain and the second source/drain are respectively in contact with the N-type heavily doped region on both sides of the first polysilicon segment and the second polysilicon segment via a
  • the low-temperature polysilicon TFT substrate includes a display region and a driving region, the first polysilicon segment is located in a display region of the low-temperature polysilicon TFT substrate, and the second polysilicon segment is located in a driving region of the low-temperature polysilicon TFT substrate
  • the crystalline grain of the first polysilicon segment is smaller than the The crystal grains of the second polysilicon segment, and the crystal uniformity of the first polysilicon segment is greater than the crystal uniformity of the second polysilicon segment.
  • the material of the buffer layer is silicon nitride, silicon oxide, or a combination of the two.
  • the material of the interlayer insulating layer is silicon oxide, silicon nitride, or a combination of the two.
  • the material of the first gate and the second gate is a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the present invention also provides a low-temperature polysilicon TFT substrate structure, comprising a substrate, a buffer layer disposed on the substrate, a first polysilicon segment and a second polysilicon segment disposed on the buffer layer, respectively a first source/drain and a second source/drain disposed on the first polysilicon segment and the second polysilicon segment, disposed on the buffer layer, the first polysilicon segment, and the second a gate insulating layer on the polysilicon segment, a first gate and a second gate disposed on the gate insulating layer above the first polysilicon segment and the second polysilicon segment, respectively
  • the interlayer insulating layer on the gate insulating layer, the first gate and the second gate, the two sides of the first polysilicon segment and the second polysilicon segment are N-type heavily doped regions,
  • the first source/drain and the second source/drain are respectively in contact with the N-type heavily doped region on both sides of the first polysilicon segment and the second polysilicon segment via a
  • the low-temperature polysilicon TFT substrate includes a display region and a driving region, the first polysilicon segment is located in a display region of the low-temperature polysilicon TFT substrate, and the second polysilicon segment is located in a driving region of the low-temperature polysilicon TFT substrate
  • the crystal grain of the first polysilicon segment is smaller than the crystal grain of the second polysilicon segment, and the crystal uniformity of the first polysilicon segment is greater than that of the second polysilicon segment Crystal uniformity;
  • the material of the buffer layer is silicon nitride, silicon oxide, or a combination of the two;
  • the material of the interlayer insulating layer is silicon oxide, silicon nitride, or a combination of the two;
  • the material of the first gate and the second gate is a stack combination of one or more of molybdenum, titanium, aluminum and copper.
  • a pattern of amorphous silicon is first defined by a photomask, and a cold region in the crystallization process is increased, so that the crystal direction is crystallized toward the middle along the edge of the pattern, and then A silicon oxide film is deposited on the amorphous silicon layer and patterned to obtain a silicon oxide layer over the amorphous silicon layer in the display region, and then the amorphous silicon layer is subjected to excimer laser annealing treatment using a silicon oxide pattern as a mask.
  • the crystalline silicon layer is crystallized, converted into a polysilicon layer, and relatively large crystal grains are formed in the driving region to obtain high electron mobility.
  • the energy of the laser light is relatively small due to the shielding of the silicon oxide layer.
  • the relatively small but uniform crystal grains have better uniformity of electron mobility in the display region, thereby improving the quality of the low-temperature polysilicon TFT substrate, and the process is simple and easy to operate.
  • the low-temperature polysilicon TFT substrate structure provided by the invention has a larger crystal grain size of the polysilicon segment located in the driving region and is located in the display region.
  • the crystal grain of the polycrystalline silicon segment is small but uniform, so that the driving circuit has good electrical characteristics, and the electrical properties of the TFT in the display region are more uniform, so that the TFT substrate has higher quality.
  • FIG. 1 is a schematic structural view of a conventional low temperature polysilicon TFT substrate
  • FIG. 2 is a flow chart of a method for fabricating a low temperature polysilicon TFT substrate according to the present invention
  • step 1 is a schematic diagram of step 1 of a method for fabricating a low temperature polysilicon TFT substrate according to the present invention
  • 6-7 are schematic diagrams showing the third step of the method for fabricating the low temperature polysilicon TFT substrate of the present invention.
  • step 4 is a schematic diagram of step 4 of a method for fabricating a low temperature polysilicon TFT substrate according to the present invention.
  • step 5 is a schematic diagram of step 5 of a method for fabricating a low temperature polysilicon TFT substrate according to the present invention.
  • step 6 is a schematic diagram of step 6 of a method for fabricating a low temperature polysilicon TFT substrate according to the present invention
  • step 7 is a schematic diagram of step 7 of a method for fabricating a low temperature polysilicon TFT substrate according to the present invention.
  • step 8 is a schematic diagram of step 8 of a method for fabricating a low temperature polysilicon TFT substrate according to the present invention.
  • step 9 is a schematic diagram of step 9 of a method for fabricating a low temperature polysilicon TFT substrate according to the present invention.
  • FIG. 14 is a schematic view showing the step 10 of the method for fabricating a low-temperature polysilicon TFT substrate of the present invention and a cross-sectional view showing the structure of the low-temperature polysilicon TFT substrate of the present invention.
  • the present invention provides a method for fabricating a low temperature polysilicon TFT substrate, comprising the following steps:
  • Step 1 As shown in FIG. 3, a substrate 1 is provided on which a buffer layer 2 is deposited.
  • the substrate 1 is a transparent substrate.
  • the substrate 1 is a glass substrate or a plastic substrate.
  • the material of the buffer layer 2 may be silicon nitride (SiNx), silicon oxide (SiOx), or a combination of the two.
  • Step 2 As shown in FIG. 4-5, the amorphous silicon layer 3 is deposited and patterned on the buffer layer 2, and the first amorphous silicon segment 33 located at the display region and the first region located in the driving region are obtained. Two amorphous silicon segments 34.
  • the pattern of the amorphous silicon layer 3 is defined by a mask and etching, which can increase the crystallization process.
  • the crystal direction is crystallized toward the middle along the edge of the pattern, which is advantageous for the crystallization effect.
  • Step 3 depositing a silicon oxide layer on the first amorphous silicon segment 33 and the second amorphous silicon segment 34, and patterning the silicon oxide layer by a yellow light or etching process.
  • the silicon oxide layer 4 located in the display region is obtained.
  • Step 4 as shown in FIG. 8, the first amorphous silicon segment 33 and the second amorphous silicon segment 34 are subjected to excimer laser annealing treatment using the silicon oxide layer 4 as a mask to crystallize and transform into polysilicon. Floor.
  • the first amorphous silicon segment 33 and the second amorphous silicon segment 34 are subjected to excimer laser annealing treatment, since the silicon oxide layer 4 is covered over the first amorphous silicon segment 33 of the display region, the energy of the laser light is relatively Smaller, forming relatively smaller grains.
  • the second amorphous silicon segment 34 of the driving region is not covered by the silicon oxide layer 4, and thus the energy for obtaining the laser light is relatively large, forming relatively large crystal grains.
  • Step 5 as shown in FIG. 9, the silicon oxide layer 4 is removed, and a first polysilicon segment 31 located at a display region and a second polysilicon segment 32 at a driving region are obtained.
  • the crystal grains in the first polysilicon segment 31 of the display region are smaller, and the crystal grains of the second polysilicon segment 32 located in the driving region are larger, but are located in the first polysilicon segment 31 of the display region.
  • the uniformity of the crystal grains is good.
  • N-type heavily doped and N-type lightly doped regions are defined on the first polysilicon segment 31 and the second polysilicon segment 32, respectively, and are respectively N-type heavily Doping and N-type lightly doped regions are doped with different doses of P31 (phosphorus 31) to obtain lightly doped drain regions.
  • the N-type heavily doped and N-type lightly doped regions are respectively defined by the yellow mask by the two masks, and the different doses of P31 (phosphorus) are doped in the N-type heavily doped and N-type lightly doped regions, respectively. 31), a lightly doped drain region is obtained.
  • Step 7 As shown in FIG. 11, the gate insulating layer 5 is deposited and patterned on the buffer layer 2, the first polysilicon segment 31, and the second polysilicon segment 32.
  • Step 8 As shown in FIG. 12, a first metal layer is deposited and patterned on the gate insulating layer 5 corresponding to the first polysilicon segment 31 and the second polysilicon segment 32, respectively, to form a first gate.
  • the pole 61 and the second grid 62 are deposited and patterned on the gate insulating layer 5 corresponding to the first polysilicon segment 31 and the second polysilicon segment 32, respectively, to form a first gate.
  • the material of the first gate 61 and the second gate 62 may be a stacked combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • Step 9 as shown in FIG. 13, an interlayer insulating layer 7 is formed on the gate insulating layer 5, and the first polysilicon segment is corresponding to the gate insulating layer 5 and the interlayer insulating layer 7. 31.
  • a via 70 is formed over the N-type heavily doped region on both sides of the second polysilicon segment 32.
  • the material of the interlayer insulating layer 7 may be silicon nitride (SiNx), silicon oxide (SiOx), or a combination of both.
  • Step 10 depositing and patterning a second metal layer on the interlayer insulating layer 7, forming a first source/drain 81 and a second source/drain 82.
  • the first source/drain 81 and the second source/drain 82 are heavily doped with N-types on both sides of the first polysilicon segment 31 and the second polysilicon segment 32 via the via hole 70, respectively.
  • the area is in contact.
  • the subsequent process can be completed by the prior art, and finally a complete low temperature polysilicon TFT substrate is obtained.
  • the gate insulating layer 5, the first gate 61, the second gate 62, the via 70, the first source/drain 81, and the second source are obtained by a deposition, a yellow light, and an etching process. Drain 82.
  • a pattern of amorphous silicon is first defined by a photomask, a cold region is increased during the crystallization process, the crystal direction is crystallized toward the middle along the edge of the pattern, and then an oxide is deposited on the amorphous silicon layer.
  • the silicon film is patterned to obtain a silicon oxide layer above the amorphous silicon layer in the display region, and then the amorphous silicon layer is subjected to excimer laser annealing treatment using the silicon oxide pattern as a mask to crystallize and convert the amorphous silicon layer into a polysilicon layer, and relatively large crystal grains are formed in the driving region to obtain high electron mobility.
  • the energy of the laser light is relatively small due to the shielding of the silicon oxide layer, forming a relatively small but uniformity.
  • a good crystal grain has a good uniformity of electron mobility, thereby improving the quality of the low temperature polysilicon TFT substrate.
  • the present invention further provides a low temperature polysilicon TFT substrate structure, including a substrate 1 , a buffer layer 2 disposed on the substrate 1 , and a first polysilicon segment disposed on the buffer layer 2 .
  • 31 and the second polysilicon segment 32, the first source/drain 81 and the second source/drain 82 respectively disposed on the first polysilicon segment 31 and the second polysilicon segment 32 are disposed on The buffer layer 2, the first polysilicon segment 31, and the gate insulating layer 5 on the second polysilicon segment 32 are disposed on the gate insulating layer 5 at the first polysilicon segment 31 and a first gate 61 and a second gate 62 over the second polysilicon segment 32, and an interlayer insulating layer 7 disposed on the gate insulating layer 5, the first gate 61 and the second gate 62
  • the two sides of the first polysilicon segment 31 and the second polysilicon segment 32 are N-type heavily doped regions, and the first source/drain 81 and the second source/drain
  • the low temperature polysilicon TFT substrate includes a display region and a driving region, the first polysilicon segment 31 is located in a display region of the low temperature polysilicon TFT substrate, and the second polysilicon segment 32 is located on the low temperature polysilicon TFT substrate. a driving region, the crystal grain of the first polysilicon segment 31 is smaller than the crystal grain of the second polysilicon segment 32, and the crystal uniformity of the first polysilicon segment 31 is greater than the second The crystal uniformity of the polysilicon segment 32.
  • the substrate 1 is a transparent substrate.
  • the substrate 1 is a glass substrate or a plastic substrate.
  • the material of the buffer layer 2 and the interlayer insulating layer 7 may be silicon nitride (SiNx), Silicon oxide (SiOx), or a combination of the two.
  • the material of the first gate 61 and the second gate 62 may be a stacked combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • the crystal grain of the polysilicon segment located in the driving region is large, and the crystal grain of the polysilicon segment located in the display region is small but uniform, so that the driving circuit has good electrical characteristics, and the display
  • the TFTs in the region are more uniform in electrical properties, so that the TFT substrate has higher quality.
  • the method for fabricating the low-temperature polysilicon TFT substrate of the present invention first defines a pattern of amorphous silicon by using a mask, increases the cold region in the crystallization process, and crystallizes the crystal direction along the edge of the pattern to the middle, and then A silicon oxide film is deposited on the crystalline silicon layer and patterned to obtain a silicon oxide layer over the amorphous silicon layer in the display region, and then the amorphous silicon layer is subjected to excimer laser annealing treatment using a silicon oxide pattern as a mask to make amorphous The silicon layer is crystallized, converted into a polysilicon layer, and relatively large crystal grains are formed in the driving region to obtain high electron mobility.
  • the low-temperature polysilicon TFT substrate structure provided by the invention has a large crystal grain size of the polycrystalline silicon segment in the driving region, and the crystal grain of the polycrystalline silicon segment located in the display region is small but uniform, so that the driving circuit has good electrical characteristics.
  • the electrical conductivity of the TFT in the display region is more uniform, so that the TFT substrate has higher quality.

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Abstract

一种低温多晶硅TFT基板的制作方法及其结构，该方法包括：步骤1、提供基板(1)，沉积缓冲层(2)；步骤2、沉积并图案化非晶硅层(3)；步骤3、沉积并图案化氧化硅层(4)；步骤4、以氧化硅层(4)为光罩，对非晶硅层(3)进行准分子激光退火处理，使其结晶、转变为多晶硅层；步骤5、得到第一多晶硅段(31)与第二多晶硅段(32)；步骤6、分别在第一多晶硅段(31)、第二多晶硅段(32)上定义出N型重掺杂和N型轻掺杂区域，并得到轻掺杂漏区；步骤7、沉积并图案化栅极绝缘层(5)；步骤8、形成第一栅极(61)、及第二栅极(62)；步骤9、形成过孔(70)；步骤10、形成第一源/漏极(81)、及第二源/漏极(82)。

Description

低温多晶硅TFT基板的制作方法及其结构 技术领域
本发明涉及显示技术领域，尤其涉及一种低温多晶硅TFT基板的制作方法及其结构。
背景技术
薄膜晶体管液晶显示器(Thin-film transisitor liquid cystal display，TFT-LCD)分为多晶硅(Poly-Si)技术与非晶硅(a-Si)技术，低温多晶硅(Low Temperature Poly-silicon，LTPS)技术是新一代薄膜晶体管液晶显示器的制造技术，与传统非晶硅显示器最大差异在于低温多晶硅显示器反应速度较快，且有高亮度、高解析度与低耗电量等优点。
低温多晶硅的硅结晶排列较非晶硅有次序，使得电子移动率相对高一百倍以上，可以将外围驱动电路同时制作在玻璃基板上，可节省空间及驱动IC的成本。由于驱动IC线路直接制作于面板上，可以减少零件对外接点，增加可靠度、维护更简单、缩短组装制程时间及降低电磁干扰特性，可减少应用系统设计时程及扩大设计自由度。
图1所示为一种现有低温多晶硅TFT基板的结构示意图，其制作方法大致包括如下步骤：
步骤1、提供基板100，在基板100上沉积缓冲层200；
步骤2、在缓冲层200上沉积非晶硅层；
步骤3、对非晶硅层进行准分子激光退火处理，使非晶硅层结晶、转变为多晶硅层，
步骤4、通过黄光、蚀刻制程对多晶硅层进行图案化处理，形成间隔排列的第一多晶硅段310与第二多晶硅段320；
步骤5、分别在第一多晶硅段310、第二多晶硅段320上定义出N型重掺杂和N型轻掺杂区域，并分别在N型重掺杂与N型轻掺杂区域掺杂不同剂量的P31，得到轻掺杂漏区；
步骤6、在缓冲层2、第一多晶硅段310、及第二多晶硅段320上沉积并图案化栅极绝缘层500；
步骤7、在栅极绝缘层500上对应第一多晶硅段310、第二多晶硅段320的上方分别沉积并图案化第一金属层，形成第一栅极610、及第二栅极620；
步骤8、在栅极绝缘层500上形成层间绝缘层700，并在栅极绝缘层500 与层间绝缘层700上对应第一多晶硅段310、第二多晶硅段320两侧的N型重掺杂区域上方形成过孔701；
步骤9、在层间绝缘层700上沉积并图案化第二金属层，形成第一源/漏极810、及第二源/漏极820；
所述第一源/漏极810与第二源/漏极820分别经由过孔701与第一多晶硅段310、第二多晶硅段320两侧的N型重掺杂区域相接触。之后通过后续常规制程得到完整的低温多晶硅TFT基板结构。
然而低温多晶硅TFT基板中包括显示区域、及位于非显示区域的驱动区域，采用上述方法制作出的低温多晶硅TFT基板中，显示区域的均一性较差，同时驱动区域驱动电路的电子迁移率也有待提高，进而影响了低温多晶硅TFT基板的品质。
发明内容
本发明的目的在于提供一种低温多晶硅TFT基板的制作方法，能够在驱动区域形成相对较大颗粒的多晶硅晶粒，获得较大的电子迁移率，使驱动电路特性得到提高，而显示区域形成相对较小颗粒且具有较佳的均一性的多晶硅晶粒，使得显示区域内TFT的电性更均一，从而提高低温多晶硅TFT基板的品质。
本发明的另一目的在于提供一种低温多晶硅TFT基板结构，其位于驱动区域的多晶硅段的结晶晶粒较大，位于显示区域的多晶硅段的结晶晶粒较小但均一性较好，使得驱动电路具有良好的电特性，显示区域内TFT的电性更均一，从而使得TFT基板具有较高的品质。
为实现上述目的，本发明提供一种低温多晶硅TFT基板的制作方法，包括如下步骤：
步骤1、提供基板，在所述基板上沉积缓冲层；
步骤2、在所述缓冲层上沉积并图案化非晶硅层，得到间隔排列的位于显示区域的第一非晶硅段、及位于驱动区域的第二非晶硅段；
步骤3、在所述第一非晶硅段上沉积氧化硅层，并通过黄光、蚀刻制程对氧化硅层进行图案化处理，得到位于显示区域的氧化硅层；
步骤4、以所述氧化硅层作为光罩，对第一非晶硅段与第二非晶硅段进行准分子激光退火处理，使其结晶、转变为多晶硅层；
步骤5、去除所述氧化硅层，得到间隔排列的位于显示区域的第一多晶硅段、及位于驱动区域的第二多晶硅段；
步骤6、分别在所述第一多晶硅段、第二多晶硅段上定义出N型重掺 杂和N型轻掺杂区域，并分别在N型重掺杂与N型轻掺杂区域掺杂不同剂量的P31，得到轻掺杂漏区；
步骤7、在所述缓冲层、第一多晶硅段、及第二多晶硅段上沉积并图案化栅极绝缘层；
步骤8、在所述栅极绝缘层上对应第一多晶硅段、第二多晶硅段的上方分别沉积并图案化第一金属层，形成第一栅极、及第二栅极；
步骤9、在所述栅极绝缘层上形成层间绝缘层，并在所述栅极绝缘层与层间绝缘层上对应所述第一多晶硅段与第二多晶硅段两侧的N型重掺杂区域上方形成过孔；
步骤10、在所述层间绝缘层上沉积并图案化第二金属层，形成第一源/漏极、及第二源/漏极，
所述第一源/漏极与第二源/漏极分别经由所述过孔与所述第一多晶硅段与第二多晶硅段两侧的N型重掺杂区域相接触。
所述缓冲层的材料为氮化硅、氧化硅、或二者的组合。
所述层间绝缘层的材料为氧化硅、氮化硅、或二者的组合。
所述第一栅极与第二栅极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
所述步骤6用两次光罩通过黄光光阻分别定义出N型重掺杂和N型轻掺杂区域，并分别在N型重掺杂与N型轻掺杂区域掺杂不同剂量的P31，得到轻掺杂漏区。
通过沉积、黄光、及蚀刻制程得到所述栅极绝缘层、第一栅极、第二栅极、过孔、第一源/漏极、及第二源/漏极。
本发明还提供一种低温多晶硅TFT基板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上间隔排列的第一多晶硅段与第二多晶硅段、分别设于所述第一多晶硅段与第二多晶硅段上的第一源/漏极与第二源/漏极、设于所述缓冲层、第一多晶硅段、及第二多晶硅段上的栅极绝缘层、设于所述栅极绝缘层上分别位于第一多晶硅段与第二多晶硅段上方的第一栅极与第二栅极、及设于所述栅极绝缘层、第一栅极及第二栅极上的层间绝缘层，所述第一多晶硅段与第二多晶硅段的两侧为N型重掺杂区域，所述第一源/漏极与第二源/漏极分别经由一过孔与所述第一多晶硅段与第二多晶硅段两侧的N型重掺杂区域相接触。
所述低温多晶硅TFT基板包括显示区域与驱动区域，所述第一多晶硅段位于所述低温多晶硅TFT基板的显示区域，所述第二多晶硅段位于所述低温多晶硅TFT基板的驱动区域，所述第一多晶硅段的结晶晶粒小于所述 第二多晶硅段的结晶晶粒，且所述第一多晶硅段的结晶均匀度大于所述第二多晶硅段的结晶均匀度。
所述缓冲层的材料为氮化硅、氧化硅、或二者的组合。
所述层间绝缘层的材料为氧化硅、氮化硅、或二者的组合。
所述第一栅极、第二栅极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
本发明还提供一种低温多晶硅TFT基板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上间隔排列的第一多晶硅段与第二多晶硅段、分别设于所述第一多晶硅段与第二多晶硅段上的第一源/漏极与第二源/漏极、设于所述缓冲层、第一多晶硅段、及第二多晶硅段上的栅极绝缘层、设于所述栅极绝缘层上分别位于第一多晶硅段与第二多晶硅段上方的第一栅极与第二栅极、及设于所述栅极绝缘层、第一栅极及第二栅极上的层间绝缘层，所述第一多晶硅段与第二多晶硅段的两侧为N型重掺杂区域，所述第一源/漏极与第二源/漏极分别经由一过孔与所述第一多晶硅段与第二多晶硅段两侧的N型重掺杂区域相接触；
所述低温多晶硅TFT基板包括显示区域与驱动区域，所述第一多晶硅段位于所述低温多晶硅TFT基板的显示区域，所述第二多晶硅段位于所述低温多晶硅TFT基板的驱动区域，所述第一多晶硅段的结晶晶粒小于所述第二多晶硅段的结晶晶粒，且所述第一多晶硅段的结晶均匀度大于所述第二多晶硅段的结晶均匀度；
其中，所述缓冲层的材料为氮化硅、氧化硅、或二者的组合；
其中，所述层间绝缘层的材料为氧化硅、氮化硅、或二者的组合；
其中，所述第一栅极与第二栅极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
本发明的有益效果：本发明的低温多晶硅TFT基板的制作方法，先用光罩定义出非晶硅的图形，增加结晶过程中冷区域，使结晶方向沿着图形的边缘向中间结晶，再在非晶硅层上沉积氧化硅膜并图案化，得到位于显示区域的非晶硅层上方的氧化硅层，然后以氧化硅图形作为光罩对非晶硅层进行准分子激光退火处理，使非晶硅层结晶、转变为多晶硅层，并且在驱动区域形成相对较大的晶粒，以获得高的电子迁移率，在显示区域因有氧化硅层的遮挡，获得激光的能量相对较小，形成相对较小但均一性较好的晶粒，使得显示区域内电子迁移率具有较好的均一性，从而提高低温多晶硅TFT基板的品质，且制程简便，易操作。本发明提供的低温多晶硅TFT基板结构，其位于驱动区域的多晶硅段的结晶晶粒较大，位于显示区域的 多晶硅段的结晶晶粒较小但均一性较好，使得驱动电路具有良好的电特性，显示区域内TFT的电性更均一，从而使得TFT基板具有较高的品质。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为一种现有低温多晶硅TFT基板的结构示意图；
图2为本发明低温多晶硅TFT基板的制作方法的流程图；
图3为本发明低温多晶硅TFT基板的制作方法的步骤1的示意图；
图4-5为本发明低温多晶硅TFT基板的制作方法的步骤2的示意图；
图6-7为本发明低温多晶硅TFT基板的制作方法的步骤3的示意图；
图8为本发明低温多晶硅TFT基板的制作方法的步骤4的示意图；
图9为本发明低温多晶硅TFT基板的制作方法的步骤5的示意图；
图10为本发明低温多晶硅TFT基板的制作方法的步骤6的示意图；
图11为本发明低温多晶硅TFT基板的制作方法的步骤7的示意图；
图12为本发明低温多晶硅TFT基板的制作方法的步骤8的示意图；
图13为本发明低温多晶硅TFT基板的制作方法的步骤9的示意图；
图14为本发明低温多晶硅TFT基板的制作方法的步骤10的示意图暨本发明低温多晶硅TFT基板结构的剖面示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种低温多晶硅TFT基板的制作方法，包括如下步骤：
步骤1、如图3所示，提供基板1，在所述基板1上沉积缓冲层2。
所述基板1为透明基板，优选的，所述基板1为玻璃基板或塑料基板。
具体地，所述缓冲层2的材料可以是氮化硅(SiNx)、氧化硅(SiOx)、或二者的组合。
步骤2、如图4-5所示，在所述缓冲层2上沉积并图案化非晶硅层3，得到间隔排列的位于显示区域的第一非晶硅段33、及位于驱动区域的第二非晶硅段34。
该步骤中用光罩及蚀刻定义出非晶硅层3的图形，可增加结晶过程中 冷区域，使结晶方向沿着图形的边缘向中间结晶，有利于结晶效果。
步骤3、如图6-7所示，在所述第一非晶硅段33、第二非晶硅段34上沉积氧化硅层，并通过黄光、蚀刻制程对氧化硅层进行图案化处理，得到位于显示区域的氧化硅层4。
此时位于非显示区域的驱动区域的第二非晶硅段34上方没有氧化硅层4的覆盖。
步骤4、如图8所示，以所述氧化硅层4作为光罩，对第一非晶硅段33与第二非晶硅段34进行准分子激光退火处理，使其结晶、转变为多晶硅层。
在对第一非晶硅段33、第二非晶硅段34进行准分子激光退火处理时，由于显示区域的第一非晶硅段33上方有氧化硅层4覆盖，因而获得激光的能量相对较小，形成相对较小的晶粒。驱动区域的第二非晶硅段34上方没有氧化硅层4覆盖，因而获得激光的能量相对较大，形成相对较大的晶粒。
步骤5、如图9所示，去除所述氧化硅层4，得到间隔排列的位于显示区域的第一多晶硅段31、及位于驱动区域的第二多晶硅段32。
其中位于显示区域的第一多晶硅段31中的晶粒较小，位于驱动区域的第二多晶硅段32的晶粒较大，但是位于显示区域的第一多晶硅段31中的晶粒的均一性较好。
步骤6、如图10所示，分别在所述第一多晶硅段31、第二多晶硅段32上定义出N型重掺杂和N型轻掺杂区域，并分别在N型重掺杂与N型轻掺杂区域掺杂不同剂量的P31(磷31)，得到轻掺杂漏区。
具体地，用两次光罩通过黄光光阻分别定义出N型重掺杂和N型轻掺杂区域，并分别在N型重掺杂与N型轻掺杂区域掺杂不同剂量的P31(磷31)，得到轻掺杂漏区。
步骤7、如图11所示，在所述缓冲层2、第一多晶硅段31、及第二多晶硅段32上沉积并图案化栅极绝缘层5。
步骤8、如图12所示，在所述栅极绝缘层5上对应第一多晶硅段31、第二多晶硅段32的上方分别沉积并图案化第一金属层，形成第一栅极61、及第二栅极62。
具体地，所述第一栅极61、第二栅极62的材料可以是钼(Mo)、钛(Ti)、铝(Al)和铜(Cu)中的一种或多种的堆栈组合。
步骤9、如图13所示，在所述栅极绝缘层5上形成层间绝缘层7，并在所述栅极绝缘层5与层间绝缘层7上对应所述第一多晶硅段31、第二多晶硅段32两侧的N型重掺杂区域上方形成过孔70。
具体地，所述层间绝缘层7的材料可以是氮化硅(SiNx)、氧化硅(SiOx)、或二者的组合。
步骤10、如14所示，在所述层间绝缘层7上沉积并图案化第二金属层，形成第一源/漏极81、及第二源/漏极82。
所述第一源/漏极81与第二源/漏极82分别经由所述过孔70与所述第一多晶硅段31、第二多晶硅段32两侧的N型重掺杂区域相接触。之后可以采用现有技术完成后续制程，最终得到完整的低温多晶硅TFT基板。
具体地，通过沉积、黄光、及蚀刻制程得到所述栅极绝缘层5、第一栅极61、第二栅极62、过孔70、第一源/漏极81、及第二源/漏极82。
上述低温多晶硅TFT基板的制作方法中，先用光罩定义出非晶硅的图形，增加结晶过程中冷区域，使结晶方向沿着图形的边缘向中间结晶，再在非晶硅层上沉积氧化硅膜并图案化，得到位于显示区域的非晶硅层上方的氧化硅层，然后以氧化硅图形作为光罩对非晶硅层进行准分子激光退火处理，使非晶硅层结晶、转变为多晶硅层，并且在驱动区域形成相对较大的晶粒，以获得高的电子迁移率，在显示区域因有氧化硅层的遮挡，获得激光的能量相对较小，形成相对较小但均一性较好的晶粒，其电子迁移率具有较好的均一性，从而提高低温多晶硅TFT基板的品质。
请参阅图14，本发明还提供一种低温多晶硅TFT基板结构，包括基板1、设于所述基板1上的缓冲层2、设于所述缓冲层2上间隔排列的第一多晶硅段31与第二多晶硅段32、分别设于所述第一多晶硅段31与第二多晶硅段32上的第一源/漏极81与第二源/漏极82、设于所述缓冲层2、第一多晶硅段31、及第二多晶硅段32上的栅极绝缘层5、设于所述栅极绝缘层5上分别位于第一多晶硅段31与第二多晶硅段32上方的第一栅极61与第二栅极62、及设于所述栅极绝缘层5、第一栅极61及第二栅极62上的层间绝缘层7，所述第一多晶硅段31与第二多晶硅段32的两侧为N型重掺杂区域，所述第一源/漏极81与第二源/漏极82分别经由一过孔70与所述第一多晶硅段31与第二多晶硅段32两侧的N型重掺杂区域相接触；
所述低温多晶硅TFT基板包括显示区域与驱动区域，所述第一多晶硅段31位于所述低温多晶硅TFT基板的显示区域，所述第二多晶硅段32位于所述低温多晶硅TFT基板的驱动区域，所述第一多晶硅段31的结晶晶粒小于所述第二多晶硅段32的结晶晶粒，且所述第一多晶硅段31的结晶均匀度大于所述第二多晶硅段32的结晶均匀度。
所述基板1为透明基板，优选的，所述基板1为玻璃基板或塑料基板。
具体地，所述缓冲层2、层间绝缘层7的材料可以是氮化硅(SiNx)、 氧化硅(SiOx)、或二者的组合。所述第一栅极61与第二栅极62的材料可以是钼(Mo)、钛(Ti)、铝(Al)和铜(Cu)中的一种或多种的堆栈组合。
上述低温多晶硅TFT基板结构中，其位于驱动区域的多晶硅段的结晶晶粒较大，位于显示区域的多晶硅段的结晶晶粒较小但均一性较好，因而驱动电路具有良好的电特性，显示区域内TFT的电性更均一，从而使TFT基板具有较高的品质。
综上所述，本发明的低温多晶硅TFT基板的制作方法，先用光罩定义出非晶硅的图形，增加结晶过程中冷区域，使结晶方向沿着图形的边缘向中间结晶，再在非晶硅层上沉积氧化硅膜并图案化，得到位于显示区域的非晶硅层上方的氧化硅层，然后以氧化硅图形作为光罩对非晶硅层进行准分子激光退火处理，使非晶硅层结晶、转变为多晶硅层，并且在驱动区域形成相对较大的晶粒，以获得高的电子迁移率，在显示区域因有氧化硅层的遮挡，获得激光的能量相对较小，形成相对较小但均一性较好的晶粒，使得显示区域内电子迁移率具有较好的均一性，从而提高低温多晶硅TFT基板的品质，且制程简便，易操作。本发明提供的低温多晶硅TFT基板结构，其位于驱动区域的多晶硅段的结晶晶粒较大，位于显示区域的多晶硅段的结晶晶粒较小但均一性较好，使得驱动电路具有良好的电特性，显示区域内TFT的电性更均一，从而使得TFT基板具有较高的品质。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (11)

  1. 一种低温多晶硅TFT基板的制作方法，包括如下步骤：
    步骤1、提供基板，在所述基板上沉积缓冲层；
    步骤2、在所述缓冲层上沉积并图案化非晶硅层，得到间隔排列的位于显示区域的第一非晶硅段、及位于驱动区域的第二非晶硅段；
    步骤3、在所述第一非晶硅段、第二非晶硅段上沉积氧化硅层，并通过黄光、蚀刻制程对氧化硅层进行图案化处理，得到位于显示区域的氧化硅层；
    步骤4、以所述氧化硅层作为光罩，对第一非晶硅段与第二非晶硅段进行准分子激光退火处理，使其结晶、转变为多晶硅层；
    步骤5、去除所述氧化硅层，得到间隔排列的位于显示区域的第一多晶硅段、及位于驱动区域的第二多晶硅段；
    步骤6、分别在所述第一多晶硅段、第二多晶硅段上定义出N型重掺杂和N型轻掺杂区域，并分别在N型重掺杂与N型轻掺杂区域掺杂不同剂量的P31，得到轻掺杂漏区；
    步骤7、在所述缓冲层、第一多晶硅段、及第二多晶硅段上沉积并图案化栅极绝缘层；
    步骤8、在所述栅极绝缘层上对应第一多晶硅段、第二多晶硅段的上方分别沉积并图案化第一金属层，形成第一栅极、及第二栅极；
    步骤9、在所述栅极绝缘层上形成层间绝缘层，并在所述栅极绝缘层与层间绝缘层上对应所述第一多晶硅段与第二多晶硅段两侧的N型重掺杂区域上方形成过孔；
    步骤10、在所述层间绝缘层上沉积并图案化第二金属层，形成第一源/漏极、及第二源/漏极，
    所述第一源/漏极与第二源/漏极分别经由所述过孔与所述第一多晶硅段与第二多晶硅段两侧的N型重掺杂区域相接触。
  2. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，所述缓冲层的材料为氮化硅、氧化硅、或二者的组合。
  3. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，所述层间绝缘层的材料为氧化硅、氮化硅、或二者的组合。
  4. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，所述第一栅极、第二栅极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
  5. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，所述步骤6用两次光罩通过黄光光阻分别定义出N型重掺杂和N型轻掺杂区域，并分别在N型重掺杂与N型轻掺杂区域掺杂不同剂量的P31，得到轻掺杂漏区。
  6. 如权利要求1所述的低温多晶硅TFT基板的制作方法，其中，通过沉积、黄光、及蚀刻制程得到所述栅极绝缘层、第一栅极、第二栅极、过孔、第一源/漏极、及第二源/漏极。
  7. 一种低温多晶硅TFT基板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上间隔排列的第一多晶硅段与第二多晶硅段、分别设于所述第一多晶硅段与第二多晶硅段上的第一源/漏极与第二源/漏极、设于所述缓冲层、第一多晶硅段、及第二多晶硅段上的栅极绝缘层、设于所述栅极绝缘层上分别位于第一多晶硅段与第二多晶硅段上方的第一栅极与第二栅极、及设于所述栅极绝缘层、第一栅极及第二栅极上的层间绝缘层，所述第一多晶硅段与第二多晶硅段的两侧为N型重掺杂区域，所述第一源/漏极与第二源/漏极分别经由一过孔与所述第一多晶硅段与第二多晶硅段两侧的N型重掺杂区域相接触；
    所述低温多晶硅TFT基板包括显示区域与驱动区域，所述第一多晶硅段位于所述低温多晶硅TFT基板的显示区域，所述第二多晶硅段位于所述低温多晶硅TFT基板的驱动区域，所述第一多晶硅段的结晶晶粒小于所述第二多晶硅段的结晶晶粒，且所述第一多晶硅段的结晶均匀度大于所述第二多晶硅段的结晶均匀度。
  8. 如权利要求7所述的低温多晶硅TFT基板结构，其中，所述缓冲层的材料为氮化硅、氧化硅、或二者的组合。
  9. 如权利要求7所述的低温多晶硅TFT基板结构，其特中，所述层间绝缘层的材料为氧化硅、氮化硅、或二者的组合。
  10. 如权利要求7所述的低温多晶硅TFT基板结构，其中，所述第一栅极与第二栅极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
  11. 一种低温多晶硅TFT基板结构，包括基板、设于所述基板上的缓冲层、设于所述缓冲层上间隔排列的第一多晶硅段与第二多晶硅段、分别设于所述第一多晶硅段与第二多晶硅段上的第一源/漏极与第二源/漏极、设于所述缓冲层、第一多晶硅段、及第二多晶硅段上的栅极绝缘层、设于所述栅极绝缘层上分别位于第一多晶硅段与第二多晶硅段上方的第一栅极与第二栅极、及设于所述栅极绝缘层、第一栅极及第二栅极上的层间绝缘层，所述第一多晶硅段与第二多晶硅段的两侧为N型重掺杂区域，所述第一源/ 漏极与第二源/漏极分别经由一过孔与所述第一多晶硅段与第二多晶硅段两侧的N型重掺杂区域相接触；
    所述低温多晶硅TFT基板包括显示区域与驱动区域，所述第一多晶硅段位于所述低温多晶硅TFT基板的显示区域，所述第二多晶硅段位于所述低温多晶硅TFT基板的驱动区域，所述第一多晶硅段的结晶晶粒小于所述第二多晶硅段的结晶晶粒，且所述第一多晶硅段的结晶均匀度大于所述第二多晶硅段的结晶均匀度；
    其中，所述缓冲层的材料为氮化硅、氧化硅、或二者的组合；
    其中，所述层间绝缘层的材料为氧化硅、氮化硅、或二者的组合；
    其中，所述第一栅极与第二栅极的材料为钼、钛、铝和铜中的一种或多种的堆栈组合。
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