WO2016095306A1 - 一种低温多晶硅薄膜晶体管的制造方法 - Google Patents

一种低温多晶硅薄膜晶体管的制造方法 Download PDF

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WO2016095306A1
WO2016095306A1 PCT/CN2015/070890 CN2015070890W WO2016095306A1 WO 2016095306 A1 WO2016095306 A1 WO 2016095306A1 CN 2015070890 W CN2015070890 W CN 2015070890W WO 2016095306 A1 WO2016095306 A1 WO 2016095306A1
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region
layer
photoresist
polysilicon
drain
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French (fr)
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陈归
薛景峰
张鑫
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/425,052 priority Critical patent/US9647088B2/en
Publication of WO2016095306A1 publication Critical patent/WO2016095306A1/zh
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    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
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    • H10D30/022—Manufacture or treatment of FETs having insulated gates [IGFET] having lightly-doped source or drain extensions selectively formed at the sides of the gates
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    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H10D30/0229—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET forming drain regions and lightly-doped drain [LDD] simultaneously, e.g. using implantation through a T-shaped mask
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
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    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
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    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
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    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
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    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
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    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
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    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
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    • H10P95/90—Thermal treatments, e.g. annealing or sintering

Definitions

  • the invention relates to a method for manufacturing a low temperature polycrystalline silicon (LTPS) thin film transistor (TFT).
  • LTPS low temperature polycrystalline silicon
  • TFT thin film transistor
  • LCDs liquid crystal displays
  • amorphous silicon thin film transistors are widely used as switching elements of LCDs, but a-Si TFT LCDs are required to be thin, lightweight, high-definition, high in brightness, high in reliability, and low in power consumption. Other requirements are still limited.
  • LTPS low temperature polycrystal silicon
  • a substrate 10 is provided; then, a polysilicon (LTPS) layer 12 is formed on the substrate 10, wherein an amorphous silicon (a-Si) layer is formed on the substrate 10, for example, by a sputtering process. Then, a returning process is performed to recrystallize the amorphous silicon layer to form polycrystalline silicon, and finally the polycrystalline silicon layer 12 is formed by exposure and development of the polycrystalline silicon.
  • LTPS polysilicon
  • the insulating layer 14 is covered on the polysilicon layer 12; then, the gate electrode 16 is formed on the insulating layer 14; then, a photoresist layer 18 is formed on the insulating layer 14, wherein the photoresist layer 18 is formed.
  • the remaining photoresist material is removed; then, ions are implanted into the two side regions 122, 124 of the polysilicon layer 12 by an ion implantation process.
  • the photoresist layer 18 is removed, for example, the photoresist layer 18 is removed by exposure and development; then, the ion implantation process is again applied to both sides of the channel region 121 of the polysilicon layer 12.
  • the regions implant ions such that regions 122, 124 form heavily doped regions, regions 126, 128 form lightly doped regions, wherein regions 122 and regions 126 form a source region, and regions 124 and regions 128 form a drain region;
  • a passivation layer 20 is formed on the insulating layer 14, wherein the passivation layer 20 covers the insulating layer 14 and the gate electrode 16.
  • an object of the present invention is to provide a method for fabricating a low temperature polysilicon thin film transistor, comprising: providing a substrate; forming a buffer layer on the substrate; and simultaneously forming polysilicon on the buffer layer And a photoresist layer, wherein the polysilicon layer comprises a source region, a drain region, and a channel region, wherein the source region is away from a thickness of the photoresist layer on a portion of the channel region, and the source region is adjacent
  • the thickness of the photoresist layer on a portion of the channel region and the thickness of the photoresist layer on the channel region are sequentially increased, and the thickness of the photoresist layer on a portion of the drain region away from the channel region is The thickness of the photoresist layer on a portion of the drain region adjacent to the channel region and the thickness of the photoresist layer on the channel region are sequentially increased; ion implantation is performed on the source region and the drain region to The source region and the
  • a portion of the drain region away from the channel region is a drain heavily doped region, and a portion of the drain region adjacent to the channel region is a drain lightly doped region; removing the photoresist layer; Forming an insulating layer on the polysilicon layer; forming a gate electrode on the insulating layer; forming a passivation layer on the insulating layer, wherein the passivation layer covers the gate electrode.
  • the polysilicon layer and the photoresist layer are simultaneously formed by forming polysilicon on the surface of the buffer layer, and then forming a photoresist material on the surface of the polysilicon by spin coating, and then using the predetermined mask to the photoresist Exposing the material, and developing the exposed photoresist material, leaving polysilicon and photoresist material in the region where the polysilicon layer and the photoresist layer are formed, and removing polysilicon and photoresist materials at other positions.
  • the transmittance of the predetermined reticle relative to the region of the channel region, the transmittance of the predetermined reticle to the region of the source lightly doped region, and the predetermined reticle relative to the source The light transmittance of the region of the heavily doped region is sequentially increased, and the predetermined mask is transparent to the region of the channel region
  • the light transmittance, the light transmittance of the predetermined mask relative to the region of the drain lightly doped region, and the transmittance of the predetermined mask to the region of the drain heavily doped region are sequentially increased.
  • the polysilicon layer and the photoresist layer are simultaneously formed by forming polysilicon on the surface of the buffer layer, and then forming a photoresist material on the surface of the polysilicon by spin coating, and then using the predetermined mask to the photoresist Exposing the material, and developing the exposed photoresist material, leaving polysilicon and photoresist material in the region where the polysilicon layer and the photoresist layer are formed, and removing polysilicon and photoresist materials at other positions.
  • the transmittance of the predetermined reticle relative to the region of the channel region, the transmittance of the predetermined reticle to the region of the source lightly doped region, and the predetermined reticle relative to the source The light transmittance of the region of the heavily doped region is sequentially decreased, the transmittance of the predetermined mask relative to the region of the channel region, and the transmittance of the predetermined mask to the region of the lightly doped region of the drain.
  • the rate and the transmittance of the predetermined reticle relative to the region of the heavily doped region of the drain are sequentially reduced.
  • forming the polycrystalline silicon forms an amorphous silicon layer on the surface of the buffer layer by sputtering, and recrystallizing the amorphous silicon layer by annealing.
  • the predetermined reticle is a halftone reticle or a gray scale reticle.
  • the material of the photoresist layer is a positive photoresist material.
  • the material of the photoresist layer is a negative photoresist material.
  • the thickness of the photoresist layer on the source heavily doped region is the same as the thickness of the photoresist layer on the drain heavily doped region, and the thickness of the photoresist layer on the source lightly doped region is The photoresist layer on the drain lightly doped region has the same thickness.
  • the invention only uses the primary mask process and the primary ion implantation process to complete the fabrication process of the polysilicon layer, simplifies the process, thereby reducing the process cost and facilitating the improvement of production efficiency.
  • FIG. 1A to 1C are schematic views showing a method of manufacturing a conventional low-temperature polysilicon thin film transistor
  • 2A to 2D are manufacturing sides of a low temperature polysilicon thin film transistor according to an embodiment of the present invention.
  • 3B is a schematic view of simultaneously forming a polysilicon layer and a photoresist layer according to another embodiment of the present invention.
  • 4B is a schematic view of simultaneously forming a polysilicon layer and a photoresist layer according to still another embodiment of the present invention.
  • FIG. 5B is a schematic diagram of simultaneously forming a polysilicon layer and a photoresist layer according to still another embodiment of the present invention.
  • FIGS. 2A through 2D are schematic views of a method of fabricating a low temperature polysilicon thin film transistor in accordance with an embodiment of the present invention.
  • a substrate 22 is provided, such as an insulating glass substrate or a quartz substrate.
  • a buffer layer 24 is formed on the substrate 22, such as silicon dioxide (SiO) formed on the substrate 22 by a PECVD process. 2 ).
  • a polysilicon layer 26 and a photoresist layer 28 are simultaneously formed on the buffer layer 24.
  • Simultaneously forming the polysilicon layer 26 and the photoresist layer 28 is to form polysilicon on the surface of the buffer layer 24, and then forming a photoresist material on the surface of the polysilicon by spin coating, and then exposing the photoresist material by using the halftone mask 30, and then exposing the photoresist.
  • the subsequent photoresist material is developed, leaving polysilicon and photoresist material in the regions where the polysilicon layer 26 and the photoresist layer 28 are formed, and the polysilicon and photoresist materials at the remaining positions are removed.
  • Forming polycrystalline silicon forms an amorphous silicon (a-Si) layer on the surface of the buffer layer 24 by sputtering, and recrystallizes the amorphous silicon layer by annealing.
  • the polysilicon layer 26 includes a source region 262, a drain region 264, and a channel region 266.
  • the source region 262 is away from the thickness of the photoresist layer 28 on the partial region 2621 of the channel region 266, and the source region 262.
  • the thickness of the photoresist layer 28 on the partial region 2622 adjacent to the channel region 266 and the thickness of the photoresist layer 28 on the channel region 266 are sequentially increased, and the drain region 264 is away from the photoresist layer 28 on the partial region 2641 of the channel region 266.
  • the thickness, the thickness of the photoresist layer 28 on the partial region 2642 of the drain region 264 near the channel region 266, and the thickness of the photoresist layer 28 on the channel region 266 are sequentially increased.
  • the source region 262 and the drain region 264 are ion implanted such that the source region 262 and the drain region 264 form a source electrode and a drain electrode, respectively, wherein the source region 262 is away from the channel region 266.
  • the partial region 2621 is a source heavily doped region
  • the partial region 2622 of the source region 262 near the channel region 266 is a source lightly doped region
  • the partial region 2641 of the drain region 264 away from the channel region 266 is heavily doped by the drain.
  • the partial region 2642 of the drain region 264 near the channel region 266 is a drain lightly doped region.
  • the photoresist layer 28 is formed of a positive photosensitive material.
  • the transmittance of the halftone mask 30 with respect to the region of the channel region 266, the transmittance of the halftone mask 30 with respect to the region of the source lightly doped region 2622, and the half The light transmittance of the region of the tone mask 30 with respect to the source heavily doped region 2621 is sequentially increased, and the transmittance of the halftone mask 30 with respect to the region of the channel region 266, the halftone mask 30 is lightly doped with respect to the drain.
  • the light transmittance of the region of the region 2642 and the light transmittance of the region of the halftone mask 30 with respect to the drain heavily doped region 2641 are sequentially increased.
  • the photoresist is exposed to light transmitted through different regions of the halftone mask 30, and then developed to form the photoresist layer 28 described above.
  • the thickness of the photoresist layer 28 on the source heavily doped region 2621 is the same as the thickness of the photoresist layer 28 on the drain heavily doped region 2641, and the photoresist layer 28 on the source lightly doped region 2622.
  • the thickness is the same as the thickness of the photoresist layer 28 on the drain lightly doped region 2642.
  • the transmittance of the area of the halftone mask 30 with respect to the source lightly doped region 2622 is the same as the transmittance of the area of the halftone mask 30 with respect to the drain lightly doped region 2642, and the halftone mask 30 is opposite.
  • the light transmittance of the region of the source heavily doped region 2621 is the same as the transmittance of the region of the halftone mask 30 with respect to the drain heavily doped region 2641.
  • the photoresist layer 28 is removed, for example, by removing the photoresist layer 28 by exposure development; then, an insulating layer 32 is formed on the polysilicon layer 26, for example, formed on the polysilicon layer 26 by a PECVD process.
  • a gate electrode 34 is formed on the insulating layer 32, and the material of the gate electrode 34 may be metal chromium or metal tungsten or an alloy of the two, etc.;
  • a passivation layer 36 is formed on the insulating layer 32, wherein the passivation layer 36 covers the gate electrode 34, which may be, for example, silicon dioxide (SiO 2 ) or nitride formed on the insulating layer 32 by a PECVD process. Silicon (SiN x ).
  • FIG. 3B is a schematic diagram of simultaneously forming a polysilicon layer and a photoresist layer according to another embodiment of the present invention.
  • a polysilicon layer 26 and a photoresist layer 28 are simultaneously formed on the buffer layer 24. Simultaneously forming the polysilicon layer 26 and the photoresist layer 28, polysilicon is formed on the surface of the buffer layer 24, and then a photoresist material is formed on the surface of the polysilicon by spin coating, and then the photoresist material is exposed by the gray scale mask 38, and then exposed. The subsequent photoresist material is developed, leaving polysilicon and photoresist material in the regions where the polysilicon layer 26 and the photoresist layer 28 are formed, and the polysilicon and photoresist materials at the remaining positions are removed. Forming polycrystalline silicon forms an amorphous silicon (a-Si) layer on the surface of the buffer layer 24 by sputtering, and recrystallizes the amorphous silicon layer by annealing.
  • a-Si amorphous silicon
  • the photoresist layer 28 is formed of a positive photosensitive material.
  • the transmittance of the gray scale mask 38 relative to the region of the channel region 266 ie, the slit density
  • the region of the gray scale mask 38 relative to the source lightly doped region 2622 is formed of a positive photosensitive material.
  • the light transmittance and the light transmittance of the gray scale mask 38 relative to the region of the source heavily doped region 2621 are sequentially increased, and the transmittance of the gray scale mask 38 relative to the region of the channel region 266, the gray scale mask 38
  • the light transmittance of the region of the drain lightly doped region 2642 and the transmittance of the region of the gray scale mask 38 with respect to the drain heavily doped region 2641 are sequentially increased.
  • the photoresist is exposed to light transmitted through different regions of the gray scale mask 38, and then developed to form the photoresist layer 28 described above.
  • 4B is a schematic view of simultaneously forming a polysilicon layer and a photoresist layer according to still another embodiment of the present invention.
  • the photoresist layer 28 is formed of a negative photosensitive material.
  • the light transmittance of the area of the tone mask 40 relative to the source heavily doped region 2621 is sequentially decreased, and the area of the halftone mask 40 relative to the channel region 266 is sequentially decreased.
  • the light transmittance of the domain, the light transmittance of the halftone mask 40 with respect to the region of the drain lightly doped region 2642, and the light transmittance of the region of the halftone mask 40 with respect to the drain heavily doped region 2641 are sequentially decreased.
  • the photoresist is exposed to light transmitted through different regions of the halftone mask 40, and then developed to form the photoresist layer 28 described above.
  • FIG. 5B is a schematic diagram of simultaneously forming a polysilicon layer and a photoresist layer according to still another embodiment of the present invention.
  • the photoresist layer 28 is formed of a negative photosensitive material.
  • the transmittance (slit density) of the gray scale mask 42 with respect to the region of the channel region 266, and the region of the gray scale mask 42 with respect to the source lightly doped region 2622 The light transmittance and the light transmittance of the region of the gray scale mask 42 with respect to the source heavily doped region 2621 are sequentially decreased, and the transmittance of the gray scale mask 42 with respect to the region of the channel region 266, the gray scale mask 42 is relatively
  • the light transmittance of the region of the drain lightly doped region 2642 and the light transmittance of the region of the gray scale mask 42 with respect to the drain heavily doped region 2641 are sequentially decreased.
  • the photoresist is exposed to light transmitted through different regions of the gray scale mask 42 and developed to form the photoresist layer 28 described above.
  • the present invention uses only one mask process and one ion implantation process to complete the fabrication process of the polysilicon layer, simplifies the process, thereby reducing the process cost and facilitating the improvement of production efficiency.

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  • Thin Film Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)

Abstract

一种低温多晶硅薄膜晶体管的制造方法，包括：提供一基板（22）；在所述基板（22）上形成缓冲层（24）；在所述缓冲层（24）上同时形成多晶硅层（26）及光阻层（28），对多晶硅层（26）中的源极区（262）及漏极区（264）进行离子注入，所述源极区（262）远离多晶硅层（26）中的通道区（266）的部分区（2621）上的光阻层的厚度、所述源极区（262）靠近所述通道区（266）的部分区（2622）上的光阻层的厚度及所述通道区（266）上的光阻层的厚度依次增大，所述漏极区（264）远离所述通道区（266）的部分区（2642）上的光阻层的厚度、所述漏极区（264）靠近所述通道区（266）的部分区（2641）上的光阻层的厚度及所述通道区（266）上的光阻层的厚度依次增大。以上方法仅采用一次光罩工艺及一次离子注入工艺完成对多晶硅层的制作处理，简化了工艺，因此减少工艺制程成本，且利于提高生产效率。

Description

一种低温多晶硅薄膜晶体管的制造方法 技术领域
本发明涉及一种低温多晶硅(Lower Temperature Polycrystal Silicon，LTPS)薄膜晶体管(Thin Film Transistor，TFT)的制造方法。
背景技术
随着光电与半导体技术的演进，也带动了平板显示器(Flat Panel Display)的蓬勃发展，而在诸多平板显示器中，液晶显示器(Liquid Crystal Display，简称LCD)因具有高空间利用效率、低消耗功率、无辐射以及低电磁干扰等诸多优越特性，已成为市场的主流。
目前，作为LCD的开关元件而广泛采用的是非晶硅薄膜三极管(a-Si TFT)，但a-Si TFT LCD在满足薄型、轻量、高精细度、高亮度、高可靠性、低功耗等要求仍受到限制。低温多晶硅(lower temperature polycrystal silicon，LTPS)TFT LCD与a-Si TFT LCD相比，在满足上述要求方面，具有明显优势。
首先，请参照图1A，提供一基板10；接着，在基板10上形成一多晶硅(LTPS)层12，其中，例如以溅射工序在基板10上形成一非晶硅(a-Si)层，然后进行退货工序，以使该非晶硅层再结晶形成多晶硅，最后对该多晶硅进行曝光显影后形成多晶硅层12。
接着，请参照图1B，在多晶硅层12上覆盖绝缘层14；接着，在绝缘层14上形成栅电极16；接着，在绝缘层14上形成一光阻层18，其中，该光阻层18覆盖栅电极16并位于多晶硅层12的中间区域上方，例如以利用旋涂方式在绝缘层14表面形成光阻材料，再以曝光显影的方式，留下一定厚度的光阻材料覆盖栅电极16并位于多晶硅层12的中间区域上方，去除其余位置的光阻材料；接着，利用离子注入工序向多晶硅层12的两侧区域122、124注入离子。
接着，请参照图1C，将光阻层18去除，例如以曝光显影的方式将光阻层18去除；接着，再次利用离子注入工序向多晶硅层12的通道区域121的两侧 区域注入离子，以使区域122、124形成重掺杂区域，区域126、128形成轻掺杂区域，其中，区域122与区域126组成源极区域，而区域124与区域128组成漏极区域；接着，在绝缘层14上形成一钝化层20，其中，钝化层20覆盖绝缘层14及栅电极16。
由上可知，在传统的LTPS TFT制程中，针对多晶硅层12的制作，需要采用三次光罩工艺及两次离子注入工艺，工艺复杂，因此增加工艺制程成本，且不利于提高生产效率。
发明内容
为了解决上述现有技术存在的问题，本发明的目的在于提供一种低温多晶硅薄膜晶体管的制造方法，包括：提供一基板；在所述基板上形成缓冲层；在所述缓冲层上同时形成多晶硅层及光阻层，其中，所述多晶硅层包括源极区、漏极区以及通道区，所述源极区远离所述通道区的部分区上的光阻层厚度、所述源极区靠近所述通道区的部分区上的光阻层厚度及所述通道区上的光阻层厚度依次增大，所述漏极区远离所述通道区的部分区上的光阻层厚度、所述漏极区靠近所述通道区的部分区上的光阻层厚度及所述通道区上的光阻层厚度依次增大；对所述源极区及所述漏极区进行离子注入，以使所述源极区和所述漏极区分别形成源电极和漏电极，其中，所述源极区远离所述通道区的部分为源极重掺杂区，所述源极区靠近所述通道区的部分区为源极轻掺杂区，所述漏极区远离所述通道区的部分区为漏极重掺杂区，所述漏极区靠近所述通道区的部分区为漏极轻掺杂区；将所述光阻层去除；在所述多晶硅层上形成绝缘层；在所述绝缘层上形成栅电极；在所述绝缘层上形成钝化层，其中，所述钝化层覆盖所述栅电极。
进一步地，同时形成所述多晶硅层及所述光阻层是在所述缓冲层表面形成多晶硅，再利用旋涂方式在所述多晶硅表面形成光阻材料，再利用预定光罩对所述光阻材料进行曝光，再对经曝光后的光阻材料进行显影，留下多晶硅及光阻材料在形成所述多晶硅层及所述光阻层的区域中，并去除其余位置的多晶硅及光阻材料，其中，所述预定光罩相对所述通道区的区域的透光率、所述预定光罩相对所述源极轻掺杂区的区域的透光率以及所述预定光罩相对所述源极重掺杂区的区域的透光率依次增大，所述预定光罩相对所述通道区的区域的透 光率、所述预定光罩相对所述漏极轻掺杂区的区域的透光率以及所述预定光罩相对所述漏极重掺杂区的区域的透光率依次增大。
进一步地，同时形成所述多晶硅层及所述光阻层是在所述缓冲层表面形成多晶硅，再利用旋涂方式在所述多晶硅表面形成光阻材料，再利用预定光罩对所述光阻材料进行曝光，再对经曝光后的光阻材料进行显影，留下多晶硅及光阻材料在形成所述多晶硅层及所述光阻层的区域中，并去除其余位置的多晶硅及光阻材料，其中，所述预定光罩相对所述通道区的区域的透光率、所述预定光罩相对所述源极轻掺杂区的区域的透光率以及所述预定光罩相对所述源极重掺杂区的区域的透光率依次减小，所述预定光罩相对所述通道区的区域的透光率、所述预定光罩相对所述漏极轻掺杂区的区域的透光率以及所述预定光罩相对所述漏极重掺杂区的区域的透光率依次减小。
进一步地，形成所述多晶硅是以溅射方式在所述缓冲层表面形成一非晶硅层，再以退火方式使所述非晶硅层再结晶。
进一步地，所述预定光罩为半色调光罩或者灰阶光罩。
进一步地，所述光阻层的材料为正性光阻材料。
进一步地，所述光阻层的材料为负性光阻材料。
进一步地，所述源极重掺杂区上的光阻层厚度与所述漏极重掺杂区上的光阻层厚度相同，所述源极轻掺杂区上的光阻层厚度与所述漏极轻掺杂区上的光阻层厚度相同。
本发明仅采用一次光罩工艺及一次离子注入工艺完成对多晶硅层的制作处理，简化了工艺，因此减少工艺制程成本，且利于提高生产效率。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1A至图1C是现有的低温多晶硅薄膜晶体管的制造方法的示意图；
图2A至图2D是根据本发明的实施例的低温多晶硅薄膜晶体管的制造方 法的示意图；
图3B是根据本发明的另一实施例的同时形成多晶硅层及光阻层的示意图；
图4B是根据本发明的又一实施例的同时形成多晶硅层及光阻层的示意图；
图5B是根据本发明的又一实施例的同时形成多晶硅层及光阻层的示意图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。在附图中，相同的标号将始终被用于表示相同的元件。
图2A至图2D是根据本发明的实施例的低温多晶硅薄膜晶体管的制造方法的示意图。
首先，请参照图2A，提供一基板22，例如为一绝缘的玻璃基板或石英基板；接着，在基板22上形成一缓冲层24，例如通过PECVD工艺在基板22上形成的二氧化硅(SiO2)。
接着，请参照图2B，在缓冲层24上同时形成多晶硅层26及光阻层28。同时形成多晶硅层26及光阻层28是在缓冲层24表面形成多晶硅，再利用旋涂方式在多晶硅表面形成光阻材料，再利用半色调光罩30对光阻材料进行曝光，再对经曝光后的光阻材料进行显影，留下多晶硅及光阻材料在形成多晶硅层26及光阻层28的区域中，并去除其余位置的多晶硅及光阻材料。形成多晶硅是以溅射方式在缓冲层24表面形成一非晶硅(a-Si)层，再以退火方式使非晶硅层再结晶。
在本实施例中，多晶硅层26包括源极区262、漏极区264以及通道区266，源极区262远离通道区266的部分区2621上的光阻层28的厚度、源极区262 靠近通道区266的部分区2622上的光阻层28的厚度及通道区266上的光阻层28的厚度依次增大，漏极区264远离通道区266的部分区2641上的光阻层28的厚度、漏极区264靠近通道区266的部分区2642上的光阻层28的厚度及通道区266上的光阻层28的厚度依次增大。
接着，请参照图2C，对源极区262及漏极区264进行离子注入，以使源极区262和漏极区264分别形成源电极和漏电极，其中，源极区262远离通道区266的部分区2621为源极重掺杂区，源极区262靠近通道区266的部分区2622为源极轻掺杂区，漏极区264远离通道区266的部分区2641为漏极重掺杂区，漏极区264靠近通道区266的部分区2642为漏极轻掺杂区。
一并参照图2B和图2C，光阻层28由正性感光材料形成。为了使光阻层28形成上述结构，对应的，半色调光罩30相对通道区266的区域的透光率、半色调光罩30相对源极轻掺杂区2622的区域的透光率以及半色调光罩30相对源极重掺杂区2621的区域的透光率依次增大，而半色调光罩30相对通道区266的区域的透光率、半色调光罩30相对漏极轻掺杂区2642的区域的透光率以及半色调光罩30相对漏极重掺杂区2641的区域的透光率依次增大。光阻材料经半色调光罩30不同区域透过的光进行曝光，再进行显影后而形成上述的光阻层28。
优选的，源极重掺杂区2621上的光阻层28的厚度与漏极重掺杂区2641上的光阻层28的厚度相同，源极轻掺杂区2622上的光阻层28的厚度与漏极轻掺杂区2642上的光阻层28的厚度相同。对应的，半色调光罩30相对源极轻掺杂区2622的区域的透光率与半色调光罩30相对漏极轻掺杂区2642的区域的透光率相同，半色调光罩30相对源极重掺杂区2621的区域的透光率与半色调光罩30相对漏极重掺杂区2641的区域的透光率相同。
接着，请参照图2D，将光阻层28去除，例如通过曝光显影方式将光阻层28去除；接着，在多晶硅层26上形成绝缘层32，例如通过PECVD工艺在多晶硅层26上形成的二氧化硅(SiO2)或氮化硅(SiNx)；接着，在绝缘层32上形成栅电极34，该栅电极34的材料可为金属铬或者金属钨或者二者的合金等；接着，在绝缘层32上形成钝化层36，其中，该钝化层36覆盖栅电极34，该钝化层36可例如是通过PECVD工艺在绝缘层32上形成的二氧化硅(SiO2) 或氮化硅(SiNx)。
图3B是根据本发明的另一实施例的同时形成多晶硅层及光阻层的示意图。
在图3B所示的另一实施例中，仅与图2B所示的同时形成多晶硅层及光阻层的方法有区别，其余方法均相同，因此二者相同之处在此不再赘述。
请参照图3B，在缓冲层24上同时形成多晶硅层26及光阻层28。同时形成多晶硅层26及光阻层28是在缓冲层24表面形成多晶硅，再利用旋涂方式在多晶硅表面形成光阻材料，再利用灰阶光罩38对光阻材料进行曝光，再对经曝光后的光阻材料进行显影，留下多晶硅及光阻材料在形成多晶硅层26及光阻层28的区域中，并去除其余位置的多晶硅及光阻材料。形成多晶硅是以溅射方式在缓冲层24表面形成一非晶硅(a-Si)层，再以退火方式使非晶硅层再结晶。
光阻层28由正性感光材料形成。为了使光阻层28形成上述结构，对应的，灰阶光罩38相对通道区266的区域的透光率(即狭缝密度)、灰阶光罩38相对源极轻掺杂区2622的区域的透光率以及灰阶光罩38相对源极重掺杂区2621的区域的透光率依次增大，而灰阶光罩38相对通道区266的区域的透光率、灰阶光罩38相对漏极轻掺杂区2642的区域的透光率以及灰阶光罩38相对漏极重掺杂区2641的区域的透光率依次增大。光阻材料经灰阶光罩38不同区域透过的光进行曝光，再进行显影后而形成上述的光阻层28。
图4B是根据本发明的又一实施例的同时形成多晶硅层及光阻层的示意图。
在图4B所示的又一实施例中，仅与图2B所示的同时形成多晶硅层及光阻层的方法有区别，其余方法均相同，因此二者相同之处在此不再赘述。
请参照图4B，光阻层28由负性感光材料形成。为了使光阻层28形成上述结构，对应的，半色调光罩40相对通道区266的区域的透光率、半色调光罩40相对源极轻掺杂区2622的区域的透光率以及半色调光罩40相对源极重掺杂区2621的区域的透光率依次减小，而半色调光罩40相对通道区266的区 域的透光率、半色调光罩40相对漏极轻掺杂区2642的区域的透光率以及半色调光罩40相对漏极重掺杂区2641的区域的透光率依次减小。光阻材料经半色调光罩40不同区域透过的光进行曝光，再进行显影后而形成上述的光阻层28。
图5B是根据本发明的又一实施例的同时形成多晶硅层及光阻层的示意图。
在图5B所示的又一实施例中，仅与图2B所示的同时形成多晶硅层及光阻层的方法有区别，其余方法均相同，因此二者相同之处在此不再赘述。
请参照图5B，光阻层28由负性感光材料形成。为了使光阻层28形成上述结构，对应的，灰阶光罩42相对通道区266的区域的透光率(狭缝密度)、灰阶光罩42相对源极轻掺杂区2622的区域的透光率以及灰阶光罩42相对源极重掺杂区2621的区域的透光率依次减小，而灰阶光罩42相对通道区266的区域的透光率、灰阶光罩42相对漏极轻掺杂区2642的区域的透光率以及灰阶光罩42相对漏极重掺杂区2641的区域的透光率依次减小。光阻材料经灰阶光罩42不同区域透过的光进行曝光，再进行显影后而形成上述的光阻层28。
综上，本发明仅采用一次光罩工艺及一次离子注入工艺完成对多晶硅层的制作处理，简化了工艺，因此减少工艺制程成本，且利于提高生产效率。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (14)

  1. 一种低温多晶硅薄膜晶体管的制造方法，其中，包括：
    提供一基板；
    在所述基板上形成缓冲层；
    在所述缓冲层上同时形成多晶硅层及光阻层，其中，所述多晶硅层包括源极区、漏极区以及通道区，所述源极区远离所述通道区的部分区上的光阻层的厚度、所述源极区靠近所述通道区的部分区上的光阻层的厚度及所述通道区上的光阻层的厚度依次增大，所述漏极区远离所述通道区的部分区上的光阻层的厚度、所述漏极区靠近所述通道区的部分区上的光阻层的厚度及所述通道区上的光阻层的厚度依次增大；
    对所述源极区及所述漏极区进行离子注入，以使所述源极区和所述漏极区分别形成源电极和漏电极，其中，所述源极区远离所述通道区的部分为源极重掺杂区，所述源极区靠近所述通道区的部分区为源极轻掺杂区，所述漏极区远离所述通道区的部分区为漏极重掺杂区，所述漏极区靠近所述通道区的部分区为漏极轻掺杂区；
    将所述光阻层去除；
    在所述多晶硅层上形成绝缘层；
    在所述绝缘层上形成栅电极；
    在所述绝缘层上形成钝化层，其中，所述钝化层覆盖所述栅电极。
  2. 根据权利要求1所述的制造方法，其中，同时形成所述多晶硅层及所述光阻层是在所述缓冲层表面形成多晶硅，再利用旋涂方式在所述多晶硅表面形成光阻材料，再利用预定光罩对所述光阻材料进行曝光，再对经曝光后的光阻材料进行显影，留下多晶硅及光阻材料在形成所述多晶硅层及所述光阻层的区域中，并去除其余位置的多晶硅及光阻材料，
    其中，所述预定光罩相对所述通道区的区域的透光率、所述预定光罩相对 所述源极轻掺杂区的区域的透光率以及所述预定光罩相对所述源极重掺杂区的区域的透光率依次增大，所述预定光罩相对所述通道区的区域的透光率、所述预定光罩相对所述漏极轻掺杂区的区域的透光率以及所述预定光罩相对所述漏极重掺杂区的区域的透光率依次增大。
  3. 根据权利要求1所述的制造方法，其中，同时形成所述多晶硅层及所述光阻层是在所述缓冲层表面形成多晶硅，再利用旋涂方式在所述多晶硅表面形成光阻材料，再利用预定光罩对所述光阻材料进行曝光，再对经曝光后的光阻材料进行显影，留下多晶硅及光阻材料在形成所述多晶硅层及所述光阻层的区域中，并去除其余位置的多晶硅及光阻材料，
    其中，所述预定光罩相对所述通道区的区域的透光率、所述预定光罩相对所述源极轻掺杂区的区域的透光率以及所述预定光罩相对所述源极重掺杂区的区域的透光率依次减小，所述预定光罩相对所述通道区的区域的透光率、所述预定光罩相对所述漏极轻掺杂区的区域的透光率以及所述预定光罩相对所述漏极重掺杂区的区域的透光率依次减小。
  4. 根据权利要求2所述的制造方法，其中，形成所述多晶硅是以溅射方式在所述缓冲层表面形成一非晶硅层，再以退火方式使所述非晶硅层再结晶。
  5. 根据权利要求2所述的制造方法，其中，所述预定光罩为半色调光罩或者灰阶光罩。
  6. 根据权利要求4所述的制造方法，其中，所述预定光罩为半色调光罩或者灰阶光罩。
  7. 根据权利要求3所述的制造方法，其中，形成所述多晶硅是以溅射方式在所述缓冲层表面形成一非晶硅层，再以退火方式使所述非晶硅层再结晶。
  8. 根据权利要求3所述的制造方法，其中，所述预定光罩为半色调光罩或者灰阶光罩。
  9. 根据权利要求7所述的制造方法，其中，所述预定光罩为半色调光罩或者灰阶光罩。
  10. 根据权利要求5所述的制造方法，其中，所述光阻层的材料为正性光阻材料。
  11. 根据权利要求6所述的制造方法，其中，所述光阻层的材料为正性光阻材料。
  12. 根据权利要求8所述的制造方法，其中，所述光阻层的材料为负性光阻材料。
  13. 根据权利要求9所述的制造方法，其中，所述光阻层的材料为负性光阻材料。
  14. 根据权利要求1所述的制造方法，其中，所述源极重掺杂区上的光阻层的厚度与所述漏极重掺杂区上的光阻层的厚度相同，所述源极轻掺杂区上的光阻层的厚度与所述漏极轻掺杂区上的光阻层的厚度相同。
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